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board: colibri-imx6ull: fix detecting ethernet phy

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Now that it is possible to use regulator-fixed-clock make use
of it. This makes U-Boot detect the PHY on first cold-boot.

This commit also adjusts the code in setup_fec and follows
how it is done in mx6ullevk.c

This commit also slows down the boot-process by about 150ms
as it now waits for the regulator-fixed-clock voltage that
drives the PHY to go up.
If you rely on very fast boot-speeds and don't need ethernet
for your boot-process you can safely revert the changes on
imx6ull-colibri.dtsi

Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
This commit is contained in:
Philippe Schenker 2022-04-08 10:07:11 +02:00 committed by Stefano Babic
parent f3b5100aff
commit aa6f57d877
2 changed files with 21 additions and 15 deletions
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13
arch/arm/dts/imx6ull-colibri.dtsi
View file

@ -64,6 +64,18 @@
gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; /* USBH_PEN */ gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; /* USBH_PEN */
vin-supply = <&reg_5v0>; vin-supply = <&reg_5v0>;
}; };
reg_eth_phy: regulator-eth-phy {
compatible = "regulator-fixed-clock";
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "eth_phy";
regulator-type = "voltage";
vin-supply = <&reg_module_3v3>;
clocks = <&clks IMX6UL_CLK_ENET2_REF_125M>;
startup-delay-us = <150000>;
};
}; };
&adc1 { &adc1 {
@ -84,6 +96,7 @@
pinctrl-0 = <&pinctrl_enet2>; pinctrl-0 = <&pinctrl_enet2>;
phy-mode = "rmii"; phy-mode = "rmii";
phy-handle = <&ethphy1>; phy-handle = <&ethphy1>;
phy-supply = <&reg_eth_phy>;
status = "okay"; status = "okay";
mdio { mdio {

23
board/toradex/colibri-imx6ull/colibri-imx6ull.c
View file

@ -100,26 +100,19 @@ static int setup_fec(void)
struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
int ret; int ret;
/* provide the PHY clock from the i.MX 6 */ /*
* Use 50MHz anatop loopback REF_CLK2 for ENET2,
* clear gpr1[14], set gpr1[18].
*/
clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
ret = enable_fec_anatop_clock(1, ENET_50MHZ); ret = enable_fec_anatop_clock(1, ENET_50MHZ);
if (ret) if (ret)
return ret; return ret;
/* Use 50M anatop REF_CLK and output it on ENET2_TX_CLK */ enable_enet_clk(1);
clrsetbits_le32(&iomuxc_regs->gpr[1],
IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK,
IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
/* give new Ethernet PHY power save mode circuitry time to settle */
mdelay(300);
return 0;
}
int board_phy_config(struct phy_device *phydev)
{
if (phydev->drv->config)
phydev->drv->config(phydev);
return 0; return 0;
} }
#endif /* CONFIG_FEC_MXC */ #endif /* CONFIG_FEC_MXC */