mirror of
https://github.com/AsahiLinux/u-boot
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arm: vexpress: Add a devicetree files for juno
Sync these file, obtained from Linux v5.15. Add a note for the maintainer, and SPDX lines where they are missing. The added lines are: SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause Note, this matches the text in those files, but is not the same as the GPL-2.0 of some files. [1] https://releases.linaro.org/android/reference-lcr/juno/7.1-17.05/ Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Simon Glass
Tom Rini
parent
9ae600e9e2
commit
aa26948b58
8 changed files with 1611 additions and 0 deletions
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@ -1149,7 +1149,10 @@ dtb-$(CONFIG_TARGET_GE_BX50V3) += \
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dtb-$(CONFIG_TARGET_GE_B1X5V2) += imx6dl-b1x5v2.dtb
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dtb-$(CONFIG_TARGET_MX53PPD) += imx53-ppd.dtb
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# TODO(Linus Walleij <linus.walleij@linaro.org>): Should us a single vexpress
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# Kconfig option to build all of these. See examples above.
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dtb-$(CONFIG_TARGET_VEXPRESS_CA9X4) += vexpress-v2p-ca9.dtb
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dtb-$(CONFIG_TARGET_VEXPRESS64_JUNO) += juno-r2.dtb
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dtb-$(CONFIG_TARGET_TOTAL_COMPUTE) += total_compute.dtb
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831
arch/arm/dts/juno-base.dtsi
Normal file
831
arch/arm/dts/juno-base.dtsi
Normal file
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@ -0,0 +1,831 @@
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// SPDX-License-Identifier: GPL-2.0
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#include "juno-clocks.dtsi"
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#include "juno-motherboard.dtsi"
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/ {
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/*
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* Devices shared by all Juno boards
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*/
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memtimer: timer@2a810000 {
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compatible = "arm,armv7-timer-mem";
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reg = <0x0 0x2a810000 0x0 0x10000>;
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clock-frequency = <50000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x0 0x2a820000 0x20000>;
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status = "disabled";
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frame@2a830000 {
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frame-number = <1>;
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interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x10000 0x10000>;
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};
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};
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mailbox: mhu@2b1f0000 {
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compatible = "arm,mhu", "arm,primecell";
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reg = <0x0 0x2b1f0000 0x0 0x1000>;
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
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#mbox-cells = <1>;
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clocks = <&soc_refclk100mhz>;
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clock-names = "apb_pclk";
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};
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smmu_gpu: iommu@2b400000 {
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compatible = "arm,mmu-400", "arm,smmu-v1";
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reg = <0x0 0x2b400000 0x0 0x10000>;
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interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
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#iommu-cells = <1>;
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#global-interrupts = <1>;
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power-domains = <&scpi_devpd 1>;
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dma-coherent;
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status = "disabled";
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};
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smmu_pcie: iommu@2b500000 {
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compatible = "arm,mmu-401", "arm,smmu-v1";
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reg = <0x0 0x2b500000 0x0 0x10000>;
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interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
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#iommu-cells = <1>;
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#global-interrupts = <1>;
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dma-coherent;
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status = "disabled";
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};
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smmu_etr: iommu@2b600000 {
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compatible = "arm,mmu-401", "arm,smmu-v1";
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reg = <0x0 0x2b600000 0x0 0x10000>;
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interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
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#iommu-cells = <1>;
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#global-interrupts = <1>;
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dma-coherent;
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power-domains = <&scpi_devpd 0>;
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};
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gic: interrupt-controller@2c010000 {
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compatible = "arm,gic-400", "arm,cortex-a15-gic";
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reg = <0x0 0x2c010000 0 0x1000>,
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<0x0 0x2c02f000 0 0x2000>,
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<0x0 0x2c04f000 0 0x2000>,
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<0x0 0x2c06f000 0 0x2000>;
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#address-cells = <1>;
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#interrupt-cells = <3>;
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#size-cells = <1>;
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interrupt-controller;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
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ranges = <0 0 0x2c1c0000 0x40000>;
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v2m_0: v2m@0 {
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compatible = "arm,gic-v2m-frame";
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msi-controller;
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reg = <0 0x10000>;
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};
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v2m@10000 {
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compatible = "arm,gic-v2m-frame";
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msi-controller;
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reg = <0x10000 0x10000>;
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};
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v2m@20000 {
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compatible = "arm,gic-v2m-frame";
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msi-controller;
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reg = <0x20000 0x10000>;
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};
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v2m@30000 {
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compatible = "arm,gic-v2m-frame";
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msi-controller;
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reg = <0x30000 0x10000>;
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
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};
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/*
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* Juno TRMs specify the size for these coresight components as 64K.
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* The actual size is just 4K though 64K is reserved. Access to the
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* unmapped reserved region results in a DECERR response.
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*/
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etf@20010000 { /* etf0 */
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compatible = "arm,coresight-tmc", "arm,primecell";
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reg = <0 0x20010000 0 0x1000>;
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clocks = <&soc_smc50mhz>;
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clock-names = "apb_pclk";
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power-domains = <&scpi_devpd 0>;
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in-ports {
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port {
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etf0_in_port: endpoint {
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remote-endpoint = <&main_funnel_out_port>;
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};
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};
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};
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out-ports {
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port {
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etf0_out_port: endpoint {
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};
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};
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};
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};
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tpiu@20030000 {
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compatible = "arm,coresight-tpiu", "arm,primecell";
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reg = <0 0x20030000 0 0x1000>;
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clocks = <&soc_smc50mhz>;
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clock-names = "apb_pclk";
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power-domains = <&scpi_devpd 0>;
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in-ports {
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port {
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tpiu_in_port: endpoint {
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remote-endpoint = <&replicator_out_port0>;
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};
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};
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};
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};
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/* main funnel on Juno r0, cssys0 funnel on Juno r1/r2 as per TRM*/
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main_funnel: funnel@20040000 {
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compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
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reg = <0 0x20040000 0 0x1000>;
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clocks = <&soc_smc50mhz>;
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clock-names = "apb_pclk";
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power-domains = <&scpi_devpd 0>;
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out-ports {
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port {
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main_funnel_out_port: endpoint {
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remote-endpoint = <&etf0_in_port>;
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};
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};
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};
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main_funnel_in_ports: in-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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main_funnel_in_port0: endpoint {
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remote-endpoint = <&cluster0_funnel_out_port>;
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};
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};
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port@1 {
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reg = <1>;
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main_funnel_in_port1: endpoint {
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remote-endpoint = <&cluster1_funnel_out_port>;
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};
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};
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};
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};
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etr@20070000 {
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compatible = "arm,coresight-tmc", "arm,primecell";
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reg = <0 0x20070000 0 0x1000>;
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iommus = <&smmu_etr 0>;
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clocks = <&soc_smc50mhz>;
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clock-names = "apb_pclk";
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power-domains = <&scpi_devpd 0>;
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arm,scatter-gather;
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in-ports {
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port {
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etr_in_port: endpoint {
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remote-endpoint = <&replicator_out_port1>;
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};
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};
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};
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};
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stm@20100000 {
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compatible = "arm,coresight-stm", "arm,primecell";
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reg = <0 0x20100000 0 0x1000>,
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<0 0x28000000 0 0x1000000>;
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reg-names = "stm-base", "stm-stimulus-base";
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clocks = <&soc_smc50mhz>;
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clock-names = "apb_pclk";
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power-domains = <&scpi_devpd 0>;
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out-ports {
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port {
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stm_out_port: endpoint {
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};
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};
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};
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};
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replicator@20120000 {
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compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
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reg = <0 0x20120000 0 0x1000>;
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clocks = <&soc_smc50mhz>;
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clock-names = "apb_pclk";
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power-domains = <&scpi_devpd 0>;
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out-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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/* replicator output ports */
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port@0 {
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reg = <0>;
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replicator_out_port0: endpoint {
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remote-endpoint = <&tpiu_in_port>;
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};
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};
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port@1 {
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reg = <1>;
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replicator_out_port1: endpoint {
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remote-endpoint = <&etr_in_port>;
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};
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};
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};
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in-ports {
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port {
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replicator_in_port0: endpoint {
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};
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};
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};
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};
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cpu_debug0: cpu-debug@22010000 {
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compatible = "arm,coresight-cpu-debug", "arm,primecell";
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reg = <0x0 0x22010000 0x0 0x1000>;
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clocks = <&soc_smc50mhz>;
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clock-names = "apb_pclk";
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power-domains = <&scpi_devpd 0>;
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};
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etm0: etm@22040000 {
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0 0x22040000 0 0x1000>;
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clocks = <&soc_smc50mhz>;
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clock-names = "apb_pclk";
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power-domains = <&scpi_devpd 0>;
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out-ports {
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port {
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cluster0_etm0_out_port: endpoint {
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remote-endpoint = <&cluster0_funnel_in_port0>;
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};
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};
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};
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};
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funnel@220c0000 { /* cluster0 funnel */
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compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
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reg = <0 0x220c0000 0 0x1000>;
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clocks = <&soc_smc50mhz>;
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clock-names = "apb_pclk";
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power-domains = <&scpi_devpd 0>;
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out-ports {
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port {
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cluster0_funnel_out_port: endpoint {
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remote-endpoint = <&main_funnel_in_port0>;
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};
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};
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};
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in-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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cluster0_funnel_in_port0: endpoint {
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remote-endpoint = <&cluster0_etm0_out_port>;
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};
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};
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port@1 {
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reg = <1>;
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cluster0_funnel_in_port1: endpoint {
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remote-endpoint = <&cluster0_etm1_out_port>;
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};
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};
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};
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};
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cpu_debug1: cpu-debug@22110000 {
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compatible = "arm,coresight-cpu-debug", "arm,primecell";
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reg = <0x0 0x22110000 0x0 0x1000>;
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clocks = <&soc_smc50mhz>;
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clock-names = "apb_pclk";
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power-domains = <&scpi_devpd 0>;
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};
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etm1: etm@22140000 {
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0 0x22140000 0 0x1000>;
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clocks = <&soc_smc50mhz>;
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clock-names = "apb_pclk";
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power-domains = <&scpi_devpd 0>;
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out-ports {
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port {
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cluster0_etm1_out_port: endpoint {
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remote-endpoint = <&cluster0_funnel_in_port1>;
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};
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};
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};
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};
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cpu_debug2: cpu-debug@23010000 {
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compatible = "arm,coresight-cpu-debug", "arm,primecell";
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reg = <0x0 0x23010000 0x0 0x1000>;
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clocks = <&soc_smc50mhz>;
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clock-names = "apb_pclk";
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power-domains = <&scpi_devpd 0>;
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};
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etm2: etm@23040000 {
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0 0x23040000 0 0x1000>;
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clocks = <&soc_smc50mhz>;
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clock-names = "apb_pclk";
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power-domains = <&scpi_devpd 0>;
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out-ports {
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port {
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cluster1_etm0_out_port: endpoint {
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remote-endpoint = <&cluster1_funnel_in_port0>;
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};
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};
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};
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};
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funnel@230c0000 { /* cluster1 funnel */
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compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
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reg = <0 0x230c0000 0 0x1000>;
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clocks = <&soc_smc50mhz>;
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clock-names = "apb_pclk";
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power-domains = <&scpi_devpd 0>;
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out-ports {
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port {
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cluster1_funnel_out_port: endpoint {
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remote-endpoint = <&main_funnel_in_port1>;
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};
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};
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};
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in-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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cluster1_funnel_in_port0: endpoint {
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remote-endpoint = <&cluster1_etm0_out_port>;
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};
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};
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port@1 {
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reg = <1>;
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cluster1_funnel_in_port1: endpoint {
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remote-endpoint = <&cluster1_etm1_out_port>;
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};
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};
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port@2 {
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reg = <2>;
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cluster1_funnel_in_port2: endpoint {
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remote-endpoint = <&cluster1_etm2_out_port>;
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};
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};
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port@3 {
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reg = <3>;
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cluster1_funnel_in_port3: endpoint {
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remote-endpoint = <&cluster1_etm3_out_port>;
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};
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};
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};
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};
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cpu_debug3: cpu-debug@23110000 {
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compatible = "arm,coresight-cpu-debug", "arm,primecell";
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reg = <0x0 0x23110000 0x0 0x1000>;
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clocks = <&soc_smc50mhz>;
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clock-names = "apb_pclk";
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power-domains = <&scpi_devpd 0>;
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};
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etm3: etm@23140000 {
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0 0x23140000 0 0x1000>;
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clocks = <&soc_smc50mhz>;
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clock-names = "apb_pclk";
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||||
power-domains = <&scpi_devpd 0>;
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out-ports {
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||||
port {
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cluster1_etm1_out_port: endpoint {
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remote-endpoint = <&cluster1_funnel_in_port1>;
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||||
};
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||||
};
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||||
};
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||||
};
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cpu_debug4: cpu-debug@23210000 {
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compatible = "arm,coresight-cpu-debug", "arm,primecell";
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reg = <0x0 0x23210000 0x0 0x1000>;
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||||
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clocks = <&soc_smc50mhz>;
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||||
clock-names = "apb_pclk";
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||||
power-domains = <&scpi_devpd 0>;
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||||
};
|
||||
|
||||
etm4: etm@23240000 {
|
||||
compatible = "arm,coresight-etm4x", "arm,primecell";
|
||||
reg = <0 0x23240000 0 0x1000>;
|
||||
|
||||
clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
power-domains = <&scpi_devpd 0>;
|
||||
out-ports {
|
||||
port {
|
||||
cluster1_etm2_out_port: endpoint {
|
||||
remote-endpoint = <&cluster1_funnel_in_port2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cpu_debug5: cpu-debug@23310000 {
|
||||
compatible = "arm,coresight-cpu-debug", "arm,primecell";
|
||||
reg = <0x0 0x23310000 0x0 0x1000>;
|
||||
|
||||
clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
power-domains = <&scpi_devpd 0>;
|
||||
};
|
||||
|
||||
etm5: etm@23340000 {
|
||||
compatible = "arm,coresight-etm4x", "arm,primecell";
|
||||
reg = <0 0x23340000 0 0x1000>;
|
||||
|
||||
clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
power-domains = <&scpi_devpd 0>;
|
||||
out-ports {
|
||||
port {
|
||||
cluster1_etm3_out_port: endpoint {
|
||||
remote-endpoint = <&cluster1_funnel_in_port3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gpu: gpu@2d000000 {
|
||||
compatible = "arm,juno-mali", "arm,mali-t624";
|
||||
reg = <0 0x2d000000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "job", "mmu", "gpu";
|
||||
clocks = <&scpi_dvfs 2>;
|
||||
power-domains = <&scpi_devpd 1>;
|
||||
dma-coherent;
|
||||
/* The SMMU is only really of interest to bare-metal hypervisors */
|
||||
/* iommus = <&smmu_gpu 0>; */
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sram: sram@2e000000 {
|
||||
compatible = "arm,juno-sram-ns", "mmio-sram";
|
||||
reg = <0x0 0x2e000000 0x0 0x8000>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x0 0x2e000000 0x8000>;
|
||||
|
||||
cpu_scp_lpri: scp-sram@0 {
|
||||
compatible = "arm,juno-scp-shmem";
|
||||
reg = <0x0 0x200>;
|
||||
};
|
||||
|
||||
cpu_scp_hpri: scp-sram@200 {
|
||||
compatible = "arm,juno-scp-shmem";
|
||||
reg = <0x200 0x200>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie_ctlr: pcie@40000000 {
|
||||
compatible = "arm,juno-r1-pcie", "plda,xpressrich3-axi", "pci-host-ecam-generic";
|
||||
device_type = "pci";
|
||||
reg = <0 0x40000000 0 0x10000000>; /* ECAM config space */
|
||||
bus-range = <0 255>;
|
||||
linux,pci-domain = <0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
dma-coherent;
|
||||
ranges = <0x01000000 0x00 0x00000000 0x00 0x5f800000 0x0 0x00800000>,
|
||||
<0x02000000 0x00 0x50000000 0x00 0x50000000 0x0 0x08000000>,
|
||||
<0x42000000 0x40 0x00000000 0x40 0x00000000 0x1 0x00000000>;
|
||||
/* Standard AXI Translation entries as programmed by EDK2 */
|
||||
dma-ranges = <0x02000000 0x0 0x2c1c0000 0x0 0x2c1c0000 0x0 0x00040000>,
|
||||
<0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x80000000>,
|
||||
<0x43000000 0x8 0x00000000 0x8 0x00000000 0x2 0x00000000>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &gic 0 GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 2 &gic 0 GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 3 &gic 0 GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 4 &gic 0 GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
|
||||
msi-parent = <&v2m_0>;
|
||||
status = "disabled";
|
||||
iommu-map-mask = <0x0>; /* RC has no means to output PCI RID */
|
||||
iommu-map = <0x0 &smmu_pcie 0x0 0x1>;
|
||||
};
|
||||
|
||||
scpi {
|
||||
compatible = "arm,scpi";
|
||||
mboxes = <&mailbox 1>;
|
||||
shmem = <&cpu_scp_hpri>;
|
||||
|
||||
clocks {
|
||||
compatible = "arm,scpi-clocks";
|
||||
|
||||
scpi_dvfs: clocks-0 {
|
||||
compatible = "arm,scpi-dvfs-clocks";
|
||||
#clock-cells = <1>;
|
||||
clock-indices = <0>, <1>, <2>;
|
||||
clock-output-names = "atlclk", "aplclk","gpuclk";
|
||||
};
|
||||
scpi_clk: clocks-1 {
|
||||
compatible = "arm,scpi-variable-clocks";
|
||||
#clock-cells = <1>;
|
||||
clock-indices = <3>;
|
||||
clock-output-names = "pxlclk";
|
||||
};
|
||||
};
|
||||
|
||||
scpi_devpd: power-controller {
|
||||
compatible = "arm,scpi-power-domains";
|
||||
num-domains = <2>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
scpi_sensors0: sensors {
|
||||
compatible = "arm,scpi-sensors";
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
pmic {
|
||||
polling-delay = <1000>;
|
||||
polling-delay-passive = <100>;
|
||||
thermal-sensors = <&scpi_sensors0 0>;
|
||||
};
|
||||
|
||||
soc {
|
||||
polling-delay = <1000>;
|
||||
polling-delay-passive = <100>;
|
||||
thermal-sensors = <&scpi_sensors0 3>;
|
||||
};
|
||||
|
||||
big_cluster_thermal_zone: big-cluster {
|
||||
polling-delay = <1000>;
|
||||
polling-delay-passive = <100>;
|
||||
thermal-sensors = <&scpi_sensors0 21>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
little_cluster_thermal_zone: little-cluster {
|
||||
polling-delay = <1000>;
|
||||
polling-delay-passive = <100>;
|
||||
thermal-sensors = <&scpi_sensors0 22>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpu0_thermal_zone: gpu0 {
|
||||
polling-delay = <1000>;
|
||||
polling-delay-passive = <100>;
|
||||
thermal-sensors = <&scpi_sensors0 23>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpu1_thermal_zone: gpu1 {
|
||||
polling-delay = <1000>;
|
||||
polling-delay-passive = <100>;
|
||||
thermal-sensors = <&scpi_sensors0 24>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
smmu_dma: iommu@7fb00000 {
|
||||
compatible = "arm,mmu-401", "arm,smmu-v1";
|
||||
reg = <0x0 0x7fb00000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#iommu-cells = <1>;
|
||||
#global-interrupts = <1>;
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
smmu_hdlcd1: iommu@7fb10000 {
|
||||
compatible = "arm,mmu-401", "arm,smmu-v1";
|
||||
reg = <0x0 0x7fb10000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#iommu-cells = <1>;
|
||||
#global-interrupts = <1>;
|
||||
};
|
||||
|
||||
smmu_hdlcd0: iommu@7fb20000 {
|
||||
compatible = "arm,mmu-401", "arm,smmu-v1";
|
||||
reg = <0x0 0x7fb20000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#iommu-cells = <1>;
|
||||
#global-interrupts = <1>;
|
||||
};
|
||||
|
||||
smmu_usb: iommu@7fb30000 {
|
||||
compatible = "arm,mmu-401", "arm,smmu-v1";
|
||||
reg = <0x0 0x7fb30000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#iommu-cells = <1>;
|
||||
#global-interrupts = <1>;
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
dma@7ff00000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x0 0x7ff00000 0 0x1000>;
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <8>;
|
||||
#dma-requests = <32>;
|
||||
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
|
||||
iommus = <&smmu_dma 0>,
|
||||
<&smmu_dma 1>,
|
||||
<&smmu_dma 2>,
|
||||
<&smmu_dma 3>,
|
||||
<&smmu_dma 4>,
|
||||
<&smmu_dma 5>,
|
||||
<&smmu_dma 6>,
|
||||
<&smmu_dma 7>,
|
||||
<&smmu_dma 8>;
|
||||
clocks = <&soc_faxiclk>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
hdlcd@7ff50000 {
|
||||
compatible = "arm,hdlcd";
|
||||
reg = <0 0x7ff50000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
|
||||
iommus = <&smmu_hdlcd1 0>;
|
||||
clocks = <&scpi_clk 3>;
|
||||
clock-names = "pxlclk";
|
||||
|
||||
port {
|
||||
hdlcd1_output: endpoint {
|
||||
remote-endpoint = <&tda998x_1_input>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hdlcd@7ff60000 {
|
||||
compatible = "arm,hdlcd";
|
||||
reg = <0 0x7ff60000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
|
||||
iommus = <&smmu_hdlcd0 0>;
|
||||
clocks = <&scpi_clk 3>;
|
||||
clock-names = "pxlclk";
|
||||
|
||||
port {
|
||||
hdlcd0_output: endpoint {
|
||||
remote-endpoint = <&tda998x_0_input>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
soc_uart0: serial@7ff80000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x0 0x7ff80000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&soc_uartclk>, <&soc_refclk100mhz>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
||||
i2c@7ffa0000 {
|
||||
compatible = "snps,designware-i2c";
|
||||
reg = <0x0 0x7ffa0000 0x0 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <400000>;
|
||||
i2c-sda-hold-time-ns = <500>;
|
||||
clocks = <&soc_smc50mhz>;
|
||||
|
||||
hdmi-transmitter@70 {
|
||||
compatible = "nxp,tda998x";
|
||||
reg = <0x70>;
|
||||
port {
|
||||
tda998x_0_input: endpoint {
|
||||
remote-endpoint = <&hdlcd0_output>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hdmi-transmitter@71 {
|
||||
compatible = "nxp,tda998x";
|
||||
reg = <0x71>;
|
||||
port {
|
||||
tda998x_1_input: endpoint {
|
||||
remote-endpoint = <&hdlcd1_output>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
usb@7ffb0000 {
|
||||
compatible = "generic-ohci";
|
||||
reg = <0x0 0x7ffb0000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
|
||||
iommus = <&smmu_usb 0>;
|
||||
clocks = <&soc_usb48mhz>;
|
||||
};
|
||||
|
||||
usb@7ffc0000 {
|
||||
compatible = "generic-ehci";
|
||||
reg = <0x0 0x7ffc0000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
|
||||
iommus = <&smmu_usb 0>;
|
||||
clocks = <&soc_usb48mhz>;
|
||||
};
|
||||
|
||||
memory-controller@7ffd0000 {
|
||||
compatible = "arm,pl354", "arm,primecell";
|
||||
reg = <0 0x7ffd0000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
/* last 16MB of the first memory area is reserved for secure world use by firmware */
|
||||
reg = <0x00000000 0x80000000 0x0 0x7f000000>,
|
||||
<0x00000008 0x80000000 0x1 0x80000000>;
|
||||
};
|
||||
|
||||
bus@8000000 {
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 15>;
|
||||
interrupt-map = <0 0 0 &gic 0 GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 1 &gic 0 GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 2 &gic 0 GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 3 &gic 0 GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 4 &gic 0 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 5 &gic 0 GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 6 &gic 0 GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 7 &gic 0 GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 8 &gic 0 GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 9 &gic 0 GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 10 &gic 0 GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 11 &gic 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 12 &gic 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
site2: tlx-bus@60000000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0x60000000 0x10000000>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0>;
|
||||
interrupt-map = <0 0 &gic 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
46
arch/arm/dts/juno-clocks.dtsi
Normal file
46
arch/arm/dts/juno-clocks.dtsi
Normal file
|
|
@ -0,0 +1,46 @@
|
|||
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
|
||||
/*
|
||||
* ARM Juno Platform clocks
|
||||
*
|
||||
* Copyright (c) 2013-2014 ARM Ltd
|
||||
*
|
||||
* This file is licensed under a dual GPLv2 or BSD license.
|
||||
*
|
||||
*/
|
||||
/ {
|
||||
/* SoC fixed clocks */
|
||||
soc_uartclk: refclk7372800hz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <7372800>;
|
||||
clock-output-names = "juno:uartclk";
|
||||
};
|
||||
|
||||
soc_usb48mhz: clk48mhz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <48000000>;
|
||||
clock-output-names = "clk48mhz";
|
||||
};
|
||||
|
||||
soc_smc50mhz: clk50mhz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <50000000>;
|
||||
clock-output-names = "smc_clk";
|
||||
};
|
||||
|
||||
soc_refclk100mhz: refclk100mhz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <100000000>;
|
||||
clock-output-names = "apb_pclk";
|
||||
};
|
||||
|
||||
soc_faxiclk: refclk400mhz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <400000000>;
|
||||
clock-output-names = "faxi_clk";
|
||||
};
|
||||
};
|
||||
85
arch/arm/dts/juno-cs-r1r2.dtsi
Normal file
85
arch/arm/dts/juno-cs-r1r2.dtsi
Normal file
|
|
@ -0,0 +1,85 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/ {
|
||||
funnel@20130000 { /* cssys1 */
|
||||
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
|
||||
reg = <0 0x20130000 0 0x1000>;
|
||||
|
||||
clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
power-domains = <&scpi_devpd 0>;
|
||||
out-ports {
|
||||
port {
|
||||
csys1_funnel_out_port: endpoint {
|
||||
remote-endpoint = <&etf1_in_port>;
|
||||
};
|
||||
};
|
||||
};
|
||||
in-ports {
|
||||
port {
|
||||
csys1_funnel_in_port0: endpoint {
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
|
||||
etf@20140000 { /* etf1 */
|
||||
compatible = "arm,coresight-tmc", "arm,primecell";
|
||||
reg = <0 0x20140000 0 0x1000>;
|
||||
|
||||
clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
power-domains = <&scpi_devpd 0>;
|
||||
in-ports {
|
||||
port {
|
||||
etf1_in_port: endpoint {
|
||||
remote-endpoint = <&csys1_funnel_out_port>;
|
||||
};
|
||||
};
|
||||
};
|
||||
out-ports {
|
||||
port {
|
||||
etf1_out_port: endpoint {
|
||||
remote-endpoint = <&csys2_funnel_in_port1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
funnel@20150000 { /* cssys2 */
|
||||
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
|
||||
reg = <0 0x20150000 0 0x1000>;
|
||||
|
||||
clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
power-domains = <&scpi_devpd 0>;
|
||||
out-ports {
|
||||
port {
|
||||
csys2_funnel_out_port: endpoint {
|
||||
remote-endpoint = <&replicator_in_port0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
in-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
csys2_funnel_in_port0: endpoint {
|
||||
slave-mode;
|
||||
remote-endpoint = <&etf0_out_port>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
csys2_funnel_in_port1: endpoint {
|
||||
slave-mode;
|
||||
remote-endpoint = <&etf1_out_port>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
};
|
||||
303
arch/arm/dts/juno-motherboard.dtsi
Normal file
303
arch/arm/dts/juno-motherboard.dtsi
Normal file
|
|
@ -0,0 +1,303 @@
|
|||
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
|
||||
/*
|
||||
* ARM Juno Platform motherboard peripherals
|
||||
*
|
||||
* Copyright (c) 2013-2014 ARM Ltd
|
||||
*
|
||||
* This file is licensed under a dual GPLv2 or BSD license.
|
||||
*
|
||||
*/
|
||||
|
||||
/ {
|
||||
mb_clk24mhz: clk24mhz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24000000>;
|
||||
clock-output-names = "juno_mb:clk24mhz";
|
||||
};
|
||||
|
||||
mb_clk25mhz: clk25mhz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <25000000>;
|
||||
clock-output-names = "juno_mb:clk25mhz";
|
||||
};
|
||||
|
||||
v2m_refclk1mhz: refclk1mhz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <1000000>;
|
||||
clock-output-names = "juno_mb:refclk1mhz";
|
||||
};
|
||||
|
||||
v2m_refclk32khz: refclk32khz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
clock-output-names = "juno_mb:refclk32khz";
|
||||
};
|
||||
|
||||
mb_fixed_3v3: mcc-sb-3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "MCC_SB_3V3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
power-button {
|
||||
debounce-interval = <50>;
|
||||
wakeup-source;
|
||||
linux,code = <116>;
|
||||
label = "POWER";
|
||||
gpios = <&iofpga_gpio0 0 0x4>;
|
||||
};
|
||||
home-button {
|
||||
debounce-interval = <50>;
|
||||
wakeup-source;
|
||||
linux,code = <102>;
|
||||
label = "HOME";
|
||||
gpios = <&iofpga_gpio0 1 0x4>;
|
||||
};
|
||||
rlock-button {
|
||||
debounce-interval = <50>;
|
||||
wakeup-source;
|
||||
linux,code = <152>;
|
||||
label = "RLOCK";
|
||||
gpios = <&iofpga_gpio0 2 0x4>;
|
||||
};
|
||||
vol-up-button {
|
||||
debounce-interval = <50>;
|
||||
wakeup-source;
|
||||
linux,code = <115>;
|
||||
label = "VOL+";
|
||||
gpios = <&iofpga_gpio0 3 0x4>;
|
||||
};
|
||||
vol-down-button {
|
||||
debounce-interval = <50>;
|
||||
wakeup-source;
|
||||
linux,code = <114>;
|
||||
label = "VOL-";
|
||||
gpios = <&iofpga_gpio0 4 0x4>;
|
||||
};
|
||||
nmi-button {
|
||||
debounce-interval = <50>;
|
||||
wakeup-source;
|
||||
linux,code = <99>;
|
||||
label = "NMI";
|
||||
gpios = <&iofpga_gpio0 5 0x4>;
|
||||
};
|
||||
};
|
||||
|
||||
bus@8000000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x8000000 0 0x8000000 0x18000000>;
|
||||
|
||||
motherboard-bus@8000000 {
|
||||
compatible = "arm,vexpress,v2p-p1", "simple-bus";
|
||||
#address-cells = <2>; /* SMB chipselect number and offset */
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0 0x08000000 0x04000000>,
|
||||
<1 0 0 0x14000000 0x04000000>,
|
||||
<2 0 0 0x18000000 0x04000000>,
|
||||
<3 0 0 0x1c000000 0x04000000>,
|
||||
<4 0 0 0x0c000000 0x04000000>,
|
||||
<5 0 0 0x10000000 0x04000000>;
|
||||
arm,hbi = <0x252>;
|
||||
arm,vexpress,site = <0>;
|
||||
|
||||
flash@0 {
|
||||
/* 2 * 32MiB NOR Flash memory mounted on CS0 */
|
||||
compatible = "arm,vexpress-flash", "cfi-flash";
|
||||
reg = <0 0x00000000 0x04000000>;
|
||||
bank-width = <4>;
|
||||
/*
|
||||
* Unfortunately, accessing the flash disturbs
|
||||
* the CPU idle states (suspend) and CPU
|
||||
* hotplug of the platform. For this reason,
|
||||
* flash hardware access is disabled by default.
|
||||
*/
|
||||
status = "disabled";
|
||||
partitions {
|
||||
compatible = "arm,arm-firmware-suite";
|
||||
};
|
||||
};
|
||||
|
||||
ethernet@200000000 {
|
||||
compatible = "smsc,lan9118", "smsc,lan9115";
|
||||
reg = <2 0x00000000 0x10000>;
|
||||
interrupts = <3>;
|
||||
phy-mode = "mii";
|
||||
reg-io-width = <4>;
|
||||
smsc,irq-active-high;
|
||||
smsc,irq-push-pull;
|
||||
clocks = <&mb_clk25mhz>;
|
||||
vdd33a-supply = <&mb_fixed_3v3>;
|
||||
vddvario-supply = <&mb_fixed_3v3>;
|
||||
};
|
||||
|
||||
iofpga-bus@300000000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 3 0 0x200000>;
|
||||
|
||||
v2m_sysctl: sysctl@20000 {
|
||||
compatible = "arm,sp810", "arm,primecell";
|
||||
reg = <0x020000 0x1000>;
|
||||
clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&mb_clk24mhz>;
|
||||
clock-names = "refclk", "timclk", "apb_pclk";
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
|
||||
assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
|
||||
assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
|
||||
};
|
||||
|
||||
apbregs@10000 {
|
||||
compatible = "syscon", "simple-mfd";
|
||||
reg = <0x010000 0x1000>;
|
||||
|
||||
led0 {
|
||||
compatible = "register-bit-led";
|
||||
offset = <0x08>;
|
||||
mask = <0x01>;
|
||||
label = "vexpress:0";
|
||||
linux,default-trigger = "heartbeat";
|
||||
default-state = "on";
|
||||
};
|
||||
led1 {
|
||||
compatible = "register-bit-led";
|
||||
offset = <0x08>;
|
||||
mask = <0x02>;
|
||||
label = "vexpress:1";
|
||||
linux,default-trigger = "mmc0";
|
||||
default-state = "off";
|
||||
};
|
||||
led2 {
|
||||
compatible = "register-bit-led";
|
||||
offset = <0x08>;
|
||||
mask = <0x04>;
|
||||
label = "vexpress:2";
|
||||
linux,default-trigger = "cpu0";
|
||||
default-state = "off";
|
||||
};
|
||||
led3 {
|
||||
compatible = "register-bit-led";
|
||||
offset = <0x08>;
|
||||
mask = <0x08>;
|
||||
label = "vexpress:3";
|
||||
linux,default-trigger = "cpu1";
|
||||
default-state = "off";
|
||||
};
|
||||
led4 {
|
||||
compatible = "register-bit-led";
|
||||
offset = <0x08>;
|
||||
mask = <0x10>;
|
||||
label = "vexpress:4";
|
||||
linux,default-trigger = "cpu2";
|
||||
default-state = "off";
|
||||
};
|
||||
led5 {
|
||||
compatible = "register-bit-led";
|
||||
offset = <0x08>;
|
||||
mask = <0x20>;
|
||||
label = "vexpress:5";
|
||||
linux,default-trigger = "cpu3";
|
||||
default-state = "off";
|
||||
};
|
||||
led6 {
|
||||
compatible = "register-bit-led";
|
||||
offset = <0x08>;
|
||||
mask = <0x40>;
|
||||
label = "vexpress:6";
|
||||
default-state = "off";
|
||||
};
|
||||
led7 {
|
||||
compatible = "register-bit-led";
|
||||
offset = <0x08>;
|
||||
mask = <0x80>;
|
||||
label = "vexpress:7";
|
||||
default-state = "off";
|
||||
};
|
||||
};
|
||||
|
||||
mmc@50000 {
|
||||
compatible = "arm,pl180", "arm,primecell";
|
||||
reg = <0x050000 0x1000>;
|
||||
interrupts = <5>;
|
||||
/* cd-gpios = <&v2m_mmc_gpios 0 0>;
|
||||
wp-gpios = <&v2m_mmc_gpios 1 0>; */
|
||||
max-frequency = <12000000>;
|
||||
vmmc-supply = <&mb_fixed_3v3>;
|
||||
clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
|
||||
clock-names = "mclk", "apb_pclk";
|
||||
};
|
||||
|
||||
kmi@60000 {
|
||||
compatible = "arm,pl050", "arm,primecell";
|
||||
reg = <0x060000 0x1000>;
|
||||
interrupts = <8>;
|
||||
clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
|
||||
clock-names = "KMIREFCLK", "apb_pclk";
|
||||
};
|
||||
|
||||
kmi@70000 {
|
||||
compatible = "arm,pl050", "arm,primecell";
|
||||
reg = <0x070000 0x1000>;
|
||||
interrupts = <8>;
|
||||
clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
|
||||
clock-names = "KMIREFCLK", "apb_pclk";
|
||||
};
|
||||
|
||||
watchdog@f0000 {
|
||||
compatible = "arm,sp805", "arm,primecell";
|
||||
reg = <0x0f0000 0x10000>;
|
||||
interrupts = <7>;
|
||||
clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
|
||||
clock-names = "wdog_clk", "apb_pclk";
|
||||
};
|
||||
|
||||
v2m_timer01: timer@110000 {
|
||||
compatible = "arm,sp804", "arm,primecell";
|
||||
reg = <0x110000 0x10000>;
|
||||
interrupts = <9>;
|
||||
clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&mb_clk24mhz>;
|
||||
clock-names = "timclken1", "timclken2", "apb_pclk";
|
||||
};
|
||||
|
||||
v2m_timer23: timer@120000 {
|
||||
compatible = "arm,sp804", "arm,primecell";
|
||||
reg = <0x120000 0x10000>;
|
||||
interrupts = <9>;
|
||||
clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&mb_clk24mhz>;
|
||||
clock-names = "timclken1", "timclken2", "apb_pclk";
|
||||
};
|
||||
|
||||
rtc@170000 {
|
||||
compatible = "arm,pl031", "arm,primecell";
|
||||
reg = <0x170000 0x10000>;
|
||||
interrupts = <0>;
|
||||
clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
iofpga_gpio0: gpio@1d0000 {
|
||||
compatible = "arm,pl061", "arm,primecell";
|
||||
reg = <0x1d0000 0x1000>;
|
||||
interrupts = <6>;
|
||||
clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
20
arch/arm/dts/juno-r2-u-boot.dtsi
Normal file
20
arch/arm/dts/juno-r2-u-boot.dtsi
Normal file
|
|
@ -0,0 +1,20 @@
|
|||
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
|
||||
/*
|
||||
* ARM Juno Platform additions for U-Boot
|
||||
*/
|
||||
|
||||
/ {
|
||||
bus@8000000 {
|
||||
motherboard-bus@8000000 {
|
||||
/*
|
||||
* This should not be marked "disabled" in U-Boot. The
|
||||
* boot loader is not using some CPU idle states and
|
||||
* hotplug but may be very interested in accessing the
|
||||
* flash.
|
||||
*/
|
||||
flash@0 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
322
arch/arm/dts/juno-r2.dts
Normal file
322
arch/arm/dts/juno-r2.dts
Normal file
|
|
@ -0,0 +1,322 @@
|
|||
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
|
||||
/*
|
||||
* ARM Ltd. Juno Platform
|
||||
*
|
||||
* Copyright (c) 2015 ARM Ltd.
|
||||
*
|
||||
* This file is licensed under a dual GPLv2 or BSD license.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include "juno-base.dtsi"
|
||||
#include "juno-cs-r1r2.dtsi"
|
||||
|
||||
/ {
|
||||
model = "ARM Juno development board (r2)";
|
||||
compatible = "arm,juno-r2", "arm,juno", "arm,vexpress";
|
||||
interrupt-parent = <&gic>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
aliases {
|
||||
serial0 = &soc_uart0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-0.2";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu-map {
|
||||
cluster0 {
|
||||
core0 {
|
||||
cpu = <&A72_0>;
|
||||
};
|
||||
core1 {
|
||||
cpu = <&A72_1>;
|
||||
};
|
||||
};
|
||||
|
||||
cluster1 {
|
||||
core0 {
|
||||
cpu = <&A53_0>;
|
||||
};
|
||||
core1 {
|
||||
cpu = <&A53_1>;
|
||||
};
|
||||
core2 {
|
||||
cpu = <&A53_2>;
|
||||
};
|
||||
core3 {
|
||||
cpu = <&A53_3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
idle-states {
|
||||
entry-method = "psci";
|
||||
|
||||
CPU_SLEEP_0: cpu-sleep-0 {
|
||||
compatible = "arm,idle-state";
|
||||
arm,psci-suspend-param = <0x0010000>;
|
||||
local-timer-stop;
|
||||
entry-latency-us = <300>;
|
||||
exit-latency-us = <1200>;
|
||||
min-residency-us = <2000>;
|
||||
};
|
||||
|
||||
CLUSTER_SLEEP_0: cluster-sleep-0 {
|
||||
compatible = "arm,idle-state";
|
||||
arm,psci-suspend-param = <0x1010000>;
|
||||
local-timer-stop;
|
||||
entry-latency-us = <400>;
|
||||
exit-latency-us = <1200>;
|
||||
min-residency-us = <2500>;
|
||||
};
|
||||
};
|
||||
|
||||
A72_0: cpu@0 {
|
||||
compatible = "arm,cortex-a72";
|
||||
reg = <0x0 0x0>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0xc000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&A72_L2>;
|
||||
clocks = <&scpi_dvfs 0>;
|
||||
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
dynamic-power-coefficient = <450>;
|
||||
};
|
||||
|
||||
A72_1: cpu@1 {
|
||||
compatible = "arm,cortex-a72";
|
||||
reg = <0x0 0x1>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0xc000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&A72_L2>;
|
||||
clocks = <&scpi_dvfs 0>;
|
||||
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
dynamic-power-coefficient = <450>;
|
||||
};
|
||||
|
||||
A53_0: cpu@100 {
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x0 0x100>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0x8000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&A53_L2>;
|
||||
clocks = <&scpi_dvfs 1>;
|
||||
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||
capacity-dmips-mhz = <485>;
|
||||
dynamic-power-coefficient = <140>;
|
||||
};
|
||||
|
||||
A53_1: cpu@101 {
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x0 0x101>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0x8000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&A53_L2>;
|
||||
clocks = <&scpi_dvfs 1>;
|
||||
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||
capacity-dmips-mhz = <485>;
|
||||
dynamic-power-coefficient = <140>;
|
||||
};
|
||||
|
||||
A53_2: cpu@102 {
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x0 0x102>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0x8000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&A53_L2>;
|
||||
clocks = <&scpi_dvfs 1>;
|
||||
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||
capacity-dmips-mhz = <485>;
|
||||
dynamic-power-coefficient = <140>;
|
||||
};
|
||||
|
||||
A53_3: cpu@103 {
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x0 0x103>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0x8000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&A53_L2>;
|
||||
clocks = <&scpi_dvfs 1>;
|
||||
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||
capacity-dmips-mhz = <485>;
|
||||
dynamic-power-coefficient = <140>;
|
||||
};
|
||||
|
||||
A72_L2: l2-cache0 {
|
||||
compatible = "cache";
|
||||
cache-size = <0x200000>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <2048>;
|
||||
};
|
||||
|
||||
A53_L2: l2-cache1 {
|
||||
compatible = "cache";
|
||||
cache-size = <0x100000>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <1024>;
|
||||
};
|
||||
};
|
||||
|
||||
pmu-a72 {
|
||||
compatible = "arm,cortex-a72-pmu";
|
||||
interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-affinity = <&A72_0>,
|
||||
<&A72_1>;
|
||||
};
|
||||
|
||||
pmu-a53 {
|
||||
compatible = "arm,cortex-a53-pmu";
|
||||
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-affinity = <&A53_0>,
|
||||
<&A53_1>,
|
||||
<&A53_2>,
|
||||
<&A53_3>;
|
||||
};
|
||||
};
|
||||
|
||||
&memtimer {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie_ctlr {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&smmu_pcie {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&etm0 {
|
||||
cpu = <&A72_0>;
|
||||
};
|
||||
|
||||
&etm1 {
|
||||
cpu = <&A72_1>;
|
||||
};
|
||||
|
||||
&etm2 {
|
||||
cpu = <&A53_0>;
|
||||
};
|
||||
|
||||
&etm3 {
|
||||
cpu = <&A53_1>;
|
||||
};
|
||||
|
||||
&etm4 {
|
||||
cpu = <&A53_2>;
|
||||
};
|
||||
|
||||
&etm5 {
|
||||
cpu = <&A53_3>;
|
||||
};
|
||||
|
||||
&big_cluster_thermal_zone {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&little_cluster_thermal_zone {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpu0_thermal_zone {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpu1_thermal_zone {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&etf0_out_port {
|
||||
remote-endpoint = <&csys2_funnel_in_port0>;
|
||||
};
|
||||
|
||||
&replicator_in_port0 {
|
||||
remote-endpoint = <&csys2_funnel_out_port>;
|
||||
};
|
||||
|
||||
&csys1_funnel_in_port0 {
|
||||
remote-endpoint = <&stm_out_port>;
|
||||
};
|
||||
|
||||
&stm_out_port {
|
||||
remote-endpoint = <&csys1_funnel_in_port0>;
|
||||
};
|
||||
|
||||
&cpu_debug0 {
|
||||
cpu = <&A72_0>;
|
||||
};
|
||||
|
||||
&cpu_debug1 {
|
||||
cpu = <&A72_1>;
|
||||
};
|
||||
|
||||
&cpu_debug2 {
|
||||
cpu = <&A53_0>;
|
||||
};
|
||||
|
||||
&cpu_debug3 {
|
||||
cpu = <&A53_1>;
|
||||
};
|
||||
|
||||
&cpu_debug4 {
|
||||
cpu = <&A53_2>;
|
||||
};
|
||||
|
||||
&cpu_debug5 {
|
||||
cpu = <&A53_3>;
|
||||
};
|
||||
|
|
@ -8,6 +8,7 @@ CONFIG_SYS_MEMTEST_START=0x80000000
|
|||
CONFIG_SYS_MEMTEST_END=0xff000000
|
||||
CONFIG_ENV_SIZE=0x10000
|
||||
CONFIG_ENV_SECT_SIZE=0x10000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="juno-r2"
|
||||
CONFIG_IDENT_STRING=" vexpress_aemv8a"
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_SYS_LOAD_ADDR=0x90000000
|
||||
|
|
|
|||
Loading…
Reference in a new issue