From 2645bc0e12f831377884433a11f1607106edb0e7 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Fri, 22 Apr 2022 14:34:18 -0400 Subject: [PATCH 01/26] arm: layerscape: Add sfp driver This adds a driver for the Security Fuse Processor (SFP) present on LS1012A, LS1021A, LS1043A, and LS1046A processors. It holds the Super-Root Key (SRK), One-Time-Programmable Master Key (OTPMK), and other "security" related fuses. Similar devices (sharing the same name) are present on other processors, but for the moment this just supports the LS2 variants. The mirror registers are loaded during power-on reset. All mirror registers must be programmed or read at once. Because of this, `fuse prog` will program all fuses, even though only one might be specified. To prevent accidentally burning through all your fuse programming cycles with something like `fuse prog 0 0 A B C D`, we limit ourselves to one programming cycle per reset. Fuses are numbered based on their address. The fuse at 0x1e80200 is 0, the fuse at 0x1e80204 is 1, etc. The TA_PROG_SFP supply must be enabled when programming fuses, but must be disabled when reading them. Typically this supply is enabled by inserting a jumper or by setting a register in the board's FPGA. I've also added support for using a regulator. This could be helpful for automatically issuing the FPGA write, or for toggling a GPIO controlling the supply. I suggest using the following procedure for programming: 1. Override the fuses you wish to program => fuse override 0 2 A B C D 2. Inspect the values and ensure that they are what you expect => fuse sense 0 2 4 3. Enable TA_PROG_SFP 4. Issue a program command using OSPR0 as a dummy. Since it contains the write-protect bit you will usually want to write it last anyway. => fuse prog 0 0 0 5. Disable TA_PROG_SFP 6. Read back the fuses and ensure they are correct => fuse read 0 2 4 Signed-off-by: Sean Anderson --- MAINTAINERS | 5 + drivers/misc/Kconfig | 14 ++ drivers/misc/Makefile | 1 + drivers/misc/ls2_sfp.c | 350 +++++++++++++++++++++++++++++++++++++++++ 4 files changed, 370 insertions(+) create mode 100644 drivers/misc/ls2_sfp.c diff --git a/MAINTAINERS b/MAINTAINERS index 1ba36b62cc..5912980614 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -293,6 +293,11 @@ F: drivers/spi/spi-qup.c F: drivers/net/mdio-ipq4019.c F: drivers/rng/msm_rng.c +ARM LAYERSCAPE SFP +M: Sean Anderson +S: Maintained +F: drivers/misc/ls2_sfp.c + ARM MARVELL KIRKWOOD ARMADA-XP ARMADA-38X ARMADA-37XX ARMADA-7K/8K M: Stefan Roese S: Maintained diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index f368d52c56..31b10f989c 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -289,6 +289,20 @@ config JZ4780_EFUSE help This selects support for the eFUSE on Ingenic JZ4780 SoCs. +config LS2_SFP + bool "Layerscape Security Fuse Processor" + depends on FSL_LSCH2 || ARCH_LS1021A + depends on MISC + imply DM_REGULATOR + help + This adds support for the Security Fuse Processor found on Layerscape + SoCs. It contains various fuses related to secure boot, including the + Super Root Key hash, One-Time-Programmable Master Key, Debug + Challenge/Response values, and others. Fuses are numbered according + to their four-byte offset from the start of the bank. + + If you don't need to read/program fuses, say 'n'. + config MXC_OCOTP bool "Enable MXC OCOTP Driver" depends on ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610 diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 6c79030893..7d15e9f1f6 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -52,6 +52,7 @@ obj-$(CONFIG_IMX8ULP) += imx8ulp/ obj-$(CONFIG_LED_STATUS) += status_led.o obj-$(CONFIG_LED_STATUS_GPIO) += gpio_led.o obj-$(CONFIG_MPC83XX_SERDES) += mpc83xx_serdes.o +obj-$(CONFIG_$(SPL_TPL_)LS2_SFP) += ls2_sfp.o obj-$(CONFIG_$(SPL_)MXC_OCOTP) += mxc_ocotp.o obj-$(CONFIG_MXS_OCOTP) += mxs_ocotp.o obj-$(CONFIG_NUVOTON_NCT6102D) += nuvoton_nct6102d.o diff --git a/drivers/misc/ls2_sfp.c b/drivers/misc/ls2_sfp.c new file mode 100644 index 0000000000..dd104962c2 --- /dev/null +++ b/drivers/misc/ls2_sfp.c @@ -0,0 +1,350 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 Sean Anderson + * + * This driver supports the Security Fuse Processor device found on some + * Layerscape processors. At the moment, we only support a few processors. + * This driver was written with reference to the Layerscape SDK User + * Guide [1] and the ATF SFP driver [2]. + * + * [1] https://docs.nxp.com/bundle/GUID-487B2E69-BB19-42CB-AC38-7EF18C0FE3AE/page/GUID-27FC40AD-3321-4A82-B29E-7BB49EE94F23.html + * [2] https://source.codeaurora.org/external/qoriq/qoriq-components/atf/tree/drivers/nxp/sfp?h=github.com/master + */ + +#define LOG_CATEGORY UCLASS_MISC +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define SFP_INGR 0x20 +#define SFP_SVHESR 0x24 +#define SFP_SFPCR 0x28 + +#define SFP_START 0x200 +#define SFP_END 0x284 +#define SFP_SIZE (SFP_END - SFP_START + 4) + +#define SFP_INGR_ERR BIT(8) +#define SFP_INGR_INST GENMASK(7, 0) + +#define SFP_INGR_READFB 0x01 +#define SFP_INGR_PROGFB 0x02 + +#define SFP_SFPCR_PPW GENMASK(15, 0) + +enum ls2_sfp_ioctl { + LS2_SFP_IOCTL_READ, + LS2_SFP_IOCTL_PROG, +}; + +/** + * struct ls2_sfp_priv - private data for LS2 SFP + * @base: Base address of SFP + * @supply: The (optional) supply for TA_PROG_SFP + * @programmed: Whether we've already programmed the fuses since the last + * reset. The SFP has a *very* limited amount of programming + * cycles (two to six, depending on the model), so we try and + * prevent accidentally performing additional programming + * cycles. + * @dirty: Whether the mirror registers have been written to (overridden) + * since we've last read the fuses (either as part of the reset + * process or using a READFB instruction). There is a much larger, + * but still finite, limit on the number of SFP read cycles (around + * 300,000), so we try and minimize reads as well. + */ +struct ls2_sfp_priv { + void __iomem *base; + struct udevice *supply; + bool programmed, dirty; +}; + +static u32 ls2_sfp_readl(struct ls2_sfp_priv *priv, ulong off) +{ + u32 val = be32_to_cpu(readl(priv->base + off)); + + log_debug("%08x = readl(%p)\n", val, priv->base + off); + return val; +} + +static void ls2_sfp_writel(struct ls2_sfp_priv *priv, ulong val, ulong off) +{ + log_debug("writel(%08lx, %p)\n", val, priv->base + off); + writel(cpu_to_be32(val), priv->base + off); +} + +static bool ls2_sfp_validate(struct udevice *dev, int offset, int size) +{ + if (offset < 0 || size < 0) { + dev_notice(dev, "size and offset must be positive\n"); + return false; + } + + if (offset & 3 || size & 3) { + dev_notice(dev, "size and offset must be multiples of 4\n"); + return false; + } + + if (offset + size > SFP_SIZE) { + dev_notice(dev, "size + offset must be <= %#x\n", SFP_SIZE); + return false; + } + + return true; +} + +static int ls2_sfp_read(struct udevice *dev, int offset, void *buf_bytes, + int size) +{ + int i; + struct ls2_sfp_priv *priv = dev_get_priv(dev); + u32 *buf = buf_bytes; + + if (!ls2_sfp_validate(dev, offset, size)) + return -EINVAL; + + for (i = 0; i < size; i += 4) + buf[i >> 2] = ls2_sfp_readl(priv, SFP_START + offset + i); + + return size; +} + +static int ls2_sfp_write(struct udevice *dev, int offset, + const void *buf_bytes, int size) +{ + int i; + struct ls2_sfp_priv *priv = dev_get_priv(dev); + const u32 *buf = buf_bytes; + + if (!ls2_sfp_validate(dev, offset, size)) + return -EINVAL; + + for (i = 0; i < size; i += 4) + ls2_sfp_writel(priv, buf[i >> 2], SFP_START + offset + i); + + priv->dirty = true; + return size; +} + +static int ls2_sfp_check_secret(struct udevice *dev) +{ + struct ls2_sfp_priv *priv = dev_get_priv(dev); + u32 svhesr = ls2_sfp_readl(priv, SFP_SVHESR); + + if (svhesr) { + dev_warn(dev, "secret value hamming error not zero: %08x\n", + svhesr); + return -EIO; + } + return 0; +} + +static int ls2_sfp_transaction(struct ls2_sfp_priv *priv, ulong inst) +{ + u32 ingr; + + ls2_sfp_writel(priv, inst, SFP_INGR); + + do { + ingr = ls2_sfp_readl(priv, SFP_INGR); + } while (FIELD_GET(SFP_INGR_INST, ingr)); + + return FIELD_GET(SFP_INGR_ERR, ingr) ? -EIO : 0; +} + +static int ls2_sfp_ioctl(struct udevice *dev, unsigned long request, void *buf) +{ + int ret; + struct ls2_sfp_priv *priv = dev_get_priv(dev); + + switch (request) { + case LS2_SFP_IOCTL_READ: + if (!priv->dirty) { + dev_dbg(dev, "ignoring read request, since fuses are not dirty\n"); + return 0; + } + + ret = ls2_sfp_transaction(priv, SFP_INGR_READFB); + if (ret) { + dev_err(dev, "error reading fuses\n"); + return ret; + } + + ls2_sfp_check_secret(dev); + priv->dirty = false; + return 0; + case LS2_SFP_IOCTL_PROG: + if (priv->programmed) { + dev_warn(dev, "fuses already programmed\n"); + return -EPERM; + } + + ret = ls2_sfp_check_secret(dev); + if (ret) + return ret; + + if (priv->supply) { + ret = regulator_set_enable(priv->supply, true); + if (ret) + return ret; + } + + ret = ls2_sfp_transaction(priv, SFP_INGR_PROGFB); + priv->programmed = true; + if (priv->supply) + regulator_set_enable(priv->supply, false); + + if (ret) + dev_err(dev, "error programming fuses\n"); + return ret; + default: + dev_dbg(dev, "unknown ioctl %lu\n", request); + return -EINVAL; + } +} + +static const struct misc_ops ls2_sfp_ops = { + .read = ls2_sfp_read, + .write = ls2_sfp_write, + .ioctl = ls2_sfp_ioctl, +}; + +static int ls2_sfp_probe(struct udevice *dev) +{ + int ret; + struct clk clk; + struct ls2_sfp_priv *priv = dev_get_priv(dev); + ulong rate; + + priv->base = dev_read_addr_ptr(dev); + if (!priv->base) { + dev_dbg(dev, "could not read register base\n"); + return -EINVAL; + } + + ret = device_get_supply_regulator(dev, "ta-sfp-prog", &priv->supply); + if (ret && ret != -ENODEV && ret != -ENOSYS) { + dev_dbg(dev, "problem getting supply (err %d)\n", ret); + return ret; + } + + ret = clk_get_by_name(dev, "sfp", &clk); + if (ret == -ENOSYS) { + rate = gd->bus_clk / 4; + } else if (ret) { + dev_dbg(dev, "could not get clock (err %d)\n", ret); + return ret; + } else { + ret = clk_enable(&clk); + if (ret) { + dev_dbg(dev, "could not enable clock (err %d)\n", ret); + return ret; + } + + rate = clk_get_rate(&clk); + clk_free(&clk); + if (!rate || IS_ERR_VALUE(rate)) { + ret = rate ? rate : -ENOENT; + dev_dbg(dev, "could not get clock rate (err %d)\n", + ret); + return ret; + } + } + + /* sfp clock in MHz * 12 */ + ls2_sfp_writel(priv, FIELD_PREP(SFP_SFPCR_PPW, rate * 12 / 1000000), + SFP_SFPCR); + + ls2_sfp_check_secret(dev); + return 0; +} + +static const struct udevice_id ls2_sfp_ids[] = { + { .compatible = "fsl,ls1021a-sfp" }, + { } +}; + +U_BOOT_DRIVER(ls2_sfp) = { + .name = "ls2_sfp", + .id = UCLASS_MISC, + .of_match = ls2_sfp_ids, + .probe = ls2_sfp_probe, + .ops = &ls2_sfp_ops, + .priv_auto = sizeof(struct ls2_sfp_priv), +}; + +static int ls2_sfp_device(struct udevice **dev) +{ + int ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_DRIVER_GET(ls2_sfp), dev); + + if (ret) + log_debug("device not found (err %d)\n", ret); + return ret; +} + +int fuse_read(u32 bank, u32 word, u32 *val) +{ + int ret; + struct udevice *dev; + + ret = ls2_sfp_device(&dev); + if (ret) + return ret; + + ret = misc_ioctl(dev, LS2_SFP_IOCTL_READ, NULL); + if (ret) + return ret; + + ret = misc_read(dev, word << 2, val, sizeof(*val)); + return ret < 0 ? ret : 0; +} + +int fuse_sense(u32 bank, u32 word, u32 *val) +{ + int ret; + struct udevice *dev; + + ret = ls2_sfp_device(&dev); + if (ret) + return ret; + + ret = misc_read(dev, word << 2, val, sizeof(*val)); + return ret < 0 ? ret : 0; +} + +int fuse_prog(u32 bank, u32 word, u32 val) +{ + int ret; + struct udevice *dev; + + ret = ls2_sfp_device(&dev); + if (ret) + return ret; + + ret = misc_write(dev, word << 2, &val, sizeof(val)); + if (ret < 0) + return ret; + + return misc_ioctl(dev, LS2_SFP_IOCTL_PROG, NULL); +} + +int fuse_override(u32 bank, u32 word, u32 val) +{ + int ret; + struct udevice *dev; + + ret = ls2_sfp_device(&dev); + if (ret) + return ret; + + ret = misc_write(dev, word << 2, &val, sizeof(val)); + return ret < 0 ? ret : 0; +} From f99068a8b11f0ba33b5802754d8de183f3ca2b1d Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Fri, 22 Apr 2022 14:34:19 -0400 Subject: [PATCH 02/26] ARM: dts: ls1021a: update the clockgen node QorIQ platforms now use different clock bindings. Although we don't use the device tree for clocks on this platform, it is helpful to sync it because then the bindings will more closely match Linux. Additionally, it allows for using more clock fractions (such as platform/4). This corresponds to Linux commit b6f5e7019391 ("ARM: dts: ls1021a: update the clockgen node"). Signed-off-by: Sean Anderson --- arch/arm/dts/ls1021a.dtsi | 80 ++++++++++++++------------------------- 1 file changed, 28 insertions(+), 52 deletions(-) diff --git a/arch/arm/dts/ls1021a.dtsi b/arch/arm/dts/ls1021a.dtsi index be330c130f..063655f7ac 100644 --- a/arch/arm/dts/ls1021a.dtsi +++ b/arch/arm/dts/ls1021a.dtsi @@ -31,17 +31,24 @@ compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <0xf00>; - clocks = <&cluster1_clk>; + clocks = <&clockgen 1 0>; }; cpu@f01 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <0xf01>; - clocks = <&cluster1_clk>; + clocks = <&clockgen 1 0>; }; }; + sysclk: sysclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "sysclk"; + }; + timer { compatible = "arm,armv7-timer"; interrupts = , @@ -185,41 +192,10 @@ }; clockgen: clocking@1ee1000 { - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x1ee1000 0x10000>; - - sysclk: sysclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-output-names = "sysclk"; - }; - - cga_pll1: pll@800 { - compatible = "fsl,qoriq-core-pll-2.0"; - #clock-cells = <1>; - reg = <0x800 0x10>; - clocks = <&sysclk>; - clock-output-names = "cga-pll1", "cga-pll1-div2", - "cga-pll1-div4"; - }; - - platform_clk: pll@c00 { - compatible = "fsl,qoriq-core-pll-2.0"; - #clock-cells = <1>; - reg = <0xc00 0x10>; - clocks = <&sysclk>; - clock-output-names = "platform-clk", "platform-clk-div2"; - }; - - cluster1_clk: clk0c0@0 { - compatible = "fsl,qoriq-core-mux-2.0"; - #clock-cells = <0>; - reg = <0x0 0x10>; - clock-names = "pll1cga", "pll1cga-div2", "pll1cga-div4"; - clocks = <&cga_pll1 0>, <&cga_pll1 1>, <&cga_pll1 2>; - clock-output-names = "cluster1-clk"; - }; + compatible = "fsl,ls1021a-clockgen"; + reg = <0x0 0x1ee1000 0x0 0x1000>; + #clock-cells = <2>; + clocks = <&sysclk>; }; dspi0: dspi@2100000 { @@ -229,7 +205,7 @@ reg = <0x2100000 0x10000>; interrupts = ; clock-names = "dspi"; - clocks = <&platform_clk 1>; + clocks = <&clockgen 4 1>; spi-num-chipselects = <6>; big-endian; status = "disabled"; @@ -242,7 +218,7 @@ reg = <0x2110000 0x10000>; interrupts = ; clock-names = "dspi"; - clocks = <&platform_clk 1>; + clocks = <&clockgen 4 1>; spi-num-chipselects = <6>; big-endian; status = "disabled"; @@ -265,7 +241,7 @@ reg = <0x2180000 0x10000>; interrupts = ; clock-names = "i2c"; - clocks = <&platform_clk 1>; + clocks = <&clockgen 4 1>; status = "disabled"; }; @@ -276,7 +252,7 @@ reg = <0x2190000 0x10000>; interrupts = ; clock-names = "i2c"; - clocks = <&platform_clk 1>; + clocks = <&clockgen 4 1>; status = "disabled"; }; @@ -287,7 +263,7 @@ reg = <0x21a0000 0x10000>; interrupts = ; clock-names = "i2c"; - clocks = <&platform_clk 1>; + clocks = <&clockgen 4 1>; status = "disabled"; }; @@ -336,7 +312,7 @@ compatible = "fsl,ls1021a-lpuart"; reg = <0x2960000 0x1000>; interrupts = ; - clocks = <&platform_clk 1>; + clocks = <&clockgen 4 1>; clock-names = "ipg"; status = "disabled"; }; @@ -345,7 +321,7 @@ compatible = "fsl,ls1021a-lpuart"; reg = <0x2970000 0x1000>; interrupts = ; - clocks = <&platform_clk 1>; + clocks = <&clockgen 4 1>; clock-names = "ipg"; status = "disabled"; }; @@ -354,7 +330,7 @@ compatible = "fsl,ls1021a-lpuart"; reg = <0x2980000 0x1000>; interrupts = ; - clocks = <&platform_clk 1>; + clocks = <&clockgen 4 1>; clock-names = "ipg"; status = "disabled"; }; @@ -363,7 +339,7 @@ compatible = "fsl,ls1021a-lpuart"; reg = <0x2990000 0x1000>; interrupts = ; - clocks = <&platform_clk 1>; + clocks = <&clockgen 4 1>; clock-names = "ipg"; status = "disabled"; }; @@ -372,7 +348,7 @@ compatible = "fsl,ls1021a-lpuart"; reg = <0x29a0000 0x1000>; interrupts = ; - clocks = <&platform_clk 1>; + clocks = <&clockgen 4 1>; clock-names = "ipg"; status = "disabled"; }; @@ -381,7 +357,7 @@ compatible = "fsl,imx21-wdt"; reg = <0x2ad0000 0x10000>; interrupts = ; - clocks = <&platform_clk 1>; + clocks = <&clockgen 4 1>; clock-names = "wdog-en"; big-endian; }; @@ -390,7 +366,7 @@ compatible = "fsl,vf610-sai"; reg = <0x2b50000 0x10000>; interrupts = ; - clocks = <&platform_clk 1>; + clocks = <&clockgen 4 1>; clock-names = "sai"; dma-names = "tx", "rx"; dmas = <&edma0 1 47>, @@ -403,7 +379,7 @@ compatible = "fsl,vf610-sai"; reg = <0x2b60000 0x10000>; interrupts = ; - clocks = <&platform_clk 1>; + clocks = <&clockgen 4 1>; clock-names = "sai"; dma-names = "tx", "rx"; dmas = <&edma0 1 45>, @@ -424,8 +400,8 @@ dma-channels = <32>; big-endian; clock-names = "dmamux0", "dmamux1"; - clocks = <&platform_clk 1>, - <&platform_clk 1>; + clocks = <&clockgen 4 1>, + <&clockgen 4 1>; }; enet0: ethernet@2d10000 { From 7041601141447105249fdb71166a7abaee6fa378 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Fri, 22 Apr 2022 14:34:20 -0400 Subject: [PATCH 03/26] arch: layerscape: Add SFP binding This adds an SFP binding for the processors it is present on. I have only tested this for the LS1046A. Signed-off-by: Sean Anderson --- arch/arm/dts/fsl-ls1012a.dtsi | 7 +++++++ arch/arm/dts/fsl-ls1043a.dtsi | 7 +++++++ arch/arm/dts/fsl-ls1046a.dtsi | 7 +++++++ arch/arm/dts/ls1021a.dtsi | 7 +++++++ 4 files changed, 28 insertions(+) diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi index 1cdcc99c1e..796d72fc9e 100644 --- a/arch/arm/dts/fsl-ls1012a.dtsi +++ b/arch/arm/dts/fsl-ls1012a.dtsi @@ -34,6 +34,13 @@ #size-cells = <2>; ranges; + sfp: efuse@1e80000 { + compatible = "fsl,ls1021a-sfp"; + reg = <0x0 0x1e80000 0x0 0x1000>; + clocks = <&clockgen 4 3>; + clock-names = "sfp"; + }; + clockgen: clocking@1ee1000 { compatible = "fsl,ls1012a-clockgen"; reg = <0x0 0x1ee1000 0x0 0x1000>; diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi index 72877d2ff5..4960973a60 100644 --- a/arch/arm/dts/fsl-ls1043a.dtsi +++ b/arch/arm/dts/fsl-ls1043a.dtsi @@ -38,6 +38,13 @@ #size-cells = <2>; ranges; + sfp: efuse@1e80000 { + compatible = "fsl,ls1021a-sfp"; + reg = <0x0 0x1e80000 0x0 0x1000>; + clocks = <&clockgen 4 3>; + clock-names = "sfp"; + }; + clockgen: clocking@1ee1000 { compatible = "fsl,ls1043a-clockgen"; reg = <0x0 0x1ee1000 0x0 0x1000>; diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi index c655e002aa..060dc399c2 100644 --- a/arch/arm/dts/fsl-ls1046a.dtsi +++ b/arch/arm/dts/fsl-ls1046a.dtsi @@ -38,6 +38,13 @@ #size-cells = <2>; ranges; + sfp: efuse@1e80000 { + compatible = "fsl,ls1021a-sfp"; + reg = <0x0 0x1e80000 0x0 0x1000>; + clocks = <&clockgen 4 3>; + clock-names = "sfp"; + }; + clockgen: clocking@1ee1000 { compatible = "fsl,ls1046a-clockgen"; reg = <0x0 0x1ee1000 0x0 0x1000>; diff --git a/arch/arm/dts/ls1021a.dtsi b/arch/arm/dts/ls1021a.dtsi index 063655f7ac..4f65ee765e 100644 --- a/arch/arm/dts/ls1021a.dtsi +++ b/arch/arm/dts/ls1021a.dtsi @@ -89,6 +89,13 @@ interrupts = ; }; + sfp: efuse@1e80000 { + compatible = "fsl,ls1021a-sfp"; + reg = <0x0 0x1e80000 0x0 0x10000>; + clocks = <&clockgen 4 3>; + clock-names = "sfp"; + }; + dcfg: dcfg@1ee0000 { compatible = "fsl,ls1021a-dcfg", "syscon"; reg = <0x1ee0000 0x10000>; From bcb3dae32517a384138a953521436b37512fdd1c Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Tue, 26 Apr 2022 14:31:49 -0400 Subject: [PATCH 04/26] ARM: layerscape: Use ARCH_LS104?A insead of TARGET_LS104?ARDB These frequency calculations depend on the RCW format, which is not dependent on any particular board. Switch to using ARCH symbols instead of TARGET. This whole function could probably use less ifdefs, but for now just do a minimal conversion. Fixes: 24cb6f2295 ("fsl-layerscape: Add fsl_esdhc peripheral clock support") Signed-off-by: Sean Anderson --- arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c index 570105a75e..840e6d412b 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c @@ -29,8 +29,8 @@ void get_sys_info(struct sys_info *sys_info) * mux 2 clock for LS1043A/LS1046A. */ #if defined(CONFIG_SYS_DPAA_FMAN) || \ - defined(CONFIG_TARGET_LS1046ARDB) || \ - defined(CONFIG_TARGET_LS1043ARDB) + defined(CONFIG_ARCH_LS1046A) || \ + defined(CONFIG_ARCH_LS1043A) u32 rcw_tmp; #endif struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR); @@ -129,13 +129,13 @@ void get_sys_info(struct sys_info *sys_info) #define HWA_CGA_M2_CLK_SEL 0x00000007 #define HWA_CGA_M2_CLK_SHIFT 0 -#if defined(CONFIG_TARGET_LS1046ARDB) || defined(CONFIG_TARGET_LS1043ARDB) +#if defined(CONFIG_ARCH_LS1046A) || defined(CONFIG_ARCH_LS1043A) rcw_tmp = in_be32(&gur->rcwsr[15]); switch ((rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT) { case 1: sys_info->freq_cga_m2 = freq_c_pll[1]; break; -#if defined(CONFIG_TARGET_LS1046ARDB) +#if defined(CONFIG_ARCH_LS1046A) case 2: sys_info->freq_cga_m2 = freq_c_pll[1] / 2; break; @@ -143,7 +143,7 @@ void get_sys_info(struct sys_info *sys_info) case 3: sys_info->freq_cga_m2 = freq_c_pll[1] / 3; break; -#if defined(CONFIG_TARGET_LS1046ARDB) +#if defined(CONFIG_ARCH_LS1046A) case 6: sys_info->freq_cga_m2 = freq_c_pll[0] / 2; break; From 1cb0f98f910d10370e3ae11a9c37860a97ac0706 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Wed, 27 Apr 2022 16:04:58 +0200 Subject: [PATCH 05/26] powerpc: dts: p2020: Define MPIC nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Copy definition of MPIC nodes from upstream Linux kernel P2020 dts files. Signed-off-by: Pali Rohár --- arch/powerpc/dts/p2020-post.dtsi | 3 + arch/powerpc/dts/pq3-mpic-timer-B.dtsi | 42 ++++++++++++++ arch/powerpc/dts/pq3-mpic.dtsi | 79 ++++++++++++++++++++++++++ 3 files changed, 124 insertions(+) create mode 100644 arch/powerpc/dts/pq3-mpic-timer-B.dtsi create mode 100644 arch/powerpc/dts/pq3-mpic.dtsi diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi index 1c3f78798e..dd878bf555 100644 --- a/arch/powerpc/dts/p2020-post.dtsi +++ b/arch/powerpc/dts/p2020-post.dtsi @@ -73,6 +73,9 @@ /include/ "pq3-etsec1-1.dtsi" /include/ "pq3-etsec1-2.dtsi" + +/include/ "pq3-mpic.dtsi" +/include/ "pq3-mpic-timer-B.dtsi" }; /* PCIe controller base address 0x8000 */ diff --git a/arch/powerpc/dts/pq3-mpic-timer-B.dtsi b/arch/powerpc/dts/pq3-mpic-timer-B.dtsi new file mode 100644 index 0000000000..8734cffae1 --- /dev/null +++ b/arch/powerpc/dts/pq3-mpic-timer-B.dtsi @@ -0,0 +1,42 @@ +/* + * PQ3 MPIC Timer (Group B) device tree stub [ controller @ offset 0x42100 ] + * + * Copyright 2011 Freescale Semiconductor Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +timer@42100 { + compatible = "fsl,mpic-global-timer"; + reg = <0x42100 0x100 0x42300 4>; + interrupts = <4 0 3 0 + 5 0 3 0 + 6 0 3 0 + 7 0 3 0>; +}; diff --git a/arch/powerpc/dts/pq3-mpic.dtsi b/arch/powerpc/dts/pq3-mpic.dtsi new file mode 100644 index 0000000000..71c30eb100 --- /dev/null +++ b/arch/powerpc/dts/pq3-mpic.dtsi @@ -0,0 +1,79 @@ +/* + * PQ3 MPIC device tree stub [ controller @ offset 0x40000 ] + * + * Copyright 2011 Freescale Semiconductor Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +mpic: pic@40000 { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <4>; + reg = <0x40000 0x40000>; + compatible = "fsl,mpic"; + device_type = "open-pic"; + big-endian; + single-cpu-affinity; + last-interrupt-source = <255>; +}; + +timer@41100 { + compatible = "fsl,mpic-global-timer"; + reg = <0x41100 0x100 0x41300 4>; + interrupts = <0 0 3 0 + 1 0 3 0 + 2 0 3 0 + 3 0 3 0>; +}; + +message@41400 { + compatible = "fsl,mpic-v3.1-msgr"; + reg = <0x41400 0x200>; + interrupts = < + 0xb0 2 0 0 + 0xb1 2 0 0 + 0xb2 2 0 0 + 0xb3 2 0 0>; +}; + +msi@41600 { + compatible = "fsl,mpic-msi"; + reg = <0x41600 0x80>; + msi-available-ranges = <0 0x100>; + interrupts = < + 0xe0 0 0 0 + 0xe1 0 0 0 + 0xe2 0 0 0 + 0xe3 0 0 0 + 0xe4 0 0 0 + 0xe5 0 0 0 + 0xe6 0 0 0 + 0xe7 0 0 0>; +}; From 99f17774b7555de960106c41c97de168d6255246 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Wed, 27 Apr 2022 16:04:59 +0200 Subject: [PATCH 06/26] powerpc: dts: p2020: Define crypto node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Copy definition of crypto node from upstream Linux kernel P2020 dts files. Signed-off-by: Pali Rohár --- arch/powerpc/dts/p2020-post.dtsi | 1 + arch/powerpc/dts/pq3-sec3.1-0.dtsi | 45 ++++++++++++++++++++++++++++++ 2 files changed, 46 insertions(+) create mode 100644 arch/powerpc/dts/pq3-sec3.1-0.dtsi diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi index dd878bf555..e0f1f999ac 100644 --- a/arch/powerpc/dts/p2020-post.dtsi +++ b/arch/powerpc/dts/p2020-post.dtsi @@ -74,6 +74,7 @@ /include/ "pq3-etsec1-1.dtsi" /include/ "pq3-etsec1-2.dtsi" +/include/ "pq3-sec3.1-0.dtsi" /include/ "pq3-mpic.dtsi" /include/ "pq3-mpic-timer-B.dtsi" }; diff --git a/arch/powerpc/dts/pq3-sec3.1-0.dtsi b/arch/powerpc/dts/pq3-sec3.1-0.dtsi new file mode 100644 index 0000000000..8f0a5669be --- /dev/null +++ b/arch/powerpc/dts/pq3-sec3.1-0.dtsi @@ -0,0 +1,45 @@ +/* + * PQ3 Sec/Crypto 3.1 device tree stub [ controller @ offset 0x30000 ] + * + * Copyright 2011 Freescale Semiconductor Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +crypto@30000 { + compatible = "fsl,sec3.1", "fsl,sec3.0", + "fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1", + "fsl,sec2.0"; + reg = <0x30000 0x10000>; + interrupts = <45 2 0 0 58 2 0 0>; + fsl,num-channels = <4>; + fsl,channel-fifo-len = <24>; + fsl,exec-units-mask = <0xbfe>; + fsl,descriptor-types-mask = <0x3ab0ebf>; +}; From f0bb612d5b1cdca94e086373fcd38d52451d8971 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Wed, 27 Apr 2022 16:05:00 +0200 Subject: [PATCH 07/26] powerpc: dts: p2020: Define DMA nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Copy definition of DMA nodes from upstream Linux kernel P2020 dts files. Signed-off-by: Pali Rohár --- arch/powerpc/dts/p2020-post.dtsi | 3 ++ arch/powerpc/dts/pq3-dma-0.dtsi | 66 ++++++++++++++++++++++++++++++++ arch/powerpc/dts/pq3-dma-1.dtsi | 66 ++++++++++++++++++++++++++++++++ 3 files changed, 135 insertions(+) create mode 100644 arch/powerpc/dts/pq3-dma-0.dtsi create mode 100644 arch/powerpc/dts/pq3-dma-1.dtsi diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi index e0f1f999ac..d6bad4118c 100644 --- a/arch/powerpc/dts/p2020-post.dtsi +++ b/arch/powerpc/dts/p2020-post.dtsi @@ -64,6 +64,9 @@ interrupts = <16 2 0 0>; }; +/include/ "pq3-dma-0.dtsi" +/include/ "pq3-dma-1.dtsi" + /include/ "pq3-etsec1-0.dtsi" /include/ "pq3-etsec1-timer-0.dtsi" diff --git a/arch/powerpc/dts/pq3-dma-0.dtsi b/arch/powerpc/dts/pq3-dma-0.dtsi new file mode 100644 index 0000000000..b5b37ad30e --- /dev/null +++ b/arch/powerpc/dts/pq3-dma-0.dtsi @@ -0,0 +1,66 @@ +/* + * PQ3 DMA device tree stub [ controller @ offset 0x21000 ] + * + * Copyright 2011 Freescale Semiconductor Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +dma@21300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,eloplus-dma"; + reg = <0x21300 0x4>; + ranges = <0x0 0x21100 0x200>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + cell-index = <0>; + interrupts = <20 2 0 0>; + }; + dma-channel@80 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupts = <21 2 0 0>; + }; + dma-channel@100 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupts = <22 2 0 0>; + }; + dma-channel@180 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupts = <23 2 0 0>; + }; +}; diff --git a/arch/powerpc/dts/pq3-dma-1.dtsi b/arch/powerpc/dts/pq3-dma-1.dtsi new file mode 100644 index 0000000000..28cb8a55d8 --- /dev/null +++ b/arch/powerpc/dts/pq3-dma-1.dtsi @@ -0,0 +1,66 @@ +/* + * PQ3 DMA device tree stub [ controller @ offset 0xc300 ] + * + * Copyright 2011 Freescale Semiconductor Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +dma@c300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,eloplus-dma"; + reg = <0xc300 0x4>; + ranges = <0x0 0xc100 0x200>; + cell-index = <1>; + dma-channel@0 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + cell-index = <0>; + interrupts = <76 2 0 0>; + }; + dma-channel@80 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupts = <77 2 0 0>; + }; + dma-channel@100 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupts = <78 2 0 0>; + }; + dma-channel@180 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupts = <79 2 0 0>; + }; +}; From 26f6f7188bf03dbf9499ef626253cf3b2c1bd3de Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Wed, 27 Apr 2022 16:05:01 +0200 Subject: [PATCH 08/26] powerpc: dts: p2020: Define ecm, memory and guts nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Copy definition of these nodes from upstream Linux kernel P2020 dts files. Signed-off-by: Pali Rohár --- arch/powerpc/dts/p2020-post.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi index d6bad4118c..d281bed5af 100644 --- a/arch/powerpc/dts/p2020-post.dtsi +++ b/arch/powerpc/dts/p2020-post.dtsi @@ -56,6 +56,24 @@ /include/ "pq3-duart-0.dtsi" /include/ "pq3-gpio-0.dtsi" + ecm-law@0 { + compatible = "fsl,ecm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <12>; + }; + + ecm@1000 { + compatible = "fsl,p2020-ecm", "fsl,ecm"; + reg = <0x1000 0x1000>; + interrupts = <17 2 0 0>; + }; + + memory-controller@2000 { + compatible = "fsl,p2020-memory-controller"; + reg = <0x2000 0x1000>; + interrupts = <18 2 0 0>; + }; + L2: l2-cache-controller@20000 { compatible = "fsl,p2020-l2-cache-controller"; reg = <0x20000 0x1000>; @@ -80,6 +98,12 @@ /include/ "pq3-sec3.1-0.dtsi" /include/ "pq3-mpic.dtsi" /include/ "pq3-mpic-timer-B.dtsi" + + global-utilities@e0000 { + compatible = "fsl,p2020-guts"; + reg = <0xe0000 0x1000>; + fsl,has-rstcr; + }; }; /* PCIe controller base address 0x8000 */ From 549bb6b2376b81f30b9492afeff5d6cdf7523eeb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Thu, 28 Apr 2022 13:31:43 +0200 Subject: [PATCH 09/26] powerpc: mpc85xx: Fix compilation with CONFIG_WDT MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When CONFIG_WDT is enabled then non-DM watchdog code cannot be used due to conflicting functions like watchdog_reset(). So disable compilation of mpc85xx watchdog_reset() function when CONFIG_WDT is enabled. Signed-off-by: Pali Rohár --- arch/powerpc/cpu/mpc85xx/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index a82516a75b..ba9736ebef 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -344,6 +344,7 @@ __weak unsigned long get_tbclk(void) } +#ifndef CONFIG_WDT #if defined(CONFIG_WATCHDOG) #define WATCHDOG_MASK (TCR_WP(63) | TCR_WRC(3) | TCR_WIE) void @@ -372,6 +373,7 @@ watchdog_reset(void) enable_interrupts(); } #endif /* CONFIG_WATCHDOG */ +#endif /* * Initializes on-chip MMC controllers. From ae0e7ee88658bf9226a29453664e7b5c26d2c0a0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Sun, 1 May 2022 14:20:48 +0200 Subject: [PATCH 10/26] board: freescale: p1_p2_rdb_pc: Enable TDM function only for P1010 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit TDM function is supported only on P1010. P2020 does not have PMUXCR_TDM_ENA register, so do not enable it. Signed-off-by: Pali Rohár --- board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index 6665aa4ba9..fc676eb31f 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -154,7 +154,9 @@ int board_early_init_f(void) clrbits_be32(&gur->sdhcdcr, SDHCDCR_CD_INV); clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA); +#if defined(CONFIG_TARGET_P1020RDB_PD) || defined(CONFIG_TARGET_P1020RDB_PC) setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TDM_ENA); +#endif board_gpio_init(); board_cpld_init(); From 20fb58fc5a1c83ee0085b2e9f7ecda8b761a5592 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Sun, 1 May 2022 14:23:14 +0200 Subject: [PATCH 11/26] board: freescale: p1_p2_rdb_pc: Implement board_reset() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Do board reset via CPLD's system reset register. Signed-off-by: Pali Rohár --- board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index fc676eb31f..947bbc9a5a 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -83,6 +83,12 @@ struct cpld_data { #define CPLD_FXS_LED 0x0F #define CPLD_SYS_RST 0x00 +void board_reset(void) +{ + struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + out_8(&cpld_data->system_rst, 1); +} + void board_cpld_init(void) { struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); From 02c8fbdb8d41cfa81e2df990da8151ea93bb2f7e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Sun, 1 May 2022 17:45:58 +0200 Subject: [PATCH 12/26] powerpc: fsl_law: Add definition for first PCIe target interface MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Header file asm/fsl_law.h already provides correct definition for second and third PCIe controller (LAW_TRGT_IF_PCIE_2 and LAW_TRGT_IF_PCIE_3). But is missing definition for the first PCIe controller (LAW_TRGT_IF_PCIE_1). Note that existing definition for LAW_TRGT_IF_PCIE_2 and LAW_TRGT_IF_PCIE_3 are slightly complicated, but are really correct for P2020 platform. Signed-off-by: Pali Rohár --- arch/powerpc/include/asm/fsl_law.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/powerpc/include/asm/fsl_law.h b/arch/powerpc/include/asm/fsl_law.h index 39fbc04e47..9e2f2d5370 100644 --- a/arch/powerpc/include/asm/fsl_law.h +++ b/arch/powerpc/include/asm/fsl_law.h @@ -78,6 +78,7 @@ enum law_trgt_if { enum law_trgt_if { LAW_TRGT_IF_PCI = 0x00, LAW_TRGT_IF_PCI_2 = 0x01, + LAW_TRGT_IF_PCIE_1 = 0x02, #if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132) LAW_TRGT_IF_OCN_DSP = 0x03, #else From 6b6c377feb4805f56bfd8de42143b75fc4a186af Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Sun, 1 May 2022 19:17:35 +0200 Subject: [PATCH 13/26] powerpc: mmu: Fix FSL_BOOKE_MAS2() macro MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Effective page number mask for MAS2 register is stored in macro MAS2_EPN. Fixes: 2146cf56821c ("Reworked FSL Book-E TLB macros to be more readable") Signed-off-by: Pali Rohár --- arch/powerpc/include/asm/mmu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h index 2e6255f0d6..b0aafdcdae 100644 --- a/arch/powerpc/include/asm/mmu.h +++ b/arch/powerpc/include/asm/mmu.h @@ -447,7 +447,7 @@ extern void print_bats(void); (((ts) << 12) & MAS1_TS) |\ (MAS1_TSIZE(tsize))) #define FSL_BOOKE_MAS2(epn, wimge) \ - (((epn) & MAS3_RPN) | (wimge)) + (((epn) & MAS2_EPN) | (wimge)) #define FSL_BOOKE_MAS3(rpn, user, perms) \ (((rpn) & MAS3_RPN) | (user) | (perms)) #define FSL_BOOKE_MAS7(rpn) \ From 26153d0b054874c8ed2f5ef98231e4397175f8bd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Mon, 2 May 2022 18:28:08 +0200 Subject: [PATCH 14/26] mtd: rawnand: fsl_elbc: Fix DM support in DTS code path MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit For proper DM support it is required to fill also mtd->dev member. Otherwise DM would not see nand device at all. Signed-off-by: Pali Rohár --- drivers/mtd/nand/raw/fsl_elbc_nand.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/nand/raw/fsl_elbc_nand.c b/drivers/mtd/nand/raw/fsl_elbc_nand.c index e734139b5e..b0e3eb607e 100644 --- a/drivers/mtd/nand/raw/fsl_elbc_nand.c +++ b/drivers/mtd/nand/raw/fsl_elbc_nand.c @@ -668,7 +668,7 @@ static void fsl_elbc_ctrl_init(void) elbc_ctrl->addr = NULL; } -static int fsl_elbc_chip_init(int devnum, u8 *addr, ofnode flash_node) +static int fsl_elbc_chip_init(int devnum, u8 *addr, struct udevice *dev) { struct mtd_info *mtd; struct nand_chip *nand; @@ -716,7 +716,8 @@ static int fsl_elbc_chip_init(int devnum, u8 *addr, ofnode flash_node) elbc_ctrl->chips[priv->bank] = priv; /* fill in nand_chip structure */ - nand->flash_node = flash_node; + mtd->dev = dev; + nand->flash_node = dev ? dev_ofnode(dev) : ofnode_null(); /* set up function call table */ nand->read_byte = fsl_elbc_read_byte; @@ -827,14 +828,14 @@ void board_nand_init(void) int i; for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) - fsl_elbc_chip_init(i, (u8 *)base_address[i], ofnode_null()); + fsl_elbc_chip_init(i, (u8 *)base_address[i], NULL); } #else static int fsl_elbc_nand_probe(struct udevice *dev) { - return fsl_elbc_chip_init(0, (void *)dev_read_addr(dev), dev_ofnode(dev)); + return fsl_elbc_chip_init(0, (void *)dev_read_addr(dev), dev); } static const struct udevice_id fsl_elbc_nand_dt_ids[] = { From 39f42fe20a8239c6a878f7fac03e758b2117009e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Mon, 2 May 2022 18:29:25 +0200 Subject: [PATCH 15/26] powerpc: mpc85xx: Set default SYS_IMMR value for P1/P2 CPUs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This reduce usage of per-board custom settings. Signed-off-by: Pali Rohár --- arch/Kconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/Kconfig b/arch/Kconfig index 12de8a1165..b396263e3b 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -371,6 +371,9 @@ config SYS_IMMR default 0xF0000000 if ARCH_MPC8313 default 0xE0000000 if MPC83xx && !ARCH_MPC8313 default 0x01000000 if ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3 + default 0xFFE00000 if ARCH_P1010 || ARCH_P1011 || ARCH_P1020 || \ + ARCH_P1021 || ARCH_P1024 || ARCH_P1025 || \ + ARCH_P2020 default SYS_CCSRBAR_DEFAULT help Address for the Internal Memory-Mapped Registers (IMMR) window used From d49480637681c0939f7d86b41318e3cc45795036 Mon Sep 17 00:00:00 2001 From: Alison Wang Date: Tue, 10 May 2022 18:29:10 +0800 Subject: [PATCH 16/26] ls1028a: hdp: Add config support for HDP firmware loading This patch adds config support for HDP firmware loading on LS1028A. Signed-off-by: Oliver Brown Signed-off-by: Alison Wang Signed-off-by: Ye Li Signed-off-by: Yangbo Lu --- board/freescale/ls1028a/ls1028a.c | 7 ++++++- configs/ls1028aqds_tfa_SECURE_BOOT_defconfig | 2 ++ configs/ls1028aqds_tfa_defconfig | 2 ++ configs/ls1028ardb_tfa_SECURE_BOOT_defconfig | 2 ++ configs/ls1028ardb_tfa_defconfig | 2 ++ 5 files changed, 14 insertions(+), 1 deletion(-) diff --git a/board/freescale/ls1028a/ls1028a.c b/board/freescale/ls1028a/ls1028a.c index 71a086ef67..1a7806fad7 100644 --- a/board/freescale/ls1028a/ls1028a.c +++ b/board/freescale/ls1028a/ls1028a.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2019, 2021 NXP + * Copyright 2019-2022 NXP */ #include @@ -328,3 +328,8 @@ int checkboard(void) return 0; } #endif + +void *video_hw_init(void) +{ + return NULL; +} diff --git a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig index 7b8f71cfb5..1badfb513a 100644 --- a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig @@ -100,3 +100,5 @@ CONFIG_WDT_SP805=y CONFIG_RSA=y CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_VIDEO=y +CONFIG_VIDEO_LS_HDP_LOAD=y diff --git a/configs/ls1028aqds_tfa_defconfig b/configs/ls1028aqds_tfa_defconfig index 8c1655341e..9439bda71e 100644 --- a/configs/ls1028aqds_tfa_defconfig +++ b/configs/ls1028aqds_tfa_defconfig @@ -105,3 +105,5 @@ CONFIG_WDT=y CONFIG_WDT_SP805=y CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_VIDEO=y +CONFIG_VIDEO_LS_HDP_LOAD=y diff --git a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig index 15777f93b6..8e15ee5b7d 100644 --- a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig @@ -94,3 +94,5 @@ CONFIG_WDT_SP805=y CONFIG_RSA=y CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_VIDEO=y +CONFIG_VIDEO_LS_HDP_LOAD=y diff --git a/configs/ls1028ardb_tfa_defconfig b/configs/ls1028ardb_tfa_defconfig index ec4f253e9f..51fec79b3b 100644 --- a/configs/ls1028ardb_tfa_defconfig +++ b/configs/ls1028ardb_tfa_defconfig @@ -103,3 +103,5 @@ CONFIG_WDT=y CONFIG_WDT_SP805=y CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_VIDEO=y +CONFIG_VIDEO_LS_HDP_LOAD=y From a29eb319a3f8ccfb657053b2941581fa1933974e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Wed, 11 May 2022 20:27:12 +0200 Subject: [PATCH 17/26] mmc: fsl_esdhc: Set fallback mode to 1-bit MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit 8-bit mode is not supported by SD cards and on P2020 are four SDHC pins shared with SPI (so if P2020 board have also SPI then only 4-bit SDHC mode is provided). So 8-bit SDHC mode is really bad default. When max bus width is not provided then set mode to 1-bit. This mode is supported by all cards, so it is the best option for fallback mode. Also P2020 bootrom sets mode to 1-bit when booting from SD/MMC card. Signed-off-by: Pali Rohár Reviewed-by: Jaehoon Chung --- drivers/mmc/fsl_esdhc.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index fdf2cc290e..6c6d03d450 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -946,9 +946,8 @@ int fsl_esdhc_initialize(struct bd_info *bis, struct fsl_esdhc_cfg *cfg) } else if (cfg->max_bus_width == 1) { mmc_cfg->host_caps |= MMC_MODE_1BIT; } else { - mmc_cfg->host_caps |= MMC_MODE_1BIT | MMC_MODE_4BIT | - MMC_MODE_8BIT; - printf("No max bus width provided. Assume 8-bit supported.\n"); + mmc_cfg->host_caps |= MMC_MODE_1BIT; + printf("No max bus width provided. Fallback to 1-bit mode.\n"); } if (IS_ENABLED(CONFIG_ESDHC_DETECT_8_BIT_QUIRK)) From 8f3f8ba945f7e6b4225b2a5f171a64f7679bc8ba Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Wed, 11 May 2022 20:27:13 +0200 Subject: [PATCH 18/26] mmc: fsl_esdhc: Add new config option for default fallback mode MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently default fallback SDHC mode is 1-bit. Add new config option CONFIG_SYS_FSL_ESDHC_DEFAULT_BUS_WIDTH to allow specifying default fallback mode. This is useful e.g. for SPL builds which loads other parts from SD card during boot process. Signed-off-by: Pali Rohár Reviewed-by: Jaehoon Chung --- drivers/mmc/Kconfig | 5 +++++ drivers/mmc/fsl_esdhc.c | 1 + 2 files changed, 6 insertions(+) diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index c8f9709d2d..5a87db6be0 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -839,6 +839,11 @@ config FSL_ESDHC_VS33_NOT_SUPPORT For eSDHC, power supply is through peripheral circuit. 3.3V support is common. Select this if 3.3V power supply not supported. +config SYS_FSL_ESDHC_DEFAULT_BUS_WIDTH + int + depends on FSL_ESDHC + default 1 + config FSL_ESDHC_IMX bool "Freescale/NXP i.MX eSDHC controller support" help diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 6c6d03d450..4e7bfdfaa7 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -971,6 +971,7 @@ int fsl_esdhc_mmc_init(struct bd_info *bis) cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1); cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR; + cfg->max_bus_width = CONFIG_SYS_FSL_ESDHC_DEFAULT_BUS_WIDTH; /* Prefer peripheral clock which provides higher frequency. */ if (gd->arch.sdhc_per_clk) cfg->sdhc_clk = gd->arch.sdhc_per_clk; From 3acf0be4e6f78feec53df9ab897bf0b26c6fe7c3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Tue, 24 May 2022 13:24:59 +0200 Subject: [PATCH 19/26] powerpc: dts: p2020: Define PMC node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Copy definition of PMC node from upstream Linux kernel P2020 dts files. Signed-off-by: Pali Rohár --- arch/powerpc/dts/p2020-post.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi index d281bed5af..0d0cd2273c 100644 --- a/arch/powerpc/dts/p2020-post.dtsi +++ b/arch/powerpc/dts/p2020-post.dtsi @@ -104,6 +104,11 @@ reg = <0xe0000 0x1000>; fsl,has-rstcr; }; + + pmc: power@e0070 { + compatible = "fsl,mpc8548-pmc"; + reg = <0xe0070 0x20>; + }; }; /* PCIe controller base address 0x8000 */ From 676f682bad2ed93a20fcf35dd5af5163d11c126f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Thu, 26 May 2022 10:52:27 +0200 Subject: [PATCH 20/26] board: freescale: p1_p2_rdb_pc: Move boot reset macros to p1_p2_bootsrc.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Code for changing boot source is platform generic and can be used by any P1* and P2* compatible RDB board. Not only by boards which use config header file p1_p2_rdb_pc.h. So move this code from p1_p2_rdb_pc.h to p1_p2_bootsrc.h and cleanup macros for generating boot source env variables in CONFIG_EXTRA_ENV_SETTINGS. This allows to use code for resetting board and rebooting to other boot source also by other boards in future. Signed-off-by: Pali Rohár --- include/configs/p1_p2_bootsrc.h | 59 +++++++++++++++++++++++++++++++++ include/configs/p1_p2_rdb_pc.h | 41 +++++------------------ 2 files changed, 68 insertions(+), 32 deletions(-) create mode 100644 include/configs/p1_p2_bootsrc.h diff --git a/include/configs/p1_p2_bootsrc.h b/include/configs/p1_p2_bootsrc.h new file mode 100644 index 0000000000..13e4fdb4fd --- /dev/null +++ b/include/configs/p1_p2_bootsrc.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2010-2011 Freescale Semiconductor, Inc. + * Copyright 2020 NXP + * Copyright 2022 Pali Rohár + */ + +#include + +#if !defined(CONFIG_SYS_SPD_BUS_NUM) || !defined(CONFIG_SYS_I2C_PCA9557_ADDR) +#error "CONFIG_SYS_SPD_BUS_NUM and CONFIG_SYS_I2C_PCA9557_ADDR are required" +#endif + +#define __BOOTSRC_CMD(src, msk) i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 src 1; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 msk 1 + +#define __VAR_CMD(var, cmd) __stringify(var=cmd\0) +#define __VAR_CMD_RST(var, cmd) __VAR_CMD(var, cmd; reset) + +#ifdef __SW_NOR_BANK_LO +#define MAP_NOR_LO_CMD(var, ...) __VAR_CMD(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_NOR_BANK_LO, __SW_NOR_BANK_MASK)) +#else +#define MAP_NOR_LO_CMD(var, ...) "" +#endif + +#ifdef __SW_NOR_BANK_UP +#define MAP_NOR_UP_CMD(var, ...) __VAR_CMD(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_NOR_BANK_UP, __SW_NOR_BANK_MASK)) +#else +#define MAP_NOR_UP_CMD(var, ...) "" +#endif + +#ifdef __SW_BOOT_NOR +#define RST_NOR_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_NOR, __SW_BOOT_MASK)) +#else +#define RST_NOR_CMD(var, ...) "" +#endif + +#ifdef __SW_BOOT_SPI +#define RST_SPI_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_SPI, __SW_BOOT_MASK)) +#else +#define RST_SPI_CMD(var, ...) "" +#endif + +#ifdef __SW_BOOT_SD +#define RST_SD_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_SD, __SW_BOOT_MASK)) +#else +#define RST_SD_CMD(var, ...) "" +#endif + +#ifdef __SW_BOOT_NAND +#define RST_NAND_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_NAND, __SW_BOOT_MASK)) +#else +#define RST_NAND_CMD(var, ...) "" +#endif + +#ifdef __SW_BOOT_PCIE +#define RST_PCIE_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_PCIE, __SW_BOOT_MASK)) +#else +#define RST_PCIE_CMD(var, ...) "" +#endif diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index f74ad628fe..56a16502dc 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -491,31 +491,7 @@ #define CONFIG_ROOTPATH "/opt/nfsroot" #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ -#ifdef __SW_BOOT_NOR -#define __NOR_RST_CMD \ -norboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_NOR 1; \ -i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset -#endif -#ifdef __SW_BOOT_SPI -#define __SPI_RST_CMD \ -spiboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_SPI 1; \ -i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset -#endif -#ifdef __SW_BOOT_SD -#define __SD_RST_CMD \ -sdboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_SD 1; \ -i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset -#endif -#ifdef __SW_BOOT_NAND -#define __NAND_RST_CMD \ -nandboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_NAND 1; \ -i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset -#endif -#ifdef __SW_BOOT_PCIE -#define __PCIE_RST_CMD \ -pciboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_PCIE 1; \ -i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset -#endif +#include "p1_p2_bootsrc.h" #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ @@ -542,13 +518,14 @@ i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset "nandfdtaddr=80000\0" \ "ramdisk_size=120000\0" \ __VSCFW_ADDR \ -"map_lowernorbank=i2c dev "__stringify(CONFIG_SYS_SPD_BUS_NUM)"; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 1 "__stringify(__SW_NOR_BANK_LO)" 1; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 3 "__stringify(__SW_NOR_BANK_MASK)" 1\0" \ -"map_uppernorbank=i2c dev "__stringify(CONFIG_SYS_SPD_BUS_NUM)"; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 1 "__stringify(__SW_NOR_BANK_UP)" 1; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 3 "__stringify(__SW_NOR_BANK_MASK)" 1\0" \ -__stringify(__NOR_RST_CMD)"\0" \ -__stringify(__SPI_RST_CMD)"\0" \ -__stringify(__SD_RST_CMD)"\0" \ -__stringify(__NAND_RST_CMD)"\0" \ -__stringify(__PCIE_RST_CMD)"\0" +MAP_NOR_LO_CMD(map_lowernorbank) \ +MAP_NOR_UP_CMD(map_uppernorbank) \ +RST_NOR_CMD(norboot) \ +RST_SPI_CMD(spiboot) \ +RST_SD_CMD(sdboot) \ +RST_NAND_CMD(nandboot) \ +RST_PCIE_CMD(pciboot) \ +"" #define CONFIG_USB_FAT_BOOT \ "setenv bootargs root=/dev/ram rw " \ From 66b2dd9ac3de47376f0ceae22c586a9d725fe071 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Thu, 26 May 2022 14:36:03 +0200 Subject: [PATCH 21/26] powerpc: bootm: Fix sizes in memory adjusting warning MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Old size is stored in size variable and new size is in bootm_size variable. Signed-off-by: Pali Rohár --- arch/powerpc/lib/bootm.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/lib/bootm.c b/arch/powerpc/lib/bootm.c index 3b43066bb4..d365705856 100644 --- a/arch/powerpc/lib/bootm.c +++ b/arch/powerpc/lib/bootm.c @@ -137,7 +137,8 @@ void arch_lmb_reserve(struct lmb *lmb) if (size < bootm_size) { ulong base = bootmap_base + size; - printf("WARNING: adjusting available memory to %lx\n", size); + printf("WARNING: adjusting available memory from 0x%lx to 0x%llx\n", + size, (unsigned long long)bootm_size); lmb_reserve(lmb, base, bootm_size - size); } From 2a9cf320afb051f40a4bbb98aa9a6b1a94332d27 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Mon, 30 May 2022 23:02:05 +0200 Subject: [PATCH 22/26] armv8: layerscape: add missing RCW source defines A board might need to get the source of the RCW word, which is also the boot source in most cases. These defines are taken from the LS1028A and I expect they are the same across the SoCs with the same chassis, after all, there was already a reset source for NOR flash. Signed-off-by: Michael Walle --- arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 863618a5f3..304cd7980a 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -230,6 +230,10 @@ #define DCFG_BASE 0x01e00000 #define DCFG_PORSR1 0x000 #define DCFG_PORSR1_RCW_SRC 0xff800000 +#define DCFG_PORSR1_RCW_SRC_SDHC1 0x04000000 +#define DCFG_PORSR1_RCW_SRC_SDHC2 0x04800000 +#define DCFG_PORSR1_RCW_SRC_I2C 0x05000000 +#define DCFG_PORSR1_RCW_SRC_FSPI_NOR 0x07800000 #define DCFG_PORSR1_RCW_SRC_NOR 0x12f00000 #define DCFG_RCWSR12 0x12c #define DCFG_RCWSR12_SDHC_SHIFT 24 From 6bdda4b2003fadbcbcc28a1d395ec1f6f6557539 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Mon, 30 May 2022 23:02:07 +0200 Subject: [PATCH 23/26] board: sl28: set CPO value With a 8GiB memory board, it seems that the "very unlikely event" of a DDR initialization with non-optimal values are not really that unlikely. It happens in about every other reboot. As described in erratum A-009942, preset the DEBUG_28 register with an optimal value. The value iself depends on the memory configuration of the board, but the used value seems to work well for all variants. Signed-off-by: Michael Walle --- board/kontron/sl28/ddr.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/board/kontron/sl28/ddr.c b/board/kontron/sl28/ddr.c index 41426996ab..d75b23e54c 100644 --- a/board/kontron/sl28/ddr.c +++ b/board/kontron/sl28/ddr.c @@ -54,6 +54,9 @@ static fsl_ddr_cfg_regs_t __maybe_unused ddr_cfg_regs = { .ddr_cdr1 = 0x80040000, .ddr_cdr2 = 0x0000bc01, + + /* Erratum A-009942, set optimal CPO value */ + .debug[28] = 0x00700040, }; int fsl_initdram(void) From 7fd5ca15019577418cdc058049fd9f814696014d Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Mon, 30 May 2022 23:02:08 +0200 Subject: [PATCH 24/26] board: sl28: remove unneeded ddr config parameter config_2 doesn't need to be set to zero because that is already the default value. Signed-off-by: Michael Walle --- board/kontron/sl28/ddr.c | 1 - 1 file changed, 1 deletion(-) diff --git a/board/kontron/sl28/ddr.c b/board/kontron/sl28/ddr.c index d75b23e54c..ed799c6e34 100644 --- a/board/kontron/sl28/ddr.c +++ b/board/kontron/sl28/ddr.c @@ -69,7 +69,6 @@ int fsl_initdram(void) dram_size = 0x80000000; ddr_cfg_regs.cs[1].bnds = 0; ddr_cfg_regs.cs[1].config = 0; - ddr_cfg_regs.cs[1].config_2 = 0; break; case GPPORCR1_MEM_4GB_CS0_1: dram_size = 0x100000000ULL; From 1029249b0065b32ae74e3fa7cd7d0f27d1b80efd Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Mon, 30 May 2022 23:02:09 +0200 Subject: [PATCH 25/26] board: sl28: support 8 GiB memory The board supports up to 8 GiB memory. The memory is soldered on the board but the configuration is equivalent to a dual chip select, dual rank DIMM module. Signed-off-by: Michael Walle --- board/kontron/sl28/ddr.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/board/kontron/sl28/ddr.c b/board/kontron/sl28/ddr.c index ed799c6e34..315d9f99c7 100644 --- a/board/kontron/sl28/ddr.c +++ b/board/kontron/sl28/ddr.c @@ -73,6 +73,13 @@ int fsl_initdram(void) case GPPORCR1_MEM_4GB_CS0_1: dram_size = 0x100000000ULL; break; + case GPPORCR1_MEM_8GB_CS0_1: + dram_size = 0x200000000ULL; + ddr_cfg_regs.cs[0].bnds = 0x000000ff; + ddr_cfg_regs.cs[0].config = 0x80044403; + ddr_cfg_regs.cs[1].bnds = 0x010001ff; + ddr_cfg_regs.cs[1].config = 0x80044403; + break; case GPPORCR1_MEM_512MB_CS0: dram_size = 0x20000000; fallthrough; /* for now */ @@ -82,7 +89,6 @@ int fsl_initdram(void) case GPPORCR1_MEM_4GB_CS0_2: dram_size = 0x100000000ULL; fallthrough; /* for now */ - case GPPORCR1_MEM_8GB_CS0_1: case GPPORCR1_MEM_8GB_CS0_1_2_3: dram_size = 0x200000000ULL; fallthrough; /* for now */ From 7bc683afda5ede82cfcace77cecab1891d6d93ff Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Mon, 30 May 2022 23:02:10 +0200 Subject: [PATCH 26/26] board: sl28: rename include guard macro Avoid name clashes with an include file on board level. Signed-off-by: Michael Walle --- include/configs/kontron_sl28.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/include/configs/kontron_sl28.h b/include/configs/kontron_sl28.h index 6beb0bdf3e..2373abf3e3 100644 --- a/include/configs/kontron_sl28.h +++ b/include/configs/kontron_sl28.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ -#ifndef __SL28_H -#define __SL28_H +#ifndef __SL28_CONFIG_H +#define __SL28_CONFIG_H #include #include @@ -80,4 +80,4 @@ ENV_MEM_LAYOUT_SETTINGS \ BOOTENV -#endif /* __SL28_H */ +#endif /* __SL28_CONFIG_H */