mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-25 06:00:43 +00:00
ARM: dts: stm32: Rework DDR DT inclusion
Adjust the DDR configuration dtsi such that they only generate the DRAM configuration node, the DDR controller node is moved into the stm32mp157-u-boot.dtsi itself. This permits including multiple DDR configuration dtsi files in board DT. Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com>
This commit is contained in:
Marek Vasut
Patrick Delaunay
parent
0c27c16495
commit
a8c97f4a00
4 changed files with 248 additions and 137 deletions
|
|
@ -2,30 +2,13 @@
|
|||
/*
|
||||
* Copyright : STMicroelectronics 2018
|
||||
*/
|
||||
#include <linux/stringify.h>
|
||||
|
||||
/ {
|
||||
soc {
|
||||
ddr: ddr@5a003000 {
|
||||
&ddr {
|
||||
config-DDR_MEM_COMPATIBLE {
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
compatible = "st,stm32mp1-ddr";
|
||||
|
||||
reg = <0x5A003000 0x550
|
||||
0x5A004000 0x234>;
|
||||
|
||||
clocks = <&rcc AXIDCG>,
|
||||
<&rcc DDRC1>,
|
||||
<&rcc DDRC2>,
|
||||
<&rcc DDRPHYC>,
|
||||
<&rcc DDRCAPB>,
|
||||
<&rcc DDRPHYCAPB>;
|
||||
|
||||
clock-names = "axidcg",
|
||||
"ddrc1",
|
||||
"ddrc2",
|
||||
"ddrphyc",
|
||||
"ddrcapb",
|
||||
"ddrphycapb";
|
||||
compatible = __stringify(st,DDR_MEM_COMPATIBLE);
|
||||
|
||||
st,mem-name = DDR_MEM_NAME;
|
||||
st,mem-speed = <DDR_MEM_SPEED>;
|
||||
|
|
@ -154,4 +137,105 @@
|
|||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
#undef DDR_MEM_COMPATIBLE
|
||||
#undef DDR_MEM_NAME
|
||||
#undef DDR_MEM_SPEED
|
||||
#undef DDR_MEM_SIZE
|
||||
|
||||
#undef DDR_MSTR
|
||||
#undef DDR_MRCTRL0
|
||||
#undef DDR_MRCTRL1
|
||||
#undef DDR_DERATEEN
|
||||
#undef DDR_DERATEINT
|
||||
#undef DDR_PWRCTL
|
||||
#undef DDR_PWRTMG
|
||||
#undef DDR_HWLPCTL
|
||||
#undef DDR_RFSHCTL0
|
||||
#undef DDR_RFSHCTL3
|
||||
#undef DDR_RFSHTMG
|
||||
#undef DDR_CRCPARCTL0
|
||||
#undef DDR_DRAMTMG0
|
||||
#undef DDR_DRAMTMG1
|
||||
#undef DDR_DRAMTMG2
|
||||
#undef DDR_DRAMTMG3
|
||||
#undef DDR_DRAMTMG4
|
||||
#undef DDR_DRAMTMG5
|
||||
#undef DDR_DRAMTMG6
|
||||
#undef DDR_DRAMTMG7
|
||||
#undef DDR_DRAMTMG8
|
||||
#undef DDR_DRAMTMG14
|
||||
#undef DDR_ZQCTL0
|
||||
#undef DDR_DFITMG0
|
||||
#undef DDR_DFITMG1
|
||||
#undef DDR_DFILPCFG0
|
||||
#undef DDR_DFIUPD0
|
||||
#undef DDR_DFIUPD1
|
||||
#undef DDR_DFIUPD2
|
||||
#undef DDR_DFIPHYMSTR
|
||||
#undef DDR_ADDRMAP1
|
||||
#undef DDR_ADDRMAP2
|
||||
#undef DDR_ADDRMAP3
|
||||
#undef DDR_ADDRMAP4
|
||||
#undef DDR_ADDRMAP5
|
||||
#undef DDR_ADDRMAP6
|
||||
#undef DDR_ADDRMAP9
|
||||
#undef DDR_ADDRMAP10
|
||||
#undef DDR_ADDRMAP11
|
||||
#undef DDR_ODTCFG
|
||||
#undef DDR_ODTMAP
|
||||
#undef DDR_SCHED
|
||||
#undef DDR_SCHED1
|
||||
#undef DDR_PERFHPR1
|
||||
#undef DDR_PERFLPR1
|
||||
#undef DDR_PERFWR1
|
||||
#undef DDR_DBG0
|
||||
#undef DDR_DBG1
|
||||
#undef DDR_DBGCMD
|
||||
#undef DDR_POISONCFG
|
||||
#undef DDR_PCCFG
|
||||
#undef DDR_PCFGR_0
|
||||
#undef DDR_PCFGW_0
|
||||
#undef DDR_PCFGQOS0_0
|
||||
#undef DDR_PCFGQOS1_0
|
||||
#undef DDR_PCFGWQOS0_0
|
||||
#undef DDR_PCFGWQOS1_0
|
||||
#undef DDR_PCFGR_1
|
||||
#undef DDR_PCFGW_1
|
||||
#undef DDR_PCFGQOS0_1
|
||||
#undef DDR_PCFGQOS1_1
|
||||
#undef DDR_PCFGWQOS0_1
|
||||
#undef DDR_PCFGWQOS1_1
|
||||
#undef DDR_PGCR
|
||||
#undef DDR_PTR0
|
||||
#undef DDR_PTR1
|
||||
#undef DDR_PTR2
|
||||
#undef DDR_ACIOCR
|
||||
#undef DDR_DXCCR
|
||||
#undef DDR_DSGCR
|
||||
#undef DDR_DCR
|
||||
#undef DDR_DTPR0
|
||||
#undef DDR_DTPR1
|
||||
#undef DDR_DTPR2
|
||||
#undef DDR_MR0
|
||||
#undef DDR_MR1
|
||||
#undef DDR_MR2
|
||||
#undef DDR_MR3
|
||||
#undef DDR_ODTCR
|
||||
#undef DDR_ZQ0CR1
|
||||
#undef DDR_DX0GCR
|
||||
#undef DDR_DX0DLLCR
|
||||
#undef DDR_DX0DQTR
|
||||
#undef DDR_DX0DQSTR
|
||||
#undef DDR_DX1GCR
|
||||
#undef DDR_DX1DLLCR
|
||||
#undef DDR_DX1DQTR
|
||||
#undef DDR_DX1DQSTR
|
||||
#undef DDR_DX2GCR
|
||||
#undef DDR_DX2DLLCR
|
||||
#undef DDR_DX2DQTR
|
||||
#undef DDR_DX2DQSTR
|
||||
#undef DDR_DX3GCR
|
||||
#undef DDR_DX3DLLCR
|
||||
#undef DDR_DX3DQTR
|
||||
#undef DDR_DX3DQSTR
|
||||
|
|
|
|||
|
|
@ -16,6 +16,7 @@
|
|||
* address mapping : RBC
|
||||
* Tc > + 85C : N
|
||||
*/
|
||||
#define DDR_MEM_COMPATIBLE ddr3-1066-888-bin-g-1x4gb-533mhz
|
||||
#define DDR_MEM_NAME "DDR3-1066/888 bin G 1x4Gb 533MHz v1.45"
|
||||
#define DDR_MEM_SPEED 533000
|
||||
#define DDR_MEM_SIZE 0x20000000
|
||||
|
|
|
|||
|
|
@ -16,6 +16,7 @@
|
|||
* address mapping : RBC
|
||||
* Tc > + 85C : N
|
||||
*/
|
||||
#define DDR_MEM_COMPATIBLE ddr3-1066-888-bin-g-2x4gb-533mhz
|
||||
#define DDR_MEM_NAME "DDR3-1066/888 bin G 2x4Gb 533MHz v1.45"
|
||||
#define DDR_MEM_SPEED 533000
|
||||
#define DDR_MEM_SIZE 0x40000000
|
||||
|
|
|
|||
|
|
@ -36,6 +36,31 @@
|
|||
|
||||
soc {
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
ddr: ddr@5a003000 {
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
compatible = "st,stm32mp1-ddr";
|
||||
|
||||
reg = <0x5A003000 0x550
|
||||
0x5A004000 0x234>;
|
||||
|
||||
clocks = <&rcc AXIDCG>,
|
||||
<&rcc DDRC1>,
|
||||
<&rcc DDRC2>,
|
||||
<&rcc DDRPHYC>,
|
||||
<&rcc DDRCAPB>,
|
||||
<&rcc DDRPHYCAPB>;
|
||||
|
||||
clock-names = "axidcg",
|
||||
"ddrc1",
|
||||
"ddrc2",
|
||||
"ddrphyc",
|
||||
"ddrcapb",
|
||||
"ddrphycapb";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue