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mpc83xx: Fix the LAW1/3 bug
The patch solves the alignment problem of the local bus access windows to render accessible the memory bank and PHY registers of UPC 1 (starting at 0xf801 0000). What we actually did was to adjust the sizes of the bus access windows so that the base address alignment requirement would be met. Signed-off-by: Chereji Marian <marian.chereji@freescale.com> Signed-off-by: Gridish Shlomi <gridish@freescale.com> Signed-off-by: Dave Liu <daveliu@freescale.com>
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1 changed files with 3 additions and 3 deletions
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@ -188,7 +188,7 @@
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*/
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#define CFG_BCSR 0xF8000000
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#define CFG_LBLAWBAR1_PRELIM CFG_BCSR /* Access window base at BCSR base */
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#define CFG_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */
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#define CFG_LBLAWAR1_PRELIM 0x8000000F /* Access window size 64K */
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#define CFG_BR1_PRELIM (CFG_BCSR|0x00000801) /* Port size=8bit, MSEL=GPCM */
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#define CFG_OR1_PRELIM 0xFFFFE9f7 /* length 32K */
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@ -278,8 +278,8 @@
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/*
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* Windows to access PIB via local bus
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*/
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#define CFG_LBLAWBAR3_PRELIM 0xf8008000 /* windows base 0xf8008000 */
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#define CFG_LBLAWAR3_PRELIM 0x8000000f /* windows size 64KB */
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#define CFG_LBLAWBAR3_PRELIM 0xf8010000 /* windows base 0xf8010000 */
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#define CFG_LBLAWAR3_PRELIM 0x8000000e /* windows size 32KB */
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/*
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* CS4 on Local Bus, to PIB
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