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Use standard LAWAR_TRGT_IF_* defines for LAW setup on 85xx

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We already had defines for LAWAR_TRGT_IF_* that we should use
rather than creating new ones.  Also, added some missing defines for
PCIE targets.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Kumar Gala 2007-11-29 02:18:59 -06:00
parent 04db400892
commit a853d56c59
4 changed files with 28 additions and 47 deletions
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25
board/cds/mpc8548cds/init.S
View file

@ -28,13 +28,6 @@
#include <config.h> #include <config.h>
#include <mpc85xx.h> #include <mpc85xx.h>
#define LAWAR_TRGT_PCI1 0x00000000
#define LAWAR_TRGT_PCI2 0x00100000
#define LAWAR_TRGT_PCIE 0x00200000
#define LAWAR_TRGT_RIO 0x00c00000
#define LAWAR_TRGT_LBC 0x00400000
#define LAWAR_TRGT_DDR 0x00f00000
/* /*
* TLB0 and TLB1 Entries * TLB0 and TLB1 Entries
* *
@ -232,39 +225,39 @@ law_entry:
.long (4f-3f)/8 .long (4f-3f)/8
3: 3:
.long 0 .long 0
.long (LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN .long (LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN
#ifdef CFG_PCI1_MEM_PHYS #ifdef CFG_PCI1_MEM_PHYS
.long (CFG_PCI1_MEM_PHYS>>12) & 0xfffff .long (CFG_PCI1_MEM_PHYS>>12) & 0xfffff
.long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M) .long LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
.long (CFG_PCI1_IO_PHYS>>12) & 0xfffff .long (CFG_PCI1_IO_PHYS>>12) & 0xfffff
.long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M) .long LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M)
#endif #endif
#ifdef CFG_PCI2_MEM_PHYS #ifdef CFG_PCI2_MEM_PHYS
.long (CFG_PCI2_MEM_PHYS>>12) & 0xfffff .long (CFG_PCI2_MEM_PHYS>>12) & 0xfffff
.long LAWAR_EN | LAWAR_TRGT_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M) .long LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)
.long (CFG_PCI2_IO_PHYS>>12) & 0xfffff .long (CFG_PCI2_IO_PHYS>>12) & 0xfffff
.long LAWAR_EN | LAWAR_TRGT_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M) .long LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M)
#endif #endif
#ifdef CFG_PCIE1_MEM_PHYS #ifdef CFG_PCIE1_MEM_PHYS
.long (CFG_PCIE1_MEM_PHYS>>12) & 0xfffff .long (CFG_PCIE1_MEM_PHYS>>12) & 0xfffff
.long LAWAR_EN | LAWAR_TRGT_PCIE | (LAWAR_SIZE & LAWAR_SIZE_512M) .long LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
.long (CFG_PCIE1_IO_PHYS>>12) & 0xfffff .long (CFG_PCIE1_IO_PHYS>>12) & 0xfffff
.long LAWAR_EN | LAWAR_TRGT_PCIE | (LAWAR_SIZE & LAWAR_SIZE_1M) .long LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_1M)
#endif #endif
/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
.long (CFG_LBC_CACHE_BASE>>12) & 0xfffff .long (CFG_LBC_CACHE_BASE>>12) & 0xfffff
.long LAWAR_EN | LAWAR_TRGT_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M) .long LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)
#ifdef CFG_RIO_MEM_PHYS #ifdef CFG_RIO_MEM_PHYS
.long (CFG_RIO_MEM_PHYS>>12) & 0xfffff .long (CFG_RIO_MEM_PHYS>>12) & 0xfffff
.long LAWAR_EN | LAWAR_TRGT_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M) .long LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)
#endif #endif
4: 4:
entry_end entry_end

25
board/freescale/mpc8544ds/init.S
View file

@ -27,13 +27,6 @@
#include <config.h> #include <config.h>
#include <mpc85xx.h> #include <mpc85xx.h>
#define LAWAR_TRGT_PCI1 0x00000000
#define LAWAR_TRGT_PCIE1 0x00200000
#define LAWAR_TRGT_PCIE2 0x00100000
#define LAWAR_TRGT_PCIE3 0x00300000
#define LAWAR_TRGT_LBC 0x00400000
#define LAWAR_TRGT_DDR 0x00f00000
/* /*
* TLB0 and TLB1 Entries * TLB0 and TLB1 Entries
* *
@ -212,31 +205,31 @@ law_entry:
.long (4f-3f)/8 .long (4f-3f)/8
3: 3:
.long 0 .long 0
.long (LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN .long (LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN
.long (CFG_PCI1_MEM_PHYS>>12) & 0xfffff .long (CFG_PCI1_MEM_PHYS>>12) & 0xfffff
.long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M) .long LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
.long (CFG_PCI1_IO_PHYS>>12) & 0xfffff .long (CFG_PCI1_IO_PHYS>>12) & 0xfffff
.long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_64K) .long LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_64K)
.long (CFG_LBC_CACHE_BASE>>12) & 0xfffff .long (CFG_LBC_CACHE_BASE>>12) & 0xfffff
.long LAWAR_EN | LAWAR_TRGT_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M) .long LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)
.long (CFG_PCIE1_MEM_PHYS>>12) & 0xfffff .long (CFG_PCIE1_MEM_PHYS>>12) & 0xfffff
.long LAWAR_EN | LAWAR_TRGT_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_256M) .long LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_256M)
.long (CFG_PCIE1_IO_PHYS>>12) & 0xfffff .long (CFG_PCIE1_IO_PHYS>>12) & 0xfffff
.long LAWAR_EN | LAWAR_TRGT_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_64K) .long LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_64K)
.long (CFG_PCIE2_MEM_PHYS>>12) & 0xfffff .long (CFG_PCIE2_MEM_PHYS>>12) & 0xfffff
.long LAWAR_EN | LAWAR_TRGT_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_512M) .long LAWAR_EN | LAWAR_TRGT_IF_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_512M)
.long (CFG_PCIE2_IO_PHYS>>12) & 0xfffff .long (CFG_PCIE2_IO_PHYS>>12) & 0xfffff
.long LAWAR_EN | LAWAR_TRGT_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_64K) .long LAWAR_EN | LAWAR_TRGT_IF_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_64K)
/* contains both PCIE3 MEM & IO space */ /* contains both PCIE3 MEM & IO space */
.long (CFG_PCIE3_MEM_PHYS>>12) & 0xfffff .long (CFG_PCIE3_MEM_PHYS>>12) & 0xfffff
.long LAWAR_EN | LAWAR_TRGT_PCIE3 | (LAWAR_SIZE & LAWAR_SIZE_4M) .long LAWAR_EN | LAWAR_TRGT_IF_PCIE3 | (LAWAR_SIZE & LAWAR_SIZE_4M)
4: 4:
entry_end entry_end

21
board/mpc8568mds/init.S
View file

@ -28,12 +28,6 @@
#include <config.h> #include <config.h>
#include <mpc85xx.h> #include <mpc85xx.h>
#define LAWAR_TRGT_PCI1 0x00000000
#define LAWAR_TRGT_PCIE1 0x00200000
#define LAWAR_TRGT_RIO 0x00c00000
#define LAWAR_TRGT_LBC 0x00400000
#define LAWAR_TRGT_DDR 0x00f00000
/* /*
* TLB0 and TLB1 Entries * TLB0 and TLB1 Entries
* *
@ -216,27 +210,26 @@ tlb1_entry:
*/ */
#define LAWBAR0 0 #define LAWBAR0 0
#define LAWAR0 ((LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) #define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) #define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) #define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
#define LAWBAR2 ((CFG_PCIE1_MEM_BASE>>12) & 0xfffff) #define LAWBAR2 ((CFG_PCIE1_MEM_BASE>>12) & 0xfffff)
#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) #define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff) #define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_8M)) #define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_8M))
#define LAWBAR4 ((CFG_PCIE1_IO_PHYS>>12) & 0xfffff) #define LAWBAR4 ((CFG_PCIE1_IO_PHYS>>12) & 0xfffff)
#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_8M)) #define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_8M))
#define LAWBAR5 ((CFG_SRIO_MEM_BASE>>12) & 0xfffff) #define LAWBAR5 ((CFG_SRIO_MEM_BASE>>12) & 0xfffff)
#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)) #define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
/* LBC window - maps 256M. That's SDRAM, BCSR, PIBs, and Flash */ /* LBC window - maps 256M. That's SDRAM, BCSR, PIBs, and Flash */
#define LAWBAR6 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) #define LAWBAR6 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
#define LAWAR6 (LAWAR_EN | LAWAR_TRGT_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) #define LAWAR6 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
.section .bootpg, "ax" .section .bootpg, "ax"
.globl law_entry .globl law_entry

4
include/asm-ppc/mmu.h
View file

@ -413,7 +413,9 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower);
#define LAWAR_TRGT_IF_PCI1 0x00000000 #define LAWAR_TRGT_IF_PCI1 0x00000000
#define LAWAR_TRGT_IF_PCIX 0x00000000 #define LAWAR_TRGT_IF_PCIX 0x00000000
#define LAWAR_TRGT_IF_PCI2 0x00100000 #define LAWAR_TRGT_IF_PCI2 0x00100000
#define LAWAR_TRGT_IF_PEX 0x00200000 #define LAWAR_TRGT_IF_PCIE1 0x00200000
#define LAWAR_TRGT_IF_PCIE2 0x00100000
#define LAWAR_TRGT_IF_PCIE3 0x00300000
#define LAWAR_TRGT_IF_LBC 0x00400000 #define LAWAR_TRGT_IF_LBC 0x00400000
#define LAWAR_TRGT_IF_CCSR 0x00800000 #define LAWAR_TRGT_IF_CCSR 0x00800000
#define LAWAR_TRGT_IF_DDR_INTERLEAVED 0x00B00000 #define LAWAR_TRGT_IF_DDR_INTERLEAVED 0x00B00000