mirror of
https://github.com/AsahiLinux/u-boot
synced 2025-02-18 06:58:54 +00:00
Merge with /home/wd/git/u-boot/custodian/u-boot-mpc86xx
This commit is contained in:
Wolfgang Denk
commit
a8227b66fa
6 changed files with 198 additions and 126 deletions
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@ -23,14 +23,25 @@
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*/
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#include <common.h>
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#include <watchdog.h>
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#include <command.h>
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#include <watchdog.h>
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#include <asm/cache.h>
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#include <mpc86xx.h>
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#include "pixis.h"
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static ulong strfractoint(uchar *strptr);
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/*
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* Simple board reset.
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*/
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void pixis_reset(void)
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{
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out8(PIXIS_BASE + PIXIS_RST, 0);
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}
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/*
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* Per table 27, page 58 of MPC8641HPCN spec.
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*/
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@ -235,7 +246,8 @@ void set_px_go_with_watchdog(void)
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}
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int disable_watchdog(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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int pixis_disable_watchdog_cmd(cmd_tbl_t *cmdtp,
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int flag, int argc, char *argv[])
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{
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u8 tmp;
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@ -252,7 +264,7 @@ int disable_watchdog(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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}
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U_BOOT_CMD(
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diswd, 1, 0, disable_watchdog,
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diswd, 1, 0, pixis_disable_watchdog_cmd,
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"diswd - Disable watchdog timer \n",
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NULL);
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@ -263,7 +275,7 @@ U_BOOT_CMD(
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* input: strptr i.e. argv[2]
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*/
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ulong strfractoint(uchar *strptr)
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static ulong strfractoint(uchar *strptr)
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{
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int i, j, retval;
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int mulconst;
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@ -319,3 +331,142 @@ ulong strfractoint(uchar *strptr)
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return retval;
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}
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int
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pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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ulong val;
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ulong corepll;
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/*
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* No args is a simple reset request.
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*/
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if (argc <= 1) {
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pixis_reset();
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/* not reached */
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}
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if (strcmp(argv[1], "cf") == 0) {
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/*
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* Reset with frequency changed:
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* cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
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*/
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if (argc < 5) {
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puts(cmdtp->usage);
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return 1;
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}
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read_from_px_regs(0);
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val = set_px_sysclk(simple_strtoul(argv[2], NULL, 10));
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corepll = strfractoint(argv[3]);
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val = val + set_px_corepll(corepll);
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val = val + set_px_mpxpll(simple_strtoul(argv[4], NULL, 10));
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if (val == 3) {
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puts("Setting registers VCFGEN0 and VCTL\n");
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read_from_px_regs(1);
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puts("Resetting board with values from ");
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puts("VSPEED0, VSPEED1, VCLKH, and VCLKL \n");
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set_px_go();
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} else {
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puts(cmdtp->usage);
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return 1;
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}
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while (1) ; /* Not reached */
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} else if (strcmp(argv[1], "altbank") == 0) {
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/*
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* Reset using alternate flash bank:
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*/
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if (argv[2] == 0) {
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/*
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* Reset from alternate bank without changing
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* frequency and without watchdog timer enabled.
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* altbank
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*/
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read_from_px_regs(0);
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read_from_px_regs_altbank(0);
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if (argc > 2) {
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puts(cmdtp->usage);
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return 1;
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}
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puts("Setting registers VCFGNE1, VBOOT, and VCTL\n");
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set_altbank();
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read_from_px_regs_altbank(1);
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puts("Resetting board to boot from the other bank.\n");
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set_px_go();
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} else if (strcmp(argv[2], "cf") == 0) {
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/*
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* Reset with frequency changed
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* altbank cf <SYSCLK freq> <COREPLL ratio>
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* <MPXPLL ratio>
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*/
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read_from_px_regs(0);
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read_from_px_regs_altbank(0);
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val = set_px_sysclk(simple_strtoul(argv[3], NULL, 10));
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corepll = strfractoint(argv[4]);
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val = val + set_px_corepll(corepll);
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val = val + set_px_mpxpll(simple_strtoul(argv[5],
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NULL, 10));
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if (val == 3) {
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puts("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n");
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set_altbank();
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read_from_px_regs(1);
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read_from_px_regs_altbank(1);
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puts("Enabling watchdog timer on the FPGA\n");
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puts("Resetting board with values from ");
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puts("VSPEED0, VSPEED1, VCLKH and VCLKL ");
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puts("to boot from the other bank.\n");
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set_px_go_with_watchdog();
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} else {
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puts(cmdtp->usage);
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return 1;
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}
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while (1) ; /* Not reached */
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} else if (strcmp(argv[2], "wd") == 0) {
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/*
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* Reset from alternate bank without changing
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* frequencies but with watchdog timer enabled:
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* altbank wd
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*/
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read_from_px_regs(0);
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read_from_px_regs_altbank(0);
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puts("Setting registers VCFGEN1, VBOOT, and VCTL\n");
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set_altbank();
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read_from_px_regs_altbank(1);
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puts("Enabling watchdog timer on the FPGA\n");
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puts("Resetting board to boot from the other bank.\n");
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set_px_go_with_watchdog();
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while (1) ; /* Not reached */
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} else {
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puts(cmdtp->usage);
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return 1;
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}
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} else {
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puts(cmdtp->usage);
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return 1;
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}
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return 0;
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}
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U_BOOT_CMD(
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pixis_reset, CFG_MAXARGS, 1, pixis_reset_cmd,
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"pixis_reset - Reset the board using the FPGA sequencer\n",
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" pixis_reset\n"
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" pixis_reset [altbank]\n"
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" pixis_reset altbank wd\n"
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" pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n"
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" pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n"
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);
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@ -20,6 +20,7 @@
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* MA 02111-1307 USA
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*/
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extern void pixis_reset(void);
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extern int set_px_sysclk(ulong sysclk);
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extern int set_px_mpxpll(ulong mpxpll);
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extern int set_px_corepll(ulong corepll);
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@ -28,6 +29,3 @@ extern void read_from_px_regs_altbank(int set);
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extern void set_altbank(void);
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extern void set_px_go(void);
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extern void set_px_go_with_watchdog(void);
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extern int disable_watchdog(cmd_tbl_t *cmdtp,
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int flag, int argc, char *argv[]);
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extern ulong strfractoint(uchar *strptr);
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@ -25,7 +25,9 @@ include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).a
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COBJS := $(BOARD).o pixis.o sys_eeprom.o
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COBJS := $(BOARD).o sys_eeprom.o \
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../freescale/common/pixis.o
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SOBJS := init.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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@ -1,9 +1,5 @@
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/*
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* Copyright 2004 Freescale Semiconductor.
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* Jeff Brown
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* Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
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*
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* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
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* Copyright 2006, 2007 Freescale Semiconductor.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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@ -25,18 +21,18 @@
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*/
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#include <common.h>
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#include <command.h>
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#include <pci.h>
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#include <asm/processor.h>
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#include <asm/immap_86xx.h>
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#include <spd.h>
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#include <asm/io.h>
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#if defined(CONFIG_OF_FLAT_TREE)
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#include <ft_build.h>
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extern void ft_cpu_setup(void *blob, bd_t *bd);
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#endif
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#include "pixis.h"
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#include "../freescale/common/pixis.h"
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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extern void ddr_enable_ecc(unsigned int dram_size);
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@ -258,109 +254,6 @@ ft_board_setup(void *blob, bd_t *bd)
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#endif
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void
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mpc8641_reset_board(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
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{
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char cmd;
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ulong val;
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ulong corepll;
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/*
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* No args is a simple reset request.
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*/
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if (argc <= 1) {
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out8(PIXIS_BASE + PIXIS_RST, 0);
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/* not reached */
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}
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cmd = argv[1][1];
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switch (cmd) {
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case 'f': /* reset with frequency changed */
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if (argc < 5)
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goto my_usage;
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read_from_px_regs(0);
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val = set_px_sysclk(simple_strtoul(argv[2], NULL, 10));
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corepll = strfractoint(argv[3]);
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val = val + set_px_corepll(corepll);
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val = val + set_px_mpxpll(simple_strtoul(argv[4], NULL, 10));
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if (val == 3) {
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puts("Setting registers VCFGEN0 and VCTL\n");
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read_from_px_regs(1);
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puts("Resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL ....\n");
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set_px_go();
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} else
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goto my_usage;
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while (1) ; /* Not reached */
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case 'l':
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if (argv[2][1] == 'f') {
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read_from_px_regs(0);
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read_from_px_regs_altbank(0);
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/* reset with frequency changed */
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val = set_px_sysclk(simple_strtoul(argv[3], NULL, 10));
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corepll = strfractoint(argv[4]);
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val = val + set_px_corepll(corepll);
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val = val + set_px_mpxpll(simple_strtoul(argv[5],
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NULL, 10));
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if (val == 3) {
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puts("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n");
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set_altbank();
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read_from_px_regs(1);
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read_from_px_regs_altbank(1);
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puts("Enabling watchdog timer on the FPGA and resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL to boot from the other bank ....\n");
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set_px_go_with_watchdog();
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} else
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goto my_usage;
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while (1) ; /* Not reached */
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} else if (argv[2][1] == 'd') {
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/*
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* Reset from alternate bank without changing
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* frequencies but with watchdog timer enabled.
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*/
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read_from_px_regs(0);
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read_from_px_regs_altbank(0);
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puts("Setting registers VCFGEN1, VBOOT, and VCTL\n");
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set_altbank();
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read_from_px_regs_altbank(1);
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puts("Enabling watchdog timer on the FPGA and resetting board to boot from the other bank....\n");
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set_px_go_with_watchdog();
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while (1) ; /* Not reached */
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} else {
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/*
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* Reset from next bank without changing
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* frequency and without watchdog timer enabled.
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*/
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read_from_px_regs(0);
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read_from_px_regs_altbank(0);
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if (argc > 2)
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goto my_usage;
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puts("Setting registers VCFGNE1, VBOOT, and VCTL\n");
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set_altbank();
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read_from_px_regs_altbank(1);
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puts("Resetting board to boot from the other bank....\n");
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set_px_go();
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}
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default:
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goto my_usage;
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}
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my_usage:
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puts("\nUsage: reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n");
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puts(" reset altbank [cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>]\n");
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puts(" reset altbank [wd]\n");
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puts("For example: reset cf 40 2.5 10\n");
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puts("See MPC8641HPCN Design Workbook for valid values of command line parameters.\n");
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}
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/*
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* get_board_sys_clk
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* Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
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|
|
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@ -32,12 +32,6 @@
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#include <ft_build.h>
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#endif
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#ifdef CONFIG_MPC8641HPCN
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extern void mpc8641_reset_board(cmd_tbl_t *cmdtp, int flag,
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int argc, char *argv[]);
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#endif
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int
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checkcpu(void)
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{
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@ -185,7 +179,7 @@ do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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#else /* CONFIG_MPC8641HPCN */
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mpc8641_reset_board(cmdtp, flag, argc, argv);
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out8(PIXIS_BASE + PIXIS_RST, 0);
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#endif /* !CONFIG_MPC8641HPCN */
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|
|
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@ -121,3 +121,37 @@ To Flash U-boot into the alternative bank (0xFF800000 - 0xFFBFFFFF):
|
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0xe300_0000 0xe3ff_ffff PCI2/PEX2 IO 16M
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0xfe00_0000 0xfeff_ffff Flash(alternate)16M
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0xff00_0000 0xffff_ffff Flash(boot bank)16M
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5. pixis_reset command
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--------------------
|
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A new command, "pixis_reset", is introduced to reset mpc8641hpcn board
|
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using the FPGA sequencer. When the board restarts, it has the option
|
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of using either the current or alternate flash bank as the boot
|
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image, with or without the watchdog timer enabled, and finally with
|
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or without frequency changes.
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||||
|
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Usage is;
|
||||
|
||||
pixis_reset
|
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pixis_reset altbank
|
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pixis_reset altbank wd
|
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pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
|
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pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
|
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|
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Examples;
|
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|
||||
/* reset to current bank, like "reset" command */
|
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pixis_reset
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||||
|
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/* reset board but use the to alternate flash bank */
|
||||
pixis_reset altbank
|
||||
|
||||
/* reset board, use alternate flash bank with watchdog timer enabled*/
|
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pixis_reset altbank wd
|
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|
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/* reset board to alternate bank with frequency changed.
|
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* 40 is SYSCLK, 2.5 is COREPLL ratio, 10 is MPXPLL ratio
|
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*/
|
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pixis-reset altbank cf 40 2.5 10
|
||||
|
||||
Valid clock choices are in the 8641 Reference Manuals.
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue