drivers: ata: Remove mvsata_ide driver

The mvsata_ide driver was due for DM conversion by v2019.07.  As that
has long passed, remove the driver and disable it in the boards which
had enabled it.

Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini 2021-02-09 21:42:56 -05:00
parent 34af2da9ad
commit a80e03683b
25 changed files with 0 additions and 276 deletions

View file

@ -1084,8 +1084,6 @@ endif
$(call deprecated,CONFIG_DM_MMC CONFIG_BLK,MMC,v2019.04,$(CONFIG_MMC))
$(call deprecated,CONFIG_DM_USB CONFIG_OF_CONTROL CONFIG_BLK,\
USB,v2019.07,$(CONFIG_USB))
$(call deprecated,CONFIG_AHCI,AHCI instead of CONFIG_MVSATA_IDE,v2019.07, \
$(CONFIG_MVSATA_IDE))
$(call deprecated,CONFIG_AHCI,AHCI,v2019.07, $(CONFIG_LIBATA))
$(call deprecated,CONFIG_DM_PCI,PCI,v2019.07,$(CONFIG_PCI))
$(call deprecated,CONFIG_DM_VIDEO,video,v2019.07,\

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@ -74,8 +74,6 @@
*/
#ifdef CONFIG_IDE
#define __io
#define CONFIG_IDE_PREINIT
#define CONFIG_MVSATA_IDE_USE_PORT1
/* Needs byte-swapping for ATA data register */
#define CONFIG_IDE_SWAP_IO
/* Data, registers and alternate blocks are at the same offset */

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@ -36,7 +36,6 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_NETCONSOLE=y
CONFIG_DM=y
CONFIG_MVSATA_IDE=y
CONFIG_BLK=y
# CONFIG_MMC is not set
CONFIG_MTD=y

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@ -34,7 +34,6 @@ CONFIG_ENV_SPI_MAX_HZ=50000000
CONFIG_ENV_ADDR=0x100000
CONFIG_NETCONSOLE=y
CONFIG_DM=y
CONFIG_MVSATA_IDE=y
CONFIG_BLK=y
# CONFIG_MMC is not set
CONFIG_MTD=y

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@ -30,7 +30,6 @@ CONFIG_ENV_SPI_MAX_HZ=50000000
CONFIG_ENV_ADDR=0x3D0000
CONFIG_NETCONSOLE=y
CONFIG_DM=y
CONFIG_MVSATA_IDE=y
CONFIG_BLK=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MVTWSI=y

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@ -32,7 +32,6 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xFFF84000
CONFIG_NETCONSOLE=y
CONFIG_MVSATA_IDE=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y

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@ -37,7 +37,6 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_NETCONSOLE=y
CONFIG_DM=y
CONFIG_MVSATA_IDE=y
CONFIG_BLK=y
# CONFIG_MMC is not set
CONFIG_MTD=y

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@ -38,7 +38,6 @@ CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NETCONSOLE=y
CONFIG_DM=y
CONFIG_MVSATA_IDE=y
CONFIG_BLK=y
# CONFIG_MMC is not set
CONFIG_MTD=y

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@ -35,7 +35,6 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NETCONSOLE=y
CONFIG_MVSATA_IDE=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y

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@ -38,7 +38,6 @@ CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NETCONSOLE=y
CONFIG_DM=y
CONFIG_MVSATA_IDE=y
CONFIG_BLK=y
# CONFIG_MMC is not set
CONFIG_MTD=y

View file

@ -32,7 +32,6 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NETCONSOLE=y
CONFIG_MVSATA_IDE=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y

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@ -83,12 +83,6 @@ config FSL_SATA
Enable this driver to support the SATA controller found in
some Freescale PowerPC SoCs.
config MVSATA_IDE
bool "Enable Marvell SATA controller driver support via IDE interface"
help
Enable this driver to support the SATA controller found in
some Marvell SoCs, running in IDE compatibility mode using PIO.
config SATA_MV
bool "Enable Marvell SATA controller driver support"
select AHCI

View file

@ -10,7 +10,6 @@ obj-$(CONFIG_SCSI_AHCI) += ahci.o
obj-$(CONFIG_DWC_AHSATA) += dwc_ahsata.o
obj-$(CONFIG_FSL_SATA) += fsl_sata.o
obj-$(CONFIG_LIBATA) += libata.o
obj-$(CONFIG_MVSATA_IDE) += mvsata_ide.o
obj-$(CONFIG_SATA) += sata.o
obj-$(CONFIG_SATA_CEVA) += sata_ceva.o
obj-$(CONFIG_SATA_MV) += sata_mv.o

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@ -1,199 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
*
* Written-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
*/
#include <common.h>
#include <asm/io.h>
#include <linux/delay.h>
#if defined(CONFIG_ARCH_ORION5X)
#include <asm/arch/orion5x.h>
#elif defined(CONFIG_ARCH_KIRKWOOD)
#include <asm/arch/soc.h>
#elif defined(CONFIG_ARCH_MVEBU)
#include <linux/mbus.h>
#endif
/* SATA port registers */
struct mvsata_port_registers {
u32 reserved0[10];
u32 edma_cmd;
u32 reserved1[181];
/* offset 0x300 : ATA Interface registers */
u32 sstatus;
u32 serror;
u32 scontrol;
u32 ltmode;
u32 phymode3;
u32 phymode4;
u32 reserved2[5];
u32 phymode1;
u32 phymode2;
u32 bist_cr;
u32 bist_dw1;
u32 bist_dw2;
u32 serrorintrmask;
};
/*
* Sanity checks:
* - to compile at all, we need CONFIG_SYS_ATA_BASE_ADDR.
* - for ide_preinit to make sense, we need at least one of
* CONFIG_SYS_ATA_IDE0_OFFSET or CONFIG_SYS_ATA_IDE1_OFFSET;
* - for ide_preinit to be called, we need CONFIG_IDE_PREINIT.
* Fail with an explanation message if these conditions are not met.
* This is particularly important for CONFIG_IDE_PREINIT, because
* its lack would not cause a build error.
*/
#if !defined(CONFIG_SYS_ATA_BASE_ADDR)
#error CONFIG_SYS_ATA_BASE_ADDR must be defined
#elif !defined(CONFIG_SYS_ATA_IDE0_OFFSET) \
&& !defined(CONFIG_SYS_ATA_IDE1_OFFSET)
#error CONFIG_SYS_ATA_IDE0_OFFSET or CONFIG_SYS_ATA_IDE1_OFFSET \
must be defined
#elif !defined(CONFIG_IDE_PREINIT)
#error CONFIG_IDE_PREINIT must be defined
#endif
/*
* Masks and values for SControl DETection and Interface Power Management,
* and for SStatus DETection.
*/
#define MVSATA_EDMA_CMD_ATA_RST 0x00000004
#define MVSATA_SCONTROL_DET_MASK 0x0000000F
#define MVSATA_SCONTROL_DET_NONE 0x00000000
#define MVSATA_SCONTROL_DET_INIT 0x00000001
#define MVSATA_SCONTROL_IPM_MASK 0x00000F00
#define MVSATA_SCONTROL_IPM_NO_LP_ALLOWED 0x00000300
#define MVSATA_SCONTROL_MASK \
(MVSATA_SCONTROL_DET_MASK|MVSATA_SCONTROL_IPM_MASK)
#define MVSATA_PORT_INIT \
(MVSATA_SCONTROL_DET_INIT|MVSATA_SCONTROL_IPM_NO_LP_ALLOWED)
#define MVSATA_PORT_USE \
(MVSATA_SCONTROL_DET_NONE|MVSATA_SCONTROL_IPM_NO_LP_ALLOWED)
#define MVSATA_SSTATUS_DET_MASK 0x0000000F
#define MVSATA_SSTATUS_DET_DEVCOMM 0x00000003
/*
* Status codes to return to client callers. Currently, callers ignore
* exact value and only care for zero or nonzero, so no need to make this
* public, it is only #define'd for clarity.
* If/when standard negative codes are implemented in U-Boot, then these
* #defines should be moved to, or replaced by ones from, the common list
* of status codes.
*/
#define MVSATA_STATUS_OK 0
#define MVSATA_STATUS_TIMEOUT -1
/*
* Registers for SATA MBUS memory windows
*/
#define MVSATA_WIN_CONTROL(w) (MVEBU_AXP_SATA_BASE + 0x30 + ((w) << 4))
#define MVSATA_WIN_BASE(w) (MVEBU_AXP_SATA_BASE + 0x34 + ((w) << 4))
/*
* Initialize SATA memory windows for Armada XP
*/
#ifdef CONFIG_ARCH_MVEBU
static void mvsata_ide_conf_mbus_windows(void)
{
const struct mbus_dram_target_info *dram;
int i;
dram = mvebu_mbus_dram_info();
/* Disable windows, Set Size/Base to 0 */
for (i = 0; i < 4; i++) {
writel(0, MVSATA_WIN_CONTROL(i));
writel(0, MVSATA_WIN_BASE(i));
}
for (i = 0; i < dram->num_cs; i++) {
const struct mbus_dram_window *cs = dram->cs + i;
writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
(dram->mbus_dram_target_id << 4) | 1,
MVSATA_WIN_CONTROL(i));
writel(cs->base & 0xffff0000, MVSATA_WIN_BASE(i));
}
}
#endif
/*
* Initialize one MVSATAHC port: set SControl's IPM to "always active"
* and DET to "reset", then wait for SStatus's DET to become "device and
* comm ok" (or time out after 50 us if no device), then set SControl's
* DET back to "no action".
*/
static int mvsata_ide_initialize_port(struct mvsata_port_registers *port)
{
u32 control;
u32 status;
u32 timeleft = 10000; /* wait at most 10 ms for SATA reset to complete */
/* Hard reset */
writel(MVSATA_EDMA_CMD_ATA_RST, &port->edma_cmd);
udelay(25); /* taken from original marvell port */
writel(0, &port->edma_cmd);
/* Set control IPM to 3 (no low power) and DET to 1 (initialize) */
control = readl(&port->scontrol);
control = (control & ~MVSATA_SCONTROL_MASK) | MVSATA_PORT_INIT;
writel(control, &port->scontrol);
/* Toggle control DET back to 0 (normal operation) */
control = (control & ~MVSATA_SCONTROL_MASK) | MVSATA_PORT_USE;
writel(control, &port->scontrol);
/* wait for status DET to become 3 (device and communication OK) */
while (--timeleft) {
status = readl(&port->sstatus) & MVSATA_SSTATUS_DET_MASK;
if (status == MVSATA_SSTATUS_DET_DEVCOMM)
break;
udelay(1);
}
/* return success or time-out error depending on time left */
if (!timeleft)
return MVSATA_STATUS_TIMEOUT;
return MVSATA_STATUS_OK;
}
/*
* ide_preinit() will be called by ide_init in cmd_ide.c and will
* reset the MVSTATHC ports needed by the board.
*/
int ide_preinit(void)
{
int ret = MVSATA_STATUS_TIMEOUT;
int status;
#ifdef CONFIG_ARCH_MVEBU
mvsata_ide_conf_mbus_windows();
#endif
/* Enable ATA port 0 (could be SATA port 0 or 1) if declared */
#if defined(CONFIG_SYS_ATA_IDE0_OFFSET)
status = mvsata_ide_initialize_port(
(struct mvsata_port_registers *)
(CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET));
if (status == MVSATA_STATUS_OK)
ret = MVSATA_STATUS_OK;
#endif
/* Enable ATA port 1 (could be SATA port 0 or 1) if declared */
#if defined(CONFIG_SYS_ATA_IDE1_OFFSET)
status = mvsata_ide_initialize_port(
(struct mvsata_port_registers *)
(CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE1_OFFSET));
if (status == MVSATA_STATUS_OK)
ret = MVSATA_STATUS_OK;
#endif
/* Return success if at least one port initialization succeeded */
return ret;
}

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@ -35,14 +35,6 @@
#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
#endif
/*
* SATA Driver configuration
*/
#ifdef CONFIG_MVSATA_IDE
#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET
#endif
/*
* Enable GPI0 support
*/

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@ -52,11 +52,4 @@
#define CONFIG_PHY_BASE_ADR 0
#endif /* CONFIG_CMD_NET */
/*
* SATA Driver configuration
*/
#ifdef CONFIG_MVSATA_IDE
#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
#endif /*CONFIG_MVSATA_IDE*/
#endif /* _CONFIG_DREAMPLUG_H */

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@ -55,11 +55,4 @@
#define CONFIG_PHY_BASE_ADR 8
#endif /* CONFIG_CMD_NET */
/*
* SATA Driver configuration
*/
#ifdef CONFIG_MVSATA_IDE
#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
#endif /*CONFIG_MVSATA_IDE*/
#endif /* _CONFIG_DS109_H */

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@ -122,9 +122,6 @@
*/
#ifdef CONFIG_IDE
#define __io
#define CONFIG_IDE_PREINIT
/* ED Mini V has an IDE-compatible SATA connector for port 1 */
#define CONFIG_MVSATA_IDE_USE_PORT1
/* Needs byte-swapping for ATA data register */
#define CONFIG_IDE_SWAP_IO
/* Data, registers and alternate blocks are at the same offset */

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@ -72,11 +72,4 @@
#define CONFIG_PHY_BASE_ADR 0
#endif /* CONFIG_CMD_NET */
/*
* * SATA Driver configuration
* */
#ifdef CONFIG_MVSATA_IDE
#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
#endif /*CONFIG_MVSATA_IDE*/
#endif /* _CONFIG_GOFLEXHOME_H */

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@ -66,11 +66,4 @@
#define CONFIG_PHY_BASE_ADR 0
#endif /* CONFIG_CMD_NET */
/*
* SATA Driver configuration
*/
#ifdef CONFIG_MVSATA_IDE
#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
#endif /*CONFIG_MVSATA_IDE*/
#endif /* _CONFIG_GURUPLUG_H */

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@ -56,9 +56,6 @@
*/
#ifdef CONFIG_IDE
#define __io
#define CONFIG_IDE_PREINIT
#define CONFIG_MVSATA_IDE_USE_PORT0
#define CONFIG_MVSATA_IDE_USE_PORT1
#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET
#endif /* CONFIG_IDE */

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@ -80,14 +80,6 @@
#define CONFIG_JFFS2_NAND
#define CONFIG_JFFS2_LZO
/*
* SATA
*/
#ifdef CONFIG_MVSATA_IDE
#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET
#endif
/*
* EFI partition
*/

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@ -48,8 +48,6 @@
/* SATA driver configuration */
#ifdef CONFIG_IDE
#define __io
#define CONFIG_IDE_PREINIT
#define CONFIG_MVSATA_IDE_USE_PORT0
#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
#endif /* CONFIG_IDE */

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@ -55,9 +55,6 @@
*/
#ifdef CONFIG_IDE
#define __io
#define CONFIG_IDE_PREINIT
#define CONFIG_MVSATA_IDE_USE_PORT0
#define CONFIG_MVSATA_IDE_USE_PORT1
#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET
#endif /* CONFIG_IDE */

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@ -1079,8 +1079,6 @@ CONFIG_MUSB_HOST
CONFIG_MVGBE_PORTS
CONFIG_MVMFP_V2
CONFIG_MVS
CONFIG_MVSATA_IDE_USE_PORT0
CONFIG_MVSATA_IDE_USE_PORT1
CONFIG_MV_ETH_RXQ
CONFIG_MV_I2C_NUM
CONFIG_MV_I2C_REG