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mtd: nand: omap: remove unused #defines from common omap_gpmc.h
OMAP NAND driver can detect Page-size and OOB-size of NAND device from ONFI params or nand_id[] table. And based on that it defines ECC layout. This patch 1) removes following board configs used for defining NAND ECC layout - GPMC_NAND_ECC_LP_x16_LAYOUT (for large page x16 NAND) - GPMC_NAND_ECC_LP_x8_LAYOUT (for large page x8 NAND) - GPMC_NAND_ECC_SP_x16_LAYOUT (for small page x16 NAND) - GPMC_NAND_ECC_SP_x8_LAYOUT (for small page x8 NAND) 2) removes unused #defines in common omap_gpmc.h depending on above configs Build tested using: ./MAKEALL -s am33xx -s omap3 -s omap4 -s omap5 Signed-off-by: Pekon Gupta <pekon@ti.com>
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50899183c9
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19 changed files with 0 additions and 73 deletions
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@ -12,53 +12,6 @@
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#define GPMC_BUF_EMPTY 0
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#define GPMC_BUF_FULL 1
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/* Generic ECC Layouts */
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/* Large Page x8 NAND device Layout */
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#ifdef GPMC_NAND_ECC_LP_x8_LAYOUT
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#define GPMC_NAND_HW_ECC_LAYOUT {\
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.eccbytes = 12,\
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.eccpos = {1, 2, 3, 4, 5, 6, 7, 8,\
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9, 10, 11, 12},\
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.oobfree = {\
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{.offset = 13,\
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.length = 51 } } \
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}
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#endif
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/* Large Page x16 NAND device Layout */
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#ifdef GPMC_NAND_ECC_LP_x16_LAYOUT
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#define GPMC_NAND_HW_ECC_LAYOUT {\
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.eccbytes = 12,\
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.eccpos = {2, 3, 4, 5, 6, 7, 8, 9,\
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10, 11, 12, 13},\
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.oobfree = {\
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{.offset = 14,\
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.length = 50 } } \
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}
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#endif
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/* Small Page x8 NAND device Layout */
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#ifdef GPMC_NAND_ECC_SP_x8_LAYOUT
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#define GPMC_NAND_HW_ECC_LAYOUT {\
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.eccbytes = 3,\
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.eccpos = {1, 2, 3},\
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.oobfree = {\
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{.offset = 4,\
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.length = 12 } } \
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}
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#endif
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/* Small Page x16 NAND device Layout */
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#ifdef GPMC_NAND_ECC_SP_x16_LAYOUT
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#define GPMC_NAND_HW_ECC_LAYOUT {\
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.eccbytes = 3,\
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.eccpos = {2, 3, 4},\
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.oobfree = {\
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{.offset = 5,\
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.length = 11 } } \
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}
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#endif
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enum omap_ecc {
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/* 1-bit ECC calculation by Software, Error detection by Software */
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OMAP_ECC_HAM1_CODE_SW = 1, /* avoid un-initialized int can be 0x0 */
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@ -404,7 +404,6 @@
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/* NAND support */
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#ifdef CONFIG_NAND
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#define CONFIG_CMD_NAND
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#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
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#if !defined(CONFIG_SPI_BOOT) && !defined(CONFIG_NOR_BOOT)
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#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
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#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:128k(SPL)," \
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@ -188,7 +188,6 @@
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#define CONFIG_NAND
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#define CONFIG_NAND_OMAP_GPMC
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#define CONFIG_NAND_OMAP_ELM
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#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
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#define CONFIG_SYS_NAND_BASE (0x08000000) /* phys address CS0 */
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_ONFI_DETECTION 1
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@ -268,7 +268,6 @@
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
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#define CONFIG_NAND_OMAP_GPMC
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#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
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#define CONFIG_ENV_IS_IN_NAND 1
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#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
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@ -277,7 +277,6 @@
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
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#define CONFIG_NAND_OMAP_GPMC
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#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
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#define CONFIG_ENV_IS_IN_NAND 1
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#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
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@ -156,8 +156,6 @@
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#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
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/* to access nand at */
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/* CS0 */
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#define GPMC_NAND_ECC_LP_x8_LAYOUT
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#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
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/* devices */
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/* Environment information */
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@ -116,8 +116,6 @@
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#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
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/* to access nand at */
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/* CS0 */
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#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
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#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
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/* devices */
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#define CONFIG_JFFS2_NAND
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@ -143,8 +143,6 @@
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#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
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/* to access nand at */
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/* CS0 */
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#define GPMC_NAND_ECC_LP_x16_LAYOUT
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#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
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#if defined(CONFIG_CMD_NET)
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@ -321,7 +321,6 @@
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#define PISMO1_NAND_SIZE GPMC_SIZE_128M
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#define CONFIG_NAND_OMAP_GPMC
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#define GPMC_NAND_ECC_LP_x16_LAYOUT
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#define CONFIG_ENV_IS_IN_NAND
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#define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */
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@ -183,8 +183,6 @@
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#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
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/* to access nand at */
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/* CS0 */
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#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
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#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
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/* devices */
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@ -208,7 +208,6 @@
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#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
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#define CONFIG_NAND_OMAP_GPMC
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#define GPMC_NAND_ECC_LP_x16_LAYOUT
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#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
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#elif defined(CONFIG_CMD_ONENAND)
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#define CONFIG_SYS_FLASH_BASE PISMO1_ONEN_BASE
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@ -154,7 +154,6 @@
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#ifdef CONFIG_NAND
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#define PISMO1_NAND_SIZE GPMC_SIZE_128M /* Configure the PISMO */
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#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
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#define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */
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#define CONFIG_ENV_IS_IN_NAND 1
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#define CONFIG_ENV_SIZE (512 << 10) /* Total Size Environment */
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@ -295,7 +295,6 @@
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#if defined(CONFIG_CMD_NAND)
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#define CONFIG_NAND_OMAP_GPMC
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#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
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#define CONFIG_ENV_IS_IN_NAND
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#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
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#endif
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@ -119,8 +119,6 @@
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#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
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/* to access nand */
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/* at CS0 */
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#define GPMC_NAND_ECC_LP_x16_LAYOUT
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#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
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/* devices */
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#define CONFIG_JFFS2_NAND
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@ -131,8 +131,6 @@
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#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
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/* to access nand */
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/* at CS0 */
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#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
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#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
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/* devices */
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@ -138,8 +138,6 @@
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#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
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/* to access nand at */
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/* CS0 */
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#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
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#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
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/* devices */
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#define CONFIG_JFFS2_NAND
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@ -457,7 +457,6 @@
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#define CONFIG_NAND_OMAP_GPMC
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#define CONFIG_NAND_OMAP_ELM
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#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
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#define CONFIG_SYS_NAND_BASE (0x08000000) /* physical address */
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/* to access nand at */
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/* CS0 */
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@ -186,7 +186,6 @@
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#define PISMO1_NAND_SIZE GPMC_SIZE_128M
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#define CONFIG_NAND_OMAP_GPMC
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#define GPMC_NAND_ECC_LP_x16_LAYOUT
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#define CONFIG_ENV_IS_IN_NAND
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#define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */
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@ -134,8 +134,6 @@
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#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
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/* to access nand at */
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/* CS0 */
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#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
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#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
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/* devices */
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#define CONFIG_BCH
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