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Add VGA support (CT69000) to CPCI750 board.

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Insert missing __le32_to_cpu() for filesize in ext2fs_read_file().

Patch by Reinhard Arlt, 30 Dec 2005
This commit is contained in:
Stefan Roese 2006-01-18 20:05:34 +01:00
parent 2076d0a15f
commit a7b9fb9110
7 changed files with 135 additions and 10 deletions
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4
CHANGELOG
View file

@ -2,6 +2,10 @@
Changes since U-Boot 1.1.4:
======================================================================
* Add VGA support (CT69000) to CPCI750 board.
Insert missing __le32_to_cpu() for filesize in ext2fs_read_file().
Patch by Reinhard Arlt, 30 Dec 2005
* PMC405 and CPCI405: Moved configuration of pci resources
into config file.
PMC405 and CPCI2DP: Added firmware download and booting via pci.

74
board/esd/cpci750/pci.c
View file

@ -44,6 +44,14 @@ static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = {
{0, 0, 0, 0, 0, 0, 0, 29, 29, [9 ... PCI_MAX_DEVICES - 1] = 0 },
};
#ifdef CONFIG_USE_CPCIDVI
typedef struct {
unsigned int base;
unsigned int init;
} GT_CPCIDVI_ROM_T;
static GT_CPCIDVI_ROM_T gt_cpcidvi_rom = {0, 0};
#endif
#ifdef DEBUG
static const unsigned int pci_bus_list[] = { PCI_0_MODE, PCI_1_MODE };
@ -800,9 +808,9 @@ static void gt_setup_ide (struct pci_controller *hose,
unsigned int offset =
(bar < 2) ? bar * 8 : 0x100 + (bar - 2) * 8;
pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + offset,
pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + offset,
0x0);
pci_read_config_dword (dev, PCI_BASE_ADDRESS_0 + offset,
pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + offset,
&bar_response);
pciauto_region_allocate (bar_response &
@ -810,11 +818,53 @@ static void gt_setup_ide (struct pci_controller *hose,
pci_io : hose->pci_mem, ide_bar[bar],
&bar_value);
pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + bar * 4,
pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + bar * 4,
bar_value);
}
}
#ifdef CONFIG_USE_CPCIDVI
static void gt_setup_cpcidvi (struct pci_controller *hose,
pci_dev_t dev, struct pci_config_table *entry)
{
u32 bar_value, pci_response;
pci_hose_read_config_dword (hose, dev, PCI_COMMAND, &pci_response);
pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0, 0xffffffff);
pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0, &pci_response);
pciauto_region_allocate (hose->pci_mem, 0x01000000, &bar_value);
pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0, (bar_value & 0xffffff00));
pci_hose_write_config_dword (hose, dev, PCI_ROM_ADDRESS, 0x0);
pciauto_region_allocate (hose->pci_mem, 0x40000, &bar_value);
pci_hose_write_config_dword (hose, dev, PCI_ROM_ADDRESS, (bar_value & 0xffffff00) | 0x01);
gt_cpcidvi_rom.base = bar_value & 0xffffff00;
gt_cpcidvi_rom.init = 1;
}
unsigned char gt_cpcidvi_in8(unsigned int offset)
{
unsigned char data;
if (gt_cpcidvi_rom.init == 0) {
return(0);
}
data = in8((offset & 0x04) + 0x3f000 + gt_cpcidvi_rom.base);
return(data);
}
void gt_cpcidvi_out8(unsigned int offset, unsigned char data)
{
unsigned int off;
if (gt_cpcidvi_rom.init == 0) {
return;
}
off = data;
off = ((off << 3) & 0x7f8) + (offset & 0x4) + 0x3e000 + gt_cpcidvi_rom.base;
in8(off);
return;
}
#endif
/* TODO BJW: Change this for DB64360. This was pulled from the EV64260 */
/* and is curently not called *. */
@ -835,9 +885,12 @@ static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
#endif
struct pci_config_table gt_config_table[] = {
#ifdef CONFIG_USE_CPCIDVI
{PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_69030, PCI_CLASS_DISPLAY_VGA,
PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_cpcidvi},
#endif
{PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_ide},
{}
};
@ -857,10 +910,21 @@ void pci_init_board (void)
#ifdef CONFIG_PCI_PNP
unsigned int bar;
#endif
#ifdef DEBUG
gt_pci_bus_mode_display (PCI_HOST0);
#endif
#ifdef CONFIG_USE_CPCIDVI
gt_cpcidvi_rom.init = 0;
gt_cpcidvi_rom.base = 0;
#endif
pci0_hose.config_table = gt_config_table;
pci1_hose.config_table = gt_config_table;
#ifdef CONFIG_USE_CPCIDVI
gt_config_table[0].config_device = gt_setup_cpcidvi;
#endif
gt_config_table[1].config_device = gt_setup_ide;
pci0_hose.first_busno = 0;
pci0_hose.last_busno = 0xff;

21
drivers/ct69000.c
View file

@ -272,6 +272,9 @@ struct ctfb_chips_properties {
static const struct ctfb_chips_properties chips[] = {
{PCI_DEVICE_ID_CT_69000, 0x200000, 1, 4, -2, 3, 257, 100, 220},
#ifdef CONFIG_USE_CPCIDVI
{PCI_DEVICE_ID_CT_69030, 0x400000, 1, 4, -2, 3, 257, 100, 220},
#endif
{PCI_DEVICE_ID_CT_65555, 0x100000, 16, 4, 0, 1, 255, 48, 220}, /* NOT TESTED */
{0, 0, 0, 0, 0, 0, 0, 0, 0} /* Terminator */
};
@ -957,6 +960,9 @@ SetDrawingEngine (int bits_per_pixel)
*/
static struct pci_device_id supported[] = {
{PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_69000},
#ifdef CONFIG_USE_CPCIDVI
{PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_69030},
#endif
{}
};
@ -1121,7 +1127,22 @@ video_hw_init (void)
pGD->cprBase = pci_mem_base; /* Dummy */
/* set up Hardware */
#ifdef CONFIG_USE_CPCIDVI
if (device_id == PCI_DEVICE_ID_CT_69030) {
ctWrite (CT_MSR_W_O, 0x0b);
ctWrite (0x3cd, 0x13);
ctWrite_i (CT_FP_O, 0x02, 0x00);
ctWrite_i (CT_FP_O, 0x05, 0x00);
ctWrite_i (CT_FP_O, 0x06, 0x00);
ctWrite (0x3c2, 0x0b);
ctWrite_i (CT_FP_O, 0x02, 0x10);
ctWrite_i (CT_FP_O, 0x01, 0x09);
} else {
ctWrite (CT_MSR_W_O, 0x01);
}
#else
ctWrite (CT_MSR_W_O, 0x01);
#endif
/* set the extended Registers */
ctLoadRegs (CT_XR_O, xreg);

19
drivers/i8042.c
View file

@ -29,6 +29,14 @@
#ifdef CONFIG_I8042_KBD
#ifdef CONFIG_USE_CPCIDVI
extern u8 gt_cpcidvi_in8(u32 offset);
extern void gt_cpcidvi_out8(u32 offset, u8 data);
#define in8(a) gt_cpcidvi_in8(a)
#define out8(a, b) gt_cpcidvi_out8(a,b)
#endif
#include <i8042.h>
/* defines */
@ -318,6 +326,13 @@ int i8042_kbd_init (void)
int keymap, try;
char *penv;
#ifdef CONFIG_USE_CPCIDVI
if ((penv = getenv ("console")) != NULL) {
if (strncmp (penv, "serial", 7) == 0) {
return -1;
}
}
#endif
/* Init keyboard device (default US layout) */
keymap = KBD_US;
if ((penv = getenv ("keymap")) != NULL)
@ -633,7 +648,11 @@ static int kbd_reset (void)
if (kbd_input_empty() == 0)
return -1;
#ifdef CONFIG_USE_CPCIDVI
out8 (I8042_COMMAND_REG, 0x60);
#else
out8 (I8042_DATA_REG, 0x60);
#endif
if (kbd_input_empty() == 0)
return -1;

2
fs/ext2/ext2fs.c
View file

@ -389,7 +389,7 @@ int ext2fs_read_file
int blockcnt;
int log2blocksize = LOG2_EXT2_BLOCK_SIZE (node->data);
int blocksize = 1 << (log2blocksize + DISK_SECTOR_BITS);
unsigned int filesize = node->inode.size;
unsigned int filesize = __le32_to_cpu(node->inode.size);
/* Adjust len so it we can't read past the end of the file. */
if (len > filesize) {

18
include/configs/CPCI750.h
View file

@ -70,10 +70,12 @@
#define CONFIG_IDENT_STRING "Marvell 64360 + IBM750FX"
/*#define CFG_HUSH_PARSER*/
#undef CFG_HUSH_PARSER
#define CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#define CFG_AUTO_COMPLETE 1
/* Define which ETH port will be used for connecting the network */
#define CFG_ETH_PORT ETH_0
@ -155,6 +157,18 @@
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define CONFIG_USE_CPCIDVI
#ifdef CONFIG_USE_CPCIDVI
#define CONFIG_VIDEO
#define CONFIG_VIDEO_CT69000
#define CONFIG_CFB_CONSOLE
#define CONFIG_VIDEO_SW_CURSOR
#define CONFIG_VIDEO_LOGO
#define CONFIG_I8042_KBD
#define CFG_ISA_IO 0
#endif
/*
* Miscellaneous configurable options
*/
@ -401,6 +415,8 @@
#define CFG_PCI1_IO_SPACE (CFG_PCI1_IO_BASE)
#define CFG_PCI1_IO_SPACE_PCI 0x00000000
#define CFG_ISA_IO_BASE_ADDRESS (CFG_PCI0_IO_BASE)
#if defined (CONFIG_750CX)
#define CFG_PCI_IDSEL 0x0
#else

1
include/pci_ids.h
View file

@ -510,6 +510,7 @@
#define PCI_DEVICE_ID_CT_65554 0x00e4
#define PCI_DEVICE_ID_CT_65555 0x00e5
#define PCI_DEVICE_ID_CT_69000 0x00c0
#define PCI_DEVICE_ID_CT_69030 0x0c30
#define PCI_VENDOR_ID_MIRO 0x1031
#define PCI_DEVICE_ID_MIRO_36050 0x5601