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Merge branch 't-ml-master' into t-master

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This commit is contained in:
Tom Rix 2010-01-18 08:08:32 -06:00
commit a7709d926d
157 changed files with 4048 additions and 1854 deletions
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7
MAINTAINERS
View file

@ -943,6 +943,7 @@ Blackfin Team <u-boot-devel@blackfin.uclinux.org>
BF518F-EZBRD BF518
BF526-EZBRD BF526
BF527-EZKIT BF527
BF527-EZKIT-V2 BF527
BF533-EZKIT BF533
BF533-STAMP BF533
BF537-PNAV BF537
@ -960,6 +961,7 @@ Blackfin Team <u-boot-devel@blackfin.uclinux.org>
CM-BF537U BF537
CM-BF548 BF548
CM-BF561 BF561
TCM-BF518 BF518
TCM-BF537 BF537
Martin Strubel <strubel@section5.ch>
@ -978,6 +980,11 @@ Blackfin Team <u-boot-devel@blackfin.uclinux.org>
IBF-DSP561 BF561
Valentin Yakovenkov <yakovenkov@niistt.ru>
Anton Shurpin <shurpin.aa@niistt.ru>
BF561-ACVILON BF561
#########################################################################
# End of MAINTAINERS list #
#########################################################################

3
MAKEALL
View file

@ -871,6 +871,7 @@ LIST_blackfin=" \
bf518f-ezbrd \
bf526-ezbrd \
bf527-ezkit \
bf527-ezkit-v2 \
bf533-ezkit \
bf533-stamp \
bf537-minotaur \
@ -879,6 +880,7 @@ LIST_blackfin=" \
bf537-stamp \
bf538f-ezkit \
bf548-ezkit \
bf561-acvilon \
bf561-ezkit \
blackstamp \
cm-bf527 \
@ -888,6 +890,7 @@ LIST_blackfin=" \
cm-bf548 \
cm-bf561 \
ibf-dsp561 \
tcm-bf518 \
tcm-bf537 \
"

11
Makefile
View file

@ -308,7 +308,7 @@ $(obj)u-boot.bin: $(obj)u-boot
$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
$(obj)u-boot.ldr: $(obj)u-boot
$(obj)tools/envcrc --binary > $(obj)env-ldr.o
$(CREATE_LDR_ENV)
$(LDR) -T $(CONFIG_BFIN_CPU) -c $@ $< $(LDR_FLAGS)
$(obj)u-boot.ldr.hex: $(obj)u-boot.ldr
@ -3528,10 +3528,11 @@ BFIN_BOARDS = bf518f-ezbrd bf526-ezbrd bf527-ezkit bf533-ezkit bf533-stamp \
bf537-pnav bf537-stamp bf538f-ezkit bf548-ezkit bf561-ezkit
# Bluetechnix tinyboards
BFIN_BOARDS += cm-bf527 cm-bf533 cm-bf537e cm-bf537u cm-bf548 cm-bf561 tcm-bf537
BFIN_BOARDS += cm-bf527 cm-bf533 cm-bf537e cm-bf537u cm-bf548 cm-bf561 \
tcm-bf518 tcm-bf537
# Misc third party boards
BFIN_BOARDS += bf537-minotaur bf537-srv1 blackstamp
BFIN_BOARDS += bf537-minotaur bf537-srv1 bf561-acvilon blackstamp
# I-SYST Micromodule
BFIN_BOARDS += ibf-dsp561
@ -3539,6 +3540,10 @@ BFIN_BOARDS += ibf-dsp561
$(BFIN_BOARDS:%=%_config) : unconfig
@$(MKCONFIG) $(@:_config=) blackfin blackfin $(@:_config=)
bf527-ezkit-v2_config : unconfig
@$(MKCONFIG) -t BF527_EZKIT_REV_2_1 \
bf527-ezkit blackfin blackfin bf527-ezkit
#========================================================================
# AVR32
#========================================================================

13
README
View file

@ -2447,6 +2447,19 @@ to save the current settings.
- CONFIG_SYS_EEPROM_SIZE:
The size in bytes of the EEPROM device.
- CONFIG_ENV_EEPROM_IS_ON_I2C
define this, if you have I2C and SPI activated, and your
EEPROM, which holds the environment, is on the I2C bus.
- CONFIG_I2C_ENV_EEPROM_BUS
if you have an Environment on an EEPROM reached over
I2C muxes, you can define here, how to reach this
EEPROM. For example:
#define CONFIG_I2C_ENV_EEPROM_BUS "pca9547:70:d\0"
EEPROM which holds the environment, is reached over
a pca9547 i2c mux with address 0x70, channel 3.
- CONFIG_ENV_IS_IN_DATAFLASH:

2
board/amcc/yucca/yucca.c
View file

@ -609,7 +609,7 @@ int board_pcie_card_present(int port)
/*
* For the given slot, set endpoint mode, send power to the slot,
* turn on the green LED and turn off the yellow LED, enable the
* clock. In end point mode reset bit is read only.
* clock. In endpoint mode reset bit is read only.
*/
void board_pcie_setup_port(int port, int rootpoint)
{

2
board/atum8548/atum8548.c
View file

@ -219,7 +219,7 @@ void pci_init_board(void)
pcie1_hose.region_count = 1;
#endif
printf (" PCIE1 connected to Slot as %s (base addr %lx)\n",
pcie_ep ? "End Point" : "Root Complex",
pcie_ep ? "Endpoint" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],

15
board/bf518f-ezbrd/bf518f-ezbrd.c
View file

@ -15,6 +15,7 @@
#include <asm/blackfin.h>
#include <asm/net.h>
#include <asm/mach-common/bits/otp.h>
#include <asm/sdh.h>
DECLARE_GLOBAL_DATA_PTR;
@ -25,13 +26,6 @@ int checkboard(void)
return 0;
}
phys_size_t initdram(int board_type)
{
gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
return gd->bd->bi_memsize;
}
#if defined(CONFIG_BFIN_MAC)
static void board_init_enetaddr(uchar *mac_addr)
{
@ -162,3 +156,10 @@ int board_early_init_f(void)
#endif
return 0;
}
#ifdef CONFIG_BFIN_SDH
int board_mmc_init(bd_t *bis)
{
return bfin_mmc_init(bis);
}
#endif

7
board/bf526-ezbrd/bf526-ezbrd.c
View file

@ -24,13 +24,6 @@ int checkboard(void)
return 0;
}
phys_size_t initdram(int board_type)
{
gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
return gd->bd->bi_memsize;
}
#ifdef CONFIG_BFIN_MAC
static void board_init_enetaddr(uchar *mac_addr)
{

20
board/bf527-ezkit/bf527-ezkit.c
View file

@ -24,13 +24,6 @@ int checkboard(void)
return 0;
}
phys_size_t initdram(int board_type)
{
gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
return gd->bd->bi_memsize;
}
#ifdef CONFIG_BFIN_MAC
static void board_init_enetaddr(uchar *mac_addr)
{
@ -75,3 +68,16 @@ int misc_init_r(void)
return 0;
}
#ifdef CONFIG_USB_BLACKFIN
void board_musb_init(void)
{
/*
* BF527 EZ-KITs require PG13 to be high for HOST mode
*/
bfin_write_PORTG_FER(bfin_read_PORTG_FER() & ~PG13);
bfin_write_PORTGIO_DIR(bfin_read_PORTGIO_DIR() | PG13);
bfin_write_PORTGIO_SET(PG13);
SSYNC();
}
#endif

148
board/bf527-ezkit/video.c
View file

@ -12,40 +12,111 @@
#include <malloc.h>
#include <asm/blackfin.h>
#include <asm/mach-common/bits/dma.h>
#include <i2c.h>
#include <spi.h>
#include <linux/types.h>
#include <stdio_dev.h>
#define DMA_SIZE16 2
#include <asm/mach-common/bits/ppi.h>
#include <asm/mach-common/bits/timer.h>
#include <asm/bfin_logo_230x230.h>
#define LCD_X_RES 320 /* Horizontal Resolution */
#define LCD_Y_RES 240 /* Vertical Resolution */
#define LCD_BPP 24 /* Bit Per Pixel */
#define LCD_PIXEL_SIZE (LCD_BPP / 8)
#define DMA_BUS_SIZE 16
#define DMA_BUS_SIZE 16
#define LCD_CLK (12*1000*1000) /* 12MHz */
#ifdef CONFIG_MK_BF527_EZKIT_REV_2_1 /* lq035q1 */
#define CLOCKS_PER_PIX 3
#if !defined(CONFIG_LQ035Q1_USE_RGB888_8_BIT_PPI) && \
!defined(CONFIG_LQ035Q1_USE_RGB565_8_BIT_PPI)
# define CONFIG_LQ035Q1_USE_RGB565_8_BIT_PPI
#endif
/* Interface 16/18-bit TFT over an 8-bit wide PPI using a
* small Programmable Logic Device (CPLD)
* http://blackfin.uclinux.org/gf/project/stamp/frs/?action=FrsReleaseBrowse&frs_package_id=165
*/
#ifdef CONFIG_LQ035Q1_USE_RGB565_8_BIT_PPI
#include <asm/bfin_logo_rgb565_230x230.h>
#define LCD_BPP 16 /* Bit Per Pixel */
#define CLOCKS_PPIX 2 /* Clocks per pixel */
#define CPLD_DELAY 3 /* RGB565 pipeline delay */
#endif
#ifdef CONFIG_LQ035Q1_USE_RGB888_8_BIT_PPI
#include <asm/bfin_logo_230x230.h>
#define LCD_BPP 24 /* Bit Per Pixel */
#define CLOCKS_PPIX 3 /* Clocks per pixel */
#define CPLD_DELAY 5 /* RGB888 pipeline delay */
#endif
/*
* HS and VS timing parameters (all in number of PPI clk ticks)
*/
#define H_ACTPIX (LCD_X_RES * CLOCKS_PPIX) /* active horizontal pixel */
#define H_PERIOD (336 * CLOCKS_PPIX) /* HS period */
#define H_PULSE (2 * CLOCKS_PPIX) /* HS pulse width */
#define H_START (7 * CLOCKS_PPIX + CPLD_DELAY) /* first valid pixel */
#define U_LINE 4 /* Blanking Lines */
#define V_LINES (LCD_Y_RES + U_LINE) /* total vertical lines */
#define V_PULSE (2 * CLOCKS_PPIX) /* VS pulse width (1-5 H_PERIODs) */
#define V_PERIOD (H_PERIOD * V_LINES) /* VS period */
#define ACTIVE_VIDEO_MEM_OFFSET ((U_LINE / 2) * LCD_X_RES * (LCD_BPP / 8))
/*
* LCD Modes
*/
#define LQ035_RL (0 << 8) /* Right -> Left Scan */
#define LQ035_LR (1 << 8) /* Left -> Right Scan */
#define LQ035_TB (1 << 9) /* Top -> Botton Scan */
#define LQ035_BT (0 << 9) /* Botton -> Top Scan */
#define LQ035_BGR (1 << 11) /* Use BGR format */
#define LQ035_RGB (0 << 11) /* Use RGB format */
#define LQ035_NORM (1 << 13) /* Reversal */
#define LQ035_REV (0 << 13) /* Reversal */
#define LQ035_INDEX 0x74
#define LQ035_DATA 0x76
#define LQ035_DRIVER_OUTPUT_CTL 0x1
#define LQ035_SHUT_CTL 0x11
#define LQ035_DRIVER_OUTPUT_MASK (LQ035_LR | LQ035_TB | LQ035_BGR | LQ035_REV)
#define LQ035_DRIVER_OUTPUT_DEFAULT (0x2AEF & ~LQ035_DRIVER_OUTPUT_MASK)
#define LQ035_SHUT (1 << 0) /* Shutdown */
#define LQ035_ON (0 << 0) /* Shutdown */
#ifndef CONFIG_LQ035Q1_LCD_MODE
#define CONFIG_LQ035Q1_LCD_MODE (LQ035_NORM | LQ035_RL | LQ035_TB | LQ035_BGR)
#endif
#else /* t350mcqb */
#include <asm/bfin_logo_230x230.h>
#define LCD_BPP 24 /* Bit Per Pixel */
#define CLOCKS_PPIX 3 /* Clocks per pixel */
/* HS and VS timing parameters (all in number of PPI clk ticks) */
#define H_ACTPIX (LCD_X_RES * CLOCKS_PER_PIX) /* active horizontal pixel */
#define H_PERIOD (408 * CLOCKS_PER_PIX) /* HS period */
#define H_ACTPIX (LCD_X_RES * CLOCKS_PPIX) /* active horizontal pixel */
#define H_PERIOD (408 * CLOCKS_PPIX) /* HS period */
#define H_PULSE 90 /* HS pulse width */
#define H_START 204 /* first valid pixel */
#define U_LINE 1 /* Blanking Lines */
#define V_LINES (LCD_Y_RES + U_LINE) /* total vertical lines */
#define V_LINES (LCD_Y_RES + U_LINE) /* total vertical lines */
#define V_PULSE (3 * H_PERIOD) /* VS pulse width (1-5 H_PERIODs) */
#define V_PERIOD (H_PERIOD * V_LINES) /* VS period */
#define ACTIVE_VIDEO_MEM_OFFSET (U_LINE * H_ACTPIX)
#endif
#define LCD_PIXEL_SIZE (LCD_BPP / 8)
#define DMA_SIZE16 2
#define PPI_TX_MODE 0x2
#define PPI_XFER_TYPE_11 0xC
@ -53,6 +124,40 @@
#define PPI_PACK_EN 0x80
#define PPI_POLS_1 0x8000
#ifdef CONFIG_MK_BF527_EZKIT_REV_2_1
static struct spi_slave *slave;
static int lq035q1_control(unsigned char reg, unsigned short value)
{
int ret;
u8 regs[3] = {LQ035_INDEX, 0, 0};
u8 data[3] = {LQ035_DATA, 0, 0};
u8 dummy[3];
regs[2] = reg;
data[1] = value >> 8;
data[2] = value & 0xFF;
if (!slave) {
/* FIXME: Verify the max SCK rate */
slave = spi_setup_slave(CONFIG_LQ035Q1_SPI_BUS,
CONFIG_LQ035Q1_SPI_CS, 20000000,
SPI_MODE_3);
if (!slave)
return -1;
}
if (spi_claim_bus(slave))
return -1;
ret = spi_xfer(slave, 24, regs, dummy, SPI_XFER_BEGIN | SPI_XFER_END);
ret |= spi_xfer(slave, 24, data, dummy, SPI_XFER_BEGIN | SPI_XFER_END);
spi_release_bus(slave);
return ret;
}
#endif
/* enable and disable PPI functions */
void EnablePPI(void)
{
@ -80,7 +185,7 @@ void Init_PPI(void)
*pPPI_DELAY = H_START;
*pPPI_COUNT = (H_ACTPIX-1);
*pPPI_FRAME = 0;
*pPPI_FRAME = V_LINES;
/* PPI control, to be replaced with definitions */
*pPPI_CONTROL = PPI_TX_MODE | /* output mode , PORT_DIR */
@ -188,9 +293,20 @@ void DisableTIMER1(void)
SSYNC();
}
void EnableTIMER12(void)
{
*pTIMER_ENABLE |= TIMEN1 | TIMEN0;
SSYNC();
}
int video_init(void *dst)
{
#ifdef CONFIG_MK_BF527_EZKIT_REV_2_1
lq035q1_control(LQ035_SHUT_CTL, LQ035_ON);
lq035q1_control(LQ035_DRIVER_OUTPUT_CTL, (CONFIG_LQ035Q1_LCD_MODE &
LQ035_DRIVER_OUTPUT_MASK) | LQ035_DRIVER_OUTPUT_DEFAULT);
#endif
Init_Ports();
Init_DMA(dst);
EnableDMA();
@ -199,6 +315,9 @@ int video_init(void *dst)
Init_PPI();
EnablePPI();
#ifdef CONFIG_MK_BF527_EZKIT_REV_2_1
EnableTIMER12();
#else
/* Frame sync 2 (VS) needs to start at least one PPI clk earlier */
EnableTIMER1();
/* Add Some Delay ... */
@ -209,6 +328,7 @@ int video_init(void *dst)
/* now start frame sync 1 */
EnableTIMER0();
#endif
return 0;
}

7
board/bf533-ezkit/bf533-ezkit.c
View file

@ -39,13 +39,6 @@ int checkboard(void)
return 0;
}
phys_size_t initdram(int board_type)
{
gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
return gd->bd->bi_memsize;
}
/* miscellaneous platform dependent initialisations */
int misc_init_r(void)
{

1
board/bf533-stamp/Makefile
View file

@ -30,6 +30,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS-y := $(BOARD).o
COBJS-$(CONFIG_STAMP_CF) += ide-cf.o
COBJS-$(CONFIG_VIDEO) += video.o
SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)

120
board/bf533-stamp/bf533-stamp.c
View file

@ -39,13 +39,6 @@ int checkboard(void)
return 0;
}
phys_size_t initdram(int board_type)
{
gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
return gd->bd->bi_memsize;
}
/* PF0 and PF1 are used to switch between the ethernet and flash:
* PF0 PF1
* flash: 0 0
@ -69,118 +62,11 @@ void swap_to(int device_id)
/* miscellaneous platform dependent initialisations */
int misc_init_r(void)
{
int i;
int cf_stat = 0;
/* Check whether CF card is inserted */
*pFIO_EDGE = FIO_EDGE_CF_BITS;
*pFIO_POLAR = FIO_POLAR_CF_BITS;
for (i = 0; i < 0x300; i++)
asm("nop;");
if ((*pFIO_FLAG_S) & CF_STAT_BITS) {
cf_stat = 0;
} else {
cf_stat = 1;
}
*pFIO_EDGE = FIO_EDGE_BITS;
*pFIO_POLAR = FIO_POLAR_BITS;
if (cf_stat) {
printf("Booting from COMPACT flash\n");
for (i = 0; i < 0x1000; i++)
asm("nop;");
for (i = 0; i < 0x1000; i++)
asm("nop;");
for (i = 0; i < 0x1000; i++)
asm("nop;");
serial_setbrg();
ide_init();
setenv("bootargs", "");
setenv("bootcmd",
"fatload ide 0:1 0x1000000 uImage-stamp;bootm 0x1000000;bootm 0x20100000");
} else {
printf("Booting from FLASH\n");
}
return 0;
}
#ifdef CONFIG_STAMP_CF
cf_ide_init();
#endif
#ifdef CONFIG_STAMP_CF
void cf_outb(unsigned char val, volatile unsigned char *addr)
{
/*
* Set PF1 PF0 respectively to 0 1 to divert address
* to the expansion memory banks
*/
*pFIO_FLAG_S = CF_PF0;
*pFIO_FLAG_C = CF_PF1;
SSYNC();
*(addr) = val;
SSYNC();
/* Setback PF1 PF0 to 0 0 to address external
* memory banks */
*(volatile unsigned short *)pFIO_FLAG_C = CF_PF1_PF0;
SSYNC();
}
unsigned char cf_inb(volatile unsigned char *addr)
{
volatile unsigned char c;
*pFIO_FLAG_S = CF_PF0;
*pFIO_FLAG_C = CF_PF1;
SSYNC();
c = *(addr);
SSYNC();
*pFIO_FLAG_C = CF_PF1_PF0;
SSYNC();
return c;
}
void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words)
{
int i;
*pFIO_FLAG_S = CF_PF0;
*pFIO_FLAG_C = CF_PF1;
SSYNC();
for (i = 0; i < words; i++) {
*(sect_buf + i) = *(addr);
SSYNC();
}
*pFIO_FLAG_C = CF_PF1_PF0;
SSYNC();
}
void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words)
{
int i;
*pFIO_FLAG_S = CF_PF0;
*pFIO_FLAG_C = CF_PF1;
SSYNC();
for (i = 0; i < words; i++) {
*(addr) = *(sect_buf + i);
SSYNC();
}
*pFIO_FLAG_C = CF_PF1_PF0;
SSYNC();
return 0;
}
#endif

90
board/bf533-stamp/ide-cf.c Normal file
View file

@ -0,0 +1,90 @@
/*
* CF IDE addon card code
*
* Enter bugs at http://blackfin.uclinux.org/
*
* Copyright (c) 2005-2009 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#include <common.h>
#include <config.h>
#include <asm/blackfin.h>
#include "bf533-stamp.h"
void cf_outb(unsigned char val, volatile unsigned char *addr)
{
/* "ETHERNET" means the expansion memory banks */
swap_to(ETHERNET);
*addr = val;
SSYNC();
swap_to(FLASH);
}
unsigned char cf_inb(volatile unsigned char *addr)
{
unsigned char c;
swap_to(ETHERNET);
c = *addr;
SSYNC();
swap_to(FLASH);
return c;
}
void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words)
{
int i;
swap_to(ETHERNET);
for (i = 0; i < words; i++) {
*(sect_buf + i) = *addr;
SSYNC();
}
swap_to(FLASH);
}
void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words)
{
int i;
swap_to(ETHERNET);
for (i = 0; i < words; i++) {
*addr = *(sect_buf + i);
SSYNC();
}
swap_to(FLASH);
}
void cf_ide_init(void)
{
int i, cf_stat;
/* Check whether CF card is inserted */
bfin_write_FIO_EDGE(FIO_EDGE_CF_BITS);
bfin_write_FIO_POLAR(FIO_POLAR_CF_BITS);
for (i = 0; i < 0x300; i++)
asm volatile("nop;");
cf_stat = bfin_read_FIO_FLAG_S() & CF_STAT_BITS;
bfin_write_FIO_EDGE(FIO_EDGE_BITS);
bfin_write_FIO_POLAR(FIO_POLAR_BITS);
if (!cf_stat) {
for (i = 0; i < 0x3000; i++)
asm volatile("nop;");
ide_init();
}
}

7
board/bf537-minotaur/bf537-minotaur.c
View file

@ -23,13 +23,6 @@ int checkboard(void)
return 0;
}
phys_size_t initdram(int board_type)
{
gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
return gd->bd->bi_memsize;
}
#ifdef CONFIG_BFIN_MAC
static void board_init_enetaddr(uchar *mac_addr)
{

7
board/bf537-pnav/bf537-pnav.c
View file

@ -23,13 +23,6 @@ int checkboard(void)
return 0;
}
phys_size_t initdram(int board_type)
{
gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
return gd->bd->bi_memsize;
}
#ifdef CONFIG_BFIN_MAC
static void board_init_enetaddr(uchar *mac_addr)
{

7
board/bf537-srv1/bf537-srv1.c
View file

@ -23,13 +23,6 @@ int checkboard(void)
return 0;
}
phys_size_t initdram(int board_type)
{
gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
return gd->bd->bi_memsize;
}
#ifdef CONFIG_BFIN_MAC
static void board_init_enetaddr(uchar *mac_addr)
{

7
board/bf537-stamp/bf537-stamp.c
View file

@ -43,13 +43,6 @@ int checkboard(void)
return 0;
}
phys_size_t initdram(int board_type)
{
gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
return gd->bd->bi_memsize;
}
void board_reset(void)
{
/* workaround for weak pull ups on ssel */

7
board/bf538f-ezkit/bf538f-ezkit.c
View file

@ -20,13 +20,6 @@ int checkboard(void)
return 0;
}
phys_size_t initdram(int board_type)
{
gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
return gd->bd->bi_memsize;
}
#ifdef CONFIG_SMC91111
int board_eth_init(bd_t *bis)
{

31
board/bf548-ezkit/bf548-ezkit.c
View file

@ -11,6 +11,7 @@
#include <config.h>
#include <command.h>
#include <asm/blackfin.h>
#include <asm/sdh.h>
DECLARE_GLOBAL_DATA_PTR;
@ -21,13 +22,6 @@ int checkboard(void)
return 0;
}
phys_size_t initdram(int board_type)
{
gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
return gd->bd->bi_memsize;
}
int board_early_init_f(void)
{
/* Port H: PH8 - PH13 == A4 - A9
@ -85,3 +79,26 @@ int board_eth_init(bd_t *bis)
return smc911x_initialize(0, CONFIG_SMC911X_BASE);
}
#endif
#ifdef CONFIG_BFIN_SDH
int board_mmc_init(bd_t *bis)
{
return bfin_mmc_init(bis);
}
#endif
#ifdef CONFIG_USB_BLACKFIN
void board_musb_init(void)
{
/*
* Rev 1.0 BF549 EZ-KITs require PE7 to be high for both device
* and OTG host modes, while rev 1.1 and greater require PE7 to
* be low for device mode and high for host mode. We set it high
* here because we are in host mode.
*/
bfin_write_PORTE_FER(bfin_read_PORTE_FER() & ~PE7);
bfin_write_PORTE_DIR_SET(PE7);
bfin_write_PORTE_SET(PE7);
SSYNC();
}
#endif

56
board/bf561-acvilon/Makefile Normal file
View file

@ -0,0 +1,56 @@
#
# U-boot - Makefile
#
# Copyright (c) 2005-2007 Analog Device Inc.
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2009 CJSC "NII STT", Russia, Smolensk
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS-y := $(BOARD).o
SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
SOBJS := $(addprefix $(obj),$(SOBJS-y))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

51
board/bf561-acvilon/bf561-acvilon.c Normal file
View file

@ -0,0 +1,51 @@
/*
* File: board/bf561-acvilon/bf561-acvilon.c
* Based on: board/bf561-ezkit/bf561-ezkit.c
* Author:
*
* Created: 2009-06-23
* Description: Acvilon System On Module board file
*
* Modified:
* Copyright 2009 CJSC "NII STT", http://www.niistt.ru/
* Copyright (c) 2005-2008 Analog Devices Inc.
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Bugs:
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, see the file COPYING, or write
* to the Free Software Foundation, Inc.,
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <common.h>
#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
int checkboard(void)
{
printf("Board: CJSC \"NII STT\"-=Acvilon Platform=- [U-Boot]\n");
printf(" Support: http://www.niistt.ru/\n");
return 0;
}
#ifdef CONFIG_SMC911X
int board_eth_init(bd_t *bis)
{
return smc911x_initialize(0, CONFIG_SMC911X_BASE);
}
#endif

34
board/bf561-acvilon/config.mk Normal file
View file

@ -0,0 +1,34 @@
#
# Copyright (c) 2005-2008 Analog Device Inc.
#
# (C) Copyright 2001
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
# This is not actually used for Blackfin boards so do not change it
#TEXT_BASE = do-not-use-me
CFLAGS_lib_generic += -O2
CFLAGS_lzma += -O2
# Set some default LDR flags based on boot mode.
LDR_FLAGS-BFIN_BOOT_PARA := --bits 16
LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))

7
board/bf561-ezkit/bf561-ezkit.c
View file

@ -38,13 +38,6 @@ int checkboard(void)
return 0;
}
phys_size_t initdram(int board_type)
{
gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
return gd->bd->bi_memsize;
}
#ifdef CONFIG_SMC91111
int board_eth_init(bd_t *bis)
{

7
board/blackstamp/blackstamp.c
View file

@ -24,13 +24,6 @@ int checkboard(void)
return 0;
}
phys_size_t initdram(int board_type)
{
gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
return gd->bd->bi_memsize;
}
#ifdef SHARED_RESOURCES
void swap_to(int device_id)
{

7
board/cm-bf527/cm-bf527.c
View file

@ -24,13 +24,6 @@ int checkboard(void)
return 0;
}
phys_size_t initdram(int board_type)
{
gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
return gd->bd->bi_memsize;
}
#ifdef CONFIG_BFIN_MAC
static void board_init_enetaddr(uchar *mac_addr)
{

7
board/cm-bf533/cm-bf533.c
View file

@ -18,13 +18,6 @@ int checkboard(void)
return 0;
}
phys_size_t initdram(int board_type)
{
gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
return gd->bd->bi_memsize;
}
#ifdef CONFIG_SMC91111
int board_eth_init(bd_t *bis)
{

7
board/cm-bf537e/cm-bf537e.c
View file

@ -24,13 +24,6 @@ int checkboard(void)
return 0;
}
phys_size_t initdram(int board_type)
{
gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
return gd->bd->bi_memsize;
}
#ifdef CONFIG_BFIN_MAC
static void board_init_enetaddr(uchar *mac_addr)
{

7
board/cm-bf537u/cm-bf537u.c
View file

@ -24,13 +24,6 @@ int checkboard(void)
return 0;
}
phys_size_t initdram(int board_type)
{
gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
return gd->bd->bi_memsize;
}
#ifdef CONFIG_BFIN_MAC
static void board_init_enetaddr(uchar *mac_addr)
{

7
board/cm-bf548/cm-bf548.c
View file

@ -21,13 +21,6 @@ int checkboard(void)
return 0;
}
phys_size_t initdram(int board_type)
{
gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
return gd->bd->bi_memsize;
}
int board_early_init_f(void)
{
/* Port H: PH8 - PH13 == A4 - A9

7
board/cm-bf561/cm-bf561.c
View file

@ -18,13 +18,6 @@ int checkboard(void)
return 0;
}
phys_size_t initdram(int board_type)
{
gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
return gd->bd->bi_memsize;
}
#ifdef CONFIG_SMC91111
int board_eth_init(bd_t *bis)
{

6
board/freescale/mpc8536ds/mpc8536ds.c
View file

@ -226,7 +226,7 @@ void pci_init_board(void)
SET_STD_PCIE_INFO(pci_info[num], 3);
pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
printf (" PCIE3 connected to Slot3 as %s (base address %lx)\n",
pcie_ep ? "End Point" : "Root Complex",
pcie_ep ? "Endpoint" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie3_hose, first_free_busno);
@ -246,7 +246,7 @@ void pci_init_board(void)
SET_STD_PCIE_INFO(pci_info[num], 1);
pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
printf (" PCIE1 connected to Slot1 as %s (base address %lx)\n",
pcie_ep ? "End Point" : "Root Complex",
pcie_ep ? "Endpoint" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie1_hose, first_free_busno);
@ -266,7 +266,7 @@ void pci_init_board(void)
SET_STD_PCIE_INFO(pci_info[num], 2);
pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
printf (" PCIE2 connected to Slot 2 as %s (base address %lx)\n",
pcie_ep ? "End Point" : "Root Complex",
pcie_ep ? "Endpoint" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie2_hose, first_free_busno);

6
board/freescale/mpc8544ds/mpc8544ds.c
View file

@ -144,7 +144,7 @@ void pci_init_board(void)
pcie3_hose.region_count = 1;
#endif
printf (" PCIE3 connected to ULI as %s (base addr %lx)\n",
pcie_ep ? "End Point" : "Root Complex",
pcie_ep ? "Endpoint" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie3_hose, first_free_busno);
@ -179,7 +179,7 @@ void pci_init_board(void)
pcie1_hose.region_count = 1;
#endif
printf (" PCIE1 connected to Slot 2 as %s (base addr %lx)\n",
pcie_ep ? "End Point" : "Root Complex",
pcie_ep ? "Endpoint" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
@ -210,7 +210,7 @@ void pci_init_board(void)
pcie2_hose.region_count = 1;
#endif
printf (" PCIE2 connected to Slot 1 as %s (base addr %lx)\n",
pcie_ep ? "End Point" : "Root Complex",
pcie_ep ? "Endpoint" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie2_hose, first_free_busno);

2
board/freescale/mpc8548cds/mpc8548cds.c
View file

@ -343,7 +343,7 @@ void pci_init_board(void)
SET_STD_PCIE_INFO(pci_info[num], 1);
pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
printf (" PCIE1 connected to Slot as %s (base addr %lx)\n",
pcie_ep ? "End Point" : "Root Complex",
pcie_ep ? "Endpoint" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],

2
board/freescale/mpc8568mds/mpc8568mds.c
View file

@ -408,7 +408,7 @@ void pci_init_board(void)
SET_STD_PCIE_INFO(pci_info[num], 1);
pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
printf (" PCIE1 connected to Slot as %s (base addr %lx)\n",
pcie_ep ? "End Point" : "Root Complex",
pcie_ep ? "Endpoint" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],

2
board/freescale/mpc8569mds/mpc8569mds.c
View file

@ -552,7 +552,7 @@ void pci_init_board(void)
SET_STD_PCIE_INFO(pci_info[num], 1);
pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
printf (" PCIE1 connected to Slot as %s (base addr %lx)\n",
pcie_ep ? "End Point" : "Root Complex",
pcie_ep ? "Endpoint" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie1_hose, first_free_busno);

6
board/freescale/mpc8572ds/mpc8572ds.c
View file

@ -194,7 +194,7 @@ void pci_init_board(void)
SET_STD_PCIE_INFO(pci_info[num], 3);
pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
printf (" PCIE3 connected to ULI as %s (base addr %lx)\n",
pcie_ep ? "End Point" : "Root Complex",
pcie_ep ? "Endpoint" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie3_hose, first_free_busno);
@ -226,7 +226,7 @@ void pci_init_board(void)
SET_STD_PCIE_INFO(pci_info[num], 2);
pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
printf (" PCIE2 connected to Slot 1 as %s (base addr %lx)\n",
pcie_ep ? "End Point" : "Root Complex",
pcie_ep ? "Endpoint" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie2_hose, first_free_busno);
@ -246,7 +246,7 @@ void pci_init_board(void)
SET_STD_PCIE_INFO(pci_info[num], 1);
pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
printf (" PCIE1 connected to Slot 2 as %s (base addr %lx)\n",
pcie_ep ? "End Point" : "Root Complex",
pcie_ep ? "Endpoint" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie1_hose, first_free_busno);

4
board/freescale/mpc8610hpcd/mpc8610hpcd.c
View file

@ -249,7 +249,7 @@ void pci_init_board(void)
SET_STD_PCIE_INFO(pci_info[num], 1);
pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
printf (" PCIE1 connected to ULI as %s (base addr %lx)\n",
pcie_ep ? "End Point" : "Root Complex",
pcie_ep ? "Endpoint" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
@ -270,7 +270,7 @@ void pci_init_board(void)
SET_STD_PCIE_INFO(pci_info[num], 2);
pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
printf (" PCIE2 connected to Slot as %s (base addr %lx)\n",
pcie_ep ? "End Point" : "Root Complex",
pcie_ep ? "Endpoint" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie2_hose, first_free_busno);

4
board/freescale/p1_p2_rdb/pci.c
View file

@ -66,7 +66,7 @@ void pci_init_board(void)
SET_STD_PCIE_INFO(pci_info[num], 2);
pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
printf(" PCIE2 connected to Slot 1 as %s (base addr %lx)\n",
pcie_ep ? "End Point" : "Root Complex",
pcie_ep ? "Endpoint" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie2_hose, first_free_busno);
@ -85,7 +85,7 @@ void pci_init_board(void)
SET_STD_PCIE_INFO(pci_info[num], 1);
pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
printf(" PCIE1 connected to Slot 2 as %s (base addr %lx)\n",
pcie_ep ? "End Point" : "Root Complex",
pcie_ep ? "Endpoint" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie1_hose, first_free_busno);

6
board/freescale/p2020ds/p2020ds.c
View file

@ -222,7 +222,7 @@ void pci_init_board(void)
SET_STD_PCIE_INFO(pci_info[num], 2);
pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
printf(" PCIE2 connected to ULI as %s (base addr %lx)\n",
pcie_ep ? "End Point" : "Root Complex",
pcie_ep ? "Endpoint" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie2_hose, first_free_busno);
@ -262,7 +262,7 @@ void pci_init_board(void)
SET_STD_PCIE_INFO(pci_info[num], 3);
pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
printf(" PCIE3 connected to Slot 1 as %s (base addr %lx)\n",
pcie_ep ? "End Point" : "Root Complex",
pcie_ep ? "Endpoint" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie3_hose, first_free_busno);
@ -281,7 +281,7 @@ void pci_init_board(void)
SET_STD_PCIE_INFO(pci_info[num], 1);
pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
printf(" PCIE1 connected to Slot 2 as %s (base addr %lx)\n",
pcie_ep ? "End Point" : "Root Complex",
pcie_ep ? "Endpoint" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie1_hose, first_free_busno);

7
board/ibf-dsp561/ibf-dsp561.c
View file

@ -16,10 +16,3 @@ int checkboard(void)
printf(" Support: http://www.i-syst.com/\n");
return 0;
}
phys_size_t initdram(int board_type)
{
gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
return gd->bd->bi_memsize;
}

45
board/keymile/km8xx/km8xx.c
View file

@ -147,7 +147,9 @@ phys_size_t initdram (int board_type)
int board_early_init_r(void)
{
/* setup the UPIOx */
out_8((u8 *)(CONFIG_SYS_PIGGY_BASE + 0x02), 0xc0);
/* General Unit Reset disabled, Flash Bank enabled, UnitLed on */
out_8((u8 *)(CONFIG_SYS_PIGGY_BASE + 0x02), 0xc2);
/* SCC4 enable, halfduplex, FCC1 powerdown, ANDI enable*/
out_8((u8 *)(CONFIG_SYS_PIGGY_BASE + 0x03), 0x35);
return 0;
}
@ -160,51 +162,12 @@ int hush_init_var (void)
#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
/*
* update "memory" property in the blob
* update "brg" property in the blob
*/
void ft_blob_update (void *blob, bd_t *bd)
{
ulong brg_data[1] = {0};
ulong memory_data[2] = {0};
ulong *flash_data = NULL;
ulong flash_reg[3] = {0};
flash_info_t *info;
int len;
int i = 0;
memory_data[0] = cpu_to_be32 (bd->bi_memstart);
memory_data[1] = cpu_to_be32 (bd->bi_memsize);
fdt_set_node_and_value (blob, "/memory", "reg", memory_data,
sizeof (memory_data));
len = fdt_get_node_and_value (blob, "/localbus", "ranges",
(void *)&flash_data);
if (flash_data == NULL) {
printf ("%s: error /localbus/ranges entry\n", __FUNCTION__);
return;
}
/* update Flash addr, size */
while ( i < (len / 4)) {
switch (flash_data[i]) {
case 0:
info = flash_get_info(CONFIG_SYS_FLASH_BASE);
flash_data[i + 1] = 0;
flash_data[i + 2] = cpu_to_be32 (CONFIG_SYS_FLASH_BASE);
flash_data[i + 3] = cpu_to_be32 (info->size);
break;
default:
break;
}
i += 4;
}
fdt_set_node_and_value (blob, "/localbus", "ranges", flash_data,
len);
flash_reg[2] = cpu_to_be32 (bd->bi_flashsize);
fdt_set_node_and_value (blob, "/localbus/flash@0,0", "reg", flash_reg,
sizeof (flash_reg));
/* BRG */
brg_data[0] = cpu_to_be32 (bd->bi_busfreq);
fdt_set_node_and_value (blob, "/soc/cpm", "brg-frequency", brg_data,

50
board/keymile/kmeter1/kmeter1.c
View file

@ -99,6 +99,10 @@ int board_early_init_r (void)
}
/* enable the PHY on the PIGGY */
setbits (8, (void *)(CONFIG_SYS_PIGGY_BASE + 0x10003), 0x01);
/* enable the Unit LED (green) */
setbits (8, (void *)(CONFIG_SYS_PIGGY_BASE + 0x00002), 0x01);
/* take FE/GbE PHYs out of reset */
setbits (8, (void *)(CONFIG_SYS_PIGGY_BASE + 0x0000f), 0x1c);
return 0;
}
@ -188,53 +192,11 @@ int checkboard (void)
#if defined(CONFIG_OF_BOARD_SETUP)
/*
* update "/localbus/ranges" property in the blob
* update property in the blob
*/
void ft_blob_update (void *blob, bd_t *bd)
{
ulong *flash_data = NULL;
flash_info_t *info;
ulong flash_reg[6] = {0};
int len;
int size = 0;
int i = 0;
len = fdt_get_node_and_value (blob, "/localbus", "ranges",
(void *)&flash_data);
if (flash_data == NULL) {
printf ("%s: error /localbus/ranges entry\n", __FUNCTION__);
return;
}
/* update Flash addr, size */
while ( i < (len / 4)) {
switch (flash_data[i]) {
case 0:
info = flash_get_info(CONFIG_SYS_FLASH_BASE);
size = info->size;
info = flash_get_info(CONFIG_SYS_FLASH_BASE_1);
size += info->size;
flash_data[i + 1] = 0;
flash_data[i + 2] = cpu_to_be32 (CONFIG_SYS_FLASH_BASE);
flash_data[i + 3] = cpu_to_be32 (size);
break;
default:
break;
}
i += 4;
}
fdt_set_node_and_value (blob, "/localbus", "ranges", flash_data,
len);
info = flash_get_info(CONFIG_SYS_FLASH_BASE);
size = info->size;
flash_reg[2] = cpu_to_be32 (size);
flash_reg[4] = flash_reg[2];
info = flash_get_info(CONFIG_SYS_FLASH_BASE_1);
flash_reg[5] = cpu_to_be32 (info->size);
fdt_set_node_and_value (blob, "/localbus/flash@f0000000,0", "reg", flash_reg,
sizeof (flash_reg));
/* no board specific update */
}

62
board/keymile/mgcoge/mgcoge.c
View file

@ -299,7 +299,9 @@ int checkboard(void)
int board_early_init_r (void)
{
/* setup the UPIOx */
out_8((u8 *)(CONFIG_SYS_PIGGY_BASE + 0x02), 0xc0);
/* General Unit Reset disabled, Flash Bank enabled, UnitLed on */
out_8((u8 *)(CONFIG_SYS_PIGGY_BASE + 0x02), 0xc2);
/* SCC4 enable, halfduplex, FCC1 powerdown */
out_8((u8 *)(CONFIG_SYS_PIGGY_BASE + 0x03), 0x15);
return 0;
}
@ -311,66 +313,8 @@ int hush_init_var (void)
}
#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
/*
* update "flash" property in the blob
*/
void ft_blob_update (void *blob, bd_t *bd)
{
ulong *flash_data = NULL;
ulong flash_reg[6] = {0};
flash_info_t *info;
int len;
int size;
int i = 0;
len = fdt_get_node_and_value (blob, "/localbus", "ranges",
(void *)&flash_data);
if (flash_data == NULL) {
printf ("%s: error /localbus/ranges entry\n", __FUNCTION__);
return;
}
/* update Flash addr, size */
while ( i < (len / 4)) {
switch (flash_data[i]) {
case 0:
info = flash_get_info(CONFIG_SYS_FLASH_BASE);
flash_data[i + 1] = 0;
flash_data[i + 2] = cpu_to_be32 (CONFIG_SYS_FLASH_BASE);
flash_data[i + 3] = cpu_to_be32 (info->size);
break;
case 5:
info = flash_get_info(CONFIG_SYS_FLASH_BASE_1);
size = info->size;
info = flash_get_info(CONFIG_SYS_FLASH_BASE_2);
size += info->size;
flash_data[i + 1] = 0;
flash_data[i + 2] = cpu_to_be32 (CONFIG_SYS_FLASH_BASE_1);
flash_data[i + 3] = cpu_to_be32 (size);
break;
default:
break;
}
i += 4;
}
fdt_set_node_and_value (blob, "/localbus", "ranges", flash_data,
len);
info = flash_get_info(CONFIG_SYS_FLASH_BASE_1);
flash_reg[0] = cpu_to_be32 (5);
flash_reg[2] = cpu_to_be32 (info->size);
flash_reg[3] = flash_reg[0];
flash_reg[4] = flash_reg[2];
info = flash_get_info(CONFIG_SYS_FLASH_BASE_2);
flash_reg[5] = cpu_to_be32 (info->size);
fdt_set_node_and_value (blob, "/localbus/flash@5,0", "reg", flash_reg,
sizeof (flash_reg));
}
void ft_board_setup (void *blob, bd_t *bd)
{
ft_cpu_setup (blob, bd);
ft_blob_update (blob, bd);
}
#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */

54
board/tcm-bf518/Makefile Normal file
View file

@ -0,0 +1,54 @@
#
# U-boot - Makefile
#
# Copyright (c) 2005-2008 Analog Device Inc.
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS-y := $(BOARD).o
SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
SOBJS := $(addprefix $(obj),$(SOBJS-y))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

33
board/tcm-bf518/config.mk Normal file
View file

@ -0,0 +1,33 @@
#
# Copyright (c) 2005-2008 Analog Device Inc.
#
# (C) Copyright 2001
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
# This is not actually used for Blackfin boards so do not change it
#TEXT_BASE = do-not-use-me
CFLAGS_lib_generic += -O2
CFLAGS_lzma += -O2
# Set some default LDR flags based on boot mode.
LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))

78
board/tcm-bf518/tcm-bf518.c Normal file
View file

@ -0,0 +1,78 @@
/*
* U-boot - main board file
*
* Copyright (c) 2008-2009 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#include <common.h>
#include <config.h>
#include <net.h>
#include <netdev.h>
#include <asm/blackfin.h>
#include <asm/net.h>
#include <asm/mach-common/bits/otp.h>
#include <asm/sdh.h>
int checkboard(void)
{
printf("Board: Bluetechnix TCM-BF518 board\n");
printf(" Support: http://www.bluetechnix.com/\n");
printf(" http://blackfin.uclinux.org/\n");
return 0;
}
#if defined(CONFIG_BFIN_MAC)
static void board_init_enetaddr(uchar *mac_addr)
{
bool valid_mac = false;
#if 0
/* the MAC is stored in OTP memory page 0xDF */
uint32_t ret;
uint64_t otp_mac;
ret = bfrom_OtpRead(0xDF, OTP_LOWER_HALF, &otp_mac);
if (!(ret & OTP_MASTER_ERROR)) {
uchar *otp_mac_p = (uchar *)&otp_mac;
for (ret = 0; ret < 6; ++ret)
mac_addr[ret] = otp_mac_p[5 - ret];
if (is_valid_ether_addr(mac_addr))
valid_mac = true;
}
#endif
if (!valid_mac) {
puts("Warning: Generating 'random' MAC address\n");
bfin_gen_rand_mac(mac_addr);
}
eth_setenv_enetaddr("ethaddr", mac_addr);
}
int board_eth_init(bd_t *bis)
{
return bfin_EMAC_initialize(bis);
}
#endif
int misc_init_r(void)
{
#ifdef CONFIG_BFIN_MAC
uchar enetaddr[6];
if (!eth_getenv_enetaddr("ethaddr", enetaddr))
board_init_enetaddr(enetaddr);
#endif
return 0;
}
#ifdef CONFIG_BFIN_SDH
int board_mmc_init(bd_t *bis)
{
return bfin_mmc_init(bis);
}
#endif

7
board/tcm-bf537/tcm-bf537.c
View file

@ -24,13 +24,6 @@ int checkboard(void)
return 0;
}
phys_size_t initdram(int board_type)
{
gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
return gd->bd->bi_memsize;
}
#ifdef CONFIG_BFIN_MAC
static void board_init_enetaddr(uchar *mac_addr)
{

2
board/tqc/tqm85xx/tqm85xx.c
View file

@ -636,7 +636,7 @@ static inline void init_pcie1(void)
if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
printf ("PCIe: %s, base address %x",
pcie_ep ? "End point" : "Root complex", (uint)pci);
pcie_ep ? "Endpoint" : "Root complex", (uint)pci);
if (pci->pme_msg_det) {
pci->pme_msg_det = 0xffffffff;

6
board/xes/common/fsl_8xxx_pci.c
View file

@ -256,7 +256,7 @@ void pci_init_board(void)
if (width && !(devdisr & MPC8xxx_DEVDISR_PCIE1)) {
printf("\n PCIE1 connected as %s (x%d)",
host ? "Root Complex" : "End Point", width);
host ? "Root Complex" : "Endpoint", width);
if (in_be32(&pci->pme_msg_det)) {
out_be32(&pci->pme_msg_det, 0xffffffff);
debug(" with errors. Clearing. Now 0x%08x",
@ -305,7 +305,7 @@ void pci_init_board(void)
if (width && !(devdisr & MPC8xxx_DEVDISR_PCIE2)) {
printf("\n PCIE2 connected as %s (x%d)",
host ? "Root Complex" : "End Point", width);
host ? "Root Complex" : "Endpoint", width);
if (in_be32(&pci->pme_msg_det)) {
out_be32(&pci->pme_msg_det, 0xffffffff);
debug(" with errors. Clearing. Now 0x%08x",
@ -354,7 +354,7 @@ void pci_init_board(void)
if (width && !(devdisr & MPC8xxx_DEVDISR_PCIE3)) {
printf("\n PCIE3 connected as %s (x%d)",
host ? "Root Complex" : "End Point", width);
host ? "Root Complex" : "Endpoint", width);
if (in_be32(&pci->pme_msg_det)) {
out_be32(&pci->pme_msg_det, 0xffffffff);
debug(" with errors. Clearing. Now 0x%08x",

3
common/Makefile
View file

@ -105,6 +105,7 @@ COBJS-$(CONFIG_CMD_IMMAP) += cmd_immap.o
COBJS-$(CONFIG_CMD_IRQ) += cmd_irq.o
COBJS-$(CONFIG_CMD_ITEST) += cmd_itest.o
COBJS-$(CONFIG_CMD_JFFS2) += cmd_jffs2.o
COBJS-$(CONFIG_CMD_CRAMFS) += cmd_cramfs.o
COBJS-$(CONFIG_CMD_LICENSE) += cmd_license.o
COBJS-y += cmd_load.o
COBJS-$(CONFIG_LOGBUFFER) += cmd_log.o
@ -157,7 +158,7 @@ COBJS-$(CONFIG_DDR_SPD) += ddr_spd.o
COBJS-$(CONFIG_HWCONFIG) += hwconfig.o
COBJS-$(CONFIG_CONSOLE_MUX) += iomux.o
COBJS-y += flash.o
COBJS-$(CONFIG_CMD_KGDB) += kgdb.o
COBJS-$(CONFIG_CMD_KGDB) += kgdb.o kgdb_stubs.o
COBJS-$(CONFIG_KALLSYMS) += kallsyms.o
COBJS-$(CONFIG_LCD) += lcd.o
COBJS-$(CONFIG_LYNXKDI) += lynxkdi.o

10
common/cmd_bootm.c
View file

@ -105,10 +105,6 @@ extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
typedef int boot_os_fn (int flag, int argc, char *argv[],
bootm_headers_t *images); /* pointers to os/initrd/fdt */
#define CONFIG_BOOTM_LINUX 1
#define CONFIG_BOOTM_NETBSD 1
#define CONFIG_BOOTM_RTEMS 1
#ifdef CONFIG_BOOTM_LINUX
extern boot_os_fn do_bootm_linux;
#endif
@ -297,7 +293,8 @@ static int bootm_start(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
return 1;
}
if (images.os.os == IH_OS_LINUX) {
if ((images.os.type == IH_TYPE_KERNEL) &&
(images.os.os == IH_OS_LINUX)) {
/* find ramdisk */
ret = boot_get_ramdisk (argc, argv, &images, IH_INITRD_ARCH,
&images.rd_start, &images.rd_end);
@ -888,9 +885,6 @@ static void *boot_get_kernel (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]
image_multi_getimg (hdr, 0, os_data, os_len);
break;
case IH_TYPE_STANDALONE:
if (argc >2) {
hdr->ih_load = htonl(simple_strtoul(argv[2], NULL, 16));
}
*os_data = image_get_data (hdr);
*os_len = image_get_data_size (hdr);
break;

216
common/cmd_cramfs.c Normal file
View file

@ -0,0 +1,216 @@
/*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* based on: cmd_jffs2.c
*
* Add support for a CRAMFS located in RAM
*/
/*
* CRAMFS support
*/
#include <common.h>
#include <command.h>
#include <malloc.h>
#include <linux/list.h>
#include <linux/ctype.h>
#include <jffs2/jffs2.h>
#include <jffs2/load_kernel.h>
#include <cramfs/cramfs_fs.h>
/* enable/disable debugging messages */
#define DEBUG_CRAMFS
#undef DEBUG_CRAMFS
#ifdef DEBUG_CRAMFS
# define DEBUGF(fmt, args...) printf(fmt ,##args)
#else
# define DEBUGF(fmt, args...)
#endif
#ifdef CONFIG_CRAMFS_CMDLINE
flash_info_t flash_info[1];
#ifndef CONFIG_CMD_JFFS2
#include <linux/stat.h>
char *mkmodestr(unsigned long mode, char *str)
{
static const char *l = "xwr";
int mask = 1, i;
char c;
switch (mode & S_IFMT) {
case S_IFDIR: str[0] = 'd'; break;
case S_IFBLK: str[0] = 'b'; break;
case S_IFCHR: str[0] = 'c'; break;
case S_IFIFO: str[0] = 'f'; break;
case S_IFLNK: str[0] = 'l'; break;
case S_IFSOCK: str[0] = 's'; break;
case S_IFREG: str[0] = '-'; break;
default: str[0] = '?';
}
for(i = 0; i < 9; i++) {
c = l[i%3];
str[9-i] = (mode & mask)?c:'-';
mask = mask<<1;
}
if(mode & S_ISUID) str[3] = (mode & S_IXUSR)?'s':'S';
if(mode & S_ISGID) str[6] = (mode & S_IXGRP)?'s':'S';
if(mode & S_ISVTX) str[9] = (mode & S_IXOTH)?'t':'T';
str[10] = '\0';
return str;
}
#endif /* CONFIG_CMD_JFFS2 */
extern int cramfs_check (struct part_info *info);
extern int cramfs_load (char *loadoffset, struct part_info *info, char *filename);
extern int cramfs_ls (struct part_info *info, char *filename);
extern int cramfs_info (struct part_info *info);
/***************************************************/
/* U-boot commands */
/***************************************************/
/**
* Routine implementing fsload u-boot command. This routine tries to load
* a requested file from cramfs filesystem at location 'cramfsaddr'.
* cramfsaddr is an evironment variable.
*
* @param cmdtp command internal data
* @param flag command flag
* @param argc number of arguments supplied to the command
* @param argv arguments list
* @return 0 on success, 1 otherwise
*/
int do_cramfs_load(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
char *filename;
int size;
ulong offset = load_addr;
struct part_info part;
struct mtd_device dev;
struct mtdids id;
ulong addr;
addr = simple_strtoul(getenv("cramfsaddr"), NULL, 16);
/* hack! */
/* cramfs_* only supports NOR flash chips */
/* fake the device type */
id.type = MTD_DEV_TYPE_NOR;
id.num = 0;
dev.id = &id;
part.dev = &dev;
/* fake the address offset */
part.offset = addr - flash_info[id.num].start[0];
/* pre-set Boot file name */
if ((filename = getenv("bootfile")) == NULL) {
filename = "uImage";
}
if (argc == 2) {
filename = argv[1];
}
if (argc == 3) {
offset = simple_strtoul(argv[1], NULL, 0);
load_addr = offset;
filename = argv[2];
}
size = 0;
if (cramfs_check(&part))
size = cramfs_load ((char *) offset, &part, filename);
if (size > 0) {
char buf[10];
printf("### CRAMFS load complete: %d bytes loaded to 0x%lx\n",
size, offset);
sprintf(buf, "%x", size);
setenv("filesize", buf);
} else {
printf("### CRAMFS LOAD ERROR<%x> for %s!\n", size, filename);
}
return !(size > 0);
}
/**
* Routine implementing u-boot ls command which lists content of a given
* directory at location 'cramfsaddr'.
* cramfsaddr is an evironment variable.
*
* @param cmdtp command internal data
* @param flag command flag
* @param argc number of arguments supplied to the command
* @param argv arguments list
* @return 0 on success, 1 otherwise
*/
int do_cramfs_ls(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
char *filename = "/";
int ret;
struct part_info part;
struct mtd_device dev;
struct mtdids id;
ulong addr;
addr = simple_strtoul(getenv("cramfsaddr"), NULL, 16);
/* hack! */
/* cramfs_* only supports NOR flash chips */
/* fake the device type */
id.type = MTD_DEV_TYPE_NOR;
id.num = 0;
dev.id = &id;
part.dev = &dev;
/* fake the address offset */
part.offset = addr - flash_info[id.num].start[0];
if (argc == 2)
filename = argv[1];
ret = 0;
if (cramfs_check(&part))
ret = cramfs_ls (&part, filename);
return ret ? 0 : 1;
}
/* command line only */
/***************************************************/
U_BOOT_CMD(
cramfsload, 3, 0, do_cramfs_load,
"cramfsload\t- load binary file from a filesystem image",
"[ off ] [ filename ]\n"
" - load binary file from address 'cramfsaddr'\n"
" with offset 'off'\n"
);
U_BOOT_CMD(
cramfsls, 2, 1, do_cramfs_ls,
"cramfsls\t- list files in a directory (default /)",
"[ directory ]\n"
" - list files in a directory.\n"
);
#endif /* #ifdef CONFIG_CRAMFS_CMDLINE */
/***************************************************/

14
common/cmd_eeprom.c
View file

@ -79,7 +79,7 @@ int do_eeprom ( cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
ulong cnt = simple_strtoul (argv[4], NULL, 16);
#endif /* CONFIG_SYS_I2C_MULTI_EEPROMS */
# ifndef CONFIG_SPI
# if !defined(CONFIG_SPI) || defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
eeprom_init ();
# endif /* !CONFIG_SPI */
@ -118,7 +118,7 @@ int do_eeprom ( cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
* 0x00000nxx for EEPROM address selectors and page number at n.
*/
#ifndef CONFIG_SPI
#if !defined(CONFIG_SPI) || defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
#if !defined(CONFIG_SYS_I2C_EEPROM_ADDR_LEN) || CONFIG_SYS_I2C_EEPROM_ADDR_LEN < 1 || CONFIG_SYS_I2C_EEPROM_ADDR_LEN > 2
#error CONFIG_SYS_I2C_EEPROM_ADDR_LEN must be 1 or 2
#endif
@ -176,7 +176,7 @@ int eeprom_read (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt
len = maxlen;
#endif
#ifdef CONFIG_SPI
#if defined(CONFIG_SPI) && !defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
spi_read (addr, alen, buffer, len);
#else
if (i2c_read (addr[0], offset, alen-1, buffer, len) != 0)
@ -272,7 +272,7 @@ int eeprom_write (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cn
len = maxlen;
#endif
#ifdef CONFIG_SPI
#if defined(CONFIG_SPI) && !defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
spi_write (addr, alen, buffer, len);
#else
#if defined(CONFIG_SYS_EEPROM_X40430)
@ -374,7 +374,7 @@ int eeprom_write (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cn
return rcode;
}
#ifndef CONFIG_SPI
#if !defined(CONFIG_SPI) || defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
int
eeprom_probe (unsigned dev_addr, unsigned offset)
{
@ -403,7 +403,8 @@ eeprom_probe (unsigned dev_addr, unsigned offset)
void eeprom_init (void)
{
#if defined(CONFIG_SPI)
#if defined(CONFIG_SPI) && !defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
spi_init_f ();
#endif
#if defined(CONFIG_HARD_I2C) || \
@ -411,6 +412,7 @@ void eeprom_init (void)
i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#endif
}
/*-----------------------------------------------------------------------
*/

6
common/dlmalloc.c
View file

@ -2179,6 +2179,12 @@ Void_t* mALLOc(bytes) size_t bytes;
INTERNAL_SIZE_T nb;
/* check if mem_malloc_init() was run */
if ((mem_malloc_start == 0) && (mem_malloc_end == 0)) {
/* not initialized yet */
return 0;
}
if ((long)bytes < 0) return 0;
nb = request2size(bytes); /* padded request size; */

195
common/env_eeprom.c
View file

@ -28,19 +28,85 @@
#include <command.h>
#include <environment.h>
#include <linux/stddef.h>
#if defined(CONFIG_I2C_ENV_EEPROM_BUS)
#include <i2c.h>
#endif
#ifdef CONFIG_ENV_OFFSET_REDUND
#define ACTIVE_FLAG 1
#define OBSOLETE_FLAG 0
#endif
DECLARE_GLOBAL_DATA_PTR;
env_t *env_ptr = NULL;
char * env_name_spec = "EEPROM";
int env_eeprom_bus = -1;
static int eeprom_bus_read (unsigned dev_addr, unsigned offset, uchar *buffer,
unsigned cnt)
{
int rcode;
#if defined(CONFIG_I2C_ENV_EEPROM_BUS)
int old_bus = i2c_get_bus_num();
if (gd->flags & GD_FLG_RELOC) {
if (env_eeprom_bus == -1) {
I2C_MUX_DEVICE *dev = NULL;
dev = i2c_mux_ident_muxstring(
(uchar *)CONFIG_I2C_ENV_EEPROM_BUS);
if (dev != NULL) {
env_eeprom_bus = dev->busid;
} else
printf ("error adding env eeprom bus.\n");
}
if (old_bus != env_eeprom_bus) {
i2c_set_bus_num(env_eeprom_bus);
old_bus = env_eeprom_bus;
}
} else {
rcode = i2c_mux_ident_muxstring_f(
(uchar *)CONFIG_I2C_ENV_EEPROM_BUS);
}
#endif
rcode = eeprom_read (dev_addr, offset, buffer, cnt);
#if defined(CONFIG_I2C_ENV_EEPROM_BUS)
if (old_bus != env_eeprom_bus)
i2c_set_bus_num(old_bus);
#endif
return rcode;
}
static int eeprom_bus_write (unsigned dev_addr, unsigned offset, uchar *buffer,
unsigned cnt)
{
int rcode;
#if defined(CONFIG_I2C_ENV_EEPROM_BUS)
int old_bus = i2c_get_bus_num();
rcode = i2c_mux_ident_muxstring_f((uchar *)CONFIG_I2C_ENV_EEPROM_BUS);
#endif
rcode = eeprom_write (dev_addr, offset, buffer, cnt);
#if defined(CONFIG_I2C_ENV_EEPROM_BUS)
i2c_set_bus_num(old_bus);
#endif
return rcode;
}
uchar env_get_char_spec (int index)
{
uchar c;
unsigned int off;
off = CONFIG_ENV_OFFSET;
#ifdef CONFIG_ENV_OFFSET_REDUND
if (gd->env_valid == 2)
off = CONFIG_ENV_OFFSET_REDUND;
#endif
eeprom_read (CONFIG_SYS_DEF_EEPROM_ADDR,
CONFIG_ENV_OFFSET+index+offsetof(env_t,data),
eeprom_bus_read (CONFIG_SYS_DEF_EEPROM_ADDR,
off + index + offsetof(env_t,data),
&c, 1);
return (c);
@ -48,18 +114,52 @@ uchar env_get_char_spec (int index)
void env_relocate_spec (void)
{
eeprom_read (CONFIG_SYS_DEF_EEPROM_ADDR,
CONFIG_ENV_OFFSET,
unsigned int off = CONFIG_ENV_OFFSET;
#ifdef CONFIG_ENV_OFFSET_REDUND
if (gd->env_valid == 2)
off = CONFIG_ENV_OFFSET_REDUND;
#endif
eeprom_bus_read (CONFIG_SYS_DEF_EEPROM_ADDR,
off,
(uchar*)env_ptr,
CONFIG_ENV_SIZE);
}
int saveenv(void)
{
return eeprom_write (CONFIG_SYS_DEF_EEPROM_ADDR,
CONFIG_ENV_OFFSET,
int rc;
unsigned int off = CONFIG_ENV_OFFSET;
#ifdef CONFIG_ENV_OFFSET_REDUND
unsigned int off_red = CONFIG_ENV_OFFSET_REDUND;
char flag_obsolete = OBSOLETE_FLAG;
if (gd->env_valid == 1) {
off = CONFIG_ENV_OFFSET_REDUND;
off_red = CONFIG_ENV_OFFSET;
}
env_ptr->flags = ACTIVE_FLAG;
#endif
rc = eeprom_bus_write (CONFIG_SYS_DEF_EEPROM_ADDR,
off,
(uchar *)env_ptr,
CONFIG_ENV_SIZE);
#ifdef CONFIG_ENV_OFFSET_REDUND
if (rc == 0) {
eeprom_bus_write (CONFIG_SYS_DEF_EEPROM_ADDR,
off_red + offsetof(env_t,flags),
(uchar *)&flag_obsolete,
1);
if (gd->env_valid == 1)
gd->env_valid = 2;
else
gd->env_valid = 1;
}
#endif
return rc;
}
/************************************************************************
@ -68,6 +168,82 @@ int saveenv(void)
* We are still running from ROM, so data use is limited
* Use a (moderately small) buffer on the stack
*/
#ifdef CONFIG_ENV_OFFSET_REDUND
int env_init(void)
{
ulong len;
ulong crc[2], crc_tmp;
unsigned int off, off_env[2];
uchar buf[64];
int crc_ok[2] = {0,0};
unsigned char flags[2];
int i;
eeprom_init (); /* prepare for EEPROM read/write */
off_env[0] = CONFIG_ENV_OFFSET;
off_env[1] = CONFIG_ENV_OFFSET_REDUND;
for (i = 0; i < 2; i++) {
/* read CRC */
eeprom_bus_read (CONFIG_SYS_DEF_EEPROM_ADDR,
off_env[i] + offsetof(env_t,crc),
(uchar *)&crc[i], sizeof(ulong));
/* read FLAGS */
eeprom_bus_read (CONFIG_SYS_DEF_EEPROM_ADDR,
off_env[i] + offsetof(env_t,flags),
(uchar *)&flags[i], sizeof(uchar));
crc_tmp= 0;
len = ENV_SIZE;
off = off_env[i] + offsetof(env_t,data);
while (len > 0) {
int n = (len > sizeof(buf)) ? sizeof(buf) : len;
eeprom_bus_read (CONFIG_SYS_DEF_EEPROM_ADDR, off,
buf, n);
crc_tmp = crc32 (crc_tmp, buf, n);
len -= n;
off += n;
}
if (crc_tmp == crc[i])
crc_ok[i] = 1;
}
if (!crc_ok[0] && !crc_ok[1]) {
gd->env_addr = 0;
gd->env_valid = 0;
return 0;
} else if (crc_ok[0] && !crc_ok[1]) {
gd->env_valid = 1;
}
else if (!crc_ok[0] && crc_ok[1]) {
gd->env_valid = 2;
} else {
/* both ok - check serial */
if (flags[0] == ACTIVE_FLAG && flags[1] == OBSOLETE_FLAG)
gd->env_valid = 1;
else if (flags[0] == OBSOLETE_FLAG && flags[1] == ACTIVE_FLAG)
gd->env_valid = 2;
else if (flags[0] == 0xFF && flags[1] == 0)
gd->env_valid = 2;
else if(flags[1] == 0xFF && flags[0] == 0)
gd->env_valid = 1;
else /* flags are equal - almost impossible */
gd->env_valid = 1;
}
if (gd->env_valid == 2)
gd->env_addr = off_env[1] + offsetof(env_t,data);
else if (gd->env_valid == 1)
gd->env_addr = off_env[0] + offsetof(env_t,data);
return (0);
}
#else
int env_init(void)
{
ulong crc, len, new;
@ -77,7 +253,7 @@ int env_init(void)
eeprom_init (); /* prepare for EEPROM read/write */
/* read old CRC */
eeprom_read (CONFIG_SYS_DEF_EEPROM_ADDR,
eeprom_bus_read (CONFIG_SYS_DEF_EEPROM_ADDR,
CONFIG_ENV_OFFSET+offsetof(env_t,crc),
(uchar *)&crc, sizeof(ulong));
@ -87,7 +263,8 @@ int env_init(void)
while (len > 0) {
int n = (len > sizeof(buf)) ? sizeof(buf) : len;
eeprom_read (CONFIG_SYS_DEF_EEPROM_ADDR, CONFIG_ENV_OFFSET+off, buf, n);
eeprom_bus_read (CONFIG_SYS_DEF_EEPROM_ADDR,
CONFIG_ENV_OFFSET + off, buf, n);
new = crc32 (new, buf, n);
len -= n;
off += n;
@ -103,3 +280,5 @@ int env_init(void)
return (0);
}
#endif

43
common/kgdb.c
View file

@ -132,11 +132,20 @@ hex(unsigned char ch)
static unsigned char *
mem2hex(char *mem, char *buf, int count)
{
char *tmp;
unsigned char ch;
/*
* We use the upper half of buf as an intermediate buffer for the
* raw memory copy. Hex conversion will work against this one.
*/
tmp = buf + count;
longjmp_on_fault = 1;
memcpy(tmp, mem, count);
while (count-- > 0) {
ch = *mem++;
ch = *tmp++;
*buf++ = hexchars[ch >> 4];
*buf++ = hexchars[ch & 0xf];
}
@ -151,21 +160,33 @@ mem2hex(char *mem, char *buf, int count)
static char *
hex2mem(char *buf, char *mem, int count)
{
int i, hexValue;
unsigned char ch;
char *mem_start = mem;
int hexValue;
char *tmp_raw, *tmp_hex;
/*
* We use the upper half of buf as an intermediate buffer for the
* raw memory that is converted from hex.
*/
tmp_raw = buf + count * 2;
tmp_hex = tmp_raw - 1;
longjmp_on_fault = 1;
for (i=0; i<count; i++) {
if ((hexValue = hex(*buf++)) < 0)
while (tmp_hex >= buf) {
tmp_raw--;
hexValue = hex(*tmp_hex--);
if (hexValue < 0)
kgdb_error(KGDBERR_NOTHEXDIG);
ch = hexValue << 4;
if ((hexValue = hex(*buf++)) < 0)
*tmp_raw = hexValue;
hexValue = hex(*tmp_hex--);
if (hexValue < 0)
kgdb_error(KGDBERR_NOTHEXDIG);
ch |= hexValue;
*mem++ = ch;
*tmp_raw |= hexValue << 4;
}
kgdb_flush_cache_range((void *)mem_start, (void *)(mem - 1));
memcpy(mem, tmp_raw, count);
kgdb_flush_cache_range((void *)mem, (void *)(mem+count));
longjmp_on_fault = 0;
return buf;

64
common/kgdb_stubs.c Normal file
View file

@ -0,0 +1,64 @@
/*
* U-boot - stub functions for common kgdb code,
* can be overridden in board specific files
*
* Copyright 2009 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#include <common.h>
#include <kgdb.h>
int (*debugger_exception_handler)(struct pt_regs *);
__attribute__((weak))
void kgdb_serial_init(void)
{
puts("[on serial] ");
}
__attribute__((weak))
void putDebugChar(int c)
{
serial_putc(c);
}
__attribute__((weak))
void putDebugStr(const char *str)
{
#ifdef DEBUG
serial_puts(str);
#endif
}
__attribute__((weak))
int getDebugChar(void)
{
return serial_getc();
}
__attribute__((weak))
void kgdb_interruptible(int yes)
{
return;
}
__attribute__((weak))
void kgdb_flush_cache_range(void *from, void *to)
{
flush_cache((unsigned long)from, (unsigned long)(to - from));
}
__attribute__((weak))
void kgdb_flush_cache_all(void)
{
if (dcache_status()) {
dcache_disable();
dcache_enable();
}
if (icache_status()) {
icache_disable();
icache_enable();
}
}

4
cpu/74xx_7xx/traps.c
View file

@ -40,10 +40,6 @@
DECLARE_GLOBAL_DATA_PTR;
#endif
#if defined(CONFIG_CMD_KGDB)
int (*debugger_exception_handler)(struct pt_regs *) = 0;
#endif
/* Returns 0 if exception not found and fixup otherwise. */
extern unsigned long search_exception_table(unsigned long);

2
cpu/blackfin/Makefile
View file

@ -24,7 +24,7 @@ COBJS-y += os_log.o
COBJS-y += reset.o
COBJS-y += serial.o
COBJS-y += traps.o
COBJS-y += watchdog.o
COBJS-$(CONFIG_HW_WATCHDOG) += watchdog.o
ifeq ($(CONFIG_BFIN_BOOT_MODE),BFIN_BOOT_BYPASS)
COBJS-y += initcode.o

11
cpu/blackfin/cpu.c
View file

@ -25,13 +25,12 @@ ulong bfin_poweron_retx;
__attribute__ ((__noreturn__))
void cpu_init_f(ulong bootflag, ulong loaded_from_ldr)
{
extern char _stext_l1;
#ifndef CONFIG_BFIN_BOOTROM_USES_EVT1
/* Build a NOP slide over the LDR jump block. Whee! */
char nops[0xC];
serial_early_puts("NOP Slide\n");
memset(nops, 0x00, sizeof(nops));
memcpy(&_stext_l1 - sizeof(nops), nops, sizeof(nops));
memcpy((void *)L1_INST_SRAM, nops, sizeof(nops));
#endif
if (!loaded_from_ldr) {
@ -40,10 +39,10 @@ void cpu_init_f(ulong bootflag, ulong loaded_from_ldr)
* checking at build time.
*/
serial_early_puts("L1 Relocate\n");
extern char _stext_l1, _etext_l1, _stext_l1_lma;
memcpy(&_stext_l1, &_stext_l1_lma, (&_etext_l1 - &_stext_l1));
extern char _sdata_l1, _edata_l1, _sdata_l1_lma;
memcpy(&_sdata_l1, &_sdata_l1_lma, (&_edata_l1 - &_sdata_l1));
extern char _stext_l1[], _text_l1_lma[], _text_l1_len[];
memcpy(&_stext_l1, &_text_l1_lma, (unsigned long)_text_l1_len);
extern char _sdata_l1[], _data_l1_lma[], _data_l1_len[];
memcpy(&_sdata_l1, &_data_l1_lma, (unsigned long)_data_l1_len);
}
#if defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__)
/* The BF537 bootrom will reset the EBIU_AMGCTL register on us

253
cpu/blackfin/initcode.c
View file

@ -9,6 +9,8 @@
* Licensed under the GPL-2 or later.
*/
#define BFIN_IN_INITCODE
#include <config.h>
#include <asm/blackfin.h>
#include <asm/mach-common/bits/bootrom.h>
@ -17,7 +19,6 @@
#include <asm/mach-common/bits/pll.h>
#include <asm/mach-common/bits/uart.h>
#define BFIN_IN_INITCODE
#include "serial.h"
__attribute__((always_inline))
@ -33,7 +34,7 @@ static inline void serial_init(void)
size_t i;
/* force RTS rather than relying on auto RTS */
bfin_write_UART1_MCR(bfin_read_UART1_MCR() | FCPOL);
bfin_write16(&pUART->mcr, bfin_read16(&pUART->mcr) | FCPOL);
/* Wait for the line to clear up. We cannot rely on UART
* registers as none of them reflect the status of the RSR.
@ -63,7 +64,7 @@ static inline void serial_init(void)
#endif
if (BFIN_DEBUG_EARLY_SERIAL) {
int ucen = *pUART_GCTL & UCEN;
int ucen = bfin_read16(&pUART->gctl) & UCEN;
serial_early_init();
/* If the UART is off, that means we need to program
@ -80,7 +81,7 @@ static inline void serial_deinit(void)
#ifdef __ADSPBF54x__
if (BFIN_UART_USE_RTS && CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
/* clear forced RTS rather than relying on auto RTS */
bfin_write_UART1_MCR(bfin_read_UART1_MCR() & ~FCPOL);
bfin_write16(&pUART->mcr, bfin_read16(&pUART->mcr) & ~FCPOL);
}
#endif
}
@ -94,9 +95,9 @@ static inline void serial_putc(char c)
if (c == '\n')
serial_putc('\r');
*pUART_THR = c;
bfin_write16(&pUART->thr, c);
while (!(*pUART_LSR & TEMT))
while (!(bfin_read16(&pUART->lsr) & TEMT))
continue;
}
@ -213,6 +214,7 @@ static inline void serial_putc(char c)
# define CONFIG_HAS_VR 1
#endif
#if CONFIG_MEM_SIZE
#ifndef EBIU_RSTCTL
/* Blackfin with SDRAM */
#ifndef CONFIG_EBIU_SDBCTL_VAL
@ -245,6 +247,7 @@ static inline void serial_putc(char c)
# define CONFIG_EBIU_SDBCTL_VAL (CONFIG_EBCAW_VAL | CONFIG_EBSZ_VAL | EBE)
#endif
#endif
#endif
/* Conflicting Column Address Widths Causes SDRAM Errors:
* EB2CAW and EB3CAW must be the same
@ -255,28 +258,21 @@ static inline void serial_putc(char c)
# endif
#endif
BOOTROM_CALLED_FUNC_ATTR
void initcode(ADI_BOOT_DATA *bootstruct)
__attribute__((always_inline)) static inline void
program_early_devices(ADI_BOOT_DATA *bs, uint *sdivB, uint *divB, uint *vcoB)
{
ADI_BOOT_DATA bootstruct_scratch;
serial_putc('a');
/* Save the clock pieces that are used in baud rate calculation */
unsigned int sdivB, divB, vcoB;
serial_init();
if (BFIN_DEBUG_EARLY_SERIAL || CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
sdivB = bfin_read_PLL_DIV() & 0xf;
vcoB = (bfin_read_PLL_CTL() >> 9) & 0x3f;
divB = serial_early_get_div();
serial_putc('b');
*sdivB = bfin_read_PLL_DIV() & 0xf;
*vcoB = (bfin_read_PLL_CTL() >> 9) & 0x3f;
*divB = serial_early_get_div();
serial_putc('c');
}
serial_putc('A');
/* If the bootstruct is NULL, then it's because we're loading
* dynamically and not via LDR (bootrom). So set the struct to
* some scratch space.
*/
if (!bootstruct)
bootstruct = &bootstruct_scratch;
serial_putc('d');
#ifdef CONFIG_HW_WATCHDOG
# ifndef CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE
@ -289,28 +285,14 @@ void initcode(ADI_BOOT_DATA *bootstruct)
* timeout, so don't clobber that.
*/
if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS) {
serial_putc('e');
bfin_write_WDOG_CNT(MSEC_TO_SCLK(CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE));
bfin_write_WDOG_CTL(0);
serial_putc('f');
}
#endif
serial_putc('B');
/* If external memory is enabled, put it into self refresh first. */
bool put_into_srfs = false;
#ifdef EBIU_RSTCTL
if (bfin_read_EBIU_RSTCTL() & DDR_SRESET) {
bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | SRREQ);
put_into_srfs = true;
}
#else
if (bfin_read_EBIU_SDBCTL() & EBE) {
bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() | SRFS);
put_into_srfs = true;
}
#endif
serial_putc('C');
serial_putc('g');
/* Blackfin bootroms use the SPI slow read opcode instead of the SPI
* fast read, so we need to slow down the SPI clock a lot more during
@ -318,12 +300,54 @@ void initcode(ADI_BOOT_DATA *bootstruct)
* increase the speed appropriately.
*/
if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) {
serial_putc('h');
if (BOOTROM_SUPPORTS_SPI_FAST_READ && CONFIG_SPI_BAUD_INITBLOCK < 4)
bootstruct->dFlags |= BFLAG_FASTREAD;
bs->dFlags |= BFLAG_FASTREAD;
bfin_write_SPI_BAUD(CONFIG_SPI_BAUD_INITBLOCK);
serial_putc('i');
}
serial_putc('D');
serial_putc('j');
}
__attribute__((always_inline)) static inline bool
maybe_self_refresh(ADI_BOOT_DATA *bs)
{
serial_putc('a');
if (!CONFIG_MEM_SIZE)
return false;
/* If external memory is enabled, put it into self refresh first. */
#ifdef EBIU_RSTCTL
if (bfin_read_EBIU_RSTCTL() & DDR_SRESET) {
serial_putc('b');
bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | SRREQ);
return true;
}
#else
if (bfin_read_EBIU_SDBCTL() & EBE) {
serial_putc('b');
bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() | SRFS);
return true;
}
#endif
serial_putc('c');
return false;
}
__attribute__((always_inline)) static inline u16
program_clocks(ADI_BOOT_DATA *bs, bool put_into_srfs)
{
u16 vr_ctl;
serial_putc('a');
vr_ctl = bfin_read_VR_CTL();
serial_putc('b');
/* If we're entering self refresh, make sure it has happened. */
if (put_into_srfs)
@ -334,15 +358,14 @@ void initcode(ADI_BOOT_DATA *bootstruct)
#endif
continue;
serial_putc('E');
serial_putc('c');
/* With newer bootroms, we use the helper function to set up
* the memory controller. Older bootroms lacks such helpers
* so we do it ourselves.
*/
uint16_t vr_ctl = bfin_read_VR_CTL();
if (!ANOMALY_05000386) {
serial_putc('F');
serial_putc('d');
/* Always programming PLL_LOCKCNT avoids Anomaly 05000430 */
ADI_SYSCTRL_VALUES memory_settings;
@ -362,7 +385,9 @@ void initcode(ADI_BOOT_DATA *bootstruct)
#if ANOMALY_05000432
bfin_write_SIC_IWR1(0);
#endif
serial_putc('e');
bfrom_SysControl(actions, &memory_settings, NULL);
serial_putc('f');
#if ANOMALY_05000432
bfin_write_SIC_IWR1(-1);
#endif
@ -370,8 +395,9 @@ void initcode(ADI_BOOT_DATA *bootstruct)
bfin_write_SICA_IWR0(-1);
bfin_write_SICA_IWR1(-1);
#endif
serial_putc('g');
} else {
serial_putc('G');
serial_putc('h');
/* Disable all peripheral wakeups except for the PLL event. */
#ifdef SIC_IWR0
@ -387,38 +413,40 @@ void initcode(ADI_BOOT_DATA *bootstruct)
bfin_write_SIC_IWR(1);
#endif
serial_putc('H');
serial_putc('i');
/* Always programming PLL_LOCKCNT avoids Anomaly 05000430 */
bfin_write_PLL_LOCKCNT(CONFIG_PLL_LOCKCNT_VAL);
serial_putc('I');
serial_putc('j');
/* Only reprogram when needed to avoid triggering unnecessary
* PLL relock sequences.
*/
if (vr_ctl != CONFIG_VR_CTL_VAL) {
serial_putc('!');
serial_putc('?');
bfin_write_VR_CTL(CONFIG_VR_CTL_VAL);
asm("idle;");
serial_putc('!');
}
serial_putc('J');
serial_putc('k');
bfin_write_PLL_DIV(CONFIG_PLL_DIV_VAL);
serial_putc('K');
serial_putc('l');
/* Only reprogram when needed to avoid triggering unnecessary
* PLL relock sequences.
*/
if (ANOMALY_05000242 || bfin_read_PLL_CTL() != CONFIG_PLL_CTL_VAL) {
serial_putc('!');
serial_putc('?');
bfin_write_PLL_CTL(CONFIG_PLL_CTL_VAL);
asm("idle;");
serial_putc('!');
}
serial_putc('L');
serial_putc('m');
/* Restore all peripheral wakeups. */
#ifdef SIC_IWR0
@ -433,9 +461,19 @@ void initcode(ADI_BOOT_DATA *bootstruct)
#else
bfin_write_SIC_IWR(-1);
#endif
serial_putc('n');
}
serial_putc('M');
serial_putc('o');
return vr_ctl;
}
__attribute__((always_inline)) static inline void
update_serial_clocks(ADI_BOOT_DATA *bs, uint sdivB, uint divB, uint vcoB)
{
serial_putc('a');
/* Since we've changed the SCLK above, we may need to update
* the UART divisors (UART baud rates are based on SCLK).
@ -443,6 +481,7 @@ void initcode(ADI_BOOT_DATA *bootstruct)
* for dividing which means we'd generate a libgcc reference.
*/
if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
serial_putc('b');
unsigned int sdivR, vcoR;
sdivR = bfin_read_PLL_DIV() & 0xf;
vcoR = (bfin_read_PLL_CTL() >> 9) & 0x3f;
@ -452,20 +491,38 @@ void initcode(ADI_BOOT_DATA *bootstruct)
for (quotient = 0; dividend > 0; ++quotient)
dividend -= divisor;
serial_early_put_div(quotient - ANOMALY_05000230);
serial_putc('c');
}
serial_putc('N');
serial_putc('d');
}
__attribute__((always_inline)) static inline void
program_memory_controller(ADI_BOOT_DATA *bs, bool put_into_srfs)
{
serial_putc('a');
if (!CONFIG_MEM_SIZE)
return;
serial_putc('b');
/* Program the external memory controller before we come out of
* self-refresh. This only works with our SDRAM controller.
*/
#ifndef EBIU_RSTCTL
# ifdef CONFIG_EBIU_SDRRC_VAL
bfin_write_EBIU_SDRRC(CONFIG_EBIU_SDRRC_VAL);
# endif
# ifdef CONFIG_EBIU_SDBCTL_VAL
bfin_write_EBIU_SDBCTL(CONFIG_EBIU_SDBCTL_VAL);
# endif
# ifdef CONFIG_EBIU_SDGCTL_VAL
bfin_write_EBIU_SDGCTL(CONFIG_EBIU_SDGCTL_VAL);
# endif
#endif
serial_putc('O');
serial_putc('c');
/* Now that we've reprogrammed, take things out of self refresh. */
if (put_into_srfs)
@ -475,16 +532,24 @@ void initcode(ADI_BOOT_DATA *bootstruct)
bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() & ~(SRFS));
#endif
serial_putc('P');
serial_putc('d');
/* Our DDR controller sucks and cannot be programmed while in
* self-refresh. So we have to pull it out before programming.
*/
#ifdef EBIU_RSTCTL
# ifdef CONFIG_EBIU_RSTCTL_VAL
bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | 0x1 /*DDRSRESET*/ | CONFIG_EBIU_RSTCTL_VAL);
# endif
# ifdef CONFIG_EBIU_DDRCTL0_VAL
bfin_write_EBIU_DDRCTL0(CONFIG_EBIU_DDRCTL0_VAL);
# endif
# ifdef CONFIG_EBIU_DDRCTL1_VAL
bfin_write_EBIU_DDRCTL1(CONFIG_EBIU_DDRCTL1_VAL);
# endif
# ifdef CONFIG_EBIU_DDRCTL2_VAL
bfin_write_EBIU_DDRCTL2(CONFIG_EBIU_DDRCTL2_VAL);
# endif
# ifdef CONFIG_EBIU_DDRCTL3_VAL
/* default is disable, so don't need to force this */
bfin_write_EBIU_DDRCTL3(CONFIG_EBIU_DDRCTL3_VAL);
@ -494,7 +559,18 @@ void initcode(ADI_BOOT_DATA *bootstruct)
# endif
#endif
serial_putc('Q');
serial_putc('e');
}
__attribute__((always_inline)) static inline void
check_hibernation(ADI_BOOT_DATA *bs, u16 vr_ctl, bool put_into_srfs)
{
serial_putc('a');
if (!CONFIG_MEM_SIZE)
return;
serial_putc('b');
/* Are we coming out of hibernate (suspend to memory) ?
* The memory layout is:
@ -508,7 +584,7 @@ void initcode(ADI_BOOT_DATA *bootstruct)
uint32_t *hibernate_magic = 0;
__builtin_bfin_ssync(); /* make sure memory controller is done */
if (hibernate_magic[0] == 0xDEADBEEF) {
serial_putc('R');
serial_putc('c');
bfin_write_EVT15(hibernate_magic[1]);
bfin_write_IMASK(EVT_IVG15);
__asm__ __volatile__ (
@ -525,25 +601,80 @@ void initcode(ADI_BOOT_DATA *bootstruct)
: "p"(hibernate_magic), "d"(0x2000 /* jump.s 0 */)
);
}
serial_putc('d');
}
serial_putc('S');
serial_putc('e');
}
__attribute__((always_inline)) static inline void
program_async_controller(ADI_BOOT_DATA *bs)
{
serial_putc('a');
/* Program the async banks controller. */
bfin_write_EBIU_AMBCTL0(CONFIG_EBIU_AMBCTL0_VAL);
bfin_write_EBIU_AMBCTL1(CONFIG_EBIU_AMBCTL1_VAL);
bfin_write_EBIU_AMGCTL(CONFIG_EBIU_AMGCTL_VAL);
#ifdef EBIU_MODE
serial_putc('b');
/* Not all parts have these additional MMRs. */
#ifdef EBIU_MODE
# ifdef CONFIG_EBIU_MBSCTL_VAL
bfin_write_EBIU_MBSCTL(CONFIG_EBIU_MBSCTL_VAL);
# endif
# ifdef CONFIG_EBIU_MODE_VAL
bfin_write_EBIU_MODE(CONFIG_EBIU_MODE_VAL);
# endif
# ifdef CONFIG_EBIU_FCTL_VAL
bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTL_VAL);
# endif
#endif
serial_putc('T');
serial_putc('c');
}
BOOTROM_CALLED_FUNC_ATTR
void initcode(ADI_BOOT_DATA *bs)
{
ADI_BOOT_DATA bootstruct_scratch;
serial_init();
serial_putc('A');
/* If the bootstruct is NULL, then it's because we're loading
* dynamically and not via LDR (bootrom). So set the struct to
* some scratch space.
*/
if (!bs)
bs = &bootstruct_scratch;
serial_putc('B');
bool put_into_srfs = maybe_self_refresh(bs);
serial_putc('C');
uint sdivB, divB, vcoB;
program_early_devices(bs, &sdivB, &divB, &vcoB);
serial_putc('D');
u16 vr_ctl = program_clocks(bs, put_into_srfs);
serial_putc('E');
update_serial_clocks(bs, sdivB, divB, vcoB);
serial_putc('F');
program_memory_controller(bs, put_into_srfs);
serial_putc('G');
check_hibernation(bs, vr_ctl, put_into_srfs);
serial_putc('H');
program_async_controller(bs);
#ifdef CONFIG_BFIN_BOOTROM_USES_EVT1
serial_putc('I');
/* tell the bootrom where our entry point is */
if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS)
bfin_write_EVT1(CONFIG_SYS_MONITOR_BASE);

11
cpu/blackfin/interrupt.S
View file

@ -1,7 +1,7 @@
/*
* interrupt.S - trampoline default exceptions/interrupts to C handlers
*
* Copyright (c) 2005-2007 Analog Devices Inc.
* Copyright (c) 2005-2009 Analog Devices Inc.
* Licensed under the GPL-2 or later.
*/
@ -17,10 +17,19 @@ ENTRY(_trap)
sp.l = LO(L1_SRAM_SCRATCH_END - 20);
sp.h = HI(L1_SRAM_SCRATCH_END - 20);
SAVE_ALL_SYS
r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */
sp += -12;
call _trap_c;
sp += 12;
#if ANOMALY_05000257
R7 = LC0;
LC0 = R7;
R7 = LC1;
LC1 = R7;
#endif
RESTORE_ALL_SYS
sp = CONFIG_BFIN_SCRATCH_REG;
rtx;

12
cpu/blackfin/interrupts.c
View file

@ -97,12 +97,12 @@ void __udelay(unsigned long usec)
#define MAX_TIM_LOAD 0xFFFFFFFF
int timer_init(void)
{
*pTCNTL = 0x1;
bfin_write_TCNTL(0x1);
CSYNC();
*pTSCALE = 0x0;
*pTCOUNT = MAX_TIM_LOAD;
*pTPERIOD = MAX_TIM_LOAD;
*pTCNTL = 0x7;
bfin_write_TSCALE(0x0);
bfin_write_TCOUNT(MAX_TIM_LOAD);
bfin_write_TPERIOD(MAX_TIM_LOAD);
bfin_write_TCNTL(0x7);
CSYNC();
timestamp = 0;
@ -130,7 +130,7 @@ ulong get_timer(ulong base)
ulong milisec;
/* Number of clocks elapsed */
ulong clocks = (MAX_TIM_LOAD - (*pTCOUNT));
ulong clocks = (MAX_TIM_LOAD - bfin_read_TCOUNT());
/*
* Find if the TCOUNT is reset

26
cpu/blackfin/serial.c
View file

@ -44,10 +44,6 @@
#ifdef CONFIG_UART_CONSOLE
#if defined(UART_LSR) && (CONFIG_UART_CONSOLE != 0)
# error CONFIG_UART_CONSOLE must be 0 on parts with only one UART
#endif
#include "serial.h"
#ifdef CONFIG_DEBUG_SERIAL
@ -63,7 +59,7 @@ size_t cache_count;
static uint16_t uart_lsr_save;
static uint16_t uart_lsr_read(void)
{
uint16_t lsr = *pUART_LSR;
uint16_t lsr = bfin_read16(&pUART->lsr);
uart_lsr_save |= (lsr & (OE|PE|FE|BI));
return lsr | uart_lsr_save;
}
@ -71,15 +67,21 @@ static uint16_t uart_lsr_read(void)
static void uart_lsr_clear(void)
{
uart_lsr_save = 0;
*pUART_LSR |= -1;
bfin_write16(&pUART->lsr, bfin_read16(&pUART->lsr) | -1);
}
#else
/* When debugging is disabled, we only care about the DR bit, so if other
* bits get set/cleared, we don't really care since we don't read them
* anyways (and thus anomaly 05000099 is irrelevant).
*/
static inline uint16_t uart_lsr_read(void) { return *pUART_LSR; }
static inline void uart_lsr_clear(void) { *pUART_LSR = -1; }
static uint16_t uart_lsr_read(void)
{
return bfin_read16(&pUART->lsr);
}
static void uart_lsr_clear(void)
{
bfin_write16(&pUART->lsr, bfin_read16(&pUART->lsr) | -1);
}
#endif
/* Symbol for our assembly to call. */
@ -130,7 +132,7 @@ void serial_putc(const char c)
continue;
/* queue the character for transmission */
*pUART_THR = c;
bfin_write16(&pUART->thr, c);
SSYNC();
WATCHDOG_RESET();
@ -151,7 +153,7 @@ int serial_getc(void)
continue;
/* grab the new byte */
uart_rbr_val = *pUART_RBR;
uart_rbr_val = bfin_read16(&pUART->rbr);
#ifdef CONFIG_DEBUG_SERIAL
/* grab & clear the LSR */
@ -165,8 +167,8 @@ int serial_getc(void)
uint16_t dll, dlh;
printf("\n[SERIAL ERROR]\n");
ACCESS_LATCH();
dll = *pUART_DLL;
dlh = *pUART_DLH;
dll = bfin_read16(&pUART->dll);
dlh = bfin_read16(&pUART->dlh);
ACCESS_PORT_IER();
printf("\tDLL=0x%x DLH=0x%x\n", dll, dlh);
do {

121
cpu/blackfin/serial.h
View file

@ -24,71 +24,80 @@
# define BFIN_DEBUG_EARLY_SERIAL 0
#endif
#ifndef __ASSEMBLY__
#define LOB(x) ((x) & 0xFF)
#define HIB(x) (((x) >> 8) & 0xFF)
/*
* All Blackfin system MMRs are padded to 32bits even if the register
* itself is only 16bits. So use a helper macro to streamline this.
*/
#define __BFP(m) u16 m; u16 __pad_##m
struct bfin_mmr_serial {
#ifdef __ADSPBF54x__
__BFP(dll);
__BFP(dlh);
__BFP(gctl);
__BFP(lcr);
__BFP(mcr);
__BFP(lsr);
__BFP(msr);
__BFP(scr);
__BFP(ier_set);
__BFP(ier_clear);
__BFP(thr);
__BFP(rbr);
#else
union {
u16 dll;
u16 thr;
const u16 rbr;
};
const u16 __spad0;
union {
u16 dlh;
u16 ier;
};
const u16 __spad1;
const __BFP(iir);
__BFP(lcr);
__BFP(mcr);
__BFP(lsr);
__BFP(msr);
__BFP(scr);
const u32 __spad2;
__BFP(gctl);
#endif
};
#undef __BFP
#ifndef UART_LSR
# if (CONFIG_UART_CONSOLE == 3)
# define pUART_DLH pUART3_DLH
# define pUART_DLL pUART3_DLL
# define pUART_GCTL pUART3_GCTL
# define pUART_IER pUART3_IER
# define pUART_IERC pUART3_IER_CLEAR
# define pUART_LCR pUART3_LCR
# define pUART_LSR pUART3_LSR
# define pUART_RBR pUART3_RBR
# define pUART_THR pUART3_THR
# define UART_THR UART3_THR
# define UART_LSR UART3_LSR
# define UART_BASE UART3_DLL
# elif (CONFIG_UART_CONSOLE == 2)
# define pUART_DLH pUART2_DLH
# define pUART_DLL pUART2_DLL
# define pUART_GCTL pUART2_GCTL
# define pUART_IER pUART2_IER
# define pUART_IERC pUART2_IER_CLEAR
# define pUART_LCR pUART2_LCR
# define pUART_LSR pUART2_LSR
# define pUART_RBR pUART2_RBR
# define pUART_THR pUART2_THR
# define UART_THR UART2_THR
# define UART_LSR UART2_LSR
# define UART_BASE UART2_DLL
# elif (CONFIG_UART_CONSOLE == 1)
# define pUART_DLH pUART1_DLH
# define pUART_DLL pUART1_DLL
# define pUART_GCTL pUART1_GCTL
# define pUART_IER pUART1_IER
# define pUART_IERC pUART1_IER_CLEAR
# define pUART_LCR pUART1_LCR
# define pUART_LSR pUART1_LSR
# define pUART_RBR pUART1_RBR
# define pUART_THR pUART1_THR
# define UART_THR UART1_THR
# define UART_LSR UART1_LSR
# define UART_BASE UART1_DLL
# elif (CONFIG_UART_CONSOLE == 0)
# define pUART_DLH pUART0_DLH
# define pUART_DLL pUART0_DLL
# define pUART_GCTL pUART0_GCTL
# define pUART_IER pUART0_IER
# define pUART_IERC pUART0_IER_CLEAR
# define pUART_LCR pUART0_LCR
# define pUART_LSR pUART0_LSR
# define pUART_RBR pUART0_RBR
# define pUART_THR pUART0_THR
# define UART_THR UART0_THR
# define UART_LSR UART0_LSR
# define UART_BASE UART0_DLL
# endif
#else
# if CONFIG_UART_CONSOLE != 0
# error CONFIG_UART_CONSOLE must be 0 on parts with only one UART
# endif
# define UART_BASE UART_DLL
#endif
#ifndef __ASSEMBLY__
#define pUART ((volatile struct bfin_mmr_serial *)UART_BASE)
#ifdef __ADSPBF54x__
# define ACCESS_LATCH()
# define ACCESS_PORT_IER()
# define CLEAR_IER() (*pUART_IERC = 0)
#else
# define ACCESS_LATCH() (*pUART_LCR |= DLAB)
# define ACCESS_PORT_IER() (*pUART_LCR &= ~DLAB)
# define CLEAR_IER() (*pUART_IER = 0)
# define ACCESS_LATCH() \
bfin_write16(&pUART->lcr, bfin_read16(&pUART->lcr) | DLAB)
# define ACCESS_PORT_IER() \
bfin_write16(&pUART->lcr, bfin_read16(&pUART->lcr) & ~DLAB)
#endif
__attribute__((always_inline))
@ -142,10 +151,10 @@ static inline void serial_early_init(void)
serial_do_portmux();
/* always enable UART -- avoids anomalies 05000309 and 05000350 */
*pUART_GCTL = UCEN;
bfin_write16(&pUART->gctl, UCEN);
/* Set LCR to Word Lengh 8-bit word select */
*pUART_LCR = WLS_8;
bfin_write16(&pUART->lcr, WLS_8);
SSYNC();
}
@ -158,8 +167,8 @@ static inline void serial_early_put_div(uint16_t divisor)
SSYNC();
/* Program the divisor to get the baud rate we want */
*pUART_DLL = LOB(divisor);
*pUART_DLH = HIB(divisor);
bfin_write16(&pUART->dll, LOB(divisor));
bfin_write16(&pUART->dlh, HIB(divisor));
SSYNC();
/* Clear DLAB in LCR to Access THR RBR IER */
@ -174,8 +183,8 @@ static inline uint16_t serial_early_get_div(void)
ACCESS_LATCH();
SSYNC();
uint8_t dll = *pUART_DLL;
uint8_t dlh = *pUART_DLH;
uint8_t dll = bfin_read16(&pUART->dll);
uint8_t dlh = bfin_read16(&pUART->dlh);
uint16_t divisor = (dlh << 8) | dll;
/* Clear DLAB in LCR to Access THR RBR IER */

24
cpu/blackfin/start.S
View file

@ -95,6 +95,7 @@ ENTRY(_start)
/* Save RETX so we can pass it while booting Linux */
r7 = RETX;
#if CONFIG_MEM_SIZE
/* Figure out where we are currently executing so that we can decide
* how to best reprogram and relocate things. We'll pass below:
* R4: load address of _start
@ -131,6 +132,9 @@ ENTRY(_start)
r3.h = 0x2000;
cc = r5 < r3 (iu);
if cc jump .Ldma_and_reprogram;
#else
r6 = 1 (x); /* fake loaded_from_ldr = 1 */
#endif
r0 = 0 (x); /* set bootstruct to NULL */
call _initcode;
jump .Lprogrammed;
@ -139,11 +143,10 @@ ENTRY(_start)
.Ldma_and_reprogram:
r0.l = LO(L1_INST_SRAM);
r0.h = HI(L1_INST_SRAM);
r1.l = __initcode_start;
r1.h = __initcode_start;
r2.l = __initcode_end;
r2.h = __initcode_end;
r2 = r2 - r1; /* convert r2 into length of initcode */
r1.l = __initcode_lma;
r1.h = __initcode_lma;
r2.l = __initcode_len;
r2.h = __initcode_len;
r1 = r1 - r4; /* convert r1 from load address of initcode ... */
r1 = r1 + r5; /* ... to current (not load) address of initcode */
p3 = r0;
@ -155,6 +158,7 @@ ENTRY(_start)
.Lprogrammed:
serial_early_set_baud
#if CONFIG_MEM_SIZE
/* Relocate from wherever we are (FLASH/RAM/etc...) to the hardcoded
* monitor location in the end of RAM. We know that memcpy() only
* uses registers, so it is safe to call here. Note that this only
@ -167,18 +171,18 @@ ENTRY(_start)
r2.l = LO(CONFIG_SYS_MONITOR_LEN);
r2.h = HI(CONFIG_SYS_MONITOR_LEN);
call _memcpy_ASM;
#endif
/* Initialize BSS section ... we know that memset() does not
* use the BSS, so it is safe to call here. The bootrom LDR
* takes care of clearing things for us.
*/
serial_early_puts("Zero BSS");
r0.l = __bss_start;
r0.h = __bss_start;
r0.l = __bss_vma;
r0.h = __bss_vma;
r1 = 0 (x);
r2.l = __bss_end;
r2.h = __bss_end;
r2 = r2 - r0;
r2.l = __bss_len;
r2.h = __bss_len;
call _memset;
.Lnorelocate:

9
cpu/blackfin/traps.c
View file

@ -100,6 +100,14 @@ void trap_c(struct pt_regs *regs)
uint32_t new_cplb_addr = 0, new_cplb_data = 0;
static size_t last_evicted;
size_t i;
unsigned long tflags;
/*
* Keep the trace buffer so that a miss here points people
* to the right place (their code). Crashes here rarely
* happen. If they do, only the Blackfin maintainer cares.
*/
trace_buffer_save(tflags);
new_cplb_addr = (data ? bfin_read_DCPLB_FAULT_ADDR() : bfin_read_ICPLB_FAULT_ADDR()) & ~(4 * 1024 * 1024 - 1);
@ -156,6 +164,7 @@ void trap_c(struct pt_regs *regs)
for (i = 0; i < 16; ++i)
debug("%2i 0x%p 0x%08X\n", i, *CPLB_ADDR++, *CPLB_DATA++);
trace_buffer_restore(tflags);
break;
}

4
cpu/blackfin/watchdog.c
View file

@ -1,7 +1,7 @@
/*
* watchdog.c - driver for Blackfin on-chip watchdog
*
* Copyright (c) 2007-2008 Analog Devices Inc.
* Copyright (c) 2007-2009 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
@ -10,7 +10,6 @@
#include <watchdog.h>
#include <asm/blackfin.h>
#ifdef CONFIG_HW_WATCHDOG
void hw_watchdog_reset(void)
{
bfin_write_WDOG_STAT(0);
@ -22,4 +21,3 @@ void hw_watchdog_init(void)
hw_watchdog_reset();
bfin_write_WDOG_CTL(0x0);
}
#endif

4
cpu/mpc5xx/traps.c
View file

@ -36,10 +36,6 @@
#include <command.h>
#include <asm/processor.h>
#if defined(CONFIG_CMD_KGDB)
int (*debugger_exception_handler)(struct pt_regs *) = 0;
#endif
#if defined(CONFIG_CMD_BEDBUG)
extern void do_bedbug_breakpoint(struct pt_regs *);
#endif

126
cpu/mpc5xxx/cpu_init.c
View file

@ -1,5 +1,5 @@
/*
* (C) Copyright 2000-2003
* (C) Copyright 2000-2009
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
@ -23,6 +23,7 @@
#include <common.h>
#include <mpc5xxx.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@ -34,6 +35,16 @@ DECLARE_GLOBAL_DATA_PTR;
*/
void cpu_init_f (void)
{
volatile struct mpc5xxx_mmap_ctl *mm =
(struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;
volatile struct mpc5xxx_lpb *lpb =
(struct mpc5xxx_lpb *) MPC5XXX_LPB;
volatile struct mpc5xxx_cdm *cdm =
(struct mpc5xxx_cdm *) MPC5XXX_CDM;
volatile struct mpc5xxx_gpio *gpio =
(struct mpc5xxx_gpio *) MPC5XXX_GPIO;
volatile struct mpc5xxx_xlb *xlb =
(struct mpc5xxx_xlb *) MPC5XXX_XLBARB;
unsigned long addecr = (1 << 25); /* Boot_CS */
#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_MGT5100)
addecr |= (1 << 22); /* SDRAM enable */
@ -48,119 +59,135 @@ void cpu_init_f (void)
* Memory Controller: configure chip selects and enable them
*/
#if defined(CONFIG_SYS_BOOTCS_START) && defined(CONFIG_SYS_BOOTCS_SIZE)
*(vu_long *)MPC5XXX_BOOTCS_START = START_REG(CONFIG_SYS_BOOTCS_START);
*(vu_long *)MPC5XXX_BOOTCS_STOP = STOP_REG(CONFIG_SYS_BOOTCS_START,
CONFIG_SYS_BOOTCS_SIZE);
out_be32(&mm->boot_start, START_REG(CONFIG_SYS_BOOTCS_START));
out_be32(&mm->boot_stop, STOP_REG(CONFIG_SYS_BOOTCS_START,
CONFIG_SYS_BOOTCS_SIZE));
#endif
#if defined(CONFIG_SYS_BOOTCS_CFG)
*(vu_long *)MPC5XXX_BOOTCS_CFG = CONFIG_SYS_BOOTCS_CFG;
out_be32(&lpb->cs0_cfg, CONFIG_SYS_BOOTCS_CFG);
#endif
#if defined(CONFIG_SYS_CS0_START) && defined(CONFIG_SYS_CS0_SIZE)
*(vu_long *)MPC5XXX_CS0_START = START_REG(CONFIG_SYS_CS0_START);
*(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CONFIG_SYS_CS0_START, CONFIG_SYS_CS0_SIZE);
out_be32(&mm->cs0_start, START_REG(CONFIG_SYS_CS0_START));
out_be32(&mm->cs0_stop, STOP_REG(CONFIG_SYS_CS0_START,
CONFIG_SYS_CS0_SIZE));
/* CS0 and BOOT_CS cannot be enabled at once. */
/* addecr |= (1 << 16); */
#endif
#if defined(CONFIG_SYS_CS0_CFG)
*(vu_long *)MPC5XXX_CS0_CFG = CONFIG_SYS_CS0_CFG;
out_be32(&lpb->cs0_cfg, CONFIG_SYS_CS0_CFG);
#endif
#if defined(CONFIG_SYS_CS1_START) && defined(CONFIG_SYS_CS1_SIZE)
*(vu_long *)MPC5XXX_CS1_START = START_REG(CONFIG_SYS_CS1_START);
*(vu_long *)MPC5XXX_CS1_STOP = STOP_REG(CONFIG_SYS_CS1_START, CONFIG_SYS_CS1_SIZE);
out_be32(&mm->cs1_start, START_REG(CONFIG_SYS_CS1_START));
out_be32(&mm->cs1_stop, STOP_REG(CONFIG_SYS_CS1_START,
CONFIG_SYS_CS1_SIZE));
addecr |= (1 << 17);
#endif
#if defined(CONFIG_SYS_CS1_CFG)
*(vu_long *)MPC5XXX_CS1_CFG = CONFIG_SYS_CS1_CFG;
out_be32(&lpb->cs1_cfg, CONFIG_SYS_CS1_CFG);
#endif
#if defined(CONFIG_SYS_CS2_START) && defined(CONFIG_SYS_CS2_SIZE)
*(vu_long *)MPC5XXX_CS2_START = START_REG(CONFIG_SYS_CS2_START);
*(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CONFIG_SYS_CS2_START, CONFIG_SYS_CS2_SIZE);
out_be32(&mm->cs2_start, START_REG(CONFIG_SYS_CS2_START));
out_be32(&mm->cs2_stop, STOP_REG(CONFIG_SYS_CS2_START,
CONFIG_SYS_CS2_SIZE));
addecr |= (1 << 18);
#endif
#if defined(CONFIG_SYS_CS2_CFG)
*(vu_long *)MPC5XXX_CS2_CFG = CONFIG_SYS_CS2_CFG;
out_be32(&lpb->cs2_cfg, CONFIG_SYS_CS2_CFG);
#endif
#if defined(CONFIG_SYS_CS3_START) && defined(CONFIG_SYS_CS3_SIZE)
*(vu_long *)MPC5XXX_CS3_START = START_REG(CONFIG_SYS_CS3_START);
*(vu_long *)MPC5XXX_CS3_STOP = STOP_REG(CONFIG_SYS_CS3_START, CONFIG_SYS_CS3_SIZE);
out_be32(&mm->cs3_start, START_REG(CONFIG_SYS_CS3_START));
out_be32(&mm->cs3_stop, STOP_REG(CONFIG_SYS_CS3_START,
CONFIG_SYS_CS3_SIZE));
addecr |= (1 << 19);
#endif
#if defined(CONFIG_SYS_CS3_CFG)
*(vu_long *)MPC5XXX_CS3_CFG = CONFIG_SYS_CS3_CFG;
out_be32(&lpb->cs3_cfg, CONFIG_SYS_CS3_CFG);
#endif
#if defined(CONFIG_SYS_CS4_START) && defined(CONFIG_SYS_CS4_SIZE)
*(vu_long *)MPC5XXX_CS4_START = START_REG(CONFIG_SYS_CS4_START);
*(vu_long *)MPC5XXX_CS4_STOP = STOP_REG(CONFIG_SYS_CS4_START, CONFIG_SYS_CS4_SIZE);
out_be32(&mm->cs4_start, START_REG(CONFIG_SYS_CS4_START));
out_be32(&mm->cs4_stop, STOP_REG(CONFIG_SYS_CS4_START,
CONFIG_SYS_CS4_SIZE));
addecr |= (1 << 20);
#endif
#if defined(CONFIG_SYS_CS4_CFG)
*(vu_long *)MPC5XXX_CS4_CFG = CONFIG_SYS_CS4_CFG;
out_be32(&lpb->cs4_cfg, CONFIG_SYS_CS4_CFG);
#endif
#if defined(CONFIG_SYS_CS5_START) && defined(CONFIG_SYS_CS5_SIZE)
*(vu_long *)MPC5XXX_CS5_START = START_REG(CONFIG_SYS_CS5_START);
*(vu_long *)MPC5XXX_CS5_STOP = STOP_REG(CONFIG_SYS_CS5_START, CONFIG_SYS_CS5_SIZE);
out_be32(&mm->cs5_start, START_REG(CONFIG_SYS_CS5_START));
out_be32(&mm->cs5_stop, STOP_REG(CONFIG_SYS_CS5_START,
CONFIG_SYS_CS5_SIZE));
addecr |= (1 << 21);
#endif
#if defined(CONFIG_SYS_CS5_CFG)
*(vu_long *)MPC5XXX_CS5_CFG = CONFIG_SYS_CS5_CFG;
out_be32(&lpb->cs5_cfg, CONFIG_SYS_CS5_CFG);
#endif
#if defined(CONFIG_MPC5200)
addecr |= 1;
#if defined(CONFIG_SYS_CS6_START) && defined(CONFIG_SYS_CS6_SIZE)
*(vu_long *)MPC5XXX_CS6_START = START_REG(CONFIG_SYS_CS6_START);
*(vu_long *)MPC5XXX_CS6_STOP = STOP_REG(CONFIG_SYS_CS6_START, CONFIG_SYS_CS6_SIZE);
out_be32(&mm->cs6_start, START_REG(CONFIG_SYS_CS6_START));
out_be32(&mm->cs6_stop, STOP_REG(CONFIG_SYS_CS6_START,
CONFIG_SYS_CS6_SIZE));
addecr |= (1 << 26);
#endif
#if defined(CONFIG_SYS_CS6_CFG)
*(vu_long *)MPC5XXX_CS6_CFG = CONFIG_SYS_CS6_CFG;
out_be32(&lpb->cs6_cfg, CONFIG_SYS_CS6_CFG);
#endif
#if defined(CONFIG_SYS_CS7_START) && defined(CONFIG_SYS_CS7_SIZE)
*(vu_long *)MPC5XXX_CS7_START = START_REG(CONFIG_SYS_CS7_START);
*(vu_long *)MPC5XXX_CS7_STOP = STOP_REG(CONFIG_SYS_CS7_START, CONFIG_SYS_CS7_SIZE);
out_be32(&mm->cs7_start, START_REG(CONFIG_SYS_CS7_START));
out_be32(&mm->cs7_stop, STOP_REG(CONFIG_SYS_CS7_START,
CONFIG_SYS_CS7_SIZE));
addecr |= (1 << 27);
#endif
#if defined(CONFIG_SYS_CS7_CFG)
*(vu_long *)MPC5XXX_CS7_CFG = CONFIG_SYS_CS7_CFG;
out_be32(&lpb->cs7_cfg, CONFIG_SYS_CS7_CFG);
#endif
#if defined(CONFIG_SYS_CS_BURST)
*(vu_long *)MPC5XXX_CS_BURST = CONFIG_SYS_CS_BURST;
out_be32(&lpb->cs_burst, CONFIG_SYS_CS_BURST);
#endif
#if defined(CONFIG_SYS_CS_DEADCYCLE)
*(vu_long *)MPC5XXX_CS_DEADCYCLE = CONFIG_SYS_CS_DEADCYCLE;
out_be32(&lpb->cs_deadcycle, CONFIG_SYS_CS_DEADCYCLE);
#endif
#endif /* CONFIG_MPC5200 */
/* Enable chip selects */
*(vu_long *)MPC5XXX_ADDECR = addecr;
*(vu_long *)MPC5XXX_CS_CTRL = (1 << 24);
#if defined(CONFIG_MGT5100)
out_be32(&mm->addecr, addecr);
#elif defined(CONFIG_MPC5200)
out_be32(&mm->ipbi_ws_ctrl, addecr);
#endif
out_be32(&lpb->cs_ctrl, (1 << 24));
/* Setup pin multiplexing */
#if defined(CONFIG_SYS_GPS_PORT_CONFIG)
*(vu_long *)MPC5XXX_GPS_PORT_CONFIG = CONFIG_SYS_GPS_PORT_CONFIG;
out_be32(&gpio->port_config, CONFIG_SYS_GPS_PORT_CONFIG);
#endif
#if defined(CONFIG_MPC5200)
/* enable timebase */
*(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (1 << 13);
setbits_be32(&xlb->config, (1 << 13));
/* Enable snooping for RAM */
*(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (1 << 15);
*(vu_long *)(MPC5XXX_XLBARB + 0x70) = CONFIG_SYS_SDRAM_BASE | 0x1d;
setbits_be32(&xlb->config, (1 << 15));
out_be32(&xlb->snoop_window, CONFIG_SYS_SDRAM_BASE | 0x1d);
# if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
/* Motorola reports IPB should better run at 133 MHz. */
*(vu_long *)MPC5XXX_ADDECR |= 1;
#if defined(CONFIG_MGT5100)
setbits_be32(&mm->addecr, 1);
#elif defined(CONFIG_MPC5200)
setbits_be32(&mm->ipbi_ws_ctrl, 1);
#endif
/* pci_clk_sel = 0x02, ipb_clk_sel = 0x00; */
addecr = *(vu_long *)MPC5XXX_CDM_CFG;
addecr = in_be32(&cdm->cfg);
addecr &= ~0x103;
# if defined(CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2)
/* pci_clk_sel = 0x01 -> IPB_CLK/2 */
@ -169,15 +196,15 @@ void cpu_init_f (void)
/* pci_clk_sel = 0x02 -> XLB_CLK/4 = IPB_CLK/4 */
addecr |= 0x02;
# endif /* CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 */
*(vu_long *)MPC5XXX_CDM_CFG = addecr;
out_be32(&cdm->cfg, addecr);
# endif /* CONFIG_SYS_IPBCLK_EQUALS_XLBCLK */
/* Configure the XLB Arbiter */
*(vu_long *)MPC5XXX_XLBARB_MPRIEN = 0xff;
*(vu_long *)MPC5XXX_XLBARB_MPRIVAL = 0x11111111;
out_be32(&xlb->master_pri_enable, 0xff);
out_be32(&xlb->master_priority, 0x11111111);
# if defined(CONFIG_SYS_XLB_PIPELINING)
/* Enable piplining */
*(vu_long *)(MPC5XXX_XLBARB + 0x40) &= ~(1 << 31);
clrbits_be32(&xlb->config, (1 << 31));
# endif
#endif /* CONFIG_MPC5200 */
}
@ -187,16 +214,19 @@ void cpu_init_f (void)
*/
int cpu_init_r (void)
{
volatile struct mpc5xxx_intr *intr =
(struct mpc5xxx_intr *) MPC5XXX_ICTL;
/* mask all interrupts */
#if defined(CONFIG_MGT5100)
*(vu_long *)MPC5XXX_ICTL_PER_MASK = 0xfffffc00;
out_be32(&intr->per_mask, 0xfffffc00);
#elif defined(CONFIG_MPC5200)
*(vu_long *)MPC5XXX_ICTL_PER_MASK = 0xffffff00;
out_be32(&intr->per_mask, 0xffffff00);
#endif
*(vu_long *)MPC5XXX_ICTL_CRIT |= 0x0001ffff;
*(vu_long *)MPC5XXX_ICTL_EXT &= ~0x00000f00;
setbits_be32(&intr->main_mask, 0x0001ffff);
clrbits_be32(&intr->ctrl, 0x00000f00);
/* route critical ints to normal ints */
*(vu_long *)MPC5XXX_ICTL_EXT |= 0x00000001;
setbits_be32(&intr->ctrl, 0x00000001);
#if defined(CONFIG_CMD_NET) && defined(CONFIG_MPC5xxx_FEC)
/* load FEC microcode */

4
cpu/mpc5xxx/traps.c
View file

@ -37,10 +37,6 @@
#include <command.h>
#include <asm/processor.h>
#if defined(CONFIG_CMD_KGDB)
int (*debugger_exception_handler)(struct pt_regs *) = 0;
#endif
/* Returns 0 if exception not found and fixup otherwise. */
extern unsigned long search_exception_table(unsigned long);

4
cpu/mpc8220/traps.c
View file

@ -37,10 +37,6 @@
#include <command.h>
#include <asm/processor.h>
#if defined(CONFIG_CMD_KGDB)
int (*debugger_exception_handler) (struct pt_regs *) = 0;
#endif
/* Returns 0 if exception not found and fixup otherwise. */
extern unsigned long search_exception_table (unsigned long);

4
cpu/mpc8260/traps.c
View file

@ -37,10 +37,6 @@
#include <asm/processor.h>
#include <asm/m8260_pci.h>
#if defined(CONFIG_CMD_KGDB)
int (*debugger_exception_handler)(struct pt_regs *) = 0;
#endif
/* Returns 0 if exception not found and fixup otherwise. */
extern unsigned long search_exception_table(unsigned long);

4
cpu/mpc85xx/traps.c
View file

@ -42,10 +42,6 @@
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_CMD_KGDB)
int (*debugger_exception_handler)(struct pt_regs *) = 0;
#endif
/* Returns 0 if exception not found and fixup otherwise. */
extern unsigned long search_exception_table(unsigned long);

4
cpu/mpc86xx/traps.c
View file

@ -36,10 +36,6 @@
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_CMD_KGDB)
int (*debugger_exception_handler)(struct pt_regs *) = 0;
#endif
/* Returns 0 if exception not found and fixup otherwise. */
extern unsigned long search_exception_table(unsigned long);

4
cpu/mpc8xx/traps.c
View file

@ -36,10 +36,6 @@
#include <command.h>
#include <asm/processor.h>
#if defined(CONFIG_CMD_KGDB)
int (*debugger_exception_handler)(struct pt_regs *) = 0;
#endif
#if defined(CONFIG_CMD_BEDBUG)
extern void do_bedbug_breakpoint(struct pt_regs *);
#endif

4
cpu/ppc4xx/4xx_pcie.c
View file

@ -924,7 +924,7 @@ static inline u64 ppc4xx_get_cfgaddr(int port)
}
/*
* 4xx boards as end point and root point setup
* 4xx boards as endpoint and root point setup
* and
* testing inbound and out bound windows
*
@ -940,7 +940,7 @@ static inline u64 ppc4xx_get_cfgaddr(int port)
*
* Once your board came up as root point , you can verify by reading
* /proc/bus/pci/devices. Where you can see the configuration registers
* of end point device attached to the port.
* of endpoint device attached to the port.
*
* Enpoint cofiguration can be verified by connecting 4xx board to any
* host or another 4xx board. Then try to scan the device. In case of

4
cpu/ppc4xx/traps.c
View file

@ -38,10 +38,6 @@
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_CMD_KGDB)
int (*debugger_exception_handler)(struct pt_regs *) = 0;
#endif
/* Returns 0 if exception not found and fixup otherwise. */
extern unsigned long search_exception_table(unsigned long);

527
drivers/mmc/bfin_sdh.c
View file

@ -1,7 +1,7 @@
/*
* Driver for Blackfin on-chip SDH controller
*
* Copyright (c) 2008 Analog Devices Inc.
* Copyright (c) 2008-2009 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
@ -18,20 +18,6 @@
#include <asm/mach-common/bits/sdh.h>
#include <asm/mach-common/bits/dma.h>
#include "bfin_sdh.h"
/* SD_CLK frequency must be less than 400k in identification mode */
#ifndef CONFIG_SYS_MMC_CLK_ID
#define CONFIG_SYS_MMC_CLK_ID 200000
#endif
/* SD_CLK for normal working */
#ifndef CONFIG_SYS_MMC_CLK_OP
#define CONFIG_SYS_MMC_CLK_OP 25000000
#endif
/* support 3.2-3.3V and 3.3-3.4V */
#define CONFIG_SYS_MMC_OP_COND 0x00300000
#define MMC_DEFAULT_RCA 1
#if defined(__ADSPBF51x__)
# define bfin_read_SDH_PWR_CTL bfin_read_RSI_PWR_CONTROL
# define bfin_write_SDH_PWR_CTL bfin_write_RSI_PWR_CONTROL
@ -64,61 +50,17 @@
# error no support for this proc yet
#endif
static unsigned int mmc_rca;
static int mmc_card_is_sd;
static block_dev_desc_t mmc_blkdev;
struct mmc_cid cid;
static __u32 csd[4];
#define get_bits(resp, start, size) \
({ \
const int __size = size; \
const uint32_t __mask = (__size < 32 ? 1 << __size : 0) - 1; \
const int32_t __off = 3 - ((start) / 32); \
const int32_t __shft = (start) & 31; \
uint32_t __res; \
\
__res = resp[__off] >> __shft; \
if (__size + __shft > 32) \
__res |= resp[__off-1] << ((32 - __shft) % 32); \
__res & __mask; \
})
block_dev_desc_t *mmc_get_dev(int dev)
{
return &mmc_blkdev;
}
static void mci_set_clk(unsigned long clk)
{
unsigned long sys_clk;
unsigned long clk_div;
__u16 clk_ctl = 0;
/* setting SD_CLK */
sys_clk = get_sclk();
bfin_write_SDH_CLK_CTL(0);
if (sys_clk % (2 * clk) == 0)
clk_div = sys_clk / (2 * clk) - 1;
else
clk_div = sys_clk / (2 * clk);
if (clk_div > 0xff)
clk_div = 0xff;
clk_ctl |= (clk_div & 0xff);
clk_ctl |= CLK_E;
bfin_write_SDH_CLK_CTL(clk_ctl);
}
static int
mmc_cmd(unsigned long cmd, unsigned long arg, void *resp, unsigned long flags)
sdh_send_cmd(struct mmc *mmc, struct mmc_cmd *mmc_cmd)
{
unsigned int sdh_cmd;
unsigned int status;
int cmd = mmc_cmd->cmdidx;
int flags = mmc_cmd->resp_type;
int arg = mmc_cmd->cmdarg;
int ret = 0;
sdh_cmd = 0;
unsigned long *response = resp;
sdh_cmd |= cmd;
if (flags & MMC_RSP_PRESENT)
@ -138,336 +80,137 @@ mmc_cmd(unsigned long cmd, unsigned long arg, void *resp, unsigned long flags)
CMD_CRC_FAIL)));
if (flags & MMC_RSP_PRESENT) {
response[0] = bfin_read_SDH_RESPONSE0();
mmc_cmd->response[0] = bfin_read_SDH_RESPONSE0();
if (flags & MMC_RSP_136) {
response[1] = bfin_read_SDH_RESPONSE1();
response[2] = bfin_read_SDH_RESPONSE2();
response[3] = bfin_read_SDH_RESPONSE3();
mmc_cmd->response[1] = bfin_read_SDH_RESPONSE1();
mmc_cmd->response[2] = bfin_read_SDH_RESPONSE2();
mmc_cmd->response[3] = bfin_read_SDH_RESPONSE3();
}
}
if (status & CMD_TIME_OUT) {
printf("CMD%d timeout\n", (int)cmd);
ret |= -ETIMEDOUT;
} else if (status & CMD_CRC_FAIL && flags & MMC_RSP_CRC) {
printf("CMD%d CRC failure\n", (int)cmd);
ret |= -EILSEQ;
}
if (status & CMD_TIME_OUT)
ret |= TIMEOUT;
else if (status & CMD_CRC_FAIL && flags & MMC_RSP_CRC)
ret |= COMM_ERR;
bfin_write_SDH_STATUS_CLR(CMD_SENT_STAT | CMD_RESP_END_STAT |
CMD_TIMEOUT_STAT | CMD_CRC_FAIL_STAT);
return ret;
}
static int
mmc_acmd(unsigned long cmd, unsigned long arg, void *resp, unsigned long flags)
/* set data for single block transfer */
static int sdh_setup_data(struct mmc *mmc, struct mmc_data *data)
{
unsigned long aresp[4];
u16 data_ctl = 0;
u16 dma_cfg = 0;
int ret = 0;
ret = mmc_cmd(MMC_CMD_APP_CMD, 0, aresp,
MMC_RSP_PRESENT);
if (ret)
return ret;
/* Don't support write yet. */
if (data->flags & MMC_DATA_WRITE)
return UNUSABLE_ERR;
data_ctl |= ((ffs(data->blocksize) - 1) << 4);
data_ctl |= DTX_DIR;
bfin_write_SDH_DATA_CTL(data_ctl);
dma_cfg = WDSIZE_32 | RESTART | WNR | DMAEN;
bfin_write_SDH_DATA_TIMER(0xFFFF);
blackfin_dcache_flush_invalidate_range(data->dest,
data->dest + data->blocksize);
/* configure DMA */
bfin_write_DMA_START_ADDR(data->dest);
bfin_write_DMA_X_COUNT(data->blocksize / 4);
bfin_write_DMA_X_MODIFY(4);
bfin_write_DMA_CONFIG(dma_cfg);
bfin_write_SDH_DATA_LGTH(data->blocksize);
/* kick off transfer */
bfin_write_SDH_DATA_CTL(bfin_read_SDH_DATA_CTL() | DTX_DMA_E | DTX_E);
if ((aresp[0] & (ILLEGAL_COMMAND | APP_CMD)) != APP_CMD)
return -ENODEV;
ret = mmc_cmd(cmd, arg, resp, flags);
return ret;
}
static unsigned long
mmc_bread(int dev, unsigned long start, lbaint_t blkcnt, void *buffer)
static int bfin_sdh_request(struct mmc *mmc, struct mmc_cmd *cmd,
struct mmc_data *data)
{
int ret, i;
unsigned long resp[4];
unsigned long card_status;
__u8 *buf = buffer;
__u32 status;
__u16 data_ctl = 0;
__u16 dma_cfg = 0;
if (blkcnt == 0)
return 0;
debug("mmc_bread: dev %d, start %d, blkcnt %d\n", dev, start, blkcnt);
/* Force to use 512-byte block,because a lot of code depends on this */
data_ctl |= 9 << 4;
data_ctl |= DTX_DIR;
bfin_write_SDH_DATA_CTL(data_ctl);
dma_cfg |= WDSIZE_32 | RESTART | WNR | DMAEN;
/* FIXME later */
bfin_write_SDH_DATA_TIMER(0xFFFFFFFF);
for (i = 0; i < blkcnt; ++i, ++start) {
blackfin_dcache_flush_invalidate_range(buf + i * mmc_blkdev.blksz,
buf + (i + 1) * mmc_blkdev.blksz);
bfin_write_DMA_START_ADDR(buf + i * mmc_blkdev.blksz);
bfin_write_DMA_X_COUNT(mmc_blkdev.blksz / 4);
bfin_write_DMA_X_MODIFY(4);
bfin_write_DMA_CONFIG(dma_cfg);
bfin_write_SDH_DATA_LGTH(mmc_blkdev.blksz);
/* Put the device into Transfer state */
ret = mmc_cmd(MMC_CMD_SELECT_CARD, mmc_rca << 16, resp, MMC_RSP_R1);
if (ret) {
printf("MMC_CMD_SELECT_CARD failed\n");
goto out;
}
/* Set block length */
ret = mmc_cmd(MMC_CMD_SET_BLOCKLEN, mmc_blkdev.blksz, resp, MMC_RSP_R1);
if (ret) {
printf("MMC_CMD_SET_BLOCKLEN failed\n");
goto out;
}
ret = mmc_cmd(MMC_CMD_READ_SINGLE_BLOCK,
start * mmc_blkdev.blksz, resp,
MMC_RSP_R1);
if (ret) {
printf("MMC_CMD_READ_SINGLE_BLOCK failed\n");
goto out;
}
bfin_write_SDH_DATA_CTL(bfin_read_SDH_DATA_CTL() | DTX_DMA_E | DTX_E);
u32 status;
int ret = 0;
ret = sdh_send_cmd(mmc, cmd);
if (ret) {
printf("sending CMD%d failed\n", cmd->cmdidx);
return ret;
}
if (data) {
ret = sdh_setup_data(mmc, data);
do {
udelay(1);
status = bfin_read_SDH_STATUS();
} while (!(status & (DAT_BLK_END | DAT_END | DAT_TIME_OUT | DAT_CRC_FAIL | RX_OVERRUN)));
if (status & (DAT_TIME_OUT | DAT_CRC_FAIL | RX_OVERRUN)) {
bfin_write_SDH_STATUS_CLR(DAT_TIMEOUT_STAT | \
DAT_CRC_FAIL_STAT | RX_OVERRUN_STAT);
goto read_error;
} else {
if (status & DAT_TIME_OUT) {
bfin_write_SDH_STATUS_CLR(DAT_TIMEOUT_STAT);
ret |= TIMEOUT;
} else if (status & (DAT_CRC_FAIL | RX_OVERRUN)) {
bfin_write_SDH_STATUS_CLR(DAT_CRC_FAIL_STAT | RX_OVERRUN_STAT);
ret |= COMM_ERR;
} else
bfin_write_SDH_STATUS_CLR(DAT_BLK_END_STAT | DAT_END_STAT);
mmc_cmd(MMC_CMD_SELECT_CARD, 0, resp, 0);
if (ret) {
printf("tranfering data failed\n");
return ret;
}
}
out:
return i;
read_error:
mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, &card_status, MMC_RSP_R1);
printf("mmc: bread failed, status = %08x, card status = %08lx\n",
status, card_status);
goto out;
}
static unsigned long
mmc_bwrite(int dev, unsigned long start, lbaint_t blkcnt, const void *buffer)
{
int ret, i = 0;
unsigned long resp[4];
unsigned long card_status;
const __u8 *buf = buffer;
__u32 status;
__u16 data_ctl = 0;
__u16 dma_cfg = 0;
if (blkcnt == 0)
return 0;
debug("mmc_bwrite: dev %d, start %lx, blkcnt %lx\n",
dev, start, blkcnt);
/* Force to use 512-byte block,because a lot of code depends on this */
data_ctl |= 9 << 4;
data_ctl &= ~DTX_DIR;
bfin_write_SDH_DATA_CTL(data_ctl);
dma_cfg |= WDSIZE_32 | RESTART | DMAEN;
/* FIXME later */
bfin_write_SDH_DATA_TIMER(0xFFFFFFFF);
for (i = 0; i < blkcnt; ++i, ++start) {
bfin_write_DMA_START_ADDR(buf + i * mmc_blkdev.blksz);
bfin_write_DMA_X_COUNT(mmc_blkdev.blksz / 4);
bfin_write_DMA_X_MODIFY(4);
bfin_write_DMA_CONFIG(dma_cfg);
bfin_write_SDH_DATA_LGTH(mmc_blkdev.blksz);
/* Put the device into Transfer state */
ret = mmc_cmd(MMC_CMD_SELECT_CARD, mmc_rca << 16, resp, MMC_RSP_R1);
if (ret) {
printf("MMC_CMD_SELECT_CARD failed\n");
goto out;
}
/* Set block length */
ret = mmc_cmd(MMC_CMD_SET_BLOCKLEN, mmc_blkdev.blksz, resp, MMC_RSP_R1);
if (ret) {
printf("MMC_CMD_SET_BLOCKLEN failed\n");
goto out;
}
ret = mmc_cmd(MMC_CMD_WRITE_SINGLE_BLOCK,
start * mmc_blkdev.blksz, resp,
MMC_RSP_R1);
if (ret) {
printf("MMC_CMD_WRITE_SINGLE_BLOCK failed\n");
goto out;
}
bfin_write_SDH_DATA_CTL(bfin_read_SDH_DATA_CTL() | DTX_DMA_E | DTX_E);
do {
udelay(1);
status = bfin_read_SDH_STATUS();
} while (!(status & (DAT_BLK_END | DAT_END | DAT_TIME_OUT | DAT_CRC_FAIL | TX_UNDERRUN)));
if (status & (DAT_TIME_OUT | DAT_CRC_FAIL | TX_UNDERRUN)) {
bfin_write_SDH_STATUS_CLR(DAT_TIMEOUT_STAT |
DAT_CRC_FAIL_STAT | TX_UNDERRUN_STAT);
goto write_error;
} else {
bfin_write_SDH_STATUS_CLR(DAT_BLK_END_STAT | DAT_END_STAT);
mmc_cmd(MMC_CMD_SELECT_CARD, 0, resp, 0);
}
}
out:
return i;
write_error:
mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, &card_status, MMC_RSP_R1);
printf("mmc: bwrite failed, status = %08x, card status = %08lx\n",
status, card_status);
goto out;
}
static void mmc_parse_cid(struct mmc_cid *cid, unsigned long *resp)
{
cid->mid = resp[0] >> 24;
cid->oid = (resp[0] >> 8) & 0xffff;
cid->pnm[0] = resp[0];
cid->pnm[1] = resp[1] >> 24;
cid->pnm[2] = resp[1] >> 16;
cid->pnm[3] = resp[1] >> 8;
cid->pnm[4] = resp[1];
cid->pnm[5] = resp[2] >> 24;
cid->pnm[6] = 0;
cid->prv = resp[2] >> 16;
cid->psn = (resp[2] << 16) | (resp[3] >> 16);
cid->mdt = resp[3] >> 8;
}
static void sd_parse_cid(struct mmc_cid *cid, unsigned long *resp)
{
cid->mid = resp[0] >> 24;
cid->oid = (resp[0] >> 8) & 0xffff;
cid->pnm[0] = resp[0];
cid->pnm[1] = resp[1] >> 24;
cid->pnm[2] = resp[1] >> 16;
cid->pnm[3] = resp[1] >> 8;
cid->pnm[4] = resp[1];
cid->pnm[5] = 0;
cid->pnm[6] = 0;
cid->prv = resp[2] >> 24;
cid->psn = (resp[2] << 8) | (resp[3] >> 24);
cid->mdt = (resp[3] >> 8) & 0x0fff;
}
static void mmc_dump_cid(const struct mmc_cid *cid)
{
printf("CID information:\n");
printf("Manufacturer ID: %02X\n", cid->mid);
printf("OEM/Application ID: %04X\n", cid->oid);
printf("Product name: %s\n", cid->pnm);
printf("Product Revision: %u.%u\n",
cid->prv >> 4, cid->prv & 0x0f);
printf("Product Serial Number: %lu\n", cid->psn);
printf("Manufacturing Date: %02u/%02u\n",
cid->mdt >> 4, cid->mdt & 0x0f);
}
static void mmc_dump_csd(__u32 *csd)
{
printf("CSD information:\n");
printf("CSD structure version: 1.%u\n", get_bits(csd, 126, 2));
printf("Card command classes: %03x\n", get_bits(csd, 84, 12));
printf("Max trans speed: %s\n", (get_bits(csd, 96, 8) == 0x32) ? "25MHz" : "50MHz");
printf("Read block length: %d\n", 1 << get_bits(csd, 80, 4));
printf("Write block length: %u\n", 1 << get_bits(csd, 22, 4));
printf("Card capacity: %u bytes\n",
(get_bits(csd, 62, 12) + 1) * (1 << (get_bits(csd, 47, 3) + 2)) *
(1 << get_bits(csd, 80, 4)));
putc('\n');
}
static int mmc_idle_cards(void)
{
int ret = 0;
/* Reset all cards */
ret = mmc_cmd(MMC_CMD_GO_IDLE_STATE, 0, NULL, 0);
if (ret)
return ret;
udelay(500);
return mmc_cmd(MMC_CMD_GO_IDLE_STATE, 0, NULL, 0);
}
static int sd_init_card(struct mmc_cid *cid, int verbose)
{
unsigned long resp[4];
int i, ret = 0;
mmc_idle_cards();
for (i = 0; i < 1000; ++i) {
ret = mmc_acmd(SD_CMD_APP_SEND_OP_COND, CONFIG_SYS_MMC_OP_COND,
resp, MMC_RSP_R3);
if (ret || (resp[0] & 0x80000000))
break;
ret = -ETIMEDOUT;
}
if (ret)
return ret;
ret = mmc_cmd(MMC_CMD_ALL_SEND_CID, 0, resp, MMC_RSP_R2);
if (ret)
return ret;
sd_parse_cid(cid, resp);
if (verbose)
mmc_dump_cid(cid);
/* Get RCA of the card that responded */
ret = mmc_cmd(SD_CMD_SEND_RELATIVE_ADDR, 0, resp, MMC_RSP_R6);
if (ret)
return ret;
mmc_rca = (resp[0] >> 16) & 0xffff;
if (verbose)
printf("SD Card detected (RCA %u)\n", mmc_rca);
mmc_card_is_sd = 1;
return 0;
}
static int mmc_init_card(struct mmc_cid *cid, int verbose)
static void sdh_set_clk(unsigned long clk)
{
unsigned long resp[4];
int i, ret = 0;
unsigned long sys_clk;
unsigned long clk_div;
u16 clk_ctl = 0;
mmc_idle_cards();
for (i = 0; i < 1000; ++i) {
ret = mmc_cmd(MMC_CMD_SEND_OP_COND, CONFIG_SYS_MMC_OP_COND, resp,
MMC_RSP_R3);
if (ret || (resp[0] & 0x80000000))
break;
ret = -ETIMEDOUT;
}
if (ret)
return ret;
clk_ctl = bfin_read_SDH_CLK_CTL();
if (clk) {
/* setting SD_CLK */
sys_clk = get_sclk();
bfin_write_SDH_CLK_CTL(clk_ctl & ~CLK_E);
if (sys_clk % (2 * clk) == 0)
clk_div = sys_clk / (2 * clk) - 1;
else
clk_div = sys_clk / (2 * clk);
/* Get CID of all cards. FIXME: Support more than one card */
ret = mmc_cmd(MMC_CMD_ALL_SEND_CID, 0, resp, MMC_RSP_R2);
if (ret)
return ret;
mmc_parse_cid(cid, resp);
if (verbose)
mmc_dump_cid(cid);
/* Set Relative Address of the card that responded */
ret = mmc_cmd(MMC_CMD_SET_RELATIVE_ADDR, mmc_rca << 16, resp,
MMC_RSP_R1);
return ret;
if (clk_div > 0xff)
clk_div = 0xff;
clk_ctl |= (clk_div & 0xff);
clk_ctl |= CLK_E;
bfin_write_SDH_CLK_CTL(clk_ctl);
} else
bfin_write_SDH_CLK_CTL(clk_ctl & ~CLK_E);
}
int mmc_legacy_init(int verbose)
static void bfin_sdh_set_ios(struct mmc *mmc)
{
__u16 pwr_ctl = 0;
int ret;
unsigned int max_blksz;
/* Initialize sdh controller */
u16 cfg = 0;
u16 clk_ctl = 0;
if (mmc->bus_width == 4) {
cfg = bfin_read_SDH_CFG();
cfg &= ~0x80;
cfg |= 0x40;
bfin_write_SDH_CFG(cfg);
clk_ctl |= WIDE_BUS;
}
bfin_write_SDH_CLK_CTL(clk_ctl);
sdh_set_clk(mmc->clock);
}
static int bfin_sdh_init(struct mmc *mmc)
{
u16 pwr_ctl = 0;
/* Initialize sdh controller */
#if defined(__ADSPBF54x__)
bfin_write_DMAC1_PERIMUX(bfin_read_DMAC1_PERIMUX() | 0x1);
bfin_write_PORTC_FER(bfin_read_PORTC_FER() | 0x3F00);
@ -481,56 +224,34 @@ int mmc_legacy_init(int verbose)
bfin_write_SDH_CFG(bfin_read_SDH_CFG() | CLKS_EN);
/* Disable card detect pin */
bfin_write_SDH_CFG((bfin_read_SDH_CFG() & 0x1F) | 0x60);
mci_set_clk(CONFIG_SYS_MMC_CLK_ID);
/* setting power control */
pwr_ctl |= ROD_CTL;
pwr_ctl |= PWR_ON;
bfin_write_SDH_PWR_CTL(pwr_ctl);
mmc_card_is_sd = 0;
ret = sd_init_card(&cid, verbose);
if (ret) {
mmc_rca = MMC_DEFAULT_RCA;
ret = mmc_init_card(&cid, verbose);
}
if (ret)
return ret;
/* Get CSD from the card */
ret = mmc_cmd(MMC_CMD_SEND_CSD, mmc_rca << 16, csd, MMC_RSP_R2);
if (ret)
return ret;
if (verbose)
mmc_dump_csd(csd);
/* Initialize the blockdev structure */
mmc_blkdev.if_type = IF_TYPE_MMC;
mmc_blkdev.part_type = PART_TYPE_DOS;
mmc_blkdev.block_read = mmc_bread;
mmc_blkdev.block_write = mmc_bwrite;
sprintf(mmc_blkdev.vendor,
"Man %02x%04x Snr %08lx",
cid.mid, cid.oid, cid.psn);
strncpy(mmc_blkdev.product, cid.pnm,
sizeof(mmc_blkdev.product));
sprintf(mmc_blkdev.revision, "%x %x",
cid.prv >> 4, cid.prv & 0x0f);
max_blksz = 1 << get_bits(csd, 80, 4);
/*
* If we can't use 512 byte blocks, refuse to deal with the
* card. Tons of code elsewhere seems to depend on this.
*/
if (max_blksz < 512 || (max_blksz > 512 && !get_bits(csd, 79, 1))) {
printf("Card does not support 512 byte reads, aborting.\n");
return -ENODEV;
}
mmc_blkdev.blksz = 512;
mmc_blkdev.lba = (get_bits(csd, 62, 12) + 1) * (1 << (get_bits(csd, 47, 3) + 2));
mci_set_clk(CONFIG_SYS_MMC_CLK_OP);
init_part(&mmc_blkdev);
return 0;
}
int mmc2info(ulong addr)
int bfin_mmc_init(bd_t *bis)
{
struct mmc *mmc = NULL;
mmc = malloc(sizeof(struct mmc));
if (!mmc)
return -ENOMEM;
sprintf(mmc->name, "Blackfin SDH");
mmc->send_cmd = bfin_sdh_request;
mmc->set_ios = bfin_sdh_set_ios;
mmc->init = bfin_sdh_init;
mmc->host_caps = MMC_MODE_4BIT;
mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
mmc->f_max = get_sclk();
mmc->f_min = mmc->f_max >> 9;
mmc->block_dev.part_type = PART_TYPE_DOS;
mmc_register(mmc);
return 0;
}

59
drivers/mmc/bfin_sdh.h
View file

@ -1,59 +0,0 @@
/*
* Copyright (C) 2008 Analog Device Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __BLACKFIN_SDH_H__
#define __BLACKFIN_SDH_H__
#define MMC_RSP_PRESENT (1 << 0)
#define MMC_RSP_136 (1 << 1) /* 136 bit response */
#define MMC_RSP_CRC (1 << 2) /* expect valid crc */
#define MMC_RSP_BUSY (1 << 3) /* card may send busy */
#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */
#define MMC_CMD_MASK (3 << 5) /* non-SPI command type */
#define MMC_CMD_AC (0 << 5)
#define MMC_CMD_ADTC (1 << 5)
#define MMC_CMD_BC (2 << 5)
#define MMC_CMD_BCR (3 << 5)
#define MMC_RSP_SPI_S1 (1 << 7) /* one status byte */
#define MMC_RSP_SPI_S2 (1 << 8) /* second byte */
#define MMC_RSP_SPI_B4 (1 << 9) /* four data bytes */
#define MMC_RSP_SPI_BUSY (1 << 10) /* card may send busy */
/*
* These are the native response types, and correspond to valid bit
* patterns of the above flags. One additional valid pattern
* is all zeros, which means we don't expect a response.
*/
#define MMC_RSP_NONE (0)
#define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
#define MMC_RSP_R1B (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE|MMC_RSP_BUSY)
#define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
#define MMC_RSP_R3 (MMC_RSP_PRESENT)
#define MMC_RSP_R4 (MMC_RSP_PRESENT)
#define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
#define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
#define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
#define ILLEGAL_COMMAND (1 << 22)
#define APP_CMD (1 << 5)
#endif

10
drivers/net/netconsole.c
View file

@ -139,7 +139,7 @@ static void nc_send_packet (const char *buf, int len)
eth_halt ();
}
int nc_start (void)
static int nc_start(void)
{
int netmask, our_ip;
@ -169,7 +169,7 @@ int nc_start (void)
return 0;
}
void nc_putc (char c)
static void nc_putc(char c)
{
if (output_recursion)
return;
@ -180,7 +180,7 @@ void nc_putc (char c)
output_recursion = 0;
}
void nc_puts (const char *s)
static void nc_puts(const char *s)
{
int len;
@ -196,7 +196,7 @@ void nc_puts (const char *s)
output_recursion = 0;
}
int nc_getc (void)
static int nc_getc(void)
{
uchar c;
@ -217,7 +217,7 @@ int nc_getc (void)
return c;
}
int nc_tstc (void)
static int nc_tstc(void)
{
struct eth_device *eth;

13
drivers/spi/bfin_spi.c
View file

@ -85,6 +85,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int mode)
{
struct bfin_spi_slave *bss;
ulong sclk;
u32 mmr_base;
u32 baud;
@ -105,7 +106,11 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
default: return NULL;
}
baud = get_sclk() / (2 * max_hz);
sclk = get_sclk();
baud = sclk / (2 * max_hz);
/* baud should be rounded up */
if (sclk % (2 * max_hz))
baud += 1;
if (baud < 2)
baud = 2;
else if (baud > (u16)-1)
@ -314,6 +319,10 @@ void spi_release_bus(struct spi_slave *slave)
SSYNC();
}
#ifndef CONFIG_BFIN_SPI_IDLE_VAL
# define CONFIG_BFIN_SPI_IDLE_VAL 0xff
#endif
int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
void *din, unsigned long flags)
{
@ -340,7 +349,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
/* todo: take advantage of hardware fifos and setup RX dma */
while (bytes--) {
u8 value = (tx ? *tx++ : 0);
u8 value = (tx ? *tx++ : CONFIG_BFIN_SPI_IDLE_VAL);
debug("%s: tx:%x ", __func__, value);
write_SPI_TDBR(bss, value);
SSYNC();

2
drivers/usb/musb/musb_core.h
View file

@ -133,7 +133,7 @@ struct musb_regs {
u8 rxhubport;
} tar[16];
/*
* end point registers
* endpoint registers
* ep0 elements are valid when array index is 0
* otherwise epN is valid
*/

30
fs/jffs2/LICENCE Normal file
View file

@ -0,0 +1,30 @@
The files in this directory and elsewhere which refer to this LICENCE
file are part of JFFS2, the Journalling Flash File System v2.
Copyright © 2001-2007 Red Hat, Inc. and others
JFFS2 is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 2 or (at your option) any later
version.
JFFS2 is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
You should have received a copy of the GNU General Public License along
with JFFS2; if not, write to the Free Software Foundation, Inc.,
59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
As a special exception, if other files instantiate templates or use
macros or inline functions from these files, or you compile these
files and link them with other works to produce a work based on these
files, these files do not by themselves cause the resulting work to be
covered by the GNU General Public License. However the source code for
these files must still be made available in accordance with section (3)
of the GNU General Public License.
This exception does not invalidate any other reasons why a work based on
this file might be covered by the GNU General Public License.

3
fs/jffs2/Makefile
View file

@ -27,8 +27,7 @@ LIB = $(obj)libjffs2.a
AOBJS =
ifdef CONFIG_CMD_JFFS2
COBJS-$(CONFIG_JFFS2_LZO_LZARI) += compr_lzari.o
COBJS-$(CONFIG_JFFS2_LZO_LZARI) += compr_lzo.o
COBJS-$(CONFIG_JFFS2_LZO) += compr_lzo.o
COBJS-y += compr_rtime.o
COBJS-y += compr_rubin.o
COBJS-y += compr_zlib.o

259
fs/jffs2/compr_lzari.c
View file

@ -1,259 +0,0 @@
/*
* JFFS2 -- Journalling Flash File System, Version 2.
*
* Copyright (C) 2004 Patrik Kluba,
* University of Szeged, Hungary
*
* For licensing information, see the file 'LICENCE' in the
* jffs2 directory.
*
* $Id: compr_lzari.c,v 1.3 2004/06/23 16:34:39 havasi Exp $
*
*/
/*
Lempel-Ziv-Arithmetic coding compression module for jffs2
Based on the LZARI source included in LDS (lossless datacompression sources)
*/
/* -*- Mode: C; indent-tabs-mode: t; c-basic-offset: 4; tab-width: 4 -*- */
/*
Original copyright follows:
**************************************************************
LZARI.C -- A Data Compression Program
(tab = 4 spaces)
**************************************************************
4/7/1989 Haruhiko Okumura
Use, distribute, and modify this program freely.
Please send me your improved versions.
PC-VAN SCIENCE
NIFTY-Serve PAF01022
CompuServe 74050,1022
**************************************************************
LZARI.C (c)1989 by Haruyasu Yoshizaki, Haruhiko Okumura, and Kenji Rikitake.
All rights reserved. Permission granted for non-commercial use.
*/
/*
2004-02-18 pajko <pajko(AT)halom(DOT)u-szeged(DOT)hu>
Removed unused variables and fixed no return value
2004-02-16 pajko <pajko(AT)halom(DOT)u-szeged(DOT)hu>
Initial release
*/
#include <config.h>
#include <linux/stddef.h>
#include <jffs2/jffs2.h>
#define N 4096 /* size of ring buffer */
#define F 60 /* upper limit for match_length */
#define THRESHOLD 2 /* encode string into position and length
if match_length is greater than this */
#define NIL N /* index for root of binary search trees */
static unsigned char
text_buf[N + F - 1]; /* ring buffer of size N,
with extra F-1 bytes to facilitate string comparison */
/********** Arithmetic Compression **********/
/* If you are not familiar with arithmetic compression, you should read
I. E. Witten, R. M. Neal, and J. G. Cleary,
Communications of the ACM, Vol. 30, pp. 520-540 (1987),
from which much have been borrowed. */
#define M 15
/* Q1 (= 2 to the M) must be sufficiently large, but not so
large as the unsigned long 4 * Q1 * (Q1 - 1) overflows. */
#define Q1 (1UL << M)
#define Q2 (2 * Q1)
#define Q3 (3 * Q1)
#define Q4 (4 * Q1)
#define MAX_CUM (Q1 - 1)
#define N_CHAR (256 - THRESHOLD + F)
/* character code = 0, 1, ..., N_CHAR - 1 */
static unsigned long char_to_sym[N_CHAR], sym_to_char[N_CHAR + 1];
static unsigned long
sym_freq[N_CHAR + 1], /* frequency for symbols */
sym_cum[N_CHAR + 1], /* cumulative freq for symbols */
position_cum[N + 1]; /* cumulative freq for positions */
static void StartModel(void) /* Initialize model */
{
unsigned long ch, sym, i;
sym_cum[N_CHAR] = 0;
for (sym = N_CHAR; sym >= 1; sym--) {
ch = sym - 1;
char_to_sym[ch] = sym; sym_to_char[sym] = ch;
sym_freq[sym] = 1;
sym_cum[sym - 1] = sym_cum[sym] + sym_freq[sym];
}
sym_freq[0] = 0; /* sentinel (!= sym_freq[1]) */
position_cum[N] = 0;
for (i = N; i >= 1; i--)
position_cum[i - 1] = position_cum[i] + 10000 / (i + 200);
/* empirical distribution function (quite tentative) */
/* Please devise a better mechanism! */
}
static void UpdateModel(unsigned long sym)
{
unsigned long c, ch_i, ch_sym;
unsigned long i;
if (sym_cum[0] >= MAX_CUM) {
c = 0;
for (i = N_CHAR; i > 0; i--) {
sym_cum[i] = c;
c += (sym_freq[i] = (sym_freq[i] + 1) >> 1);
}
sym_cum[0] = c;
}
for (i = sym; sym_freq[i] == sym_freq[i - 1]; i--) ;
if (i < sym) {
ch_i = sym_to_char[i]; ch_sym = sym_to_char[sym];
sym_to_char[i] = ch_sym; sym_to_char[sym] = ch_i;
char_to_sym[ch_i] = sym; char_to_sym[ch_sym] = i;
}
sym_freq[i]++;
while (--i > 0) sym_cum[i]++;
sym_cum[0]++;
}
static unsigned long BinarySearchSym(unsigned long x)
/* 1 if x >= sym_cum[1],
N_CHAR if sym_cum[N_CHAR] > x,
i such that sym_cum[i - 1] > x >= sym_cum[i] otherwise */
{
unsigned long i, j, k;
i = 1; j = N_CHAR;
while (i < j) {
k = (i + j) / 2;
if (sym_cum[k] > x) i = k + 1; else j = k;
}
return i;
}
unsigned long BinarySearchPos(unsigned long x)
/* 0 if x >= position_cum[1],
N - 1 if position_cum[N] > x,
i such that position_cum[i] > x >= position_cum[i + 1] otherwise */
{
unsigned long i, j, k;
i = 1; j = N;
while (i < j) {
k = (i + j) / 2;
if (position_cum[k] > x) i = k + 1; else j = k;
}
return i - 1;
}
static int Decode(unsigned char *srcbuf, unsigned char *dstbuf, unsigned long srclen,
unsigned long dstlen) /* Just the reverse of Encode(). */
{
unsigned long i, r, j, k, c, range, sym;
unsigned char *ip, *op;
unsigned char *srcend = srcbuf + srclen;
unsigned char *dstend = dstbuf + dstlen;
unsigned char buffer = 0;
unsigned char mask = 0;
unsigned long low = 0;
unsigned long high = Q4;
unsigned long value = 0;
ip = srcbuf;
op = dstbuf;
for (i = 0; i < M + 2; i++) {
value *= 2;
if ((mask >>= 1) == 0) {
buffer = (ip >= srcend) ? 0 : *(ip++);
mask = 128;
}
value += ((buffer & mask) != 0);
}
StartModel();
for (i = 0; i < N - F; i++) text_buf[i] = ' ';
r = N - F;
while (op < dstend) {
range = high - low;
sym = BinarySearchSym((unsigned long)
(((value - low + 1) * sym_cum[0] - 1) / range));
high = low + (range * sym_cum[sym - 1]) / sym_cum[0];
low += (range * sym_cum[sym ]) / sym_cum[0];
for ( ; ; ) {
if (low >= Q2) {
value -= Q2; low -= Q2; high -= Q2;
} else if (low >= Q1 && high <= Q3) {
value -= Q1; low -= Q1; high -= Q1;
} else if (high > Q2) break;
low += low; high += high;
value *= 2;
if ((mask >>= 1) == 0) {
buffer = (ip >= srcend) ? 0 : *(ip++);
mask = 128;
}
value += ((buffer & mask) != 0);
}
c = sym_to_char[sym];
UpdateModel(sym);
if (c < 256) {
if (op >= dstend) return -1;
*(op++) = c;
text_buf[r++] = c;
r &= (N - 1);
} else {
j = c - 255 + THRESHOLD;
range = high - low;
i = BinarySearchPos((unsigned long)
(((value - low + 1) * position_cum[0] - 1) / range));
high = low + (range * position_cum[i ]) / position_cum[0];
low += (range * position_cum[i + 1]) / position_cum[0];
for ( ; ; ) {
if (low >= Q2) {
value -= Q2; low -= Q2; high -= Q2;
} else if (low >= Q1 && high <= Q3) {
value -= Q1; low -= Q1; high -= Q1;
} else if (high > Q2) break;
low += low; high += high;
value *= 2;
if ((mask >>= 1) == 0) {
buffer = (ip >= srcend) ? 0 : *(ip++);
mask = 128;
}
value += ((buffer & mask) != 0);
}
i = (r - i - 1) & (N - 1);
for (k = 0; k < j; k++) {
c = text_buf[(i + k) & (N - 1)];
if (op >= dstend) return -1;
*(op++) = c;
text_buf[r++] = c;
r &= (N - 1);
}
}
}
return 0;
}
int lzari_decompress(unsigned char *data_in, unsigned char *cpage_out,
u32 srclen, u32 destlen)
{
return Decode(data_in, cpage_out, srclen, destlen);
}

8
fs/jffs2/jffs2_1pass.c
View file

@ -471,9 +471,8 @@ static char *compr_names[] = {
"COPY",
"DYNRUBIN",
"ZLIB",
#if defined(CONFIG_JFFS2_LZO_LZARI)
#if defined(CONFIG_JFFS2_LZO)
"LZO",
"LZARI",
#endif
};
@ -781,13 +780,10 @@ jffs2_1pass_read_inode(struct b_lists *pL, u32 inode, char *dest)
case JFFS2_COMPR_ZLIB:
ret = zlib_decompress(src, lDest, jNode->csize, jNode->dsize);
break;
#if defined(CONFIG_JFFS2_LZO_LZARI)
#if defined(CONFIG_JFFS2_LZO)
case JFFS2_COMPR_LZO:
ret = lzo_decompress(src, lDest, jNode->csize, jNode->dsize);
break;
case JFFS2_COMPR_LZARI:
ret = lzari_decompress(src, lDest, jNode->csize, jNode->dsize);
break;
#endif
default:
/* unknown */

8
fs/jffs2/jffs2_nand_1pass.c
View file

@ -34,9 +34,8 @@ static char *compr_names[] = {
"COPY",
"DYNRUBIN",
"ZLIB",
#if defined(CONFIG_JFFS2_LZO_LZARI)
#if defined(CONFIG_JFFS2_LZO)
"LZO",
"LZARI",
#endif
};
@ -344,13 +343,10 @@ jffs2_1pass_read_inode(struct b_lists *pL, u32 ino, char *dest,
case JFFS2_COMPR_ZLIB:
ret = zlib_decompress(src, dst, inode->csize, inode->dsize);
break;
#if defined(CONFIG_JFFS2_LZO_LZARI)
#if defined(CONFIG_JFFS2_LZO)
case JFFS2_COMPR_LZO:
ret = lzo_decompress(src, dst, inode->csize, inode->dsize);
break;
case JFFS2_COMPR_LZARI:
ret = lzari_decompress(src, dst, inode->csize, inode->dsize);
break;
#endif
default:
/* unknown */

1242
include/asm-blackfin/bfin_logo_rgb565_230x230.h Normal file
View file

File diff suppressed because it is too large Load diff

4
include/asm-blackfin/blackfin_local.h
View file

@ -25,6 +25,8 @@
#ifndef __BLACKFIN_LOCAL_H__
#define __BLACKFIN_LOCAL_H__
#include <asm/mem_map.h>
#define LO(con32) ((con32) & 0xFFFF)
#define lo(con32) ((con32) & 0xFFFF)
#define HI(con32) (((con32) >> 16) & 0xFFFF)
@ -59,7 +61,7 @@ extern u_long get_vco(void);
extern u_long get_cclk(void);
extern u_long get_sclk(void);
# define bfin_revid() (*pCHIPID >> 28)
# define bfin_revid() (bfin_read_CHIPID() >> 28)
extern bool bfin_os_log_check(void);
extern void bfin_os_log_dump(void);

3
include/asm-blackfin/config-pre.h
View file

@ -71,4 +71,7 @@ static inline const char *get_bfin_boot_mode(int bfin_boot)
# define BFIN_BOOT_SPI_SSEL 1
#endif
/* We rarely use interrupts, so favor throughput over latency */
#define CONFIG_BFIN_INS_LOWOVERHEAD
#endif

14
include/asm-blackfin/config.h
View file

@ -79,6 +79,11 @@
# define CONFIG_ENV_SPI_CS BFIN_BOOT_SPI_SSEL
#endif
/* We need envcrc to embed the env into LDRs */
#ifdef CONFIG_ENV_IS_EMBEDDED_IN_LDR
# define CONFIG_BUILD_ENVCRC
#endif
/* Default/common Blackfin memory layout */
#ifndef CONFIG_SYS_SDRAM_BASE
# define CONFIG_SYS_SDRAM_BASE 0
@ -87,7 +92,11 @@
# define CONFIG_SYS_MAX_RAM_SIZE (CONFIG_MEM_SIZE * 1024 * 1024)
#endif
#ifndef CONFIG_SYS_MONITOR_BASE
# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_MAX_RAM_SIZE - CONFIG_SYS_MONITOR_LEN)
# if CONFIG_SYS_MAX_RAM_SIZE
# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_MAX_RAM_SIZE - CONFIG_SYS_MONITOR_LEN)
# else
# define CONFIG_SYS_MONITOR_BASE 0
# endif
#endif
#ifndef CONFIG_SYS_MALLOC_BASE
# define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
@ -109,7 +118,8 @@
#endif
/* Check to make sure everything fits in external RAM */
#if ((CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) > CONFIG_SYS_MAX_RAM_SIZE)
#if CONFIG_SYS_MAX_RAM_SIZE && \
((CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) > CONFIG_SYS_MAX_RAM_SIZE)
# error Memory Map does not fit into configuration
#endif

2
include/asm-blackfin/global_data.h
View file

@ -28,6 +28,8 @@
#ifndef __ASM_GBL_DATA_H
#define __ASM_GBL_DATA_H
#include <asm/u-boot.h>
/*
* The following data structure is placed in some memory wich is
* available very early after boot (like DPRAM on MPC8xx/MPC82xx, or

204
include/asm-blackfin/io.h
View file

@ -1,25 +1,9 @@
/*
* U-boot - io.h IO routines
*
* Copyright (c) 2005-2007 Analog Devices Inc.
* Copyright 2004-2009 Analog Devices Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
* Licensed under the GPL-2 or later.
*/
#ifndef _BLACKFIN_IO_H
@ -29,17 +13,13 @@
#include <asm/blackfin.h>
#define __iomem
static inline void sync(void)
{
SSYNC();
}
/* function prototypes for CF support */
extern void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words);
extern void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words);
extern unsigned char cf_inb(volatile unsigned char *addr);
extern void cf_outb(unsigned char val, volatile unsigned char *addr);
/*
* Given a physical address and a length, return a virtual address
* that can be used to access the memory range with the caching
@ -76,114 +56,172 @@ static inline phys_addr_t virt_to_phys(void * vaddr)
*
* readX/writeX() are used to access memory mapped devices. On some
* architectures the memory mapped IO stuff needs to be accessed
* differently. On the m68k architecture, we just read/write the
* differently. On the bfin architecture, we just read/write the
* memory location directly.
*/
#ifndef __ASSEMBLY__
static inline unsigned char readb(const volatile void *addr)
static inline unsigned char readb(const volatile void __iomem *addr)
{
unsigned int val;
int tmp;
__asm__ __volatile__ ("cli %1;\n\t"
"NOP; NOP; SSYNC;\n\t"
"%0 = b [%2] (z);\n\t"
"sti %1;\n\t"
: "=d"(val), "=d"(tmp): "a"(addr));
__asm__ __volatile__ (
"cli %1;"
"NOP; NOP; SSYNC;"
"%0 = b [%2] (z);"
"sti %1;"
: "=d"(val), "=d"(tmp)
: "a"(addr)
);
return (unsigned char) val;
}
static inline unsigned short readw(const volatile void *addr)
static inline unsigned short readw(const volatile void __iomem *addr)
{
unsigned int val;
int tmp;
__asm__ __volatile__ ("cli %1;\n\t"
"NOP; NOP; SSYNC;\n\t"
"%0 = w [%2] (z);\n\t"
"sti %1;\n\t"
: "=d"(val), "=d"(tmp): "a"(addr));
__asm__ __volatile__ (
"cli %1;"
"NOP; NOP; SSYNC;"
"%0 = w [%2] (z);"
"sti %1;"
: "=d"(val), "=d"(tmp)
: "a"(addr)
);
return (unsigned short) val;
}
static inline unsigned int readl(const volatile void *addr)
static inline unsigned int readl(const volatile void __iomem *addr)
{
unsigned int val;
int tmp;
__asm__ __volatile__ ("cli %1;\n\t"
"NOP; NOP; SSYNC;\n\t"
"%0 = [%2];\n\t"
"sti %1;\n\t"
: "=d"(val), "=d"(tmp): "a"(addr));
__asm__ __volatile__ (
"cli %1;"
"NOP; NOP; SSYNC;"
"%0 = [%2];"
"sti %1;"
: "=d"(val), "=d"(tmp)
: "a"(addr)
);
return val;
}
#define __raw_readb readb
#define __raw_readw readw
#define __raw_readl readl
#endif /* __ASSEMBLY__ */
#define writeb(b, addr) (void)((*(volatile unsigned char *) (addr)) = (b))
#define writew(b, addr) (void)((*(volatile unsigned short *) (addr)) = (b))
#define writel(b, addr) (void)((*(volatile unsigned int *) (addr)) = (b))
#define __raw_readb readb
#define __raw_readw readw
#define __raw_readl readl
#define __raw_writeb writeb
#define __raw_writew writew
#define __raw_writel writel
#define memset_io(a, b, c) memset((void *)(a), (b), (c))
#define memcpy_fromio(a, b, c) memcpy((a), (void *)(b), (c))
#define memcpy_toio(a, b, c) memcpy((void *)(a), (b), (c))
#define inb(addr) cf_inb((volatile unsigned char *)(addr))
#define outb(x, addr) cf_outb((unsigned char)(x), (volatile unsigned char *)(addr))
/* Convert "I/O port addresses" to actual addresses. i.e. ugly casts. */
#define __io(port) ((void *)(unsigned long)(port))
#define insw(port, addr, count) cf_insw((unsigned short *)addr, (unsigned short *)(port), (count))
#define inb(port) readb(__io(port))
#define inw(port) readw(__io(port))
#define inl(port) readl(__io(port))
#define outb(x, port) writeb(x, __io(port))
#define outw(x, port) writew(x, __io(port))
#define outl(x, port) writel(x, __io(port))
#define outsw(port, addr, count) cf_outsw((unsigned short *)(port), (unsigned short *)addr, (count))
#define inb_p(port) inb(__io(port))
#define inw_p(port) inw(__io(port))
#define inl_p(port) inl(__io(port))
#define outb_p(x, port) outb(x, __io(port))
#define outw_p(x, port) outw(x, __io(port))
#define outl_p(x, port) outl(x, __io(port))
#define IO_SPACE_LIMIT 0xffff
#define ioread8_rep(a, d, c) readsb(a, d, c)
#define ioread16_rep(a, d, c) readsw(a, d, c)
#define ioread32_rep(a, d, c) readsl(a, d, c)
#define iowrite8_rep(a, s, c) writesb(a, s, c)
#define iowrite16_rep(a, s, c) writesw(a, s, c)
#define iowrite32_rep(a, s, c) writesl(a, s, c)
/* Values for nocacheflag and cmode */
#define IOMAP_FULL_CACHING 0
#define IOMAP_NOCACHE_SER 1
#define IOMAP_NOCACHE_NONSER 2
#define IOMAP_WRITETHROUGH 3
#define ioread8(x) readb(x)
#define ioread16(x) readw(x)
#define ioread32(x) readl(x)
#define iowrite8(val, x) writeb(val, x)
#define iowrite16(val, x) writew(val, x)
#define iowrite32(val, x) writel(val, x)
extern void *__ioremap(unsigned long physaddr, unsigned long size,
int cacheflag);
extern void __iounmap(void *addr, unsigned long size);
#define mmiowb() wmb()
extern inline void *ioremap(unsigned long physaddr, unsigned long size)
#ifndef __ASSEMBLY__
extern void outsb(unsigned long port, const void *addr, unsigned long count);
extern void outsw(unsigned long port, const void *addr, unsigned long count);
extern void outsw_8(unsigned long port, const void *addr, unsigned long count);
extern void outsl(unsigned long port, const void *addr, unsigned long count);
extern void insb(unsigned long port, void *addr, unsigned long count);
extern void insw(unsigned long port, void *addr, unsigned long count);
extern void insw_8(unsigned long port, void *addr, unsigned long count);
extern void insl(unsigned long port, void *addr, unsigned long count);
extern void insl_16(unsigned long port, void *addr, unsigned long count);
static inline void readsl(const void __iomem *addr, void *buf, int len)
{
return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
}
extern inline void *ioremap_nocache(unsigned long physaddr, unsigned long size)
{
return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
}
extern inline void *ioremap_writethrough(unsigned long physaddr,
unsigned long size)
{
return __ioremap(physaddr, size, IOMAP_WRITETHROUGH);
}
extern inline void *ioremap_fullcache(unsigned long physaddr,
unsigned long size)
{
return __ioremap(physaddr, size, IOMAP_FULL_CACHING);
insl((unsigned long)addr, buf, len);
}
extern void iounmap(void *addr);
static inline void readsw(const void __iomem *addr, void *buf, int len)
{
insw((unsigned long)addr, buf, len);
}
extern void blkfin_inv_cache_all(void);
#define dma_cache_inv(_start, _size) do { blkfin_inv_cache_all(); } while (0)
#define dma_cache_wback(_start, _size) do { } while (0)
#define dma_cache_wback_inv(_start, _size) do { blkfin_inv_cache_all(); } while (0)
static inline void readsb(const void __iomem *addr, void *buf, int len)
{
insb((unsigned long)addr, buf, len);
}
static inline void writesl(const void __iomem *addr, const void *buf, int len)
{
outsl((unsigned long)addr, buf, len);
}
static inline void writesw(const void __iomem *addr, const void *buf, int len)
{
outsw((unsigned long)addr, buf, len);
}
static inline void writesb(const void __iomem *addr, const void *buf, int len)
{
outsb((unsigned long)addr, buf, len);
}
#if defined(CONFIG_STAMP_CF) || defined(CONFIG_BFIN_IDE)
/* This hack for CF/IDE needs to be addressed at some point */
extern void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words);
extern void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words);
extern unsigned char cf_inb(volatile unsigned char *addr);
extern void cf_outb(unsigned char val, volatile unsigned char *addr);
#undef inb
#undef outb
#undef insw
#undef outsw
#define inb(addr) cf_inb((void *)(addr))
#define outb(x, addr) cf_outb((unsigned char)(x), (void *)(addr))
#define insw(port, addr, cnt) cf_insw((void *)(addr), (void *)(port), cnt)
#define outsw(port, addr, cnt) cf_outsw((void *)(port), (void *)(addr), cnt)
#endif
#endif
#endif /* __KERNEL__ */
#endif

15
include/asm-blackfin/mach-bf527/BF522_def.h
View file

@ -119,20 +119,5 @@
#define TPERIOD 0xFFE03004 /* Core Timer Period Register */
#define TSCALE 0xFFE03008 /* Core Timer Scale Register */
#define TCOUNT 0xFFE0300C /* Core Timer Count Register */
#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */
#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1)
#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE)
#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */
#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1)
#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE)
#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */
#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1)
#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE)
#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */
#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1)
#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE)
#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */
#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1)
#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE)
#endif /* __BFIN_DEF_ADSP_BF522_proc__ */

15
include/asm-blackfin/mach-bf527/BF523_def.h
View file

@ -119,20 +119,5 @@
#define TPERIOD 0xFFE03004 /* Core Timer Period Register */
#define TSCALE 0xFFE03008 /* Core Timer Scale Register */
#define TCOUNT 0xFFE0300C /* Core Timer Count Register */
#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */
#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1)
#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE)
#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */
#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1)
#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE)
#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */
#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1)
#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE)
#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */
#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1)
#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE)
#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */
#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1)
#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE)
#endif /* __BFIN_DEF_ADSP_BF523_proc__ */

15
include/asm-blackfin/mach-bf527/BF524_def.h
View file

@ -288,20 +288,5 @@
#define USB_DMA7_ADDRHIGH 0xFFC03CEC /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
#define USB_DMA7_COUNTLOW 0xFFC03CF0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
#define USB_DMA7_COUNTHIGH 0xFFC03CF4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */
#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1)
#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE)
#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */
#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1)
#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE)
#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */
#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1)
#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE)
#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */
#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1)
#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE)
#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */
#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1)
#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE)
#endif /* __BFIN_DEF_ADSP_BF524_proc__ */

15
include/asm-blackfin/mach-bf527/BF525_def.h
View file

@ -288,20 +288,5 @@
#define USB_DMA7_ADDRHIGH 0xFFC03CEC /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
#define USB_DMA7_COUNTLOW 0xFFC03CF0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
#define USB_DMA7_COUNTHIGH 0xFFC03CF4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */
#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1)
#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE)
#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */
#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1)
#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE)
#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */
#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1)
#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE)
#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */
#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1)
#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE)
#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */
#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1)
#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE)
#endif /* __BFIN_DEF_ADSP_BF525_proc__ */

15
include/asm-blackfin/mach-bf527/BF526_def.h
View file

@ -367,20 +367,5 @@
#define USB_DMA7_ADDRHIGH 0xFFC03CEC /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
#define USB_DMA7_COUNTLOW 0xFFC03CF0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
#define USB_DMA7_COUNTHIGH 0xFFC03CF4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */
#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1)
#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE)
#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */
#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1)
#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE)
#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */
#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1)
#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE)
#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */
#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1)
#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE)
#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */
#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1)
#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE)
#endif /* __BFIN_DEF_ADSP_BF526_proc__ */

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