From a76df7090882c32e9551590673fb76708346f85d Mon Sep 17 00:00:00 2001 From: Gabriel Huau Date: Sat, 26 Jul 2014 11:35:43 -0700 Subject: [PATCH] mx6: add support of multi-processor command This allows u-boot to load different OS or Bare Metal application on different cores of the i.MX6 SoC. For example: running Android on cpu0 and a RT OS like QNX/FreeRTOS on cpu1. Signed-off-by: Gabriel Huau Acked-by: Stefano Babic --- arch/arm/cpu/armv7/mx6/Makefile | 1 + arch/arm/cpu/armv7/mx6/mp.c | 87 +++++++++++++++++++++++ arch/arm/cpu/armv7/mx6/soc.c | 6 ++ arch/arm/include/asm/arch-mx6/imx-regs.h | 13 ++++ arch/arm/include/asm/arch-mx6/sys_proto.h | 1 + common/board_f.c | 8 +-- include/configs/mx6_common.h | 2 + 7 files changed, 114 insertions(+), 4 deletions(-) create mode 100644 arch/arm/cpu/armv7/mx6/mp.c diff --git a/arch/arm/cpu/armv7/mx6/Makefile b/arch/arm/cpu/armv7/mx6/Makefile index 6dc9f8ec21..bf6effc939 100644 --- a/arch/arm/cpu/armv7/mx6/Makefile +++ b/arch/arm/cpu/armv7/mx6/Makefile @@ -10,3 +10,4 @@ obj-y := soc.o clock.o obj-$(CONFIG_SPL_BUILD) += ddr.o obj-$(CONFIG_SECURE_BOOT) += hab.o +obj-$(CONFIG_MP) += mp.o diff --git a/arch/arm/cpu/armv7/mx6/mp.c b/arch/arm/cpu/armv7/mx6/mp.c new file mode 100644 index 0000000000..9f034d6e13 --- /dev/null +++ b/arch/arm/cpu/armv7/mx6/mp.c @@ -0,0 +1,87 @@ +/* + * (C) Copyright 2014 + * Gabriel Huau + * + * (C) Copyright 2009 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +#define MAX_CPUS 4 +static struct src *src = (struct src *)SRC_BASE_ADDR; + +static uint32_t cpu_reset_mask[MAX_CPUS] = { + 0, /* We don't really want to modify the cpu0 */ + SRC_SCR_CORE_1_RESET_MASK, + SRC_SCR_CORE_2_RESET_MASK, + SRC_SCR_CORE_3_RESET_MASK +}; + +static uint32_t cpu_ctrl_mask[MAX_CPUS] = { + 0, /* We don't really want to modify the cpu0 */ + SRC_SCR_CORE_1_ENABLE_MASK, + SRC_SCR_CORE_2_ENABLE_MASK, + SRC_SCR_CORE_3_ENABLE_MASK +}; + +int cpu_reset(int nr) +{ + /* Software reset of the CPU N */ + src->scr |= cpu_reset_mask[nr]; + return 0; +} + +int cpu_status(int nr) +{ + printf("core %d => %d\n", nr, !!(src->scr & cpu_ctrl_mask[nr])); + return 0; +} + +int cpu_release(int nr, int argc, char *const argv[]) +{ + uint32_t boot_addr; + + boot_addr = simple_strtoul(argv[0], NULL, 16); + + switch (nr) { + case 1: + src->gpr3 = boot_addr; + break; + case 2: + src->gpr5 = boot_addr; + break; + case 3: + src->gpr7 = boot_addr; + break; + default: + return 1; + } + + /* CPU N is ready to start */ + src->scr |= cpu_ctrl_mask[nr]; + + return 0; +} + +int is_core_valid(unsigned int core) +{ + uint32_t nr_cores = get_nr_cpus(); + + if (core > nr_cores) + return 0; + + return 1; +} + +int cpu_disable(int nr) +{ + /* Disable the CPU N */ + src->scr &= ~cpu_ctrl_mask[nr]; + return 0; +} diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index f2dee76941..ac84a1fbfb 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -35,6 +35,12 @@ struct scu_regs { u32 fpga_rev; }; +u32 get_nr_cpus(void) +{ + struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR; + return readl(&scu->config) & 3; +} + u32 get_cpu_rev(void) { struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index d4ce8a8733..2631beb924 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -324,6 +324,19 @@ extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac); +#define SRC_SCR_CORE_1_RESET_OFFSET 14 +#define SRC_SCR_CORE_1_RESET_MASK (1< #endif +#if (defined(CONFIG_MPC86xx) || defined(CONFIG_E500)) +#include +#endif #include #include @@ -43,9 +46,6 @@ #include #include #include -#ifdef CONFIG_MP -#include -#endif #include #ifdef CONFIG_X86 #include @@ -381,7 +381,7 @@ static int setup_dest_addr(void) gd->ram_top = board_get_usable_ram_top(gd->mon_len); gd->relocaddr = gd->ram_top; debug("Ram top: %08lX\n", (ulong)gd->ram_top); -#if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500)) +#if (defined(CONFIG_MPC86xx) || defined(CONFIG_E500)) /* * We need to make sure the location we intend to put secondary core * boot code is reserved and not used by any part of u-boot diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h index e4a5cc5be1..135a3f51f0 100644 --- a/include/configs/mx6_common.h +++ b/include/configs/mx6_common.h @@ -28,4 +28,6 @@ #define CONFIG_SYS_PL310_BASE L2_PL310_BASE #endif +#define CONFIG_MP + #endif