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ARM: k2g: Program DDR PHY MR2 register with the default value

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K2G GP doesn't require the MR2 register to be programed since the
default is good enough. However, newer K2G boards do need to change
this register value. Therefore, instead of not writing this register if
ran on a K2G board just program the value to be written to match the
default/reset value.

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Cooper Jr., Franklin 2017-06-16 17:25:20 -05:00 committed by Tom Rini
parent f8b4a2d7e2
commit a76a6f3e04
2 changed files with 2 additions and 3 deletions
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3
arch/arm/mach-keystone/ddr3.c
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@ -52,8 +52,7 @@ void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
__raw_writel(phy_cfg->dtpr2, base + KS2_DDRPHY_DTPR2_OFFSET);
__raw_writel(phy_cfg->mr0, base + KS2_DDRPHY_MR0_OFFSET);
__raw_writel(phy_cfg->mr1, base + KS2_DDRPHY_MR1_OFFSET);
if (!cpu_is_k2g())
__raw_writel(phy_cfg->mr2, base + KS2_DDRPHY_MR2_OFFSET);
__raw_writel(phy_cfg->mr2, base + KS2_DDRPHY_MR2_OFFSET);
__raw_writel(phy_cfg->dtcr, base + KS2_DDRPHY_DTCR_OFFSET);
__raw_writel(phy_cfg->pgcr2, base + KS2_DDRPHY_PGCR2_OFFSET);

2
board/ti/ks2_evm/ddr3_k2g.c
View file

@ -27,7 +27,7 @@ struct ddr3_phy_config ddr3phy_800_2g = {
.dtpr2 = 0x50022A00ul,
.mr0 = 0x00001430ul,
.mr1 = 0x00000006ul,
.mr2 = 0x00000018ul,
.mr2 = 0x00000000ul,
.dtcr = 0x710035C7ul,
.pgcr2 = 0x00F03D09ul,
.zq0cr1 = 0x0001005Dul,