mirror of
https://github.com/AsahiLinux/u-boot
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arm: dts: k3-j7200: Add dts support
Add the basic a72 dts for j7200. Following nodes were supported: - UART - MMC SD - I2C - TISCI communication Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Vishal Mahaveer <vishalm@ti.com> Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
This commit is contained in:
Lokesh Vutla
parent
837933a620
commit
a7551cf05d
7 changed files with 863 additions and 1 deletions
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@ -955,7 +955,8 @@ dtb-$(CONFIG_STM32MP15x) += \
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dtb-$(CONFIG_SOC_K3_AM6) += k3-am654-base-board.dtb k3-am654-r5-base-board.dtb
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dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \
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k3-j721e-r5-common-proc-board.dtb
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k3-j721e-r5-common-proc-board.dtb \
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k3-j7200-common-proc-board.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += \
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mt7622-rfb.dtb \
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104
arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
Normal file
104
arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
Normal file
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@ -0,0 +1,104 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
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*/
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/ {
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chosen {
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stdout-path = "serial2:115200n8";
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tick-timer = &timer1;
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};
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};
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&chipid {
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u-boot,dm-spl;
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};
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&cbass_main {
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u-boot,dm-spl;
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};
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&main_navss {
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u-boot,dm-spl;
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};
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&cbass_mcu_wakeup {
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u-boot,dm-spl;
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timer1: timer@40400000 {
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compatible = "ti,omap5430-timer";
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reg = <0x0 0x40400000 0x0 0x80>;
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ti,timer-alwon;
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clock-frequency = <25000000>;
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u-boot,dm-spl;
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};
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};
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&secure_proxy_main {
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u-boot,dm-spl;
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};
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&dmsc {
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u-boot,dm-spl;
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k3_sysreset: sysreset-controller {
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compatible = "ti,sci-sysreset";
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u-boot,dm-spl;
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};
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};
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&k3_pds {
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u-boot,dm-spl;
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};
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&k3_clks {
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u-boot,dm-spl;
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};
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&k3_reset {
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u-boot,dm-spl;
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};
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&wkup_pmx0 {
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u-boot,dm-spl;
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};
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&main_pmx0 {
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u-boot,dm-spl;
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};
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&main_uart0 {
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u-boot,dm-spl;
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};
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&mcu_uart0 {
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u-boot,dm-spl;
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};
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&main_sdhci0 {
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u-boot,dm-spl;
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};
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&main_sdhci1 {
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u-boot,dm-spl;
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};
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&wkup_i2c0_pins_default {
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u-boot,dm-spl;
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};
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&wkup_i2c0 {
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u-boot,dm-spl;
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};
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&main_i2c0 {
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u-boot,dm-spl;
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};
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&main_i2c0_pins_default {
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u-boot,dm-spl;
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};
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&exp2 {
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u-boot,dm-spl;
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};
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123
arch/arm/dts/k3-j7200-common-proc-board.dts
Normal file
123
arch/arm/dts/k3-j7200-common-proc-board.dts
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@ -0,0 +1,123 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
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*/
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/dts-v1/;
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#include "k3-j7200-som-p0.dtsi"
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/ {
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chosen {
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stdout-path = "serial2:115200n8";
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bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
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};
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};
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&wkup_pmx0 {
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wkup_i2c0_pins_default: wkup-i2c0-pins-default {
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pinctrl-single,pins = <
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J721E_WKUP_IOPAD(0x100, PIN_INPUT_PULLUP, 0) /* (F20) WKUP_I2C0_SCL */
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J721E_WKUP_IOPAD(0x104, PIN_INPUT_PULLUP, 0) /* (H21) WKUP_I2C0_SDA */
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>;
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};
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};
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&main_pmx0 {
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main_i2c0_pins_default: main-i2c0-pins-default {
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pinctrl-single,pins = <
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J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */
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J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */
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>;
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};
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};
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&wkup_uart0 {
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/* Wakeup UART is used by System firmware */
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status = "disabled";
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};
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&main_uart0 {
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power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
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};
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&main_uart2 {
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/* MAIN UART 2 is used by R5F firmware */
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status = "disabled";
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};
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&main_uart3 {
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/* UART not brought out */
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status = "disabled";
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};
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&main_uart4 {
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/* UART not brought out */
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status = "disabled";
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};
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&main_uart5 {
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/* UART not brought out */
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status = "disabled";
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};
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&main_uart6 {
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/* UART not brought out */
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status = "disabled";
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};
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&main_uart7 {
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/* UART not brought out */
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status = "disabled";
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};
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&main_uart8 {
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/* UART not brought out */
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status = "disabled";
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};
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&main_uart9 {
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/* UART not brought out */
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status = "disabled";
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};
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&wkup_i2c0 {
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pinctrl-names = "default";
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pinctrl-0 = <&wkup_i2c0_pins_default>;
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clock-frequency = <400000>;
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};
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&main_sdhci0 {
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/* eMMC */
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non-removable;
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ti,driver-strength-ohm = <50>;
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disable-wp;
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};
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&main_sdhci1 {
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/* SD card */
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ti,driver-strength-ohm = <50>;
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disable-wp;
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no-1-8-v;
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sdhci-caps-mask = <0x8000000F 0x0>;
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};
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&main_i2c0 {
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pinctrl-names = "default";
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pinctrl-0 = <&main_i2c0_pins_default>;
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clock-frequency = <400000>;
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exp1: gpio@20 {
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compatible = "ti,tca6416";
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reg = <0x20>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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exp2: gpio@22 {
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compatible = "ti,tca6424";
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reg = <0x22>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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313
arch/arm/dts/k3-j7200-main.dtsi
Normal file
313
arch/arm/dts/k3-j7200-main.dtsi
Normal file
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@ -0,0 +1,313 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for J7200 SoC Family Main Domain peripherals
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*
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* Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
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*/
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&cbass_main {
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msmc_ram: sram@70000000 {
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compatible = "mmio-sram";
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reg = <0x0 0x70000000 0x0 0x100000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0x70000000 0x100000>;
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atf-sram@0 {
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reg = <0x0 0x20000>;
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};
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};
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gic500: interrupt-controller@1800000 {
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compatible = "arm,gic-v3";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
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<0x00 0x01900000 0x00 0x100000>; /* GICR */
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/* vcpumntirq: virtual CPU interface maintenance interrupt */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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gic_its: msi-controller@1820000 {
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compatible = "arm,gic-v3-its";
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reg = <0x00 0x01820000 0x00 0x10000>;
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socionext,synquacer-pre-its = <0x1000000 0x400000>;
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msi-controller;
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#msi-cells = <1>;
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};
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};
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main_navss: navss@30000000 {
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compatible = "simple-mfd";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
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secure_proxy_main: mailbox@32c00000 {
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compatible = "ti,am654-secure-proxy";
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#mbox-cells = <1>;
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reg-names = "target_data", "rt", "scfg";
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reg = <0x00 0x32c00000 0x00 0x100000>,
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<0x00 0x32400000 0x00 0x100000>,
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<0x00 0x32800000 0x00 0x100000>;
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interrupt-names = "rx_011";
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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main_pmx0: pinmux@11c000 {
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compatible = "pinctrl-single";
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/* Proxy 0 addressing */
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reg = <0x0 0x11c000 0x0 0x2b4>;
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#pinctrl-cells = <1>;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0xffffffff>;
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};
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main_uart0: serial@2800000 {
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compatible = "ti,j721e-uart", "ti,am654-uart";
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reg = <0x00 0x02800000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 146 2>;
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clock-names = "fclk";
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};
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main_uart1: serial@2810000 {
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compatible = "ti,j721e-uart", "ti,am654-uart";
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reg = <0x00 0x02810000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 278 2>;
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clock-names = "fclk";
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};
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main_uart2: serial@2820000 {
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compatible = "ti,j721e-uart", "ti,am654-uart";
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reg = <0x00 0x02820000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 279 2>;
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clock-names = "fclk";
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};
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main_uart3: serial@2830000 {
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compatible = "ti,j721e-uart", "ti,am654-uart";
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reg = <0x00 0x02830000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 280 2>;
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clock-names = "fclk";
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};
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main_uart4: serial@2840000 {
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compatible = "ti,j721e-uart", "ti,am654-uart";
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reg = <0x00 0x02840000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 281 2>;
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clock-names = "fclk";
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};
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main_uart5: serial@2850000 {
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compatible = "ti,j721e-uart", "ti,am654-uart";
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reg = <0x00 0x02850000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 282 2>;
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clock-names = "fclk";
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};
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main_uart6: serial@2860000 {
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compatible = "ti,j721e-uart", "ti,am654-uart";
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reg = <0x00 0x02860000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 283 2>;
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clock-names = "fclk";
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};
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main_uart7: serial@2870000 {
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compatible = "ti,j721e-uart", "ti,am654-uart";
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reg = <0x00 0x02870000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 284 2>;
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clock-names = "fclk";
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};
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main_uart8: serial@2880000 {
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compatible = "ti,j721e-uart", "ti,am654-uart";
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reg = <0x00 0x02880000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 285 2>;
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clock-names = "fclk";
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};
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main_uart9: serial@2890000 {
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compatible = "ti,j721e-uart", "ti,am654-uart";
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reg = <0x00 0x02890000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 286 2>;
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clock-names = "fclk";
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};
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main_sdhci0: sdhci@4f80000 {
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compatible = "ti,j721e-sdhci-8bit";
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reg = <0x0 0x04f80000 0x0 0x260>, <0x0 0x4f88000 0x0 0x134>;
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interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
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clock-names = "clk_xin", "clk_ahb";
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clocks = <&k3_clks 91 3>, <&k3_clks 91 0>;
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ti,otap-del-sel-legacy = <0x0>;
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ti,otap-del-sel-mmc-hs = <0x0>;
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ti,otap-del-sel-ddr52 = <0x6>;
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ti,otap-del-sel-hs200 = <0x8>;
|
||||
ti,otap-del-sel-hs400 = <0x0>;
|
||||
ti,strobe-sel = <0x77>;
|
||||
ti,trm-icp = <0x8>;
|
||||
bus-width = <8>;
|
||||
mmc-hs200-1_8v;
|
||||
mmc-ddr-1_8v;
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
main_sdhci1: sdhci@4fb0000 {
|
||||
compatible = "ti,j721e-sdhci-4bit";
|
||||
reg = <0x0 0x04fb0000 0x0 0x260>, <0x0 0x4fb8000 0x0 0x134>;
|
||||
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
|
||||
clock-names = "clk_xin", "clk_ahb";
|
||||
clocks = <&k3_clks 92 2>, <&k3_clks 92 1>;
|
||||
ti,otap-del-sel-legacy = <0x0>;
|
||||
ti,otap-del-sel-sd-hs = <0x0>;
|
||||
ti,otap-del-sel-sdr12 = <0xf>;
|
||||
ti,otap-del-sel-sdr25 = <0xf>;
|
||||
ti,otap-del-sel-sdr50 = <0xc>;
|
||||
ti,otap-del-sel-sdr104 = <0x5>;
|
||||
ti,otap-del-sel-ddr50 = <0xc>;
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
main_i2c0: i2c@2000000 {
|
||||
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
|
||||
reg = <0x0 0x2000000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "fck";
|
||||
clocks = <&k3_clks 187 1>;
|
||||
power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>;
|
||||
};
|
||||
|
||||
main_i2c1: i2c@2010000 {
|
||||
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
|
||||
reg = <0x0 0x2010000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "fck";
|
||||
clocks = <&k3_clks 188 1>;
|
||||
power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
|
||||
};
|
||||
|
||||
main_i2c2: i2c@2020000 {
|
||||
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
|
||||
reg = <0x0 0x2020000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "fck";
|
||||
clocks = <&k3_clks 189 1>;
|
||||
power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
|
||||
};
|
||||
|
||||
main_i2c3: i2c@2030000 {
|
||||
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
|
||||
reg = <0x0 0x2030000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "fck";
|
||||
clocks = <&k3_clks 190 1>;
|
||||
power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
|
||||
};
|
||||
|
||||
main_i2c4: i2c@2040000 {
|
||||
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
|
||||
reg = <0x0 0x2040000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "fck";
|
||||
clocks = <&k3_clks 191 1>;
|
||||
power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
|
||||
};
|
||||
|
||||
main_i2c5: i2c@2050000 {
|
||||
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
|
||||
reg = <0x0 0x2050000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "fck";
|
||||
clocks = <&k3_clks 192 1>;
|
||||
power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
|
||||
};
|
||||
|
||||
main_i2c6: i2c@2060000 {
|
||||
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
|
||||
reg = <0x0 0x2060000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "fck";
|
||||
clocks = <&k3_clks 193 1>;
|
||||
power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
|
||||
};
|
||||
};
|
||||
117
arch/arm/dts/k3-j7200-mcu-wakeup.dtsi
Normal file
117
arch/arm/dts/k3-j7200-mcu-wakeup.dtsi
Normal file
|
|
@ -0,0 +1,117 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source for J7200 SoC Family MCU/WAKEUP Domain peripherals
|
||||
*
|
||||
* Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
&cbass_mcu_wakeup {
|
||||
dmsc: dmsc@44083000 {
|
||||
compatible = "ti,k2g-sci";
|
||||
ti,host-id = <12>;
|
||||
|
||||
mbox-names = "rx", "tx";
|
||||
|
||||
mboxes= <&secure_proxy_main 11>,
|
||||
<&secure_proxy_main 13>;
|
||||
|
||||
reg-names = "debug_messages";
|
||||
reg = <0x00 0x44083000 0x0 0x1000>;
|
||||
|
||||
k3_pds: power-controller {
|
||||
compatible = "ti,sci-pm-domain";
|
||||
#power-domain-cells = <2>;
|
||||
};
|
||||
|
||||
k3_clks: clocks {
|
||||
compatible = "ti,k2g-sci-clk";
|
||||
#clock-cells = <2>;
|
||||
};
|
||||
|
||||
k3_reset: reset-controller {
|
||||
compatible = "ti,sci-reset";
|
||||
#reset-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
chipid: chipid@43000014 {
|
||||
compatible = "ti,am654-chipid";
|
||||
reg = <0x0 0x43000014 0x0 0x4>;
|
||||
};
|
||||
|
||||
wkup_pmx0: pinmux@4301c000 {
|
||||
compatible = "pinctrl-single";
|
||||
/* Proxy 0 addressing */
|
||||
reg = <0x00 0x4301c000 0x00 0x178>;
|
||||
#pinctrl-cells = <1>;
|
||||
pinctrl-single,register-width = <32>;
|
||||
pinctrl-single,function-mask = <0xffffffff>;
|
||||
};
|
||||
|
||||
mcu_ram: sram@41c00000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x00 0x41c00000 0x00 0x100000>;
|
||||
ranges = <0x0 0x00 0x41c00000 0x100000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
|
||||
wkup_uart0: serial@42300000 {
|
||||
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x42300000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 287 2>;
|
||||
clock-names = "fclk";
|
||||
};
|
||||
|
||||
wkup_i2c0: i2c@42120000 {
|
||||
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
|
||||
reg = <0x0 0x42120000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "fck";
|
||||
clocks = <&k3_clks 197 1>;
|
||||
power-domains = <&k3_pds 197 TI_SCI_PD_EXCLUSIVE>;
|
||||
};
|
||||
|
||||
mcu_uart0: serial@40a00000 {
|
||||
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x40a00000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <96000000>;
|
||||
current-speed = <115200>;
|
||||
power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 149 2>;
|
||||
clock-names = "fclk";
|
||||
};
|
||||
|
||||
mcu_i2c0: i2c@40b00000 {
|
||||
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
|
||||
reg = <0x0 0x40b00000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "fck";
|
||||
clocks = <&k3_clks 194 1>;
|
||||
power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
|
||||
};
|
||||
|
||||
mcu_i2c1: i2c@40b10000 {
|
||||
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
|
||||
reg = <0x0 0x40b10000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-names = "fck";
|
||||
clocks = <&k3_clks 195 1>;
|
||||
power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
|
||||
};
|
||||
};
|
||||
29
arch/arm/dts/k3-j7200-som-p0.dtsi
Normal file
29
arch/arm/dts/k3-j7200-som-p0.dtsi
Normal file
|
|
@ -0,0 +1,29 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "k3-j7200.dtsi"
|
||||
|
||||
/ {
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
/* 4G RAM */
|
||||
reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
|
||||
<0x00000008 0x80000000 0x00000000 0x80000000>;
|
||||
};
|
||||
|
||||
reserved_memory: reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
secure_ddr: optee@9e800000 {
|
||||
reg = <0x00 0x9e800000 0x00 0x01800000>;
|
||||
alignment = <0x1000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
};
|
||||
175
arch/arm/dts/k3-j7200.dtsi
Normal file
175
arch/arm/dts/k3-j7200.dtsi
Normal file
|
|
@ -0,0 +1,175 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source for J7200 SoC Family
|
||||
*
|
||||
* Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/pinctrl/k3.h>
|
||||
#include <dt-bindings/soc/ti,sci_pm_domain.h>
|
||||
|
||||
/ {
|
||||
model = "Texas Instruments K3 J7200 SoC";
|
||||
compatible = "ti,j7200";
|
||||
interrupt-parent = <&gic500>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
aliases {
|
||||
serial0 = &wkup_uart0;
|
||||
serial1 = &mcu_uart0;
|
||||
serial2 = &main_uart0;
|
||||
serial3 = &main_uart1;
|
||||
serial4 = &main_uart2;
|
||||
serial5 = &main_uart3;
|
||||
serial6 = &main_uart4;
|
||||
serial7 = &main_uart5;
|
||||
serial8 = &main_uart6;
|
||||
serial9 = &main_uart7;
|
||||
serial10 = &main_uart8;
|
||||
serial11 = &main_uart9;
|
||||
i2c0 = &wkup_i2c0;
|
||||
i2c1 = &mcu_i2c0;
|
||||
i2c2 = &mcu_i2c1;
|
||||
i2c3 = &main_i2c0;
|
||||
i2c4 = &main_i2c1;
|
||||
i2c5 = &main_i2c2;
|
||||
i2c6 = &main_i2c3;
|
||||
i2c7 = &main_i2c4;
|
||||
i2c8 = &main_i2c5;
|
||||
i2c9 = &main_i2c6;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cpu-map {
|
||||
cluster0: cluster0 {
|
||||
core0 {
|
||||
cpu = <&cpu0>;
|
||||
};
|
||||
|
||||
core1 {
|
||||
cpu = <&cpu1>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
cpu0: cpu@0 {
|
||||
compatible = "arm,cortex-a72";
|
||||
reg = <0x000>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0xC000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
compatible = "arm,cortex-a72";
|
||||
reg = <0x001>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0xC000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <128>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
};
|
||||
|
||||
L2_0: l2-cache0 {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-size = <0x100000>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <2048>;
|
||||
next-level-cache = <&msmc_l3>;
|
||||
};
|
||||
|
||||
msmc_l3: l3-cache0 {
|
||||
compatible = "cache";
|
||||
cache-level = <3>;
|
||||
};
|
||||
|
||||
firmware {
|
||||
optee {
|
||||
compatible = "linaro,optee-tz";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
psci: psci {
|
||||
compatible = "arm,psci-1.0";
|
||||
method = "smc";
|
||||
};
|
||||
};
|
||||
|
||||
a72_timer0: timer-cl0-cpu0 {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
|
||||
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
|
||||
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
|
||||
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
|
||||
};
|
||||
|
||||
pmu: pmu {
|
||||
compatible = "arm,armv8-pmuv3";
|
||||
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
cbass_main: bus@100000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
|
||||
<0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
|
||||
<0x00 0x00A40000 0x00 0x00A40000 0x00 0x00000800>, /* timesync router */
|
||||
<0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */
|
||||
<0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
|
||||
<0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>, /* MSMC RAM */
|
||||
<0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT */
|
||||
|
||||
/* MCUSS_WKUP Range */
|
||||
<0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
|
||||
<0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>,
|
||||
<0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>,
|
||||
<0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
|
||||
<0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
|
||||
<0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>,
|
||||
<0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
|
||||
<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
|
||||
<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
|
||||
<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
|
||||
<0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>;
|
||||
|
||||
cbass_mcu_wakeup: bus@28380000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
|
||||
<0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */
|
||||
<0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
|
||||
<0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
|
||||
<0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
|
||||
<0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */
|
||||
<0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */
|
||||
<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
|
||||
<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
|
||||
<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */
|
||||
<0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>; /* FSS OSPI0/1 data region 0 */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* Now include the peripherals for each bus segments */
|
||||
#include "k3-j7200-main.dtsi"
|
||||
#include "k3-j7200-mcu-wakeup.dtsi"
|
||||
Loading…
Reference in a new issue