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clk: zynqmp: Add support to enable clocks
Add clock enable functionality in zynqmp clock driver to enable clocks from peripheral drivers using clk_ops. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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1 changed files with 49 additions and 0 deletions
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@ -199,6 +199,8 @@ static u32 zynqmp_clk_get_register(enum zynqmp_clk id)
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return CRF_APB_DDR_CTRL;
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case qspi_ref:
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return CRL_APB_QSPI_REF_CTRL;
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case usb3_dual_ref:
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return CRL_APB_USB3_DUAL_REF_CTRL;
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case gem0_ref:
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return CRL_APB_GEM0_REF_CTRL;
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case gem1_ref:
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@ -207,6 +209,10 @@ static u32 zynqmp_clk_get_register(enum zynqmp_clk id)
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return CRL_APB_GEM2_REF_CTRL;
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case gem3_ref:
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return CRL_APB_GEM3_REF_CTRL;
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case usb0_bus_ref:
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return CRL_APB_USB0_BUS_REF_CTRL;
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case usb1_bus_ref:
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return CRL_APB_USB1_BUS_REF_CTRL;
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case uart0_ref:
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return CRL_APB_UART0_REF_CTRL;
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case uart1_ref:
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@ -699,9 +705,52 @@ static int zynqmp_clk_probe(struct udevice *dev)
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return 0;
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}
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static int zynqmp_clk_enable(struct clk *clk)
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{
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enum zynqmp_clk id = clk->id;
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u32 reg, clk_ctrl, clkact_shift, mask;
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int ret;
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reg = zynqmp_clk_get_register(id);
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debug("%s, clk_id:%x, clk_base:0x%x\n", __func__, id, reg);
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switch (id) {
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case usb0_bus_ref ... usb1:
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clkact_shift = 25;
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mask = 0x1;
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break;
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case gem0_ref ... gem3_ref:
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clkact_shift = 25;
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mask = 0x3;
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break;
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case qspi_ref ... can1_ref:
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clkact_shift = 24;
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mask = 0x1;
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break;
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default:
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return -ENXIO;
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}
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ret = zynqmp_mmio_read(reg, &clk_ctrl);
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if (ret) {
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printf("%s mio read fail\n", __func__);
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return -EIO;
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}
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clk_ctrl |= (mask << clkact_shift);
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ret = zynqmp_mmio_write(reg, mask << clkact_shift, clk_ctrl);
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if (ret) {
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printf("%s mio write fail\n", __func__);
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return -EIO;
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}
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return ret;
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}
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static struct clk_ops zynqmp_clk_ops = {
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.set_rate = zynqmp_clk_set_rate,
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.get_rate = zynqmp_clk_get_rate,
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.enable = zynqmp_clk_enable,
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};
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static const struct udevice_id zynqmp_clk_ids[] = {
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