mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-19 11:18:28 +00:00
Merge branch 'master' of git://git.denx.de/u-boot
This commit is contained in:
Stefano Babic
commit
a69fdc7787
508 changed files with 17772 additions and 2846 deletions
20
Kconfig
20
Kconfig
|
|
@ -114,6 +114,16 @@ config SPL
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|||
help
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If you want to build SPL as well as the normal image, say Y.
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config SPL_SYS_MALLOC_SIMPLE
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bool
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depends on SPL
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prompt "Only use malloc_simple functions in the spl"
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help
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Say Y here to only use the *_simple malloc functions from
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malloc_simple.c, rather then using the versions from dlmalloc.c
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this will make the SPL binary smaller at the cost of more heap
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usage as the *_simple malloc functions do not re-use free-ed mem.
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config SPL_STACK_R
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depends on SPL
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bool "Enable SDRAM location for SPL stack"
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@ -132,6 +142,16 @@ config SPL_STACK_R_ADDR
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Specify the address in SDRAM for the SPL stack. This will be set up
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before board_init_r() is called.
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config SPL_STACK_R_MALLOC_SIMPLE_LEN
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depends on SPL_STACK_R && SPL_SYS_MALLOC_SIMPLE
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hex "Size of malloc_simple heap after switching to DRAM SPL stack"
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default 0x100000
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help
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Specify the amount of the stack to use as memory pool for
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malloc_simple after switching the stack to DRAM. This may be set
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to give board_init_r() a larger heap then the initial heap in
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SRAM which is limited to SYS_MALLOC_F_LEN bytes.
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config TPL
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bool
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depends on SPL && SUPPORT_TPL
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|
|
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18
Makefile
18
Makefile
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@ -1,7 +1,7 @@
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VERSION = 2015
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PATCHLEVEL = 10
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SUBLEVEL =
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EXTRAVERSION = -rc5
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EXTRAVERSION =
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NAME =
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# *DOCUMENTATION*
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|
|
@ -901,7 +901,7 @@ MKIMAGEFLAGS_u-boot.kwb = -n $(srctree)/$(CONFIG_SYS_KWD_CONFIG:"%"=%) \
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-T kwbimage -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE)
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MKIMAGEFLAGS_u-boot-spl.kwb = -n $(srctree)/$(CONFIG_SYS_KWD_CONFIG:"%"=%) \
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-T kwbimage -a $(CONFIG_SPL_TEXT_BASE) -e $(CONFIG_SPL_TEXT_BASE)
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-T kwbimage -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE)
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MKIMAGEFLAGS_u-boot.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \
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-R $(srctree)/$(CONFIG_SYS_FSL_PBL_PBI:"%"=%) -T pblimage
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@ -909,8 +909,18 @@ MKIMAGEFLAGS_u-boot.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \
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u-boot.img u-boot.kwb u-boot.pbl: u-boot.bin FORCE
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$(call if_changed,mkimage)
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u-boot-spl.kwb: u-boot.img spl/u-boot-spl.bin FORCE
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# If the kwboot xmodem protocol is used, to boot U-Boot on the MVEBU
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# SoC's, the SPL U-Boot returns to the BootROM after it completes
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# the SDRAM setup. The BootROM expects no U-Boot header in the main
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# U-Boot image. So we need to combine SPL and u-boot.bin instead of
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# u-boot.img in this case.
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ifdef CONFIG_MVEBU_BOOTROM_UARTBOOT
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u-boot-spl.kwb: u-boot-dtb.bin spl/u-boot-spl.bin FORCE
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$(call if_changed,mkimage)
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else
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u-boot-spl.kwb: u-boot-dtb.img spl/u-boot-spl.bin FORCE
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$(call if_changed,mkimage)
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endif
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MKIMAGEFLAGS_u-boot-dtb.img = $(MKIMAGEFLAGS_u-boot.img)
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@ -1278,6 +1288,7 @@ define filechk_timestamp.h
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LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_DATE "%b %d %C%y"'; \
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LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_TIME "%T"'; \
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LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_TZ "%z"'; \
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LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_DMI_DATE "%m/%d/%Y"'; \
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else \
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return 42; \
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fi; \
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|
|
@ -1285,6 +1296,7 @@ define filechk_timestamp.h
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LC_ALL=C date +'#define U_BOOT_DATE "%b %d %C%y"'; \
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LC_ALL=C date +'#define U_BOOT_TIME "%T"'; \
|
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LC_ALL=C date +'#define U_BOOT_TZ "%z"'; \
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LC_ALL=C date +'#define U_BOOT_DMI_DATE "%m/%d/%Y"'; \
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fi)
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endef
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|
|
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12
README
12
README
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|
@ -796,18 +796,10 @@ The following options need to be configured:
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- vxWorks boot parameters:
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bootvx constructs a valid bootline using the following
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environments variables: bootfile, ipaddr, serverip, hostname.
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environments variables: bootdev, bootfile, ipaddr, netmask,
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serverip, gatewayip, hostname, othbootargs.
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It loads the vxWorks image pointed bootfile.
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CONFIG_SYS_VXWORKS_BOOT_DEVICE - The vxworks device name
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CONFIG_SYS_VXWORKS_MAC_PTR - Ethernet 6 byte MA -address
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CONFIG_SYS_VXWORKS_SERVERNAME - Name of the server
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CONFIG_SYS_VXWORKS_BOOT_ADDR - Address of boot parameters
|
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CONFIG_SYS_VXWORKS_ADD_PARAMS
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||||
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Add it at the end of the bootline. E.g "u=username pw=secret"
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|
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Note: If a "bootargs" environment is defined, it will overwride
|
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the defaults discussed just above.
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|
|
|
|||
|
|
@ -105,20 +105,14 @@ config KIRKWOOD
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bool "Marvell Kirkwood"
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select CPU_ARM926EJS
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config TARGET_DB_88F6820_GP
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bool "Support DB-88F6820-GP"
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select CPU_V7
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select SUPPORT_SPL
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config TARGET_DB_MV784MP_GP
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bool "Support db-mv784mp-gp"
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select CPU_V7
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select SUPPORT_SPL
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config TARGET_MAXBCM
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bool "Support maxbcm"
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config ARCH_MVEBU
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bool "Marvell MVEBU family (Armada XP/38x)"
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select CPU_V7
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select SUPPORT_SPL
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select OF_CONTROL
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select OF_SEPARATE
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select DM
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select DM_SERIAL
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config TARGET_DEVKIT3250
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bool "Support devkit3250"
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@ -522,6 +516,8 @@ config ARCH_SUNXI
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select DM_USB
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select OF_CONTROL
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select OF_SEPARATE
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select SPL_STACK_R if !MACH_SUN9I
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select SPL_SYS_MALLOC_SIMPLE if !MACH_SUN9I
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select USB
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select USB_STORAGE
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select USB_KEYBOARD
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|
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@ -684,6 +680,8 @@ source "arch/arm/mach-keystone/Kconfig"
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|||
|
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source "arch/arm/mach-kirkwood/Kconfig"
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source "arch/arm/mach-mvebu/Kconfig"
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|
||||
source "arch/arm/cpu/armv7/mx7/Kconfig"
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||||
|
||||
source "arch/arm/cpu/armv7/mx6/Kconfig"
|
||||
|
|
|
|||
|
|
@ -41,35 +41,73 @@ void cancel_out(u32 *num, u32 *den, u32 den_limit)
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}
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}
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void __weak usb_fake_mac_from_die_id(u32 *id)
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__weak void omap_die_id(unsigned int *die_id)
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{
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uint8_t device_mac[6];
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die_id[0] = die_id[1] = die_id[2] = die_id[3] = 0;
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}
|
||||
|
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void omap_die_id_serial(void)
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||||
{
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unsigned int die_id[4] = { 0 };
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char serial_string[17] = { 0 };
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||||
|
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omap_die_id((unsigned int *)&die_id);
|
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|
||||
if (!getenv("serial#")) {
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||||
snprintf(serial_string, sizeof(serial_string),
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"%08x%08x", die_id[0], die_id[3]);
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setenv("serial#", serial_string);
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}
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}
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void omap_die_id_get_board_serial(struct tag_serialnr *serialnr)
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{
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char *serial_string;
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unsigned long long serial;
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serial_string = getenv("serial#");
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if (serial_string) {
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serial = simple_strtoull(serial_string, NULL, 16);
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serialnr->high = (unsigned int) (serial >> 32);
|
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serialnr->low = (unsigned int) (serial & 0xffffffff);
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} else {
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serialnr->high = 0;
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serialnr->low = 0;
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}
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}
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|
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void omap_die_id_usbethaddr(void)
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{
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unsigned int die_id[4] = { 0 };
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unsigned char mac[6] = { 0 };
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|
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omap_die_id((unsigned int *)&die_id);
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|
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if (!getenv("usbethaddr")) {
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/*
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* create a fake MAC address from the processor ID code.
|
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* first byte is 0x02 to signify locally administered.
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* Create a fake MAC address from the processor ID code.
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* First byte is 0x02 to signify locally administered.
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*/
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device_mac[0] = 0x02;
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device_mac[1] = id[3] & 0xff;
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device_mac[2] = id[2] & 0xff;
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device_mac[3] = id[1] & 0xff;
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device_mac[4] = id[0] & 0xff;
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device_mac[5] = (id[0] >> 8) & 0xff;
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mac[0] = 0x02;
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mac[1] = die_id[3] & 0xff;
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mac[2] = die_id[2] & 0xff;
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mac[3] = die_id[1] & 0xff;
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mac[4] = die_id[0] & 0xff;
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mac[5] = (die_id[0] >> 8) & 0xff;
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|
||||
eth_setenv_enetaddr("usbethaddr", device_mac);
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||||
eth_setenv_enetaddr("usbethaddr", mac);
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}
|
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}
|
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|
||||
void __weak usb_set_serial_num_from_die_id(u32 *id)
|
||||
void omap_die_id_display(void)
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{
|
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char serialno[72];
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uint32_t serialno_lo, serialno_hi;
|
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unsigned int die_id[4] = { 0 };
|
||||
|
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if (!getenv("serial#")) {
|
||||
serialno_hi = id[0];
|
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serialno_lo = id[1];
|
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sprintf(serialno, "%08x%08x", serialno_hi, serialno_lo);
|
||||
setenv("serial#", serialno);
|
||||
}
|
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omap_die_id(die_id);
|
||||
|
||||
printf("OMAP die ID: %08x%08x%08x%08x", die_id[0], die_id[1], die_id[2],
|
||||
die_id[3]);
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||||
}
|
||||
|
|
|
|||
|
|
@ -214,7 +214,7 @@ void board_init_f(ulong dummy)
|
|||
*/
|
||||
int __weak misc_init_r(void)
|
||||
{
|
||||
dieid_num_r();
|
||||
omap_die_id_display();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -42,39 +42,14 @@ static char *rev_s_37xx[CPU_37XX_MAX_REV] = {
|
|||
"1.2"};
|
||||
#endif /* CONFIG_DISPLAY_CPUINFO */
|
||||
|
||||
/*****************************************************************
|
||||
* get_dieid(u32 *id) - read die ID
|
||||
*****************************************************************/
|
||||
void get_dieid(u32 *id)
|
||||
void omap_die_id(unsigned int *die_id)
|
||||
{
|
||||
struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE;
|
||||
|
||||
id[3] = readl(&id_base->die_id_0);
|
||||
id[2] = readl(&id_base->die_id_1);
|
||||
id[1] = readl(&id_base->die_id_2);
|
||||
id[0] = readl(&id_base->die_id_3);
|
||||
}
|
||||
|
||||
/*****************************************************************
|
||||
* dieid_num_r(void) - read and set die ID
|
||||
*****************************************************************/
|
||||
void dieid_num_r(void)
|
||||
{
|
||||
char *uid_s, die_id[34];
|
||||
u32 id[4];
|
||||
|
||||
memset(die_id, 0, sizeof(die_id));
|
||||
|
||||
uid_s = getenv("dieid#");
|
||||
|
||||
if (uid_s == NULL) {
|
||||
get_dieid(id);
|
||||
sprintf(die_id, "%08x%08x%08x%08x", id[0], id[1], id[2], id[3]);
|
||||
setenv("dieid#", die_id);
|
||||
uid_s = die_id;
|
||||
}
|
||||
|
||||
printf("Die ID #%s\n", uid_s);
|
||||
die_id[0] = readl(&id_base->die_id_0);
|
||||
die_id[1] = readl(&id_base->die_id_1);
|
||||
die_id[2] = readl(&id_base->die_id_2);
|
||||
die_id[3] = readl(&id_base->die_id_3);
|
||||
}
|
||||
|
||||
/******************************************
|
||||
|
|
|
|||
|
|
@ -156,6 +156,14 @@ void init_omap_revision(void)
|
|||
}
|
||||
}
|
||||
|
||||
void omap_die_id(unsigned int *die_id)
|
||||
{
|
||||
die_id[0] = readl((*ctrl)->control_std_fuse_die_id_0);
|
||||
die_id[1] = readl((*ctrl)->control_std_fuse_die_id_1);
|
||||
die_id[2] = readl((*ctrl)->control_std_fuse_die_id_2);
|
||||
die_id[3] = readl((*ctrl)->control_std_fuse_die_id_3);
|
||||
}
|
||||
|
||||
#ifndef CONFIG_SYS_L2CACHE_OFF
|
||||
void v7_outer_cache_enable(void)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -280,7 +280,10 @@ struct prcm_regs const omap4_prcm = {
|
|||
|
||||
struct omap_sys_ctrl_regs const omap4_ctrl = {
|
||||
.control_status = 0x4A0022C4,
|
||||
.control_id_code = 0x4A002204,
|
||||
.control_std_fuse_die_id_0 = 0x4A002200,
|
||||
.control_std_fuse_die_id_1 = 0x4A002208,
|
||||
.control_std_fuse_die_id_2 = 0x4A00220C,
|
||||
.control_std_fuse_die_id_3 = 0x4A002210,
|
||||
.control_std_fuse_opp_bgap = 0x4a002260,
|
||||
.control_status = 0x4a0022c4,
|
||||
.control_ldosram_iva_voltage_ctrl = 0x4A002320,
|
||||
|
|
|
|||
|
|
@ -379,6 +379,14 @@ void init_omap_revision(void)
|
|||
init_cpu_configuration();
|
||||
}
|
||||
|
||||
void omap_die_id(unsigned int *die_id)
|
||||
{
|
||||
die_id[0] = readl((*ctrl)->control_std_fuse_die_id_0);
|
||||
die_id[1] = readl((*ctrl)->control_std_fuse_die_id_1);
|
||||
die_id[2] = readl((*ctrl)->control_std_fuse_die_id_2);
|
||||
die_id[3] = readl((*ctrl)->control_std_fuse_die_id_3);
|
||||
}
|
||||
|
||||
void reset_cpu(ulong ignored)
|
||||
{
|
||||
u32 omap_rev = omap_revision();
|
||||
|
|
|
|||
|
|
@ -298,6 +298,10 @@ struct prcm_regs const omap5_es1_prcm = {
|
|||
struct omap_sys_ctrl_regs const omap5_ctrl = {
|
||||
.control_status = 0x4A002134,
|
||||
.control_std_fuse_opp_vdd_mpu_2 = 0x4A0021B4,
|
||||
.control_std_fuse_die_id_0 = 0x4A002200,
|
||||
.control_std_fuse_die_id_1 = 0x4A002208,
|
||||
.control_std_fuse_die_id_2 = 0x4A00220C,
|
||||
.control_std_fuse_die_id_3 = 0x4A002210,
|
||||
.control_phy_power_usb = 0x4A002370,
|
||||
.control_phy_power_sata = 0x4A002374,
|
||||
.control_padconf_core_base = 0x4A002800,
|
||||
|
|
|
|||
|
|
@ -136,7 +136,7 @@ DECLARE_GLOBAL_DATA_PTR;
|
|||
*/
|
||||
u32 spl_boot_device(void)
|
||||
{
|
||||
struct mmc *mmc0, *mmc1;
|
||||
__maybe_unused struct mmc *mmc0, *mmc1;
|
||||
/*
|
||||
* When booting from the SD card or NAND memory, the "eGON.BT0"
|
||||
* signature is expected to be found in memory at the address 0x0004
|
||||
|
|
@ -157,15 +157,18 @@ u32 spl_boot_device(void)
|
|||
return BOOT_DEVICE_BOARD;
|
||||
|
||||
/* The BROM will try to boot from mmc0 first, so try that first. */
|
||||
#ifdef CONFIG_MMC
|
||||
mmc_initialize(gd->bd);
|
||||
mmc0 = find_mmc_device(0);
|
||||
if (sunxi_mmc_has_egon_boot_signature(mmc0))
|
||||
return BOOT_DEVICE_MMC1;
|
||||
#endif
|
||||
|
||||
/* Fallback to booting NAND if enabled. */
|
||||
if (IS_ENABLED(CONFIG_SPL_NAND_SUPPORT))
|
||||
return BOOT_DEVICE_NAND;
|
||||
|
||||
#ifdef CONFIG_MMC
|
||||
if (CONFIG_MMC_SUNXI_SLOT_EXTRA == 2) {
|
||||
mmc1 = find_mmc_device(1);
|
||||
if (sunxi_mmc_has_egon_boot_signature(mmc1)) {
|
||||
|
|
@ -179,6 +182,7 @@ u32 spl_boot_device(void)
|
|||
return BOOT_DEVICE_MMC2;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
panic("Could not determine boot source\n");
|
||||
return -1; /* Never reached */
|
||||
|
|
@ -192,6 +196,7 @@ u32 spl_boot_mode(void)
|
|||
|
||||
void board_init_f(ulong dummy)
|
||||
{
|
||||
spl_init();
|
||||
preloader_console_init();
|
||||
|
||||
#ifdef CONFIG_SPL_I2C_SUPPORT
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@
|
|||
#include <asm/io.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <axp221.h>
|
||||
#include <axp_pmic.h>
|
||||
#include <errno.h>
|
||||
|
||||
#ifdef CONFIG_MACH_SUN6I
|
||||
|
|
@ -82,7 +82,7 @@ int print_cpuinfo(void)
|
|||
int sunxi_get_sid(unsigned int *sid)
|
||||
{
|
||||
#ifdef CONFIG_AXP221_POWER
|
||||
return axp221_get_sid(sid);
|
||||
return axp_get_sid(sid);
|
||||
#elif defined SUNXI_SID_BASE
|
||||
int i;
|
||||
|
||||
|
|
|
|||
|
|
@ -17,15 +17,6 @@
|
|||
#include <asm/gpio.h>
|
||||
#include <asm/io.h>
|
||||
#include <errno.h>
|
||||
#ifdef CONFIG_AXP152_POWER
|
||||
#include <axp152.h>
|
||||
#endif
|
||||
#ifdef CONFIG_AXP209_POWER
|
||||
#include <axp209.h>
|
||||
#endif
|
||||
#ifdef CONFIG_AXP221_POWER
|
||||
#include <axp221.h>
|
||||
#endif
|
||||
|
||||
#define SUNXI_USB_PMU_IRQ_ENABLE 0x800
|
||||
#ifdef CONFIG_MACH_SUN8I_A33
|
||||
|
|
|
|||
|
|
@ -112,7 +112,7 @@ ENDPROC(__asm_flush_dcache_all)
|
|||
|
||||
ENTRY(__asm_invalidate_dcache_all)
|
||||
mov x16, lr
|
||||
mov x0, #0xffff
|
||||
mov x0, #0x1
|
||||
bl __asm_dcache_all
|
||||
mov lr, x16
|
||||
ret
|
||||
|
|
|
|||
|
|
@ -59,15 +59,15 @@ static void mmu_setup(void)
|
|||
el = current_el();
|
||||
if (el == 1) {
|
||||
set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
|
||||
TCR_FLAGS | TCR_EL1_IPS_BITS,
|
||||
TCR_EL1_RSVD | TCR_FLAGS | TCR_EL1_IPS_BITS,
|
||||
MEMORY_ATTRIBUTES);
|
||||
} else if (el == 2) {
|
||||
set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
|
||||
TCR_FLAGS | TCR_EL2_IPS_BITS,
|
||||
TCR_EL2_RSVD | TCR_FLAGS | TCR_EL2_IPS_BITS,
|
||||
MEMORY_ATTRIBUTES);
|
||||
} else {
|
||||
set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
|
||||
TCR_FLAGS | TCR_EL3_IPS_BITS,
|
||||
TCR_EL3_RSVD | TCR_FLAGS | TCR_EL3_IPS_BITS,
|
||||
MEMORY_ATTRIBUTES);
|
||||
}
|
||||
/* enable the mmu */
|
||||
|
|
|
|||
|
|
@ -41,6 +41,11 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
|
|||
tegra210-p2371-0000.dtb \
|
||||
tegra210-p2371-2180.dtb \
|
||||
tegra210-p2571.dtb
|
||||
|
||||
dtb-$(CONFIG_ARCH_MVEBU) += \
|
||||
armada-388-gp.dtb \
|
||||
armada-xp-gp.dtb
|
||||
|
||||
dtb-$(CONFIG_ARCH_UNIPHIER) += \
|
||||
uniphier-ph1-ld4-ref.dtb \
|
||||
uniphier-ph1-ld6b-ref.dtb \
|
||||
|
|
@ -61,6 +66,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \
|
|||
zynq-zc770-xm012.dtb \
|
||||
zynq-zc770-xm013.dtb
|
||||
dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-evm.dtb
|
||||
dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb
|
||||
|
||||
dtb-$(CONFIG_ARCH_SOCFPGA) += \
|
||||
socfpga_arria5_socdk.dtb \
|
||||
|
|
@ -69,7 +75,8 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \
|
|||
socfpga_cyclone5_de0_nano_soc.dtb \
|
||||
socfpga_cyclone5_sockit.dtb \
|
||||
socfpga_cyclone5_socrates.dtb
|
||||
dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb
|
||||
dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb
|
||||
dtb-$(CONFIG_TARGET_BEAGLE_X15) += am57xx-beagle-x15.dtb
|
||||
dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb
|
||||
|
||||
dtb-$(CONFIG_LS102XA) += ls1021a-qds.dtb \
|
||||
|
|
@ -107,15 +114,14 @@ dtb-$(CONFIG_MACH_SUN5I) += \
|
|||
sun5i-a10s-r7-tv-dongle.dtb \
|
||||
sun5i-a10s-wobo-i5.dtb \
|
||||
sun5i-a13-ampe-a76.dtb \
|
||||
sun5i-a13-forfun-q88db.dtb \
|
||||
sun5i-a13-hsg-h702.dtb \
|
||||
sun5i-a13-inet-86vs.dtb \
|
||||
sun5i-a13-inet-98v-rev2.dtb \
|
||||
sun5i-a13-olinuxino.dtb \
|
||||
sun5i-a13-olinuxino-micro.dtb \
|
||||
sun5i-a13-q8-tablet.dtb \
|
||||
sun5i-a13-tzx-q8-713b7.dtb \
|
||||
sun5i-a13-utoo-p66.dtb
|
||||
sun5i-a13-utoo-p66.dtb \
|
||||
sun5i-r8-chip.dtb
|
||||
dtb-$(CONFIG_MACH_SUN6I) += \
|
||||
sun6i-a31-app4-evb1.dtb \
|
||||
sun6i-a31-colombus.dtb \
|
||||
|
|
@ -125,7 +131,8 @@ dtb-$(CONFIG_MACH_SUN6I) += \
|
|||
sun6i-a31-mele-a1000g-quad.dtb \
|
||||
sun6i-a31-mixtile-loftq.dtb \
|
||||
sun6i-a31s-cs908.dtb \
|
||||
sun6i-a31s-primo81.dtb
|
||||
sun6i-a31s-primo81.dtb \
|
||||
sun6i-a31s-sinovoip-bpi-m2.dtb
|
||||
dtb-$(CONFIG_MACH_SUN7I) += \
|
||||
sun7i-a20-ainol-aw1.dtb \
|
||||
sun7i-a20-bananapi.dtb \
|
||||
|
|
@ -152,13 +159,9 @@ dtb-$(CONFIG_MACH_SUN7I) += \
|
|||
dtb-$(CONFIG_MACH_SUN8I_A23) += \
|
||||
sun8i-a23-evb.dtb \
|
||||
sun8i-a23-gt90h-v4.dtb \
|
||||
sun8i-a23-ippo-q8h-v5.dtb \
|
||||
sun8i-a23-ippo-q8h-v1.2.dtb \
|
||||
sun8i-a23-q8-tablet.dtb
|
||||
dtb-$(CONFIG_MACH_SUN8I_A33) += \
|
||||
sun8i-a33-et-q8-v1.6.dtb \
|
||||
sun8i-a33-ga10h-v1.1.dtb \
|
||||
sun8i-a33-ippo-q8h-v1.2.dtb \
|
||||
sun8i-a33-q8-tablet.dtb \
|
||||
sun8i-a33-sinlinx-sina33.dtb
|
||||
dtb-$(CONFIG_MACH_SUN9I) += \
|
||||
|
|
@ -168,6 +171,11 @@ dtb-$(CONFIG_MACH_SUN9I) += \
|
|||
dtb-$(CONFIG_VF610) += vf500-colibri.dtb \
|
||||
vf610-colibri.dtb
|
||||
|
||||
dtb-$(CONFIG_SOC_KEYSTONE) += k2hk-evm.dtb \
|
||||
k2l-evm.dtb \
|
||||
k2e-evm.dtb \
|
||||
k2g-evm.dtb
|
||||
|
||||
targets += $(dtb-y)
|
||||
|
||||
# Add any required device tree compiler flags here
|
||||
|
|
|
|||
999
arch/arm/dts/am4372.dtsi
Normal file
999
arch/arm/dts/am4372.dtsi
Normal file
|
|
@ -0,0 +1,999 @@
|
|||
/*
|
||||
* Device Tree Source for AM4372 SoC
|
||||
*
|
||||
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
#include "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "ti,am4372", "ti,am43";
|
||||
interrupt-parent = <&wakeupgen>;
|
||||
|
||||
|
||||
aliases {
|
||||
i2c0 = &i2c0;
|
||||
i2c1 = &i2c1;
|
||||
i2c2 = &i2c2;
|
||||
serial0 = &uart0;
|
||||
ethernet0 = &cpsw_emac0;
|
||||
ethernet1 = &cpsw_emac1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cpu: cpu@0 {
|
||||
compatible = "arm,cortex-a9";
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
|
||||
clocks = <&dpll_mpu_ck>;
|
||||
clock-names = "cpu";
|
||||
|
||||
clock-latency = <300000>; /* From omap-cpufreq driver */
|
||||
};
|
||||
};
|
||||
|
||||
gic: interrupt-controller@48241000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
reg = <0x48241000 0x1000>,
|
||||
<0x48240100 0x0100>;
|
||||
interrupt-parent = <&gic>;
|
||||
};
|
||||
|
||||
wakeupgen: interrupt-controller@48281000 {
|
||||
compatible = "ti,omap4-wugen-mpu";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
reg = <0x48281000 0x1000>;
|
||||
interrupt-parent = <&gic>;
|
||||
};
|
||||
|
||||
l2-cache-controller@48242000 {
|
||||
compatible = "arm,pl310-cache";
|
||||
reg = <0x48242000 0x1000>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
ocp {
|
||||
compatible = "ti,am4372-l3-noc", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
ti,hwmods = "l3_main";
|
||||
reg = <0x44000000 0x400000
|
||||
0x44800000 0x400000>;
|
||||
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
l4_wkup: l4_wkup@44c00000 {
|
||||
compatible = "ti,am4-l4-wkup", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x44c00000 0x287000>;
|
||||
|
||||
prcm: prcm@1f0000 {
|
||||
compatible = "ti,am4-prcm";
|
||||
reg = <0x1f0000 0x11000>;
|
||||
|
||||
prcm_clocks: clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
prcm_clockdomains: clockdomains {
|
||||
};
|
||||
};
|
||||
|
||||
scm: scm@210000 {
|
||||
compatible = "ti,am4-scm", "simple-bus";
|
||||
reg = <0x210000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x210000 0x4000>;
|
||||
|
||||
am43xx_pinmux: pinmux@800 {
|
||||
compatible = "ti,am437-padconf",
|
||||
"pinctrl-single";
|
||||
reg = <0x800 0x31c>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
pinctrl-single,register-width = <32>;
|
||||
pinctrl-single,function-mask = <0xffffffff>;
|
||||
};
|
||||
|
||||
scm_conf: scm_conf@0 {
|
||||
compatible = "syscon";
|
||||
reg = <0x0 0x800>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
scm_clocks: clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
scm_clockdomains: clockdomains {
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
emif: emif@4c000000 {
|
||||
compatible = "ti,emif-am4372";
|
||||
reg = <0x4c000000 0x1000000>;
|
||||
ti,hwmods = "emif";
|
||||
};
|
||||
|
||||
edma: edma@49000000 {
|
||||
compatible = "ti,edma3";
|
||||
ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
|
||||
reg = <0x49000000 0x10000>,
|
||||
<0x44e10f90 0x10>;
|
||||
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#dma-cells = <1>;
|
||||
};
|
||||
|
||||
uart0: serial@44e09000 {
|
||||
compatible = "ti,am4372-uart","ti,omap2-uart";
|
||||
reg = <0x44e09000 0x2000>;
|
||||
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "uart1";
|
||||
};
|
||||
|
||||
uart1: serial@48022000 {
|
||||
compatible = "ti,am4372-uart","ti,omap2-uart";
|
||||
reg = <0x48022000 0x2000>;
|
||||
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "uart2";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@48024000 {
|
||||
compatible = "ti,am4372-uart","ti,omap2-uart";
|
||||
reg = <0x48024000 0x2000>;
|
||||
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "uart3";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@481a6000 {
|
||||
compatible = "ti,am4372-uart","ti,omap2-uart";
|
||||
reg = <0x481a6000 0x2000>;
|
||||
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "uart4";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart4: serial@481a8000 {
|
||||
compatible = "ti,am4372-uart","ti,omap2-uart";
|
||||
reg = <0x481a8000 0x2000>;
|
||||
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "uart5";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart5: serial@481aa000 {
|
||||
compatible = "ti,am4372-uart","ti,omap2-uart";
|
||||
reg = <0x481aa000 0x2000>;
|
||||
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "uart6";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mailbox: mailbox@480C8000 {
|
||||
compatible = "ti,omap4-mailbox";
|
||||
reg = <0x480C8000 0x200>;
|
||||
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "mailbox";
|
||||
#mbox-cells = <1>;
|
||||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <8>;
|
||||
mbox_wkupm3: wkup_m3 {
|
||||
ti,mbox-tx = <0 0 0>;
|
||||
ti,mbox-rx = <0 0 3>;
|
||||
};
|
||||
};
|
||||
|
||||
timer1: timer@44e31000 {
|
||||
compatible = "ti,am4372-timer-1ms","ti,am335x-timer-1ms";
|
||||
reg = <0x44e31000 0x400>;
|
||||
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,timer-alwon;
|
||||
ti,hwmods = "timer1";
|
||||
};
|
||||
|
||||
timer2: timer@48040000 {
|
||||
compatible = "ti,am4372-timer","ti,am335x-timer";
|
||||
reg = <0x48040000 0x400>;
|
||||
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "timer2";
|
||||
};
|
||||
|
||||
timer3: timer@48042000 {
|
||||
compatible = "ti,am4372-timer","ti,am335x-timer";
|
||||
reg = <0x48042000 0x400>;
|
||||
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "timer3";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer4: timer@48044000 {
|
||||
compatible = "ti,am4372-timer","ti,am335x-timer";
|
||||
reg = <0x48044000 0x400>;
|
||||
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,timer-pwm;
|
||||
ti,hwmods = "timer4";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer5: timer@48046000 {
|
||||
compatible = "ti,am4372-timer","ti,am335x-timer";
|
||||
reg = <0x48046000 0x400>;
|
||||
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,timer-pwm;
|
||||
ti,hwmods = "timer5";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer6: timer@48048000 {
|
||||
compatible = "ti,am4372-timer","ti,am335x-timer";
|
||||
reg = <0x48048000 0x400>;
|
||||
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,timer-pwm;
|
||||
ti,hwmods = "timer6";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer7: timer@4804a000 {
|
||||
compatible = "ti,am4372-timer","ti,am335x-timer";
|
||||
reg = <0x4804a000 0x400>;
|
||||
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,timer-pwm;
|
||||
ti,hwmods = "timer7";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer8: timer@481c1000 {
|
||||
compatible = "ti,am4372-timer","ti,am335x-timer";
|
||||
reg = <0x481c1000 0x400>;
|
||||
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "timer8";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer9: timer@4833d000 {
|
||||
compatible = "ti,am4372-timer","ti,am335x-timer";
|
||||
reg = <0x4833d000 0x400>;
|
||||
interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "timer9";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer10: timer@4833f000 {
|
||||
compatible = "ti,am4372-timer","ti,am335x-timer";
|
||||
reg = <0x4833f000 0x400>;
|
||||
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "timer10";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer11: timer@48341000 {
|
||||
compatible = "ti,am4372-timer","ti,am335x-timer";
|
||||
reg = <0x48341000 0x400>;
|
||||
interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "timer11";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
counter32k: counter@44e86000 {
|
||||
compatible = "ti,am4372-counter32k","ti,omap-counter32k";
|
||||
reg = <0x44e86000 0x40>;
|
||||
ti,hwmods = "counter_32k";
|
||||
};
|
||||
|
||||
rtc: rtc@44e3e000 {
|
||||
compatible = "ti,am4372-rtc","ti,da830-rtc";
|
||||
reg = <0x44e3e000 0x1000>;
|
||||
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "rtc";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wdt: wdt@44e35000 {
|
||||
compatible = "ti,am4372-wdt","ti,omap3-wdt";
|
||||
reg = <0x44e35000 0x1000>;
|
||||
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "wd_timer2";
|
||||
};
|
||||
|
||||
gpio0: gpio@44e07000 {
|
||||
compatible = "ti,am4372-gpio","ti,omap4-gpio";
|
||||
reg = <0x44e07000 0x1000>;
|
||||
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ti,hwmods = "gpio1";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio1: gpio@4804c000 {
|
||||
compatible = "ti,am4372-gpio","ti,omap4-gpio";
|
||||
reg = <0x4804c000 0x1000>;
|
||||
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ti,hwmods = "gpio2";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio2: gpio@481ac000 {
|
||||
compatible = "ti,am4372-gpio","ti,omap4-gpio";
|
||||
reg = <0x481ac000 0x1000>;
|
||||
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ti,hwmods = "gpio3";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio3: gpio@481ae000 {
|
||||
compatible = "ti,am4372-gpio","ti,omap4-gpio";
|
||||
reg = <0x481ae000 0x1000>;
|
||||
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ti,hwmods = "gpio4";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio4: gpio@48320000 {
|
||||
compatible = "ti,am4372-gpio","ti,omap4-gpio";
|
||||
reg = <0x48320000 0x1000>;
|
||||
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ti,hwmods = "gpio5";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio5: gpio@48322000 {
|
||||
compatible = "ti,am4372-gpio","ti,omap4-gpio";
|
||||
reg = <0x48322000 0x1000>;
|
||||
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ti,hwmods = "gpio6";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
hwspinlock: spinlock@480ca000 {
|
||||
compatible = "ti,omap4-hwspinlock";
|
||||
reg = <0x480ca000 0x1000>;
|
||||
ti,hwmods = "spinlock";
|
||||
#hwlock-cells = <1>;
|
||||
};
|
||||
|
||||
i2c0: i2c@44e0b000 {
|
||||
compatible = "ti,am4372-i2c","ti,omap4-i2c";
|
||||
reg = <0x44e0b000 0x1000>;
|
||||
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "i2c1";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@4802a000 {
|
||||
compatible = "ti,am4372-i2c","ti,omap4-i2c";
|
||||
reg = <0x4802a000 0x1000>;
|
||||
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "i2c2";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@4819c000 {
|
||||
compatible = "ti,am4372-i2c","ti,omap4-i2c";
|
||||
reg = <0x4819c000 0x1000>;
|
||||
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "i2c3";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi0: spi@48030000 {
|
||||
compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
|
||||
reg = <0x48030000 0x400>;
|
||||
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "spi0";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mmc1: mmc@48060000 {
|
||||
compatible = "ti,omap4-hsmmc";
|
||||
reg = <0x48060000 0x1000>;
|
||||
ti,hwmods = "mmc1";
|
||||
ti,dual-volt;
|
||||
ti,needs-special-reset;
|
||||
dmas = <&edma 24
|
||||
&edma 25>;
|
||||
dma-names = "tx", "rx";
|
||||
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mmc2: mmc@481d8000 {
|
||||
compatible = "ti,omap4-hsmmc";
|
||||
reg = <0x481d8000 0x1000>;
|
||||
ti,hwmods = "mmc2";
|
||||
ti,needs-special-reset;
|
||||
dmas = <&edma 2
|
||||
&edma 3>;
|
||||
dma-names = "tx", "rx";
|
||||
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mmc3: mmc@47810000 {
|
||||
compatible = "ti,omap4-hsmmc";
|
||||
reg = <0x47810000 0x1000>;
|
||||
ti,hwmods = "mmc3";
|
||||
ti,needs-special-reset;
|
||||
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi1: spi@481a0000 {
|
||||
compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
|
||||
reg = <0x481a0000 0x400>;
|
||||
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "spi1";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi2: spi@481a2000 {
|
||||
compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
|
||||
reg = <0x481a2000 0x400>;
|
||||
interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "spi2";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi3: spi@481a4000 {
|
||||
compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
|
||||
reg = <0x481a4000 0x400>;
|
||||
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "spi3";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi4: spi@48345000 {
|
||||
compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
|
||||
reg = <0x48345000 0x400>;
|
||||
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "spi4";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mac: ethernet@4a100000 {
|
||||
compatible = "ti,am4372-cpsw","ti,cpsw";
|
||||
reg = <0x4a100000 0x800
|
||||
0x4a101200 0x100>;
|
||||
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ti,hwmods = "cpgmac0";
|
||||
clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
|
||||
clock-names = "fck", "cpts";
|
||||
status = "disabled";
|
||||
cpdma_channels = <8>;
|
||||
ale_entries = <1024>;
|
||||
bd_ram_size = <0x2000>;
|
||||
no_bd_ram = <0>;
|
||||
rx_descs = <64>;
|
||||
mac_control = <0x20>;
|
||||
slaves = <2>;
|
||||
active_slave = <0>;
|
||||
cpts_clock_mult = <0x80000000>;
|
||||
cpts_clock_shift = <29>;
|
||||
ranges;
|
||||
|
||||
davinci_mdio: mdio@4a101000 {
|
||||
compatible = "ti,am4372-mdio","ti,davinci_mdio";
|
||||
reg = <0x4a101000 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
ti,hwmods = "davinci_mdio";
|
||||
bus_freq = <1000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
cpsw_emac0: slave@4a100200 {
|
||||
/* Filled in by U-Boot */
|
||||
mac-address = [ 00 00 00 00 00 00 ];
|
||||
};
|
||||
|
||||
cpsw_emac1: slave@4a100300 {
|
||||
/* Filled in by U-Boot */
|
||||
mac-address = [ 00 00 00 00 00 00 ];
|
||||
};
|
||||
|
||||
phy_sel: cpsw-phy-sel@44e10650 {
|
||||
compatible = "ti,am43xx-cpsw-phy-sel";
|
||||
reg= <0x44e10650 0x4>;
|
||||
reg-names = "gmii-sel";
|
||||
};
|
||||
};
|
||||
|
||||
epwmss0: epwmss@48300000 {
|
||||
compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
|
||||
reg = <0x48300000 0x10>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
ti,hwmods = "epwmss0";
|
||||
status = "disabled";
|
||||
|
||||
ecap0: ecap@48300100 {
|
||||
compatible = "ti,am4372-ecap","ti,am33xx-ecap";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x48300100 0x80>;
|
||||
ti,hwmods = "ecap0";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehrpwm0: ehrpwm@48300200 {
|
||||
compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x48300200 0x80>;
|
||||
ti,hwmods = "ehrpwm0";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
epwmss1: epwmss@48302000 {
|
||||
compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
|
||||
reg = <0x48302000 0x10>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
ti,hwmods = "epwmss1";
|
||||
status = "disabled";
|
||||
|
||||
ecap1: ecap@48302100 {
|
||||
compatible = "ti,am4372-ecap","ti,am33xx-ecap";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x48302100 0x80>;
|
||||
ti,hwmods = "ecap1";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehrpwm1: ehrpwm@48302200 {
|
||||
compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x48302200 0x80>;
|
||||
ti,hwmods = "ehrpwm1";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
epwmss2: epwmss@48304000 {
|
||||
compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
|
||||
reg = <0x48304000 0x10>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
ti,hwmods = "epwmss2";
|
||||
status = "disabled";
|
||||
|
||||
ecap2: ecap@48304100 {
|
||||
compatible = "ti,am4372-ecap","ti,am33xx-ecap";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x48304100 0x80>;
|
||||
ti,hwmods = "ecap2";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehrpwm2: ehrpwm@48304200 {
|
||||
compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x48304200 0x80>;
|
||||
ti,hwmods = "ehrpwm2";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
epwmss3: epwmss@48306000 {
|
||||
compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
|
||||
reg = <0x48306000 0x10>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
ti,hwmods = "epwmss3";
|
||||
status = "disabled";
|
||||
|
||||
ehrpwm3: ehrpwm@48306200 {
|
||||
compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x48306200 0x80>;
|
||||
ti,hwmods = "ehrpwm3";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
epwmss4: epwmss@48308000 {
|
||||
compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
|
||||
reg = <0x48308000 0x10>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
ti,hwmods = "epwmss4";
|
||||
status = "disabled";
|
||||
|
||||
ehrpwm4: ehrpwm@48308200 {
|
||||
compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x48308200 0x80>;
|
||||
ti,hwmods = "ehrpwm4";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
epwmss5: epwmss@4830a000 {
|
||||
compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
|
||||
reg = <0x4830a000 0x10>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
ti,hwmods = "epwmss5";
|
||||
status = "disabled";
|
||||
|
||||
ehrpwm5: ehrpwm@4830a200 {
|
||||
compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x4830a200 0x80>;
|
||||
ti,hwmods = "ehrpwm5";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
tscadc: tscadc@44e0d000 {
|
||||
compatible = "ti,am3359-tscadc";
|
||||
reg = <0x44e0d000 0x1000>;
|
||||
ti,hwmods = "adc_tsc";
|
||||
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&adc_tsc_fck>;
|
||||
clock-names = "fck";
|
||||
status = "disabled";
|
||||
|
||||
tsc {
|
||||
compatible = "ti,am3359-tsc";
|
||||
};
|
||||
|
||||
adc {
|
||||
#io-channel-cells = <1>;
|
||||
compatible = "ti,am3359-adc";
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
sham: sham@53100000 {
|
||||
compatible = "ti,omap5-sham";
|
||||
ti,hwmods = "sham";
|
||||
reg = <0x53100000 0x300>;
|
||||
dmas = <&edma 36>;
|
||||
dma-names = "rx";
|
||||
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
aes: aes@53501000 {
|
||||
compatible = "ti,omap4-aes";
|
||||
ti,hwmods = "aes";
|
||||
reg = <0x53501000 0xa0>;
|
||||
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&edma 6
|
||||
&edma 5>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
des: des@53701000 {
|
||||
compatible = "ti,omap4-des";
|
||||
ti,hwmods = "des";
|
||||
reg = <0x53701000 0xa0>;
|
||||
interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&edma 34
|
||||
&edma 33>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
mcasp0: mcasp@48038000 {
|
||||
compatible = "ti,am33xx-mcasp-audio";
|
||||
ti,hwmods = "mcasp0";
|
||||
reg = <0x48038000 0x2000>,
|
||||
<0x46000000 0x400000>;
|
||||
reg-names = "mpu", "dat";
|
||||
interrupts = <80>, <81>;
|
||||
interrupt-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
dmas = <&edma 8>,
|
||||
<&edma 9>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
mcasp1: mcasp@4803C000 {
|
||||
compatible = "ti,am33xx-mcasp-audio";
|
||||
ti,hwmods = "mcasp1";
|
||||
reg = <0x4803C000 0x2000>,
|
||||
<0x46400000 0x400000>;
|
||||
reg-names = "mpu", "dat";
|
||||
interrupts = <82>, <83>;
|
||||
interrupt-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
dmas = <&edma 10>,
|
||||
<&edma 11>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
elm: elm@48080000 {
|
||||
compatible = "ti,am3352-elm";
|
||||
reg = <0x48080000 0x2000>;
|
||||
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "elm";
|
||||
clocks = <&l4ls_gclk>;
|
||||
clock-names = "fck";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpmc: gpmc@50000000 {
|
||||
compatible = "ti,am3352-gpmc";
|
||||
ti,hwmods = "gpmc";
|
||||
clocks = <&l3s_gclk>;
|
||||
clock-names = "fck";
|
||||
reg = <0x50000000 0x2000>;
|
||||
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpmc,num-cs = <7>;
|
||||
gpmc,num-waitpins = <2>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
am43xx_control_usb2phy1: control-phy@44e10620 {
|
||||
compatible = "ti,control-phy-usb2-am437";
|
||||
reg = <0x44e10620 0x4>;
|
||||
reg-names = "power";
|
||||
};
|
||||
|
||||
am43xx_control_usb2phy2: control-phy@0x44e10628 {
|
||||
compatible = "ti,control-phy-usb2-am437";
|
||||
reg = <0x44e10628 0x4>;
|
||||
reg-names = "power";
|
||||
};
|
||||
|
||||
ocp2scp0: ocp2scp@483a8000 {
|
||||
compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
ti,hwmods = "ocp2scp0";
|
||||
|
||||
usb2_phy1: phy@483a8000 {
|
||||
compatible = "ti,am437x-usb2";
|
||||
reg = <0x483a8000 0x8000>;
|
||||
ctrl-module = <&am43xx_control_usb2phy1>;
|
||||
clocks = <&usb_phy0_always_on_clk32k>,
|
||||
<&usb_otg_ss0_refclk960m>;
|
||||
clock-names = "wkupclk", "refclk";
|
||||
#phy-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
ocp2scp1: ocp2scp@483e8000 {
|
||||
compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
ti,hwmods = "ocp2scp1";
|
||||
|
||||
usb2_phy2: phy@483e8000 {
|
||||
compatible = "ti,am437x-usb2";
|
||||
reg = <0x483e8000 0x8000>;
|
||||
ctrl-module = <&am43xx_control_usb2phy2>;
|
||||
clocks = <&usb_phy1_always_on_clk32k>,
|
||||
<&usb_otg_ss1_refclk960m>;
|
||||
clock-names = "wkupclk", "refclk";
|
||||
#phy-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
dwc3_1: omap_dwc3@48380000 {
|
||||
compatible = "ti,am437x-dwc3";
|
||||
ti,hwmods = "usb_otg_ss0";
|
||||
reg = <0x48380000 0x10000>;
|
||||
interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
utmi-mode = <1>;
|
||||
ranges;
|
||||
|
||||
usb1: usb@48390000 {
|
||||
compatible = "synopsys,dwc3";
|
||||
reg = <0x48390000 0x10000>;
|
||||
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
|
||||
phys = <&usb2_phy1>;
|
||||
phy-names = "usb2-phy";
|
||||
maximum-speed = "high-speed";
|
||||
dr_mode = "otg";
|
||||
status = "disabled";
|
||||
snps,dis_u3_susphy_quirk;
|
||||
snps,dis_u2_susphy_quirk;
|
||||
};
|
||||
};
|
||||
|
||||
dwc3_2: omap_dwc3@483c0000 {
|
||||
compatible = "ti,am437x-dwc3";
|
||||
ti,hwmods = "usb_otg_ss1";
|
||||
reg = <0x483c0000 0x10000>;
|
||||
interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
utmi-mode = <1>;
|
||||
ranges;
|
||||
|
||||
usb2: usb@483d0000 {
|
||||
compatible = "synopsys,dwc3";
|
||||
reg = <0x483d0000 0x10000>;
|
||||
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
|
||||
phys = <&usb2_phy2>;
|
||||
phy-names = "usb2-phy";
|
||||
maximum-speed = "high-speed";
|
||||
dr_mode = "otg";
|
||||
status = "disabled";
|
||||
snps,dis_u3_susphy_quirk;
|
||||
snps,dis_u2_susphy_quirk;
|
||||
};
|
||||
};
|
||||
|
||||
qspi: qspi@47900000 {
|
||||
compatible = "ti,am4372-qspi";
|
||||
reg = <0x47900000 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
ti,hwmods = "qspi";
|
||||
interrupts = <0 138 0x4>;
|
||||
num-cs = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
hdq: hdq@48347000 {
|
||||
compatible = "ti,am4372-hdq";
|
||||
reg = <0x48347000 0x1000>;
|
||||
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&func_12m_clk>;
|
||||
clock-names = "fck";
|
||||
ti,hwmods = "hdq1w";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dss: dss@4832a000 {
|
||||
compatible = "ti,omap3-dss";
|
||||
reg = <0x4832a000 0x200>;
|
||||
status = "disabled";
|
||||
ti,hwmods = "dss_core";
|
||||
clocks = <&disp_clk>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
dispc: dispc@4832a400 {
|
||||
compatible = "ti,omap3-dispc";
|
||||
reg = <0x4832a400 0x400>;
|
||||
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "dss_dispc";
|
||||
clocks = <&disp_clk>;
|
||||
clock-names = "fck";
|
||||
};
|
||||
|
||||
rfbi: rfbi@4832a800 {
|
||||
compatible = "ti,omap3-rfbi";
|
||||
reg = <0x4832a800 0x100>;
|
||||
ti,hwmods = "dss_rfbi";
|
||||
clocks = <&disp_clk>;
|
||||
clock-names = "fck";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
ocmcram: ocmcram@40300000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x40300000 0x40000>; /* 256k */
|
||||
};
|
||||
|
||||
dcan0: can@481cc000 {
|
||||
compatible = "ti,am4372-d_can", "ti,am3352-d_can";
|
||||
ti,hwmods = "d_can0";
|
||||
clocks = <&dcan0_fck>;
|
||||
clock-names = "fck";
|
||||
reg = <0x481cc000 0x2000>;
|
||||
syscon-raminit = <&scm_conf 0x644 0>;
|
||||
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dcan1: can@481d0000 {
|
||||
compatible = "ti,am4372-d_can", "ti,am3352-d_can";
|
||||
ti,hwmods = "d_can1";
|
||||
clocks = <&dcan1_fck>;
|
||||
clock-names = "fck";
|
||||
reg = <0x481d0000 0x2000>;
|
||||
syscon-raminit = <&scm_conf 0x644 1>;
|
||||
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
vpfe0: vpfe@48326000 {
|
||||
compatible = "ti,am437x-vpfe";
|
||||
reg = <0x48326000 0x2000>;
|
||||
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "vpfe0";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
vpfe1: vpfe@48328000 {
|
||||
compatible = "ti,am437x-vpfe";
|
||||
reg = <0x48328000 0x2000>;
|
||||
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "vpfe1";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "am43xx-clocks.dtsi"
|
||||
797
arch/arm/dts/am437x-gp-evm.dts
Normal file
797
arch/arm/dts/am437x-gp-evm.dts
Normal file
|
|
@ -0,0 +1,797 @@
|
|||
/*
|
||||
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/* AM437x GP EVM */
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "am4372.dtsi"
|
||||
#include <dt-bindings/pinctrl/am43xx.h>
|
||||
#include <dt-bindings/pwm/pwm.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
model = "TI AM437x GP EVM";
|
||||
compatible = "ti,am437x-gp-evm","ti,am4372","ti,am43";
|
||||
|
||||
aliases {
|
||||
display0 = &lcd0;
|
||||
serial3 = &uart3;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = &uart0;
|
||||
};
|
||||
|
||||
vmmcsd_fixed: fixedregulator-sd {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vmmcsd_fixed";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
vtt_fixed: fixedregulator-vtt {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vtt_fixed";
|
||||
regulator-min-microvolt = <1500000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
enable-active-high;
|
||||
gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
vmmcwl_fixed: fixedregulator-mmcwl {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vmmcwl_fixed";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
gpio = <&gpio1 20 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
backlight {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
|
||||
brightness-levels = <0 51 53 56 62 75 101 152 255>;
|
||||
default-brightness-level = <8>;
|
||||
};
|
||||
|
||||
matrix_keypad: matrix_keypad@0 {
|
||||
compatible = "gpio-matrix-keypad";
|
||||
debounce-delay-ms = <5>;
|
||||
col-scan-delay-us = <2>;
|
||||
|
||||
row-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH /* Bank3, pin21 */
|
||||
&gpio4 3 GPIO_ACTIVE_HIGH /* Bank4, pin3 */
|
||||
&gpio4 2 GPIO_ACTIVE_HIGH>; /* Bank4, pin2 */
|
||||
|
||||
col-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH /* Bank3, pin19 */
|
||||
&gpio3 20 GPIO_ACTIVE_HIGH>; /* Bank3, pin20 */
|
||||
|
||||
linux,keymap = <0x00000201 /* P1 */
|
||||
0x00010202 /* P2 */
|
||||
0x01000067 /* UP */
|
||||
0x0101006a /* RIGHT */
|
||||
0x02000069 /* LEFT */
|
||||
0x0201006c>; /* DOWN */
|
||||
};
|
||||
|
||||
lcd0: display {
|
||||
compatible = "osddisplays,osd057T0559-34ts", "panel-dpi";
|
||||
label = "lcd";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&lcd_pins>;
|
||||
|
||||
/*
|
||||
* SelLCDorHDMI, LOW to select HDMI. This is not really the
|
||||
* panel's enable GPIO, but we don't have HDMI driver support nor
|
||||
* support to switch between two displays, so using this gpio as
|
||||
* panel's enable should be safe.
|
||||
*/
|
||||
enable-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
panel-timing {
|
||||
clock-frequency = <33000000>;
|
||||
hactive = <800>;
|
||||
vactive = <480>;
|
||||
hfront-porch = <210>;
|
||||
hback-porch = <16>;
|
||||
hsync-len = <30>;
|
||||
vback-porch = <10>;
|
||||
vfront-porch = <22>;
|
||||
vsync-len = <13>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <1>;
|
||||
};
|
||||
|
||||
port {
|
||||
lcd_in: endpoint {
|
||||
remote-endpoint = <&dpi_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* fixed 12MHz oscillator */
|
||||
refclk: oscillator {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <12000000>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
&am43xx_pinmux {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&wlan_pins_default>;
|
||||
pinctrl-1 = <&wlan_pins_sleep>;
|
||||
|
||||
i2c0_pins: i2c0_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
|
||||
0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
|
||||
>;
|
||||
};
|
||||
|
||||
i2c1_pins: i2c1_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x15c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */
|
||||
0x158 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */
|
||||
>;
|
||||
};
|
||||
|
||||
mmc1_pins: pinmux_mmc1_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
|
||||
>;
|
||||
};
|
||||
|
||||
ecap0_pins: backlight_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x164 MUX_MODE0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
|
||||
>;
|
||||
};
|
||||
|
||||
pixcir_ts_pins: pixcir_ts_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x264 (PIN_INPUT_PULLUP | MUX_MODE7) /* spi2_d0.gpio3_22 */
|
||||
>;
|
||||
};
|
||||
|
||||
cpsw_default: cpsw_default {
|
||||
pinctrl-single,pins = <
|
||||
/* Slave 1 */
|
||||
0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_txen */
|
||||
0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rxctl */
|
||||
0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd3 */
|
||||
0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd2 */
|
||||
0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd1 */
|
||||
0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd0 */
|
||||
0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rmii1_tclk */
|
||||
0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */
|
||||
0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd3 */
|
||||
0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd2 */
|
||||
0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd1 */
|
||||
0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd0 */
|
||||
>;
|
||||
};
|
||||
|
||||
cpsw_sleep: cpsw_sleep {
|
||||
pinctrl-single,pins = <
|
||||
/* Slave 1 reset value */
|
||||
0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
>;
|
||||
};
|
||||
|
||||
davinci_mdio_default: davinci_mdio_default {
|
||||
pinctrl-single,pins = <
|
||||
/* MDIO */
|
||||
0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
|
||||
0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
|
||||
>;
|
||||
};
|
||||
|
||||
davinci_mdio_sleep: davinci_mdio_sleep {
|
||||
pinctrl-single,pins = <
|
||||
/* MDIO reset value */
|
||||
0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
>;
|
||||
};
|
||||
|
||||
nand_flash_x8: nand_flash_x8 {
|
||||
pinctrl-single,pins = <
|
||||
0x26c(PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* spi2_cs0.gpio/eMMCorNANDsel */
|
||||
0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
|
||||
0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
|
||||
0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
|
||||
0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
|
||||
0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
|
||||
0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
|
||||
0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
|
||||
0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
|
||||
0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
|
||||
0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */
|
||||
0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
|
||||
0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
|
||||
0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
|
||||
0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
|
||||
0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
|
||||
>;
|
||||
};
|
||||
|
||||
dss_pins: dss_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x020 (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */
|
||||
0x024 (PIN_OUTPUT_PULLUP | MUX_MODE1)
|
||||
0x028 (PIN_OUTPUT_PULLUP | MUX_MODE1)
|
||||
0x02c (PIN_OUTPUT_PULLUP | MUX_MODE1)
|
||||
0x030 (PIN_OUTPUT_PULLUP | MUX_MODE1)
|
||||
0x034 (PIN_OUTPUT_PULLUP | MUX_MODE1)
|
||||
0x038 (PIN_OUTPUT_PULLUP | MUX_MODE1)
|
||||
0x03c (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */
|
||||
0x0a0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */
|
||||
0x0a4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
|
||||
0x0a8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
|
||||
0x0ac (PIN_OUTPUT_PULLUP | MUX_MODE0)
|
||||
0x0b0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
|
||||
0x0b4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
|
||||
0x0b8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
|
||||
0x0bc (PIN_OUTPUT_PULLUP | MUX_MODE0)
|
||||
0x0c0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
|
||||
0x0c4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
|
||||
0x0c8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
|
||||
0x0cc (PIN_OUTPUT_PULLUP | MUX_MODE0)
|
||||
0x0d0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
|
||||
0x0d4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
|
||||
0x0d8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
|
||||
0x0dc (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */
|
||||
0x0e0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */
|
||||
0x0e4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
|
||||
0x0e8 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */
|
||||
0x0ec (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */
|
||||
|
||||
>;
|
||||
};
|
||||
|
||||
lcd_pins: lcd_pins {
|
||||
pinctrl-single,pins = <
|
||||
/* GPIO 5_8 to select LCD / HDMI */
|
||||
0x238 (PIN_OUTPUT_PULLUP | MUX_MODE7)
|
||||
>;
|
||||
};
|
||||
|
||||
dcan0_default: dcan0_default_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x178 (PIN_OUTPUT | MUX_MODE2) /* uart1_ctsn.d_can0_tx */
|
||||
0x17c (PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_rtsn.d_can0_rx */
|
||||
>;
|
||||
};
|
||||
|
||||
dcan1_default: dcan1_default_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x180 (PIN_OUTPUT | MUX_MODE2) /* uart1_rxd.d_can1_tx */
|
||||
0x184 (PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_txd.d_can1_rx */
|
||||
>;
|
||||
};
|
||||
|
||||
vpfe0_pins_default: vpfe0_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
0x1B0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_hd mode 0*/
|
||||
0x1B4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_vd mode 0*/
|
||||
0x1C0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_pclk mode 0*/
|
||||
0x1C4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data8 mode 0*/
|
||||
0x1C8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data9 mode 0*/
|
||||
0x208 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data0 mode 0*/
|
||||
0x20C (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data1 mode 0*/
|
||||
0x210 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data2 mode 0*/
|
||||
0x214 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data3 mode 0*/
|
||||
0x218 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data4 mode 0*/
|
||||
0x21C (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data5 mode 0*/
|
||||
0x220 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data6 mode 0*/
|
||||
0x224 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data7 mode 0*/
|
||||
>;
|
||||
};
|
||||
|
||||
vpfe0_pins_sleep: vpfe0_pins_sleep {
|
||||
pinctrl-single,pins = <
|
||||
0x1B0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_hd mode 0*/
|
||||
0x1B4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_vd mode 0*/
|
||||
0x1C0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_pclk mode 0*/
|
||||
0x1C4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data8 mode 0*/
|
||||
0x1C8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data9 mode 0*/
|
||||
0x208 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data0 mode 0*/
|
||||
0x20C (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data1 mode 0*/
|
||||
0x210 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data2 mode 0*/
|
||||
0x214 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data3 mode 0*/
|
||||
0x218 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data4 mode 0*/
|
||||
0x21C (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data5 mode 0*/
|
||||
0x220 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data6 mode 0*/
|
||||
0x224 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data7 mode 0*/
|
||||
>;
|
||||
};
|
||||
|
||||
vpfe1_pins_default: vpfe1_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
0x1CC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data9 mode 0*/
|
||||
0x1D0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data8 mode 0*/
|
||||
0x1D4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_hd mode 0*/
|
||||
0x1D8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_vd mode 0*/
|
||||
0x1DC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_pclk mode 0*/
|
||||
0x1E8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data0 mode 0*/
|
||||
0x1EC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data1 mode 0*/
|
||||
0x1F0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data2 mode 0*/
|
||||
0x1F4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data3 mode 0*/
|
||||
0x1F8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data4 mode 0*/
|
||||
0x1FC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data5 mode 0*/
|
||||
0x200 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data6 mode 0*/
|
||||
0x204 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data7 mode 0*/
|
||||
>;
|
||||
};
|
||||
|
||||
vpfe1_pins_sleep: vpfe1_pins_sleep {
|
||||
pinctrl-single,pins = <
|
||||
0x1CC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data9 mode 0*/
|
||||
0x1D0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data8 mode 0*/
|
||||
0x1D4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_hd mode 0*/
|
||||
0x1D8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_vd mode 0*/
|
||||
0x1DC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_pclk mode 0*/
|
||||
0x1E8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data0 mode 0*/
|
||||
0x1EC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data1 mode 0*/
|
||||
0x1F0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data2 mode 0*/
|
||||
0x1F4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data3 mode 0*/
|
||||
0x1F8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data4 mode 0*/
|
||||
0x1FC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data5 mode 0*/
|
||||
0x200 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data6 mode 0*/
|
||||
0x204 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data7 mode 0*/
|
||||
>;
|
||||
};
|
||||
|
||||
mmc3_pins_default: pinmux_mmc3_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
0x8c (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc2_clk */
|
||||
0x88 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd */
|
||||
0x44 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a1.mmc2_dat0 */
|
||||
0x48 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a2.mmc2_dat1 */
|
||||
0x4c (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a3.mmc2_dat2 */
|
||||
0x78 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_be1n.mmc2_dat3 */
|
||||
>;
|
||||
};
|
||||
|
||||
mmc3_pins_sleep: pinmux_mmc3_pins_sleep {
|
||||
pinctrl-single,pins = <
|
||||
0x8c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_clk.mmc2_clk */
|
||||
0x88 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn3.mmc2_cmd */
|
||||
0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a1.mmc2_dat0 */
|
||||
0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a2.mmc2_dat1 */
|
||||
0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a3.mmc2_dat2 */
|
||||
0x78 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_be1n.mmc2_dat3 */
|
||||
>;
|
||||
};
|
||||
|
||||
wlan_pins_default: pinmux_wlan_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.gpio1_20 WL_EN */
|
||||
0x5c (PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* gpmc_a7.gpio1_23 WL_IRQ*/
|
||||
0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.gpio1_16 BT_EN*/
|
||||
>;
|
||||
};
|
||||
|
||||
wlan_pins_sleep: pinmux_wlan_pins_sleep {
|
||||
pinctrl-single,pins = <
|
||||
0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.gpio1_20 WL_EN */
|
||||
0x5c (PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* gpmc_a7.gpio1_23 WL_IRQ*/
|
||||
0x40 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a0.gpio1_16 BT_EN*/
|
||||
>;
|
||||
};
|
||||
|
||||
uart3_pins: uart3_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x228 (PIN_INPUT | MUX_MODE0) /* uart3_rxd.uart3_rxd */
|
||||
0x22c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_txd.uart3_txd */
|
||||
0x230 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_ctsn.uart3_ctsn */
|
||||
0x234 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_rtsn.uart3_rtsn */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c0_pins>;
|
||||
clock-frequency = <100000>;
|
||||
|
||||
tps65218: tps65218@24 {
|
||||
reg = <0x24>;
|
||||
compatible = "ti,tps65218";
|
||||
interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
dcdc1: regulator-dcdc1 {
|
||||
compatible = "ti,tps65218-dcdc1";
|
||||
regulator-name = "vdd_core";
|
||||
regulator-min-microvolt = <912000>;
|
||||
regulator-max-microvolt = <1144000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
dcdc2: regulator-dcdc2 {
|
||||
compatible = "ti,tps65218-dcdc2";
|
||||
regulator-name = "vdd_mpu";
|
||||
regulator-min-microvolt = <912000>;
|
||||
regulator-max-microvolt = <1378000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
dcdc3: regulator-dcdc3 {
|
||||
compatible = "ti,tps65218-dcdc3";
|
||||
regulator-name = "vdcdc3";
|
||||
regulator-min-microvolt = <1500000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
dcdc5: regulator-dcdc5 {
|
||||
compatible = "ti,tps65218-dcdc5";
|
||||
regulator-name = "v1_0bat";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
};
|
||||
|
||||
dcdc6: regulator-dcdc6 {
|
||||
compatible = "ti,tps65218-dcdc6";
|
||||
regulator-name = "v1_8bat";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
ldo1: regulator-ldo1 {
|
||||
compatible = "ti,tps65218-ldo1";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
|
||||
ov2659@30 {
|
||||
compatible = "ovti,ov2659";
|
||||
reg = <0x30>;
|
||||
|
||||
clocks = <&refclk 0>;
|
||||
clock-names = "xvclk";
|
||||
|
||||
port {
|
||||
ov2659_0: endpoint {
|
||||
remote-endpoint = <&vpfe1_ep>;
|
||||
link-frequencies = /bits/ 64 <70000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c1_pins>;
|
||||
pixcir_ts@5c {
|
||||
compatible = "pixcir,pixcir_tangoc";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pixcir_ts_pins>;
|
||||
reg = <0x5c>;
|
||||
interrupt-parent = <&gpio3>;
|
||||
interrupts = <22 0>;
|
||||
|
||||
attb-gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
touchscreen-size-x = <1024>;
|
||||
touchscreen-size-y = <600>;
|
||||
};
|
||||
|
||||
ov2659@30 {
|
||||
compatible = "ovti,ov2659";
|
||||
reg = <0x30>;
|
||||
|
||||
clocks = <&refclk 0>;
|
||||
clock-names = "xvclk";
|
||||
|
||||
port {
|
||||
ov2659_1: endpoint {
|
||||
remote-endpoint = <&vpfe0_ep>;
|
||||
link-frequencies = /bits/ 64 <70000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&epwmss0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tscadc {
|
||||
status = "okay";
|
||||
|
||||
adc {
|
||||
ti,adc-channels = <0 1 2 3 4 5 6 7>;
|
||||
};
|
||||
};
|
||||
|
||||
&ecap0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ecap0_pins>;
|
||||
};
|
||||
|
||||
&gpio0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio4 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio5 {
|
||||
status = "okay";
|
||||
ti,no-reset-on-init;
|
||||
};
|
||||
|
||||
&mmc1 {
|
||||
status = "okay";
|
||||
vmmc-supply = <&vmmcsd_fixed>;
|
||||
bus-width = <4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mmc1_pins>;
|
||||
cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
&mmc3 {
|
||||
/* disable MMC3 as SDIO is not supported in U-Boot */
|
||||
status = "disabled";
|
||||
/* these are on the crossbar and are outlined in the
|
||||
xbar-event-map element */
|
||||
dmas = <&edma 30
|
||||
&edma 31>;
|
||||
dma-names = "tx", "rx";
|
||||
vmmc-supply = <&vmmcwl_fixed>;
|
||||
bus-width = <4>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&mmc3_pins_default>;
|
||||
pinctrl-1 = <&mmc3_pins_sleep>;
|
||||
cap-power-off-card;
|
||||
keep-power-in-suspend;
|
||||
ti,non-removable;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
wlcore: wlcore@0 {
|
||||
compatible = "ti,wl1835";
|
||||
reg = <2>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
&edma {
|
||||
ti,edma-xbar-event-map = /bits/ 16 <1 30
|
||||
2 31>;
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart3_pins>;
|
||||
};
|
||||
|
||||
&usb2_phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
dr_mode = "peripheral";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2_phy2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2 {
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mac {
|
||||
slaves = <1>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&cpsw_default>;
|
||||
pinctrl-1 = <&cpsw_sleep>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&davinci_mdio {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&davinci_mdio_default>;
|
||||
pinctrl-1 = <&davinci_mdio_sleep>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpsw_emac0 {
|
||||
phy_id = <&davinci_mdio>, <0>;
|
||||
phy-mode = "rgmii";
|
||||
};
|
||||
|
||||
&elm {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpmc {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&nand_flash_x8>;
|
||||
ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
|
||||
nand@0,0 {
|
||||
reg = <0 0 4>; /* device IO registers */
|
||||
ti,nand-ecc-opt = "bch16";
|
||||
ti,elm-id = <&elm>;
|
||||
nand-bus-width = <8>;
|
||||
gpmc,device-width = <1>;
|
||||
gpmc,sync-clk-ps = <0>;
|
||||
gpmc,cs-on-ns = <0>;
|
||||
gpmc,cs-rd-off-ns = <40>;
|
||||
gpmc,cs-wr-off-ns = <40>;
|
||||
gpmc,adv-on-ns = <0>;
|
||||
gpmc,adv-rd-off-ns = <25>;
|
||||
gpmc,adv-wr-off-ns = <25>;
|
||||
gpmc,we-on-ns = <0>;
|
||||
gpmc,we-off-ns = <20>;
|
||||
gpmc,oe-on-ns = <3>;
|
||||
gpmc,oe-off-ns = <30>;
|
||||
gpmc,access-ns = <30>;
|
||||
gpmc,rd-cycle-ns = <40>;
|
||||
gpmc,wr-cycle-ns = <40>;
|
||||
gpmc,wait-pin = <0>;
|
||||
gpmc,bus-turnaround-ns = <0>;
|
||||
gpmc,cycle2cycle-delay-ns = <0>;
|
||||
gpmc,clk-activation-ns = <0>;
|
||||
gpmc,wait-monitoring-ns = <0>;
|
||||
gpmc,wr-access-ns = <40>;
|
||||
gpmc,wr-data-mux-bus-ns = <0>;
|
||||
/* MTD partition table */
|
||||
/* All SPL-* partitions are sized to minimal length
|
||||
* which can be independently programmable. For
|
||||
* NAND flash this is equal to size of erase-block */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "NAND.SPL";
|
||||
reg = <0x00000000 0x00040000>;
|
||||
};
|
||||
partition@1 {
|
||||
label = "NAND.SPL.backup1";
|
||||
reg = <0x00040000 0x00040000>;
|
||||
};
|
||||
partition@2 {
|
||||
label = "NAND.SPL.backup2";
|
||||
reg = <0x00080000 0x00040000>;
|
||||
};
|
||||
partition@3 {
|
||||
label = "NAND.SPL.backup3";
|
||||
reg = <0x000c0000 0x00040000>;
|
||||
};
|
||||
partition@4 {
|
||||
label = "NAND.u-boot-spl-os";
|
||||
reg = <0x00100000 0x00080000>;
|
||||
};
|
||||
partition@5 {
|
||||
label = "NAND.u-boot";
|
||||
reg = <0x00180000 0x00100000>;
|
||||
};
|
||||
partition@6 {
|
||||
label = "NAND.u-boot-env";
|
||||
reg = <0x00280000 0x00040000>;
|
||||
};
|
||||
partition@7 {
|
||||
label = "NAND.u-boot-env.backup1";
|
||||
reg = <0x002c0000 0x00040000>;
|
||||
};
|
||||
partition@8 {
|
||||
label = "NAND.kernel";
|
||||
reg = <0x00300000 0x00700000>;
|
||||
};
|
||||
partition@9 {
|
||||
label = "NAND.file-system";
|
||||
reg = <0x00a00000 0x1f600000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dss {
|
||||
status = "ok";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&dss_pins>;
|
||||
|
||||
port {
|
||||
dpi_out: endpoint@0 {
|
||||
remote-endpoint = <&lcd_in>;
|
||||
data-lines = <24>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dcan0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&dcan0_default>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dcan1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&dcan1_default>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vpfe0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&vpfe0_pins_default>;
|
||||
pinctrl-1 = <&vpfe0_pins_sleep>;
|
||||
|
||||
port {
|
||||
vpfe0_ep: endpoint {
|
||||
remote-endpoint = <&ov2659_1>;
|
||||
ti,am437x-vpfe-interface = <0>;
|
||||
bus-width = <8>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&vpfe1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&vpfe1_pins_default>;
|
||||
pinctrl-1 = <&vpfe1_pins_sleep>;
|
||||
|
||||
port {
|
||||
vpfe1_ep: endpoint {
|
||||
remote-endpoint = <&ov2659_0>;
|
||||
ti,am437x-vpfe-interface = <0>;
|
||||
bus-width = <8>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
704
arch/arm/dts/am437x-sk-evm.dts
Normal file
704
arch/arm/dts/am437x-sk-evm.dts
Normal file
|
|
@ -0,0 +1,704 @@
|
|||
/*
|
||||
* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/* AM437x SK EVM */
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "am4372.dtsi"
|
||||
#include <dt-bindings/pinctrl/am43xx.h>
|
||||
#include <dt-bindings/pwm/pwm.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
||||
/ {
|
||||
model = "TI AM437x SK EVM";
|
||||
compatible = "ti,am437x-sk-evm","ti,am4372","ti,am43";
|
||||
|
||||
aliases {
|
||||
display0 = &lcd0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = &uart0;
|
||||
};
|
||||
|
||||
backlight {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
|
||||
brightness-levels = <0 51 53 56 62 75 101 152 255>;
|
||||
default-brightness-level = <8>;
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "ti,da830-evm-audio";
|
||||
ti,model = "AM437x-SK-EVM";
|
||||
ti,audio-codec = <&tlv320aic3106>;
|
||||
ti,mcasp-controller = <&mcasp1>;
|
||||
ti,codec-clock-rate = <24000000>;
|
||||
ti,audio-routing =
|
||||
"Headphone Jack", "HPLOUT",
|
||||
"Headphone Jack", "HPROUT";
|
||||
};
|
||||
|
||||
matrix_keypad: matrix_keypad@0 {
|
||||
compatible = "gpio-matrix-keypad";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&matrix_keypad_pins>;
|
||||
|
||||
debounce-delay-ms = <5>;
|
||||
col-scan-delay-us = <5>;
|
||||
|
||||
row-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH /* Bank5, pin5 */
|
||||
&gpio5 6 GPIO_ACTIVE_HIGH>; /* Bank5, pin6 */
|
||||
|
||||
col-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH /* Bank5, pin13 */
|
||||
&gpio5 4 GPIO_ACTIVE_HIGH>; /* Bank5, pin4 */
|
||||
|
||||
linux,keymap = <
|
||||
MATRIX_KEY(0, 0, KEY_DOWN)
|
||||
MATRIX_KEY(0, 1, KEY_RIGHT)
|
||||
MATRIX_KEY(1, 0, KEY_LEFT)
|
||||
MATRIX_KEY(1, 1, KEY_UP)
|
||||
>;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&leds_pins>;
|
||||
|
||||
led@0 {
|
||||
label = "am437x-sk:red:heartbeat";
|
||||
gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 0 */
|
||||
linux,default-trigger = "heartbeat";
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led@1 {
|
||||
label = "am437x-sk:green:mmc1";
|
||||
gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 1 */
|
||||
linux,default-trigger = "mmc0";
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led@2 {
|
||||
label = "am437x-sk:blue:cpu0";
|
||||
gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 2 */
|
||||
linux,default-trigger = "cpu0";
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led@3 {
|
||||
label = "am437x-sk:blue:usr3";
|
||||
gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 3 */
|
||||
default-state = "off";
|
||||
};
|
||||
};
|
||||
|
||||
lcd0: display {
|
||||
compatible = "newhaven,nhd-4.3-480272ef-atxl", "panel-dpi";
|
||||
label = "lcd";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&lcd_pins>;
|
||||
|
||||
enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
panel-timing {
|
||||
clock-frequency = <9000000>;
|
||||
hactive = <480>;
|
||||
vactive = <272>;
|
||||
hfront-porch = <2>;
|
||||
hback-porch = <2>;
|
||||
hsync-len = <41>;
|
||||
vfront-porch = <2>;
|
||||
vback-porch = <2>;
|
||||
vsync-len = <10>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <1>;
|
||||
};
|
||||
|
||||
port {
|
||||
lcd_in: endpoint {
|
||||
remote-endpoint = <&dpi_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&am43xx_pinmux {
|
||||
matrix_keypad_pins: matrix_keypad_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x24c (PIN_OUTPUT | MUX_MODE7) /* gpio5_13.gpio5_13 */
|
||||
0x250 (PIN_OUTPUT | MUX_MODE7) /* spi4_sclk.gpio5_4 */
|
||||
0x254 (PIN_INPUT | MUX_MODE7) /* spi4_d0.gpio5_5 */
|
||||
0x258 (PIN_INPUT | MUX_MODE7) /* spi4_d1.gpio5_5 */
|
||||
>;
|
||||
};
|
||||
|
||||
leds_pins: leds_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x228 (PIN_OUTPUT | MUX_MODE7) /* uart3_rxd.gpio5_2 */
|
||||
0x22c (PIN_OUTPUT | MUX_MODE7) /* uart3_txd.gpio5_3 */
|
||||
0x230 (PIN_OUTPUT | MUX_MODE7) /* uart3_ctsn.gpio5_0 */
|
||||
0x234 (PIN_OUTPUT | MUX_MODE7) /* uart3_rtsn.gpio5_1 */
|
||||
>;
|
||||
};
|
||||
|
||||
i2c0_pins: i2c0_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x188 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
|
||||
0x18c (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
|
||||
>;
|
||||
};
|
||||
|
||||
i2c1_pins: i2c1_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x15c (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */
|
||||
0x158 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */
|
||||
>;
|
||||
};
|
||||
|
||||
mmc1_pins: pinmux_mmc1_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x0f0 (PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
|
||||
0x0f4 (PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
|
||||
0x0f8 (PIN_INPUT | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
|
||||
0x0fc (PIN_INPUT | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
|
||||
0x100 (PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */
|
||||
0x104 (PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
|
||||
0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
|
||||
>;
|
||||
};
|
||||
|
||||
ecap0_pins: backlight_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x164 (PIN_OUTPUT | MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out */
|
||||
>;
|
||||
};
|
||||
|
||||
edt_ft5306_ts_pins: edt_ft5306_ts_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x74 (PIN_INPUT | MUX_MODE7) /* gpmc_wpn.gpio0_31 */
|
||||
0x78 (PIN_OUTPUT | MUX_MODE7) /* gpmc_be1n.gpio1_28 */
|
||||
>;
|
||||
};
|
||||
|
||||
vpfe0_pins_default: vpfe0_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
0x1b0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_hd mode 0*/
|
||||
0x1b4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_vd mode 0*/
|
||||
0x1b8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_field mode 0*/
|
||||
0x1bc (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_wen mode 0*/
|
||||
0x1c0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_pclk mode 0*/
|
||||
0x1c4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data8 mode 0*/
|
||||
0x1c8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data9 mode 0*/
|
||||
0x208 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data0 mode 0*/
|
||||
0x20c (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data1 mode 0*/
|
||||
0x210 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data2 mode 0*/
|
||||
0x214 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data3 mode 0*/
|
||||
0x218 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data4 mode 0*/
|
||||
0x21c (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data5 mode 0*/
|
||||
0x220 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data6 mode 0*/
|
||||
0x224 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data7 mode 0*/
|
||||
>;
|
||||
};
|
||||
|
||||
vpfe0_pins_sleep: vpfe0_pins_sleep {
|
||||
pinctrl-single,pins = <
|
||||
0x1b0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
|
||||
0x1b4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
|
||||
0x1b8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
|
||||
0x1bc (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
|
||||
0x1c0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
|
||||
0x1c4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
|
||||
0x1c8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
|
||||
0x208 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
|
||||
0x20c (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
|
||||
0x210 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
|
||||
0x214 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
|
||||
0x218 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
|
||||
0x21c (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
|
||||
0x220 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
|
||||
0x224 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
|
||||
>;
|
||||
};
|
||||
|
||||
cpsw_default: cpsw_default {
|
||||
pinctrl-single,pins = <
|
||||
/* Slave 1 */
|
||||
0x12c (PIN_OUTPUT | MUX_MODE2) /* mii1_txclk.rmii1_tclk */
|
||||
0x114 (PIN_OUTPUT | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
|
||||
0x128 (PIN_OUTPUT | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
|
||||
0x124 (PIN_OUTPUT | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
|
||||
0x120 (PIN_OUTPUT | MUX_MODE2) /* mii1_txd0.rgmii1_td2 */
|
||||
0x11c (PIN_OUTPUT | MUX_MODE2) /* mii1_txd1.rgmii1_td3 */
|
||||
0x130 (PIN_INPUT | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */
|
||||
0x118 (PIN_INPUT | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
|
||||
0x140 (PIN_INPUT | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
|
||||
0x13c (PIN_INPUT | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
|
||||
0x138 (PIN_INPUT | MUX_MODE2) /* mii1_rxd0.rgmii1_rd2 */
|
||||
0x134 (PIN_INPUT | MUX_MODE2) /* mii1_rxd1.rgmii1_rd3 */
|
||||
|
||||
/* Slave 2 */
|
||||
0x58 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */
|
||||
0x40 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */
|
||||
0x54 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */
|
||||
0x50 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */
|
||||
0x4c (PIN_OUTPUT | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */
|
||||
0x48 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */
|
||||
0x5c (PIN_INPUT | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */
|
||||
0x44 (PIN_INPUT | MUX_MODE2) /* gpmc_a1.rgmii2_rtcl */
|
||||
0x6c (PIN_INPUT | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */
|
||||
0x68 (PIN_INPUT | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */
|
||||
0x64 (PIN_INPUT | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */
|
||||
0x60 (PIN_INPUT | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */
|
||||
>;
|
||||
};
|
||||
|
||||
cpsw_sleep: cpsw_sleep {
|
||||
pinctrl-single,pins = <
|
||||
/* Slave 1 reset value */
|
||||
0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
|
||||
/* Slave 2 reset value */
|
||||
0x58 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x54 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x50 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x5c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x60 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
>;
|
||||
};
|
||||
|
||||
davinci_mdio_default: davinci_mdio_default {
|
||||
pinctrl-single,pins = <
|
||||
/* MDIO */
|
||||
0x148 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
|
||||
0x14c (PIN_OUTPUT | MUX_MODE0) /* mdio_clk.mdio_clk */
|
||||
>;
|
||||
};
|
||||
|
||||
davinci_mdio_sleep: davinci_mdio_sleep {
|
||||
pinctrl-single,pins = <
|
||||
/* MDIO reset value */
|
||||
0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
>;
|
||||
};
|
||||
|
||||
dss_pins: dss_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x020 (PIN_OUTPUT | MUX_MODE1) /* gpmc ad 8 -> DSS DATA 23 */
|
||||
0x024 (PIN_OUTPUT | MUX_MODE1)
|
||||
0x028 (PIN_OUTPUT | MUX_MODE1)
|
||||
0x02c (PIN_OUTPUT | MUX_MODE1)
|
||||
0x030 (PIN_OUTPUT | MUX_MODE1)
|
||||
0x034 (PIN_OUTPUT | MUX_MODE1)
|
||||
0x038 (PIN_OUTPUT | MUX_MODE1)
|
||||
0x03c (PIN_OUTPUT | MUX_MODE1) /* gpmc ad 15 -> DSS DATA 16 */
|
||||
0x0a0 (PIN_OUTPUT | MUX_MODE0) /* DSS DATA 0 */
|
||||
0x0a4 (PIN_OUTPUT | MUX_MODE0)
|
||||
0x0a8 (PIN_OUTPUT | MUX_MODE0)
|
||||
0x0ac (PIN_OUTPUT | MUX_MODE0)
|
||||
0x0b0 (PIN_OUTPUT | MUX_MODE0)
|
||||
0x0b4 (PIN_OUTPUT | MUX_MODE0)
|
||||
0x0b8 (PIN_OUTPUT | MUX_MODE0)
|
||||
0x0bc (PIN_OUTPUT | MUX_MODE0)
|
||||
0x0c0 (PIN_OUTPUT | MUX_MODE0)
|
||||
0x0c4 (PIN_OUTPUT | MUX_MODE0)
|
||||
0x0c8 (PIN_OUTPUT | MUX_MODE0)
|
||||
0x0cc (PIN_OUTPUT | MUX_MODE0)
|
||||
0x0d0 (PIN_OUTPUT | MUX_MODE0)
|
||||
0x0d4 (PIN_OUTPUT | MUX_MODE0)
|
||||
0x0d8 (PIN_OUTPUT | MUX_MODE0)
|
||||
0x0dc (PIN_OUTPUT | MUX_MODE0) /* DSS DATA 15 */
|
||||
0x0e0 (PIN_OUTPUT | MUX_MODE0) /* DSS VSYNC */
|
||||
0x0e4 (PIN_OUTPUT | MUX_MODE0) /* DSS HSYNC */
|
||||
0x0e8 (PIN_OUTPUT | MUX_MODE0) /* DSS PCLK */
|
||||
0x0ec (PIN_OUTPUT | MUX_MODE0) /* DSS AC BIAS EN */
|
||||
|
||||
>;
|
||||
};
|
||||
|
||||
qspi_pins: qspi_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x7c (PIN_OUTPUT | MUX_MODE3) /* gpmc_csn0.qspi_csn */
|
||||
0x88 (PIN_OUTPUT | MUX_MODE2) /* gpmc_csn3.qspi_clk */
|
||||
0x90 (PIN_INPUT | MUX_MODE3) /* gpmc_advn_ale.qspi_d0 */
|
||||
0x94 (PIN_INPUT | MUX_MODE3) /* gpmc_oen_ren.qspi_d1 */
|
||||
0x98 (PIN_INPUT | MUX_MODE3) /* gpmc_wen.qspi_d2 */
|
||||
0x9c (PIN_INPUT | MUX_MODE3) /* gpmc_be0n_cle.qspi_d3 */
|
||||
>;
|
||||
};
|
||||
|
||||
mcasp1_pins: mcasp1_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
|
||||
0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
|
||||
0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
|
||||
0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
|
||||
>;
|
||||
};
|
||||
|
||||
lcd_pins: lcd_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x1c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpcm_ad7.gpio1_7 */
|
||||
>;
|
||||
};
|
||||
|
||||
usb1_pins: usb1_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x2c0 (PIN_OUTPUT | MUX_MODE0) /* usb0_drvvbus.usb0_drvvbus */
|
||||
>;
|
||||
};
|
||||
|
||||
usb2_pins: usb2_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x2c4 (PIN_OUTPUT | MUX_MODE0) /* usb0_drvvbus.usb0_drvvbus */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c0_pins>;
|
||||
clock-frequency = <400000>;
|
||||
|
||||
tps@24 {
|
||||
compatible = "ti,tps65218";
|
||||
reg = <0x24>;
|
||||
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
dcdc1: regulator-dcdc1 {
|
||||
compatible = "ti,tps65218-dcdc1";
|
||||
/* VDD_CORE limits min of OPP50 and max of OPP100 */
|
||||
regulator-name = "vdd_core";
|
||||
regulator-min-microvolt = <912000>;
|
||||
regulator-max-microvolt = <1144000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
dcdc2: regulator-dcdc2 {
|
||||
compatible = "ti,tps65218-dcdc2";
|
||||
/* VDD_MPU limits min of OPP50 and max of OPP_NITRO */
|
||||
regulator-name = "vdd_mpu";
|
||||
regulator-min-microvolt = <912000>;
|
||||
regulator-max-microvolt = <1378000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
dcdc3: regulator-dcdc3 {
|
||||
compatible = "ti,tps65218-dcdc3";
|
||||
regulator-name = "vdds_ddr";
|
||||
regulator-min-microvolt = <1500000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
dcdc4: regulator-dcdc4 {
|
||||
compatible = "ti,tps65218-dcdc4";
|
||||
regulator-name = "v3_3d";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo1: regulator-ldo1 {
|
||||
compatible = "ti,tps65218-ldo1";
|
||||
regulator-name = "v1_8d";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
power-button {
|
||||
compatible = "ti,tps65218-pwrbutton";
|
||||
status = "okay";
|
||||
interrupts = <3 IRQ_TYPE_EDGE_BOTH>;
|
||||
};
|
||||
};
|
||||
|
||||
at24@50 {
|
||||
compatible = "at24,24c256";
|
||||
pagesize = <64>;
|
||||
reg = <0x50>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c1_pins>;
|
||||
clock-frequency = <400000>;
|
||||
|
||||
edt-ft5306@38 {
|
||||
status = "okay";
|
||||
compatible = "edt,edt-ft5306", "edt,edt-ft5x06";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&edt_ft5306_ts_pins>;
|
||||
|
||||
reg = <0x38>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <31 0>;
|
||||
|
||||
reset-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
|
||||
|
||||
touchscreen-size-x = <480>;
|
||||
touchscreen-size-y = <272>;
|
||||
};
|
||||
|
||||
tlv320aic3106: tlv320aic3106@1b {
|
||||
compatible = "ti,tlv320aic3106";
|
||||
reg = <0x1b>;
|
||||
status = "okay";
|
||||
|
||||
/* Regulators */
|
||||
AVDD-supply = <&dcdc4>;
|
||||
IOVDD-supply = <&dcdc4>;
|
||||
DRVDD-supply = <&dcdc4>;
|
||||
DVDD-supply = <&ldo1>;
|
||||
};
|
||||
|
||||
lis331dlh@18 {
|
||||
compatible = "st,lis331dlh";
|
||||
reg = <0x18>;
|
||||
status = "okay";
|
||||
|
||||
Vdd-supply = <&dcdc4>;
|
||||
Vdd_IO-supply = <&dcdc4>;
|
||||
interrupts-extended = <&gpio1 6 0>, <&gpio2 1 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&epwmss0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ecap0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ecap0_pins>;
|
||||
};
|
||||
|
||||
&gpio0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio5 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mmc1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mmc1_pins>;
|
||||
|
||||
vmmc-supply = <&dcdc4>;
|
||||
bus-width = <4>;
|
||||
cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
&usb2_phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
dr_mode = "peripheral";
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usb1_pins>;
|
||||
};
|
||||
|
||||
&usb2_phy2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2 {
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usb2_pins>;
|
||||
};
|
||||
|
||||
&qspi {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qspi_pins>;
|
||||
|
||||
spi-max-frequency = <48000000>;
|
||||
m25p80@0 {
|
||||
compatible = "mx66l51235l";
|
||||
spi-max-frequency = <48000000>;
|
||||
reg = <0>;
|
||||
spi-cpol;
|
||||
spi-cpha;
|
||||
spi-tx-bus-width = <1>;
|
||||
spi-rx-bus-width = <4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
/* MTD partition table.
|
||||
* The ROM checks the first 512KiB
|
||||
* for a valid file to boot(XIP).
|
||||
*/
|
||||
partition@0 {
|
||||
label = "QSPI.U_BOOT";
|
||||
reg = <0x00000000 0x000080000>;
|
||||
};
|
||||
partition@1 {
|
||||
label = "QSPI.U_BOOT.backup";
|
||||
reg = <0x00080000 0x00080000>;
|
||||
};
|
||||
partition@2 {
|
||||
label = "QSPI.U-BOOT-SPL_OS";
|
||||
reg = <0x00100000 0x00010000>;
|
||||
};
|
||||
partition@3 {
|
||||
label = "QSPI.U_BOOT_ENV";
|
||||
reg = <0x00110000 0x00010000>;
|
||||
};
|
||||
partition@4 {
|
||||
label = "QSPI.U-BOOT-ENV.backup";
|
||||
reg = <0x00120000 0x00010000>;
|
||||
};
|
||||
partition@5 {
|
||||
label = "QSPI.KERNEL";
|
||||
reg = <0x00130000 0x0800000>;
|
||||
};
|
||||
partition@6 {
|
||||
label = "QSPI.FILESYSTEM";
|
||||
reg = <0x00930000 0x36D0000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mac {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&cpsw_default>;
|
||||
pinctrl-1 = <&cpsw_sleep>;
|
||||
dual_emac = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&davinci_mdio {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&davinci_mdio_default>;
|
||||
pinctrl-1 = <&davinci_mdio_sleep>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpsw_emac0 {
|
||||
phy_id = <&davinci_mdio>, <4>;
|
||||
phy-mode = "rgmii";
|
||||
dual_emac_res_vlan = <1>;
|
||||
};
|
||||
|
||||
&cpsw_emac1 {
|
||||
phy_id = <&davinci_mdio>, <5>;
|
||||
phy-mode = "rgmii";
|
||||
dual_emac_res_vlan = <2>;
|
||||
};
|
||||
|
||||
&elm {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mcasp1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcasp1_pins>;
|
||||
|
||||
status = "okay";
|
||||
|
||||
op-mode = <0>;
|
||||
tdm-slots = <2>;
|
||||
serial-dir = <
|
||||
0 0 1 2
|
||||
>;
|
||||
|
||||
tx-num-evt = <1>;
|
||||
rx-num-evt = <1>;
|
||||
};
|
||||
|
||||
&dss {
|
||||
status = "okay";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&dss_pins>;
|
||||
|
||||
port {
|
||||
dpi_out: endpoint@0 {
|
||||
remote-endpoint = <&lcd_in>;
|
||||
data-lines = <24>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rtc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wdt {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpu {
|
||||
cpu0-supply = <&dcdc2>;
|
||||
};
|
||||
|
||||
&vpfe0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&vpfe0_pins_default>;
|
||||
pinctrl-1 = <&vpfe0_pins_sleep>;
|
||||
|
||||
/* Camera port */
|
||||
port {
|
||||
vpfe0_ep: endpoint {
|
||||
/* remote-endpoint = <&sensor>; add once we have it */
|
||||
ti,am437x-vpfe-interface = <0>;
|
||||
bus-width = <8>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
757
arch/arm/dts/am43xx-clocks.dtsi
Normal file
757
arch/arm/dts/am43xx-clocks.dtsi
Normal file
|
|
@ -0,0 +1,757 @@
|
|||
/*
|
||||
* Device Tree Source for AM43xx clock data
|
||||
*
|
||||
* Copyright (C) 2013 Texas Instruments, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
&scm_clocks {
|
||||
sys_clkin_ck: sys_clkin_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&sysboot_freq_sel_ck>, <&crystal_freq_sel_ck>;
|
||||
ti,bit-shift = <31>;
|
||||
reg = <0x0040>;
|
||||
};
|
||||
|
||||
crystal_freq_sel_ck: crystal_freq_sel_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
|
||||
ti,bit-shift = <29>;
|
||||
reg = <0x0040>;
|
||||
};
|
||||
|
||||
sysboot_freq_sel_ck: sysboot_freq_sel_ck@44e10040 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
|
||||
ti,bit-shift = <22>;
|
||||
reg = <0x0040>;
|
||||
};
|
||||
|
||||
adc_tsc_fck: adc_tsc_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&sys_clkin_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
dcan0_fck: dcan0_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&sys_clkin_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
dcan1_fck: dcan1_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&sys_clkin_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
mcasp0_fck: mcasp0_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&sys_clkin_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
mcasp1_fck: mcasp1_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&sys_clkin_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
smartreflex0_fck: smartreflex0_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&sys_clkin_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
smartreflex1_fck: smartreflex1_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&sys_clkin_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
sha0_fck: sha0_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&sys_clkin_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
aes0_fck: aes0_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&sys_clkin_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
ehrpwm0_tbclk: ehrpwm0_tbclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&l4ls_gclk>;
|
||||
ti,bit-shift = <0>;
|
||||
reg = <0x0664>;
|
||||
};
|
||||
|
||||
ehrpwm1_tbclk: ehrpwm1_tbclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&l4ls_gclk>;
|
||||
ti,bit-shift = <1>;
|
||||
reg = <0x0664>;
|
||||
};
|
||||
|
||||
ehrpwm2_tbclk: ehrpwm2_tbclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&l4ls_gclk>;
|
||||
ti,bit-shift = <2>;
|
||||
reg = <0x0664>;
|
||||
};
|
||||
|
||||
ehrpwm3_tbclk: ehrpwm3_tbclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&l4ls_gclk>;
|
||||
ti,bit-shift = <4>;
|
||||
reg = <0x0664>;
|
||||
};
|
||||
|
||||
ehrpwm4_tbclk: ehrpwm4_tbclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&l4ls_gclk>;
|
||||
ti,bit-shift = <5>;
|
||||
reg = <0x0664>;
|
||||
};
|
||||
|
||||
ehrpwm5_tbclk: ehrpwm5_tbclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&l4ls_gclk>;
|
||||
ti,bit-shift = <6>;
|
||||
reg = <0x0664>;
|
||||
};
|
||||
};
|
||||
&prcm_clocks {
|
||||
clk_32768_ck: clk_32768_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
clk_rc32k_ck: clk_rc32k_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
virt_19200000_ck: virt_19200000_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <19200000>;
|
||||
};
|
||||
|
||||
virt_24000000_ck: virt_24000000_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
|
||||
virt_25000000_ck: virt_25000000_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
virt_26000000_ck: virt_26000000_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <26000000>;
|
||||
};
|
||||
|
||||
tclkin_ck: tclkin_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <26000000>;
|
||||
};
|
||||
|
||||
dpll_core_ck: dpll_core_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,am3-dpll-core-clock";
|
||||
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
|
||||
reg = <0x2d20>, <0x2d24>, <0x2d2c>;
|
||||
};
|
||||
|
||||
dpll_core_x2_ck: dpll_core_x2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,am3-dpll-x2-clock";
|
||||
clocks = <&dpll_core_ck>;
|
||||
};
|
||||
|
||||
dpll_core_m4_ck: dpll_core_m4_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&dpll_core_x2_ck>;
|
||||
ti,max-div = <31>;
|
||||
ti,autoidle-shift = <8>;
|
||||
reg = <0x2d38>;
|
||||
ti,index-starts-at-one;
|
||||
ti,invert-autoidle-bit;
|
||||
};
|
||||
|
||||
dpll_core_m5_ck: dpll_core_m5_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&dpll_core_x2_ck>;
|
||||
ti,max-div = <31>;
|
||||
ti,autoidle-shift = <8>;
|
||||
reg = <0x2d3c>;
|
||||
ti,index-starts-at-one;
|
||||
ti,invert-autoidle-bit;
|
||||
};
|
||||
|
||||
dpll_core_m6_ck: dpll_core_m6_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&dpll_core_x2_ck>;
|
||||
ti,max-div = <31>;
|
||||
ti,autoidle-shift = <8>;
|
||||
reg = <0x2d40>;
|
||||
ti,index-starts-at-one;
|
||||
ti,invert-autoidle-bit;
|
||||
};
|
||||
|
||||
dpll_mpu_ck: dpll_mpu_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,am3-dpll-clock";
|
||||
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
|
||||
reg = <0x2d60>, <0x2d64>, <0x2d6c>;
|
||||
};
|
||||
|
||||
dpll_mpu_m2_ck: dpll_mpu_m2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&dpll_mpu_ck>;
|
||||
ti,max-div = <31>;
|
||||
ti,autoidle-shift = <8>;
|
||||
reg = <0x2d70>;
|
||||
ti,index-starts-at-one;
|
||||
ti,invert-autoidle-bit;
|
||||
};
|
||||
|
||||
dpll_ddr_ck: dpll_ddr_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,am3-dpll-clock";
|
||||
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
|
||||
reg = <0x2da0>, <0x2da4>, <0x2dac>;
|
||||
};
|
||||
|
||||
dpll_ddr_m2_ck: dpll_ddr_m2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&dpll_ddr_ck>;
|
||||
ti,max-div = <31>;
|
||||
ti,autoidle-shift = <8>;
|
||||
reg = <0x2db0>;
|
||||
ti,index-starts-at-one;
|
||||
ti,invert-autoidle-bit;
|
||||
};
|
||||
|
||||
dpll_disp_ck: dpll_disp_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,am3-dpll-clock";
|
||||
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
|
||||
reg = <0x2e20>, <0x2e24>, <0x2e2c>;
|
||||
};
|
||||
|
||||
dpll_disp_m2_ck: dpll_disp_m2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&dpll_disp_ck>;
|
||||
ti,max-div = <31>;
|
||||
ti,autoidle-shift = <8>;
|
||||
reg = <0x2e30>;
|
||||
ti,index-starts-at-one;
|
||||
ti,invert-autoidle-bit;
|
||||
ti,set-rate-parent;
|
||||
};
|
||||
|
||||
dpll_per_ck: dpll_per_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,am3-dpll-j-type-clock";
|
||||
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
|
||||
reg = <0x2de0>, <0x2de4>, <0x2dec>;
|
||||
};
|
||||
|
||||
dpll_per_m2_ck: dpll_per_m2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&dpll_per_ck>;
|
||||
ti,max-div = <127>;
|
||||
ti,autoidle-shift = <8>;
|
||||
reg = <0x2df0>;
|
||||
ti,index-starts-at-one;
|
||||
ti,invert-autoidle-bit;
|
||||
};
|
||||
|
||||
dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll_per_m2_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <4>;
|
||||
};
|
||||
|
||||
dpll_per_m2_div4_ck: dpll_per_m2_div4_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll_per_m2_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <4>;
|
||||
};
|
||||
|
||||
clk_24mhz: clk_24mhz {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll_per_m2_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <8>;
|
||||
};
|
||||
|
||||
clkdiv32k_ck: clkdiv32k_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&clk_24mhz>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <732>;
|
||||
};
|
||||
|
||||
clkdiv32k_ick: clkdiv32k_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&clkdiv32k_ck>;
|
||||
ti,bit-shift = <8>;
|
||||
reg = <0x2a38>;
|
||||
};
|
||||
|
||||
sysclk_div: sysclk_div {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll_core_m4_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
pruss_ocp_gclk: pruss_ocp_gclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&sysclk_div>, <&dpll_disp_m2_ck>;
|
||||
reg = <0x4248>;
|
||||
};
|
||||
|
||||
clk_32k_tpm_ck: clk_32k_tpm_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
timer1_fck: timer1_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_32k_tpm_ck>;
|
||||
reg = <0x4200>;
|
||||
};
|
||||
|
||||
timer2_fck: timer2_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
|
||||
reg = <0x4204>;
|
||||
};
|
||||
|
||||
timer3_fck: timer3_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
|
||||
reg = <0x4208>;
|
||||
};
|
||||
|
||||
timer4_fck: timer4_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
|
||||
reg = <0x420c>;
|
||||
};
|
||||
|
||||
timer5_fck: timer5_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
|
||||
reg = <0x4210>;
|
||||
};
|
||||
|
||||
timer6_fck: timer6_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
|
||||
reg = <0x4214>;
|
||||
};
|
||||
|
||||
timer7_fck: timer7_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
|
||||
reg = <0x4218>;
|
||||
};
|
||||
|
||||
wdt1_fck: wdt1_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>;
|
||||
reg = <0x422c>;
|
||||
};
|
||||
|
||||
l3_gclk: l3_gclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll_core_m4_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
dpll_core_m4_div2_ck: dpll_core_m4_div2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&sysclk_div>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <2>;
|
||||
};
|
||||
|
||||
l4hs_gclk: l4hs_gclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll_core_m4_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
l3s_gclk: l3s_gclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll_core_m4_div2_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
l4ls_gclk: l4ls_gclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll_core_m4_div2_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
cpsw_125mhz_gclk: cpsw_125mhz_gclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll_core_m5_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <2>;
|
||||
};
|
||||
|
||||
cpsw_cpts_rft_clk: cpsw_cpts_rft_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&sysclk_div>, <&dpll_core_m5_ck>, <&dpll_disp_m2_ck>;
|
||||
reg = <0x4238>;
|
||||
};
|
||||
|
||||
clk_32k_mosc_ck: clk_32k_mosc_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>, <&clk_32k_mosc_ck>, <&clk_32k_tpm_ck>;
|
||||
reg = <0x4240>;
|
||||
};
|
||||
|
||||
gpio0_dbclk: gpio0_dbclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&gpio0_dbclk_mux_ck>;
|
||||
ti,bit-shift = <8>;
|
||||
reg = <0x2b68>;
|
||||
};
|
||||
|
||||
gpio1_dbclk: gpio1_dbclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&clkdiv32k_ick>;
|
||||
ti,bit-shift = <8>;
|
||||
reg = <0x8c78>;
|
||||
};
|
||||
|
||||
gpio2_dbclk: gpio2_dbclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&clkdiv32k_ick>;
|
||||
ti,bit-shift = <8>;
|
||||
reg = <0x8c80>;
|
||||
};
|
||||
|
||||
gpio3_dbclk: gpio3_dbclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&clkdiv32k_ick>;
|
||||
ti,bit-shift = <8>;
|
||||
reg = <0x8c88>;
|
||||
};
|
||||
|
||||
gpio4_dbclk: gpio4_dbclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&clkdiv32k_ick>;
|
||||
ti,bit-shift = <8>;
|
||||
reg = <0x8c90>;
|
||||
};
|
||||
|
||||
gpio5_dbclk: gpio5_dbclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&clkdiv32k_ick>;
|
||||
ti,bit-shift = <8>;
|
||||
reg = <0x8c98>;
|
||||
};
|
||||
|
||||
mmc_clk: mmc_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll_per_m2_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <2>;
|
||||
};
|
||||
|
||||
gfx_fclk_clksel_ck: gfx_fclk_clksel_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&sysclk_div>, <&dpll_per_m2_ck>;
|
||||
ti,bit-shift = <1>;
|
||||
reg = <0x423c>;
|
||||
};
|
||||
|
||||
gfx_fck_div_ck: gfx_fck_div_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&gfx_fclk_clksel_ck>;
|
||||
reg = <0x423c>;
|
||||
ti,max-div = <2>;
|
||||
};
|
||||
|
||||
disp_clk: disp_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
|
||||
reg = <0x4244>;
|
||||
ti,set-rate-parent;
|
||||
};
|
||||
|
||||
dpll_extdev_ck: dpll_extdev_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,am3-dpll-clock";
|
||||
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
|
||||
reg = <0x2e60>, <0x2e64>, <0x2e6c>;
|
||||
};
|
||||
|
||||
dpll_extdev_m2_ck: dpll_extdev_m2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&dpll_extdev_ck>;
|
||||
ti,max-div = <127>;
|
||||
ti,autoidle-shift = <8>;
|
||||
reg = <0x2e70>;
|
||||
ti,index-starts-at-one;
|
||||
ti,invert-autoidle-bit;
|
||||
};
|
||||
|
||||
mux_synctimer32k_ck: mux_synctimer32k_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>, <&clkdiv32k_ick>;
|
||||
reg = <0x4230>;
|
||||
};
|
||||
|
||||
synctimer_32kclk: synctimer_32kclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&mux_synctimer32k_ck>;
|
||||
ti,bit-shift = <8>;
|
||||
reg = <0x2a30>;
|
||||
};
|
||||
|
||||
timer8_fck: timer8_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
|
||||
reg = <0x421c>;
|
||||
};
|
||||
|
||||
timer9_fck: timer9_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
|
||||
reg = <0x4220>;
|
||||
};
|
||||
|
||||
timer10_fck: timer10_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
|
||||
reg = <0x4224>;
|
||||
};
|
||||
|
||||
timer11_fck: timer11_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
|
||||
reg = <0x4228>;
|
||||
};
|
||||
|
||||
cpsw_50m_clkdiv: cpsw_50m_clkdiv {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll_core_m5_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
cpsw_5m_clkdiv: cpsw_5m_clkdiv {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpsw_50m_clkdiv>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <10>;
|
||||
};
|
||||
|
||||
dpll_ddr_x2_ck: dpll_ddr_x2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,am3-dpll-x2-clock";
|
||||
clocks = <&dpll_ddr_ck>;
|
||||
};
|
||||
|
||||
dpll_ddr_m4_ck: dpll_ddr_m4_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&dpll_ddr_x2_ck>;
|
||||
ti,max-div = <31>;
|
||||
ti,autoidle-shift = <8>;
|
||||
reg = <0x2db8>;
|
||||
ti,index-starts-at-one;
|
||||
ti,invert-autoidle-bit;
|
||||
};
|
||||
|
||||
dpll_per_clkdcoldo: dpll_per_clkdcoldo {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,fixed-factor-clock";
|
||||
clocks = <&dpll_per_ck>;
|
||||
ti,clock-mult = <1>;
|
||||
ti,clock-div = <1>;
|
||||
ti,autoidle-shift = <8>;
|
||||
reg = <0x2e14>;
|
||||
ti,invert-autoidle-bit;
|
||||
};
|
||||
|
||||
dll_aging_clk_div: dll_aging_clk_div {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&sys_clkin_ck>;
|
||||
reg = <0x4250>;
|
||||
ti,dividers = <8>, <16>, <32>;
|
||||
};
|
||||
|
||||
div_core_25m_ck: div_core_25m_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&sysclk_div>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <8>;
|
||||
};
|
||||
|
||||
func_12m_clk: func_12m_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll_per_m2_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <16>;
|
||||
};
|
||||
|
||||
vtp_clk_div: vtp_clk_div {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&sys_clkin_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <2>;
|
||||
};
|
||||
|
||||
usbphy_32khz_clkmux: usbphy_32khz_clkmux {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>;
|
||||
reg = <0x4260>;
|
||||
};
|
||||
|
||||
usb_phy0_always_on_clk32k: usb_phy0_always_on_clk32k {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&usbphy_32khz_clkmux>;
|
||||
ti,bit-shift = <8>;
|
||||
reg = <0x2a40>;
|
||||
};
|
||||
|
||||
usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&usbphy_32khz_clkmux>;
|
||||
ti,bit-shift = <8>;
|
||||
reg = <0x2a48>;
|
||||
};
|
||||
|
||||
usb_otg_ss0_refclk960m: usb_otg_ss0_refclk960m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&dpll_per_clkdcoldo>;
|
||||
ti,bit-shift = <8>;
|
||||
reg = <0x8a60>;
|
||||
};
|
||||
|
||||
usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&dpll_per_clkdcoldo>;
|
||||
ti,bit-shift = <8>;
|
||||
reg = <0x8a68>;
|
||||
};
|
||||
};
|
||||
699
arch/arm/dts/am57xx-beagle-x15.dts
Normal file
699
arch/arm/dts/am57xx-beagle-x15.dts
Normal file
|
|
@ -0,0 +1,699 @@
|
|||
/*
|
||||
* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
/dts-v1/;
|
||||
|
||||
#include "dra74x.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
/ {
|
||||
model = "TI AM5728 BeagleBoard-X15";
|
||||
compatible = "ti,am572x-beagle-x15", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7";
|
||||
|
||||
chosen {
|
||||
stdout-path = &uart3;
|
||||
};
|
||||
|
||||
aliases {
|
||||
rtc0 = &mcp_rtc;
|
||||
rtc1 = &tps659038_rtc;
|
||||
rtc2 = &rtc;
|
||||
display0 = &hdmi0;
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x80000000>;
|
||||
};
|
||||
|
||||
vdd_3v3: fixedregulator-vdd_3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vdd_3v3";
|
||||
vin-supply = <®en1>;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
vtt_fixed: fixedregulator-vtt {
|
||||
/* TPS51200 */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vtt_fixed";
|
||||
vin-supply = <&smps3_reg>;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
enable-active-high;
|
||||
gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&leds_pins_default>;
|
||||
|
||||
led@0 {
|
||||
label = "beagle-x15:usr0";
|
||||
gpios = <&gpio7 9 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led@1 {
|
||||
label = "beagle-x15:usr1";
|
||||
gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "cpu0";
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led@2 {
|
||||
label = "beagle-x15:usr2";
|
||||
gpios = <&gpio7 14 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "mmc0";
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led@3 {
|
||||
label = "beagle-x15:usr3";
|
||||
gpios = <&gpio7 15 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "ide-disk";
|
||||
default-state = "off";
|
||||
};
|
||||
};
|
||||
|
||||
gpio_fan: gpio_fan {
|
||||
/* Based on 5v 500mA AFB02505HHB */
|
||||
compatible = "gpio-fan";
|
||||
gpios = <&tps659038_gpio 2 GPIO_ACTIVE_HIGH>;
|
||||
gpio-fan,speed-map = <0 0>,
|
||||
<13000 1>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
extcon_usb1: extcon_usb1 {
|
||||
compatible = "linux,extcon-usb-gpio";
|
||||
id-gpio = <&gpio7 25 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&extcon_usb1_pins>;
|
||||
};
|
||||
|
||||
extcon_usb2: extcon_usb2 {
|
||||
compatible = "linux,extcon-usb-gpio";
|
||||
id-gpio = <&gpio7 24 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&extcon_usb2_pins>;
|
||||
};
|
||||
|
||||
hdmi0: connector {
|
||||
compatible = "hdmi-connector";
|
||||
label = "hdmi";
|
||||
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_connector_in: endpoint {
|
||||
remote-endpoint = <&tpd12s015_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
tpd12s015: encoder {
|
||||
compatible = "ti,tpd12s015";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&tpd12s015_pins>;
|
||||
|
||||
gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>, /* gpio7_10, CT CP HPD */
|
||||
<&gpio6 28 GPIO_ACTIVE_HIGH>, /* gpio6_28, LS OE */
|
||||
<&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
tpd12s015_in: endpoint {
|
||||
remote-endpoint = <&hdmi_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
tpd12s015_out: endpoint {
|
||||
remote-endpoint = <&hdmi_connector_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dra7_pmx_core {
|
||||
leds_pins_default: leds_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
0x3a8 (PIN_OUTPUT | MUX_MODE14) /* spi1_d1.gpio7_8 */
|
||||
0x3ac (PIN_OUTPUT | MUX_MODE14) /* spi1_d0.gpio7_9 */
|
||||
0x3c0 (PIN_OUTPUT | MUX_MODE14) /* spi2_sclk.gpio7_14 */
|
||||
0x3c4 (PIN_OUTPUT | MUX_MODE14) /* spi2_d1.gpio7_15 */
|
||||
>;
|
||||
};
|
||||
|
||||
i2c1_pins_default: i2c1_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
0x400 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda.sda */
|
||||
0x404 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl.scl */
|
||||
>;
|
||||
};
|
||||
|
||||
hdmi_pins: pinmux_hdmi_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x408 (PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */
|
||||
0x40c (PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */
|
||||
>;
|
||||
};
|
||||
|
||||
i2c3_pins_default: i2c3_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
0x2a4 (PIN_INPUT| MUX_MODE10) /* mcasp1_aclkx.i2c3_sda */
|
||||
0x2a8 (PIN_INPUT| MUX_MODE10) /* mcasp1_fsx.i2c3_scl */
|
||||
>;
|
||||
};
|
||||
|
||||
uart3_pins_default: uart3_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
0x3f8 (PIN_INPUT_SLEW | MUX_MODE2) /* uart2_ctsn.uart3_rxd */
|
||||
0x3fc (PIN_INPUT_SLEW | MUX_MODE1) /* uart2_rtsn.uart3_txd */
|
||||
>;
|
||||
};
|
||||
|
||||
mmc1_pins_default: mmc1_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
0x36c (PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */
|
||||
0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
|
||||
0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
|
||||
0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
|
||||
0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
|
||||
0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
|
||||
0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
|
||||
>;
|
||||
};
|
||||
|
||||
mmc2_pins_default: mmc2_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
|
||||
0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
|
||||
0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
|
||||
0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
|
||||
0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
|
||||
0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
|
||||
0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
|
||||
0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
|
||||
0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
|
||||
0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
|
||||
>;
|
||||
};
|
||||
|
||||
cpsw_pins_default: cpsw_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
/* Slave 1 */
|
||||
0x250 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_tclk */
|
||||
0x254 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_tctl */
|
||||
0x258 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td3 */
|
||||
0x25c (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td2 */
|
||||
0x260 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td1 */
|
||||
0x264 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td0 */
|
||||
0x268 (PIN_INPUT | MUX_MODE0) /* rgmii1_rclk */
|
||||
0x26c (PIN_INPUT | MUX_MODE0) /* rgmii1_rctl */
|
||||
0x270 (PIN_INPUT | MUX_MODE0) /* rgmii1_rd3 */
|
||||
0x274 (PIN_INPUT | MUX_MODE0) /* rgmii1_rd2 */
|
||||
0x278 (PIN_INPUT | MUX_MODE0) /* rgmii1_rd1 */
|
||||
0x27c (PIN_INPUT | MUX_MODE0) /* rgmii1_rd0 */
|
||||
|
||||
/* Slave 2 */
|
||||
0x198 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_tclk */
|
||||
0x19c (PIN_OUTPUT | MUX_MODE3) /* rgmii2_tctl */
|
||||
0x1a0 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td3 */
|
||||
0x1a4 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td2 */
|
||||
0x1a8 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td1 */
|
||||
0x1ac (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td0 */
|
||||
0x1b0 (PIN_INPUT | MUX_MODE3) /* rgmii2_rclk */
|
||||
0x1b4 (PIN_INPUT | MUX_MODE3) /* rgmii2_rctl */
|
||||
0x1b8 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd3 */
|
||||
0x1bc (PIN_INPUT | MUX_MODE3) /* rgmii2_rd2 */
|
||||
0x1c0 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd1 */
|
||||
0x1c4 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd0 */
|
||||
>;
|
||||
|
||||
};
|
||||
|
||||
cpsw_pins_sleep: cpsw_pins_sleep {
|
||||
pinctrl-single,pins = <
|
||||
/* Slave 1 */
|
||||
0x250 (PIN_INPUT | MUX_MODE15)
|
||||
0x254 (PIN_INPUT | MUX_MODE15)
|
||||
0x258 (PIN_INPUT | MUX_MODE15)
|
||||
0x25c (PIN_INPUT | MUX_MODE15)
|
||||
0x260 (PIN_INPUT | MUX_MODE15)
|
||||
0x264 (PIN_INPUT | MUX_MODE15)
|
||||
0x268 (PIN_INPUT | MUX_MODE15)
|
||||
0x26c (PIN_INPUT | MUX_MODE15)
|
||||
0x270 (PIN_INPUT | MUX_MODE15)
|
||||
0x274 (PIN_INPUT | MUX_MODE15)
|
||||
0x278 (PIN_INPUT | MUX_MODE15)
|
||||
0x27c (PIN_INPUT | MUX_MODE15)
|
||||
|
||||
/* Slave 2 */
|
||||
0x198 (PIN_INPUT | MUX_MODE15)
|
||||
0x19c (PIN_INPUT | MUX_MODE15)
|
||||
0x1a0 (PIN_INPUT | MUX_MODE15)
|
||||
0x1a4 (PIN_INPUT | MUX_MODE15)
|
||||
0x1a8 (PIN_INPUT | MUX_MODE15)
|
||||
0x1ac (PIN_INPUT | MUX_MODE15)
|
||||
0x1b0 (PIN_INPUT | MUX_MODE15)
|
||||
0x1b4 (PIN_INPUT | MUX_MODE15)
|
||||
0x1b8 (PIN_INPUT | MUX_MODE15)
|
||||
0x1bc (PIN_INPUT | MUX_MODE15)
|
||||
0x1c0 (PIN_INPUT | MUX_MODE15)
|
||||
0x1c4 (PIN_INPUT | MUX_MODE15)
|
||||
>;
|
||||
};
|
||||
|
||||
davinci_mdio_pins_default: davinci_mdio_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
/* MDIO */
|
||||
0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_mclk */
|
||||
0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_d */
|
||||
>;
|
||||
};
|
||||
|
||||
davinci_mdio_pins_sleep: davinci_mdio_pins_sleep {
|
||||
pinctrl-single,pins = <
|
||||
0x23c (PIN_INPUT | MUX_MODE15)
|
||||
0x240 (PIN_INPUT | MUX_MODE15)
|
||||
>;
|
||||
};
|
||||
|
||||
tps659038_pins_default: tps659038_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
0x418 (PIN_INPUT_PULLUP | MUX_MODE14) /* wakeup0.gpio1_0 */
|
||||
>;
|
||||
};
|
||||
|
||||
tmp102_pins_default: tmp102_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
0x3C8 (PIN_INPUT_PULLUP | MUX_MODE14) /* spi2_d0.gpio7_16 */
|
||||
>;
|
||||
};
|
||||
|
||||
mcp79410_pins_default: mcp79410_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
0x424 (PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */
|
||||
>;
|
||||
};
|
||||
|
||||
usb1_pins: pinmux_usb1_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
|
||||
>;
|
||||
};
|
||||
|
||||
extcon_usb1_pins: extcon_usb1_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x3ec (PIN_INPUT_PULLUP | MUX_MODE14) /* uart1_rtsn.gpio7_25 */
|
||||
>;
|
||||
};
|
||||
|
||||
extcon_usb2_pins: extcon_usb2_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x3e8 (PIN_INPUT_PULLUP | MUX_MODE14) /* uart1_ctsn.gpio7_24 */
|
||||
>;
|
||||
};
|
||||
|
||||
tpd12s015_pins: pinmux_tpd12s015_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x3b0 (PIN_OUTPUT | MUX_MODE14) /* gpio7_10 CT_CP_HPD */
|
||||
0x3b8 (PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpio7_12 HPD */
|
||||
0x370 (PIN_OUTPUT | MUX_MODE14) /* gpio6_28 LS_OE */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c1_pins_default>;
|
||||
clock-frequency = <400000>;
|
||||
|
||||
tps659038: tps659038@58 {
|
||||
compatible = "ti,tps659038";
|
||||
reg = <0x58>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&tps659038_pins_default>;
|
||||
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
|
||||
ti,system-power-controller;
|
||||
|
||||
tps659038_pmic {
|
||||
compatible = "ti,tps659038-pmic";
|
||||
|
||||
regulators {
|
||||
smps12_reg: smps12 {
|
||||
/* VDD_MPU */
|
||||
regulator-name = "smps12";
|
||||
regulator-min-microvolt = < 850000>;
|
||||
regulator-max-microvolt = <1250000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
smps3_reg: smps3 {
|
||||
/* VDD_DDR */
|
||||
regulator-name = "smps3";
|
||||
regulator-min-microvolt = <1350000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
smps45_reg: smps45 {
|
||||
/* VDD_DSPEVE, VDD_IVA, VDD_GPU */
|
||||
regulator-name = "smps45";
|
||||
regulator-min-microvolt = < 850000>;
|
||||
regulator-max-microvolt = <1150000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
smps6_reg: smps6 {
|
||||
/* VDD_CORE */
|
||||
regulator-name = "smps6";
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1030000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
/* SMPS7 unused */
|
||||
|
||||
smps8_reg: smps8 {
|
||||
/* VDD_1V8 */
|
||||
regulator-name = "smps8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
/* SMPS9 unused */
|
||||
|
||||
ldo1_reg: ldo1 {
|
||||
/* VDD_SD */
|
||||
regulator-name = "ldo1";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
ldo2_reg: ldo2 {
|
||||
/* VDD_SHV5 */
|
||||
regulator-name = "ldo2";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
ldo3_reg: ldo3 {
|
||||
/* VDDA_1V8_PHY */
|
||||
regulator-name = "ldo3";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
ldo9_reg: ldo9 {
|
||||
/* VDD_RTC */
|
||||
regulator-name = "ldo9";
|
||||
regulator-min-microvolt = <1050000>;
|
||||
regulator-max-microvolt = <1050000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
ldoln_reg: ldoln {
|
||||
/* VDDA_1V8_PLL */
|
||||
regulator-name = "ldoln";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
ldousb_reg: ldousb {
|
||||
/* VDDA_3V_USB: VDDA_USBHS33 */
|
||||
regulator-name = "ldousb";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
regen1: regen1 {
|
||||
/* VDD_3V3_ON */
|
||||
regulator-name = "regen1";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
tps659038_rtc: tps659038_rtc {
|
||||
compatible = "ti,palmas-rtc";
|
||||
interrupt-parent = <&tps659038>;
|
||||
interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
|
||||
wakeup-source;
|
||||
};
|
||||
|
||||
tps659038_pwr_button: tps659038_pwr_button {
|
||||
compatible = "ti,palmas-pwrbutton";
|
||||
interrupt-parent = <&tps659038>;
|
||||
interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
|
||||
wakeup-source;
|
||||
ti,palmas-long-press-seconds = <12>;
|
||||
};
|
||||
|
||||
tps659038_gpio: tps659038_gpio {
|
||||
compatible = "ti,palmas-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
tmp102: tmp102@48 {
|
||||
compatible = "ti,tmp102";
|
||||
reg = <0x48>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&tmp102_pins_default>;
|
||||
interrupt-parent = <&gpio7>;
|
||||
interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c3_pins_default>;
|
||||
clock-frequency = <400000>;
|
||||
|
||||
mcp_rtc: rtc@6f {
|
||||
compatible = "microchip,mcp7941x";
|
||||
reg = <0x6f>;
|
||||
interrupts = <GIC_SPI 2 IRQ_TYPE_EDGE_RISING>; /* IRQ_SYS_1N */
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcp79410_pins_default>;
|
||||
|
||||
vcc-supply = <&vdd_3v3>;
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
&gpio7 {
|
||||
ti,no-reset-on-init;
|
||||
ti,no-idle-on-init;
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu0-supply = <&smps12_reg>;
|
||||
voltage-tolerance = <1>;
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
status = "okay";
|
||||
interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&dra7_pmx_core 0x3f8>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart3_pins_default>;
|
||||
};
|
||||
|
||||
&mac {
|
||||
status = "okay";
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&cpsw_pins_default>;
|
||||
pinctrl-1 = <&cpsw_pins_sleep>;
|
||||
dual_emac;
|
||||
};
|
||||
|
||||
&cpsw_emac0 {
|
||||
phy_id = <&davinci_mdio>, <1>;
|
||||
phy-mode = "rgmii";
|
||||
dual_emac_res_vlan = <1>;
|
||||
};
|
||||
|
||||
&cpsw_emac1 {
|
||||
phy_id = <&davinci_mdio>, <2>;
|
||||
phy-mode = "rgmii";
|
||||
dual_emac_res_vlan = <2>;
|
||||
};
|
||||
|
||||
&davinci_mdio {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&davinci_mdio_pins_default>;
|
||||
pinctrl-1 = <&davinci_mdio_pins_sleep>;
|
||||
};
|
||||
|
||||
&mmc1 {
|
||||
status = "okay";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mmc1_pins_default>;
|
||||
|
||||
vmmc-supply = <&ldo1_reg>;
|
||||
vmmc_aux-supply = <&vdd_3v3>;
|
||||
pbias-supply = <&pbias_mmc_reg>;
|
||||
bus-width = <4>;
|
||||
cd-gpios = <&gpio6 27 0>; /* gpio 219 */
|
||||
};
|
||||
|
||||
&mmc2 {
|
||||
status = "okay";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mmc2_pins_default>;
|
||||
|
||||
vmmc-supply = <&vdd_3v3>;
|
||||
bus-width = <8>;
|
||||
ti,non-removable;
|
||||
cap-mmc-dual-data-rate;
|
||||
};
|
||||
|
||||
&sata {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2_phy1 {
|
||||
phy-supply = <&ldousb_reg>;
|
||||
};
|
||||
|
||||
&usb2_phy2 {
|
||||
phy-supply = <&ldousb_reg>;
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
dr_mode = "host";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usb1_pins>;
|
||||
};
|
||||
|
||||
&omap_dwc3_1 {
|
||||
extcon = <&extcon_usb1>;
|
||||
};
|
||||
|
||||
&omap_dwc3_2 {
|
||||
extcon = <&extcon_usb2>;
|
||||
};
|
||||
|
||||
&usb2 {
|
||||
dr_mode = "peripheral";
|
||||
};
|
||||
|
||||
&cpu_trips {
|
||||
cpu_alert1: cpu_alert1 {
|
||||
temperature = <50000>; /* millicelsius */
|
||||
hysteresis = <2000>; /* millicelsius */
|
||||
type = "active";
|
||||
};
|
||||
};
|
||||
|
||||
&cpu_cooling_maps {
|
||||
map1 {
|
||||
trip = <&cpu_alert1>;
|
||||
cooling-device = <&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
|
||||
&thermal_zones {
|
||||
board_thermal: board_thermal {
|
||||
polling-delay-passive = <1250>; /* milliseconds */
|
||||
polling-delay = <1500>; /* milliseconds */
|
||||
|
||||
/* sensor ID */
|
||||
thermal-sensors = <&tmp102 0>;
|
||||
|
||||
board_trips: trips {
|
||||
board_alert0: board_alert {
|
||||
temperature = <40000>; /* millicelsius */
|
||||
hysteresis = <2000>; /* millicelsius */
|
||||
type = "active";
|
||||
};
|
||||
|
||||
board_crit: board_crit {
|
||||
temperature = <105000>; /* millicelsius */
|
||||
hysteresis = <0>; /* millicelsius */
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
|
||||
board_cooling_maps: cooling-maps {
|
||||
map0 {
|
||||
trip = <&board_alert0>;
|
||||
cooling-device =
|
||||
<&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dss {
|
||||
status = "ok";
|
||||
|
||||
vdda_video-supply = <&ldoln_reg>;
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
status = "ok";
|
||||
vdda-supply = <&ldo3_reg>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hdmi_pins>;
|
||||
|
||||
port {
|
||||
hdmi_out: endpoint {
|
||||
remote-endpoint = <&tpd12s015_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
333
arch/arm/dts/armada-370-xp.dtsi
Normal file
333
arch/arm/dts/armada-370-xp.dtsi
Normal file
|
|
@ -0,0 +1,333 @@
|
|||
/*
|
||||
* Device Tree Include file for Marvell Armada 370 and Armada XP SoC
|
||||
*
|
||||
* Copyright (C) 2012 Marvell
|
||||
*
|
||||
* Lior Amsalem <alior@marvell.com>
|
||||
* Gregory CLEMENT <gregory.clement@free-electrons.com>
|
||||
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
* Ben Dooks <ben.dooks@codethink.co.uk>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* This file contains the definitions that are common to the Armada
|
||||
* 370 and Armada XP SoC.
|
||||
*/
|
||||
|
||||
/include/ "skeleton64.dtsi"
|
||||
|
||||
#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada 370 and XP SoC";
|
||||
compatible = "marvell,armada-370-xp";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cpu@0 {
|
||||
compatible = "marvell,sheeva-v7";
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,cortex-a9-pmu";
|
||||
interrupts-extended = <&mpic 3>;
|
||||
};
|
||||
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
controller = <&mbusc>;
|
||||
interrupt-parent = <&mpic>;
|
||||
pcie-mem-aperture = <0xf8000000 0x7e00000>;
|
||||
pcie-io-aperture = <0xffe00000 0x100000>;
|
||||
|
||||
devbus-bootcs {
|
||||
compatible = "marvell,mvebu-devbus";
|
||||
reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
|
||||
ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
devbus-cs0 {
|
||||
compatible = "marvell,mvebu-devbus";
|
||||
reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
|
||||
ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
devbus-cs1 {
|
||||
compatible = "marvell,mvebu-devbus";
|
||||
reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
|
||||
ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
devbus-cs2 {
|
||||
compatible = "marvell,mvebu-devbus";
|
||||
reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
|
||||
ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
devbus-cs3 {
|
||||
compatible = "marvell,mvebu-devbus";
|
||||
reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
|
||||
ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
internal-regs {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
|
||||
|
||||
rtc@10300 {
|
||||
compatible = "marvell,orion-rtc";
|
||||
reg = <0x10300 0x20>;
|
||||
interrupts = <50>;
|
||||
};
|
||||
|
||||
spi0: spi@10600 {
|
||||
reg = <0x10600 0x28>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
interrupts = <30>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi1: spi@10680 {
|
||||
reg = <0x10680 0x28>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
interrupts = <92>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@11000 {
|
||||
compatible = "marvell,mv64xxx-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <31>;
|
||||
timeout-ms = <1000>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@11100 {
|
||||
compatible = "marvell,mv64xxx-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <32>;
|
||||
timeout-ms = <1000>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart0: serial@12000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x12000 0x100>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <41>;
|
||||
reg-io-width = <1>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@12100 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x12100 0x100>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <42>;
|
||||
reg-io-width = <1>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pinctrl: pin-ctrl@18000 {
|
||||
reg = <0x18000 0x38>;
|
||||
};
|
||||
|
||||
coredivclk: corediv-clock@18740 {
|
||||
compatible = "marvell,armada-370-corediv-clock";
|
||||
reg = <0x18740 0xc>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&mainpll>;
|
||||
clock-output-names = "nand";
|
||||
};
|
||||
|
||||
mbusc: mbus-controller@20000 {
|
||||
compatible = "marvell,mbus-controller";
|
||||
reg = <0x20000 0x100>, <0x20180 0x20>,
|
||||
<0x20250 0x8>;
|
||||
};
|
||||
|
||||
mpic: interrupt-controller@20a00 {
|
||||
compatible = "marvell,mpic";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupt-controller;
|
||||
msi-controller;
|
||||
};
|
||||
|
||||
coherency-fabric@20200 {
|
||||
compatible = "marvell,coherency-fabric";
|
||||
reg = <0x20200 0xb0>, <0x21010 0x1c>;
|
||||
};
|
||||
|
||||
timer@20300 {
|
||||
reg = <0x20300 0x30>, <0x21040 0x30>;
|
||||
interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
|
||||
};
|
||||
|
||||
watchdog@20300 {
|
||||
reg = <0x20300 0x34>, <0x20704 0x4>;
|
||||
};
|
||||
|
||||
pmsu@22000 {
|
||||
compatible = "marvell,armada-370-pmsu";
|
||||
reg = <0x22000 0x1000>;
|
||||
};
|
||||
|
||||
usb@50000 {
|
||||
compatible = "marvell,orion-ehci";
|
||||
reg = <0x50000 0x500>;
|
||||
interrupts = <45>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb@51000 {
|
||||
compatible = "marvell,orion-ehci";
|
||||
reg = <0x51000 0x500>;
|
||||
interrupts = <46>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
eth0: ethernet@70000 {
|
||||
reg = <0x70000 0x4000>;
|
||||
interrupts = <8>;
|
||||
clocks = <&gateclk 4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mdio: mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "marvell,orion-mdio";
|
||||
reg = <0x72004 0x4>;
|
||||
clocks = <&gateclk 4>;
|
||||
};
|
||||
|
||||
eth1: ethernet@74000 {
|
||||
reg = <0x74000 0x4000>;
|
||||
interrupts = <10>;
|
||||
clocks = <&gateclk 3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sata@a0000 {
|
||||
compatible = "marvell,armada-370-sata";
|
||||
reg = <0xa0000 0x5000>;
|
||||
interrupts = <55>;
|
||||
clocks = <&gateclk 15>, <&gateclk 30>;
|
||||
clock-names = "0", "1";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
nand@d0000 {
|
||||
compatible = "marvell,armada370-nand";
|
||||
reg = <0xd0000 0x54>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupts = <113>;
|
||||
clocks = <&coredivclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mvsdio@d4000 {
|
||||
compatible = "marvell,orion-sdio";
|
||||
reg = <0xd4000 0x200>;
|
||||
interrupts = <54>;
|
||||
clocks = <&gateclk 17>;
|
||||
bus-width = <4>;
|
||||
cap-sdio-irq;
|
||||
cap-sd-highspeed;
|
||||
cap-mmc-highspeed;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
clocks {
|
||||
/* 2 GHz fixed main PLL */
|
||||
mainpll: mainpll {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <2000000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
152
arch/arm/dts/armada-380.dtsi
Normal file
152
arch/arm/dts/armada-380.dtsi
Normal file
|
|
@ -0,0 +1,152 @@
|
|||
/*
|
||||
* Device Tree Include file for Marvell Armada 380 SoC.
|
||||
*
|
||||
* Copyright (C) 2014 Marvell
|
||||
*
|
||||
* Lior Amsalem <alior@marvell.com>
|
||||
* Gregory CLEMENT <gregory.clement@free-electrons.com>
|
||||
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include "armada-38x.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada 380 family SoC";
|
||||
compatible = "marvell,armada380";
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
enable-method = "marvell,armada-380-smp";
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
internal-regs {
|
||||
pinctrl@18000 {
|
||||
compatible = "marvell,mv88f6810-pinctrl";
|
||||
};
|
||||
};
|
||||
|
||||
pcie-controller {
|
||||
compatible = "marvell,armada-370-pcie";
|
||||
status = "disabled";
|
||||
device_type = "pci";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
msi-parent = <&mpic>;
|
||||
bus-range = <0x00 0xff>;
|
||||
|
||||
ranges =
|
||||
<0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
|
||||
0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
|
||||
0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
|
||||
0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
|
||||
0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
|
||||
0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */
|
||||
0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
|
||||
0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */
|
||||
0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
|
||||
0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */>;
|
||||
|
||||
/* x1 port */
|
||||
pcie@1,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
|
||||
reg = <0x0800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x1 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 8>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* x1 port */
|
||||
pcie@2,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
|
||||
reg = <0x1000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x2 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
||||
marvell,pcie-port = <1>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 5>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* x1 port */
|
||||
pcie@3,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
|
||||
reg = <0x1800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x3 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
|
||||
marvell,pcie-port = <2>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 6>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
184
arch/arm/dts/armada-385.dtsi
Normal file
184
arch/arm/dts/armada-385.dtsi
Normal file
|
|
@ -0,0 +1,184 @@
|
|||
/*
|
||||
* Device Tree Include file for Marvell Armada 385 SoC.
|
||||
*
|
||||
* Copyright (C) 2014 Marvell
|
||||
*
|
||||
* Lior Amsalem <alior@marvell.com>
|
||||
* Gregory CLEMENT <gregory.clement@free-electrons.com>
|
||||
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include "armada-38x.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada 385 family SoC";
|
||||
compatible = "marvell,armada385", "marvell,armada380";
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
enable-method = "marvell,armada-380-smp";
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <0>;
|
||||
};
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
internal-regs {
|
||||
pinctrl@18000 {
|
||||
compatible = "marvell,mv88f6820-pinctrl";
|
||||
};
|
||||
};
|
||||
|
||||
pcie-controller {
|
||||
compatible = "marvell,armada-370-pcie";
|
||||
status = "disabled";
|
||||
device_type = "pci";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
msi-parent = <&mpic>;
|
||||
bus-range = <0x00 0xff>;
|
||||
|
||||
ranges =
|
||||
<0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
|
||||
0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
|
||||
0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
|
||||
0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
|
||||
0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
|
||||
0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */
|
||||
0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
|
||||
0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */
|
||||
0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
|
||||
0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */
|
||||
0x82000000 0x4 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */
|
||||
0x81000000 0x4 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO */>;
|
||||
|
||||
/*
|
||||
* This port can be either x4 or x1. When
|
||||
* configured in x4 by the bootloader, then
|
||||
* pcie@4,0 is not available.
|
||||
*/
|
||||
pcie@1,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
|
||||
reg = <0x0800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x1 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 8>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* x1 port */
|
||||
pcie@2,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
|
||||
reg = <0x1000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x2 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
||||
marvell,pcie-port = <1>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 5>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* x1 port */
|
||||
pcie@3,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
|
||||
reg = <0x1800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x3 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
|
||||
marvell,pcie-port = <2>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 6>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/*
|
||||
* x1 port only available when pcie@1,0 is
|
||||
* configured as a x1 port
|
||||
*/
|
||||
pcie@4,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
|
||||
reg = <0x2000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x4 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
||||
marvell,pcie-port = <3>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 7>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
413
arch/arm/dts/armada-388-gp.dts
Normal file
413
arch/arm/dts/armada-388-gp.dts
Normal file
|
|
@ -0,0 +1,413 @@
|
|||
/*
|
||||
* Device Tree file for Marvell Armada 385 development board
|
||||
* (RD-88F6820-GP)
|
||||
*
|
||||
* Copyright (C) 2014 Marvell
|
||||
*
|
||||
* Gregory CLEMENT <gregory.clement@free-electrons.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without
|
||||
* any warranty of any kind, whether express or implied.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "armada-388.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada 385 GP";
|
||||
compatible = "marvell,a385-gp", "marvell,armada388", "marvell,armada380";
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x80000000>; /* 2 GB */
|
||||
};
|
||||
|
||||
soc {
|
||||
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
|
||||
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
|
||||
|
||||
internal-regs {
|
||||
spi@10600 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi0_pins>;
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "st,m25p128", "jedec,spi-nor";
|
||||
reg = <0>; /* Chip select 0 */
|
||||
spi-max-frequency = <50000000>;
|
||||
m25p,fast-read;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@11000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c0_pins>;
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
/*
|
||||
* The EEPROM located at adresse 54 is needed
|
||||
* for the boot - DO NOT ERASE IT -
|
||||
*/
|
||||
|
||||
expander0: pca9555@20 {
|
||||
compatible = "nxp,pca9555";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pca0_pins>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x20>;
|
||||
};
|
||||
|
||||
expander1: pca9555@21 {
|
||||
compatible = "nxp,pca9555";
|
||||
pinctrl-names = "default";
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x21>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
serial@12000 {
|
||||
/*
|
||||
* Exported on the micro USB connector CON16
|
||||
* through an FTDI
|
||||
*/
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* GE1 CON15 */
|
||||
ethernet@30000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ge1_rgmii_pins>;
|
||||
status = "okay";
|
||||
phy = <&phy1>;
|
||||
phy-mode = "rgmii-id";
|
||||
};
|
||||
|
||||
/* CON4 */
|
||||
usb@58000 {
|
||||
vcc-supply = <®_usb2_0_vbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* GE0 CON1 */
|
||||
ethernet@70000 {
|
||||
pinctrl-names = "default";
|
||||
/*
|
||||
* The Reference Clock 0 is used to provide a
|
||||
* clock to the PHY
|
||||
*/
|
||||
pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>;
|
||||
status = "okay";
|
||||
phy = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
};
|
||||
|
||||
|
||||
mdio@72004 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mdio_pins>;
|
||||
|
||||
phy0: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
|
||||
phy1: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
sata@a8000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sata0_pins>, <&sata1_pins>;
|
||||
status = "okay";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
sata0: sata-port@0 {
|
||||
reg = <0>;
|
||||
target-supply = <®_5v_sata0>;
|
||||
};
|
||||
|
||||
sata1: sata-port@1 {
|
||||
reg = <1>;
|
||||
target-supply = <®_5v_sata1>;
|
||||
};
|
||||
};
|
||||
|
||||
sata@e0000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sata2_pins>, <&sata3_pins>;
|
||||
status = "okay";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
sata2: sata-port@0 {
|
||||
reg = <0>;
|
||||
target-supply = <®_5v_sata2>;
|
||||
};
|
||||
|
||||
sata3: sata-port@1 {
|
||||
reg = <1>;
|
||||
target-supply = <®_5v_sata3>;
|
||||
};
|
||||
};
|
||||
|
||||
sdhci@d8000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdhci_pins>;
|
||||
cd-gpios = <&expander0 5 GPIO_ACTIVE_LOW>;
|
||||
no-1-8-v;
|
||||
wp-inverted;
|
||||
bus-width = <8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* CON5 */
|
||||
usb3@f0000 {
|
||||
vcc-supply = <®_usb2_1_vbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* CON7 */
|
||||
usb3@f8000 {
|
||||
vcc-supply = <®_usb3_vbus>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
pcie-controller {
|
||||
status = "okay";
|
||||
/*
|
||||
* One PCIe units is accessible through
|
||||
* standard PCIe slot on the board.
|
||||
*/
|
||||
pcie@1,0 {
|
||||
/* Port 0, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/*
|
||||
* The two other PCIe units are accessible
|
||||
* through mini PCIe slot on the board.
|
||||
*/
|
||||
pcie@2,0 {
|
||||
/* Port 1, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
pcie@3,0 {
|
||||
/* Port 2, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
gpio-fan {
|
||||
compatible = "gpio-fan";
|
||||
gpios = <&expander1 3 GPIO_ACTIVE_HIGH>;
|
||||
gpio-fan,speed-map = < 0 0
|
||||
3000 1>;
|
||||
};
|
||||
};
|
||||
|
||||
reg_usb3_vbus: usb3-vbus {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "usb3-vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
gpio = <&expander1 15 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
reg_usb2_0_vbus: v5-vbus0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "v5.0-vbus0";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
gpio = <&expander1 14 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
reg_usb2_1_vbus: v5-vbus1 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "v5.0-vbus1";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
gpio = <&expander0 4 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
reg_usb2_1_vbus: v5-vbus1 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "v5.0-vbus1";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
gpio = <&expander0 4 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
reg_sata0: pwr-sata0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "pwr_en_sata0";
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
|
||||
};
|
||||
|
||||
reg_5v_sata0: v5-sata0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "v5.0-sata0";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
vin-supply = <®_sata0>;
|
||||
};
|
||||
|
||||
reg_12v_sata0: v12-sata0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "v12.0-sata0";
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
regulator-always-on;
|
||||
vin-supply = <®_sata0>;
|
||||
};
|
||||
|
||||
reg_sata1: pwr-sata1 {
|
||||
regulator-name = "pwr_en_sata1";
|
||||
compatible = "regulator-fixed";
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
gpio = <&expander0 3 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
reg_5v_sata1: v5-sata1 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "v5.0-sata1";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
vin-supply = <®_sata1>;
|
||||
};
|
||||
|
||||
reg_12v_sata1: v12-sata1 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "v12.0-sata1";
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
regulator-always-on;
|
||||
vin-supply = <®_sata1>;
|
||||
};
|
||||
|
||||
reg_sata2: pwr-sata2 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "pwr_en_sata2";
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
gpio = <&expander0 11 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
reg_5v_sata2: v5-sata2 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "v5.0-sata2";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
vin-supply = <®_sata2>;
|
||||
};
|
||||
|
||||
reg_12v_sata2: v12-sata2 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "v12.0-sata2";
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
regulator-always-on;
|
||||
vin-supply = <®_sata2>;
|
||||
};
|
||||
|
||||
reg_sata3: pwr-sata3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "pwr_en_sata3";
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
gpio = <&expander0 12 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
reg_5v_sata3: v5-sata3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "v5.0-sata3";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
vin-supply = <®_sata3>;
|
||||
};
|
||||
|
||||
reg_12v_sata3: v12-sata3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "v12.0-sata3";
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
regulator-always-on;
|
||||
vin-supply = <®_sata3>;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
pca0_pins: pca0_pins {
|
||||
marvell,pins = "mpp18";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
};
|
||||
|
|
@ -1,21 +1,18 @@
|
|||
/*
|
||||
* Copyright 2015 Vishnu Patekar
|
||||
* Vishnu Patekar <vishnupatekar0510@gmail.com>
|
||||
* Device Tree Include file for Marvell Armada 388 SoC.
|
||||
*
|
||||
* Copyright (C) 2015 Marvell
|
||||
*
|
||||
* Gregory CLEMENT <gregory.clement@free-electrons.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
* a) This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without
|
||||
* any warranty of any kind, whether express or implied.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
|
|
@ -39,50 +36,35 @@
|
|||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*
|
||||
* The main difference with the Armada 385 is that the 388 can handle two more
|
||||
* SATA ports. So we can reuse the dtsi of the Armada 385, override the pinctrl
|
||||
* property and the name of the SoC, and add the second SATA host which control
|
||||
* the 2 other ports.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "sun8i-a33.dtsi"
|
||||
#include "sunxi-common-regulators.dtsi"
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/pinctrl/sun4i-a10.h>
|
||||
#include "armada-385.dtsi"
|
||||
|
||||
/ {
|
||||
model = "ET Q8 Quad Core Tablet (v1.6)";
|
||||
compatible = "et,q8-v1.6", "allwinner,sun8i-a33";
|
||||
model = "Marvell Armada 388 family SoC";
|
||||
compatible = "marvell,armada388", "marvell,armada385",
|
||||
"marvell,armada380";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
};
|
||||
soc {
|
||||
internal-regs {
|
||||
pinctrl@18000 {
|
||||
compatible = "marvell,mv88f6828-pinctrl";
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
sata@e0000 {
|
||||
compatible = "marvell,armada-380-ahci";
|
||||
reg = <0xe0000 0x2000>;
|
||||
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gateclk 30>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&lradc {
|
||||
vref-supply = <®_vcc3v0>;
|
||||
status = "okay";
|
||||
|
||||
button@200 {
|
||||
label = "Volume Up";
|
||||
linux,code = <KEY_VOLUMEUP>;
|
||||
channel = <0>;
|
||||
voltage = <200000>;
|
||||
};
|
||||
|
||||
button@400 {
|
||||
label = "Volume Down";
|
||||
linux,code = <KEY_VOLUMEDOWN>;
|
||||
channel = <0>;
|
||||
voltage = <400000>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_pins_a>;
|
||||
status = "okay";
|
||||
};
|
||||
600
arch/arm/dts/armada-38x.dtsi
Normal file
600
arch/arm/dts/armada-38x.dtsi
Normal file
|
|
@ -0,0 +1,600 @@
|
|||
/*
|
||||
* Device Tree Include file for Marvell Armada 38x family of SoCs.
|
||||
*
|
||||
* Copyright (C) 2014 Marvell
|
||||
*
|
||||
* Lior Amsalem <alior@marvell.com>
|
||||
* Gregory CLEMENT <gregory.clement@free-electrons.com>
|
||||
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include "skeleton.dtsi"
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada 38x family SoC";
|
||||
compatible = "marvell,armada380";
|
||||
|
||||
aliases {
|
||||
gpio0 = &gpio0;
|
||||
gpio1 = &gpio1;
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,cortex-a9-pmu";
|
||||
interrupts-extended = <&mpic 3>;
|
||||
};
|
||||
|
||||
soc {
|
||||
compatible = "marvell,armada380-mbus", "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
controller = <&mbusc>;
|
||||
interrupt-parent = <&gic>;
|
||||
pcie-mem-aperture = <0xe0000000 0x8000000>;
|
||||
pcie-io-aperture = <0xe8000000 0x100000>;
|
||||
|
||||
bootrom {
|
||||
compatible = "marvell,bootrom";
|
||||
reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
|
||||
};
|
||||
|
||||
devbus-bootcs {
|
||||
compatible = "marvell,mvebu-devbus";
|
||||
reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
|
||||
ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
devbus-cs0 {
|
||||
compatible = "marvell,mvebu-devbus";
|
||||
reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
|
||||
ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
devbus-cs1 {
|
||||
compatible = "marvell,mvebu-devbus";
|
||||
reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
|
||||
ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
devbus-cs2 {
|
||||
compatible = "marvell,mvebu-devbus";
|
||||
reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
|
||||
ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
devbus-cs3 {
|
||||
compatible = "marvell,mvebu-devbus";
|
||||
reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
|
||||
ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
internal-regs {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
|
||||
|
||||
L2: cache-controller@8000 {
|
||||
compatible = "arm,pl310-cache";
|
||||
reg = <0x8000 0x1000>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
scu@c000 {
|
||||
compatible = "arm,cortex-a9-scu";
|
||||
reg = <0xc000 0x58>;
|
||||
};
|
||||
|
||||
timer@c600 {
|
||||
compatible = "arm,cortex-a9-twd-timer";
|
||||
reg = <0xc600 0x20>;
|
||||
interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
|
||||
clocks = <&coreclk 2>;
|
||||
};
|
||||
|
||||
gic: interrupt-controller@d000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
#interrupt-cells = <3>;
|
||||
#size-cells = <0>;
|
||||
interrupt-controller;
|
||||
reg = <0xd000 0x1000>,
|
||||
<0xc100 0x100>;
|
||||
};
|
||||
|
||||
spi0: spi@10600 {
|
||||
compatible = "marvell,armada-380-spi",
|
||||
"marvell,orion-spi";
|
||||
reg = <0x10600 0x50>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi1: spi@10680 {
|
||||
compatible = "marvell,armada-380-spi",
|
||||
"marvell,orion-spi";
|
||||
reg = <0x10680 0x50>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@11000 {
|
||||
compatible = "marvell,mv64xxx-i2c";
|
||||
reg = <0x11000 0x20>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
||||
timeout-ms = <1000>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@11100 {
|
||||
compatible = "marvell,mv64xxx-i2c";
|
||||
reg = <0x11100 0x20>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
||||
timeout-ms = <1000>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart0: serial@12000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x12000 0x100>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-io-width = <1>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@12100 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x12100 0x100>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-io-width = <1>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pinctrl: pinctrl@18000 {
|
||||
reg = <0x18000 0x20>;
|
||||
|
||||
ge0_rgmii_pins: ge-rgmii-pins-0 {
|
||||
marvell,pins = "mpp6", "mpp7", "mpp8",
|
||||
"mpp9", "mpp10", "mpp11",
|
||||
"mpp12", "mpp13", "mpp14",
|
||||
"mpp15", "mpp16", "mpp17";
|
||||
marvell,function = "ge0";
|
||||
};
|
||||
|
||||
ge1_rgmii_pins: ge-rgmii-pins-1 {
|
||||
marvell,pins = "mpp21", "mpp27", "mpp28",
|
||||
"mpp29", "mpp30", "mpp31",
|
||||
"mpp32", "mpp37", "mpp38",
|
||||
"mpp39", "mpp40", "mpp41";
|
||||
marvell,function = "ge1";
|
||||
};
|
||||
|
||||
i2c0_pins: i2c-pins-0 {
|
||||
marvell,pins = "mpp2", "mpp3";
|
||||
marvell,function = "i2c0";
|
||||
};
|
||||
|
||||
mdio_pins: mdio-pins {
|
||||
marvell,pins = "mpp4", "mpp5";
|
||||
marvell,function = "ge";
|
||||
};
|
||||
|
||||
ref_clk0_pins: ref-clk-pins-0 {
|
||||
marvell,pins = "mpp45";
|
||||
marvell,function = "ref";
|
||||
};
|
||||
|
||||
ref_clk1_pins: ref-clk-pins-1 {
|
||||
marvell,pins = "mpp46";
|
||||
marvell,function = "ref";
|
||||
};
|
||||
|
||||
spi0_pins: spi-pins-0 {
|
||||
marvell,pins = "mpp22", "mpp23", "mpp24",
|
||||
"mpp25";
|
||||
marvell,function = "spi0";
|
||||
};
|
||||
|
||||
spi1_pins: spi-pins-1 {
|
||||
marvell,pins = "mpp56", "mpp57", "mpp58",
|
||||
"mpp59";
|
||||
marvell,function = "spi1";
|
||||
};
|
||||
|
||||
uart0_pins: uart-pins-0 {
|
||||
marvell,pins = "mpp0", "mpp1";
|
||||
marvell,function = "ua0";
|
||||
};
|
||||
|
||||
uart1_pins: uart-pins-1 {
|
||||
marvell,pins = "mpp19", "mpp20";
|
||||
marvell,function = "ua1";
|
||||
};
|
||||
|
||||
sdhci_pins: sdhci-pins {
|
||||
marvell,pins = "mpp48", "mpp49", "mpp50",
|
||||
"mpp52", "mpp53", "mpp54",
|
||||
"mpp55", "mpp57", "mpp58",
|
||||
"mpp59";
|
||||
marvell,function = "sd0";
|
||||
};
|
||||
|
||||
sata0_pins: sata-pins-0 {
|
||||
marvell,pins = "mpp20";
|
||||
marvell,function = "sata0";
|
||||
};
|
||||
|
||||
sata1_pins: sata-pins-1 {
|
||||
marvell,pins = "mpp19";
|
||||
marvell,function = "sata1";
|
||||
};
|
||||
|
||||
sata2_pins: sata-pins-2 {
|
||||
marvell,pins = "mpp47";
|
||||
marvell,function = "sata2";
|
||||
};
|
||||
|
||||
sata3_pins: sata-pins-3 {
|
||||
marvell,pins = "mpp44";
|
||||
marvell,function = "sata3";
|
||||
};
|
||||
};
|
||||
|
||||
gpio0: gpio@18100 {
|
||||
compatible = "marvell,orion-gpio";
|
||||
reg = <0x18100 0x40>;
|
||||
ngpios = <32>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
gpio1: gpio@18140 {
|
||||
compatible = "marvell,orion-gpio";
|
||||
reg = <0x18140 0x40>;
|
||||
ngpios = <28>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
system-controller@18200 {
|
||||
compatible = "marvell,armada-380-system-controller",
|
||||
"marvell,armada-370-xp-system-controller";
|
||||
reg = <0x18200 0x100>;
|
||||
};
|
||||
|
||||
gateclk: clock-gating-control@18220 {
|
||||
compatible = "marvell,armada-380-gating-clock";
|
||||
reg = <0x18220 0x4>;
|
||||
clocks = <&coreclk 0>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
coreclk: mvebu-sar@18600 {
|
||||
compatible = "marvell,armada-380-core-clock";
|
||||
reg = <0x18600 0x04>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
mbusc: mbus-controller@20000 {
|
||||
compatible = "marvell,mbus-controller";
|
||||
reg = <0x20000 0x100>, <0x20180 0x20>;
|
||||
};
|
||||
|
||||
mpic: interrupt-controller@20a00 {
|
||||
compatible = "marvell,mpic";
|
||||
reg = <0x20a00 0x2d0>, <0x21070 0x58>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupt-controller;
|
||||
msi-controller;
|
||||
interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
timer@20300 {
|
||||
compatible = "marvell,armada-380-timer",
|
||||
"marvell,armada-xp-timer";
|
||||
reg = <0x20300 0x30>, <0x21040 0x30>;
|
||||
interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&mpic 5>,
|
||||
<&mpic 6>;
|
||||
clocks = <&coreclk 2>, <&refclk>;
|
||||
clock-names = "nbclk", "fixed";
|
||||
};
|
||||
|
||||
watchdog@20300 {
|
||||
compatible = "marvell,armada-380-wdt";
|
||||
reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>;
|
||||
clocks = <&coreclk 2>, <&refclk>;
|
||||
clock-names = "nbclk", "fixed";
|
||||
};
|
||||
|
||||
cpurst@20800 {
|
||||
compatible = "marvell,armada-370-cpu-reset";
|
||||
reg = <0x20800 0x10>;
|
||||
};
|
||||
|
||||
mpcore-soc-ctrl@20d20 {
|
||||
compatible = "marvell,armada-380-mpcore-soc-ctrl";
|
||||
reg = <0x20d20 0x6c>;
|
||||
};
|
||||
|
||||
coherency-fabric@21010 {
|
||||
compatible = "marvell,armada-380-coherency-fabric";
|
||||
reg = <0x21010 0x1c>;
|
||||
};
|
||||
|
||||
pmsu@22000 {
|
||||
compatible = "marvell,armada-380-pmsu";
|
||||
reg = <0x22000 0x1000>;
|
||||
};
|
||||
|
||||
eth1: ethernet@30000 {
|
||||
compatible = "marvell,armada-370-neta";
|
||||
reg = <0x30000 0x4000>;
|
||||
interrupts-extended = <&mpic 10>;
|
||||
clocks = <&gateclk 3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
eth2: ethernet@34000 {
|
||||
compatible = "marvell,armada-370-neta";
|
||||
reg = <0x34000 0x4000>;
|
||||
interrupts-extended = <&mpic 12>;
|
||||
clocks = <&gateclk 2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb@58000 {
|
||||
compatible = "marvell,orion-ehci";
|
||||
reg = <0x58000 0x500>;
|
||||
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gateclk 18>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
xor@60800 {
|
||||
compatible = "marvell,orion-xor";
|
||||
reg = <0x60800 0x100
|
||||
0x60a00 0x100>;
|
||||
clocks = <&gateclk 22>;
|
||||
status = "okay";
|
||||
|
||||
xor00 {
|
||||
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmacap,memcpy;
|
||||
dmacap,xor;
|
||||
};
|
||||
xor01 {
|
||||
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmacap,memcpy;
|
||||
dmacap,xor;
|
||||
dmacap,memset;
|
||||
};
|
||||
};
|
||||
|
||||
xor@60900 {
|
||||
compatible = "marvell,orion-xor";
|
||||
reg = <0x60900 0x100
|
||||
0x60b00 0x100>;
|
||||
clocks = <&gateclk 28>;
|
||||
status = "okay";
|
||||
|
||||
xor10 {
|
||||
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmacap,memcpy;
|
||||
dmacap,xor;
|
||||
};
|
||||
xor11 {
|
||||
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmacap,memcpy;
|
||||
dmacap,xor;
|
||||
dmacap,memset;
|
||||
};
|
||||
};
|
||||
|
||||
eth0: ethernet@70000 {
|
||||
compatible = "marvell,armada-370-neta";
|
||||
reg = <0x70000 0x4000>;
|
||||
interrupts-extended = <&mpic 8>;
|
||||
clocks = <&gateclk 4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mdio: mdio@72004 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "marvell,orion-mdio";
|
||||
reg = <0x72004 0x4>;
|
||||
clocks = <&gateclk 4>;
|
||||
};
|
||||
|
||||
rtc@a3800 {
|
||||
compatible = "marvell,armada-380-rtc";
|
||||
reg = <0xa3800 0x20>, <0x184a0 0x0c>;
|
||||
reg-names = "rtc", "rtc-soc";
|
||||
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
sata@a8000 {
|
||||
compatible = "marvell,armada-380-ahci";
|
||||
reg = <0xa8000 0x2000>;
|
||||
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gateclk 15>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sata@e0000 {
|
||||
compatible = "marvell,armada-380-ahci";
|
||||
reg = <0xe0000 0x2000>;
|
||||
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gateclk 30>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
coredivclk: clock@e4250 {
|
||||
compatible = "marvell,armada-380-corediv-clock";
|
||||
reg = <0xe4250 0xc>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&mainpll>;
|
||||
clock-output-names = "nand";
|
||||
};
|
||||
|
||||
thermal@e8078 {
|
||||
compatible = "marvell,armada380-thermal";
|
||||
reg = <0xe4078 0x4>, <0xe4074 0x4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
flash@d0000 {
|
||||
compatible = "marvell,armada370-nand";
|
||||
reg = <0xd0000 0x54>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&coredivclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhci@d8000 {
|
||||
compatible = "marvell,armada-380-sdhci";
|
||||
reg-names = "sdhci", "mbus", "conf-sdio3";
|
||||
reg = <0xd8000 0x1000>,
|
||||
<0xdc000 0x100>,
|
||||
<0x18454 0x4>;
|
||||
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gateclk 17>;
|
||||
mrvl,clk-delay-cycles = <0x1F>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb3@f0000 {
|
||||
compatible = "marvell,armada-380-xhci";
|
||||
reg = <0xf0000 0x4000>,<0xf4000 0x4000>;
|
||||
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gateclk 9>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb3@f8000 {
|
||||
compatible = "marvell,armada-380-xhci";
|
||||
reg = <0xf8000 0x4000>,<0xfc000 0x4000>;
|
||||
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gateclk 10>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
clocks {
|
||||
/* 2 GHz fixed main PLL */
|
||||
mainpll: mainpll {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <1000000000>;
|
||||
};
|
||||
|
||||
/* 25 MHz reference crystal */
|
||||
refclk: oscillator {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
245
arch/arm/dts/armada-xp-gp.dts
Normal file
245
arch/arm/dts/armada-xp-gp.dts
Normal file
|
|
@ -0,0 +1,245 @@
|
|||
/*
|
||||
* Device Tree file for Marvell Armada XP development board
|
||||
* (DB-MV784MP-GP)
|
||||
*
|
||||
* Copyright (C) 2013-2014 Marvell
|
||||
*
|
||||
* Lior Amsalem <alior@marvell.com>
|
||||
* Gregory CLEMENT <gregory.clement@free-electrons.com>
|
||||
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Note: this Device Tree assumes that the bootloader has remapped the
|
||||
* internal registers to 0xf1000000 (instead of the default
|
||||
* 0xd0000000). The 0xf1000000 is the default used by the recent,
|
||||
* DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
|
||||
* boards were delivered with an older version of the bootloader that
|
||||
* left internal registers mapped at 0xd0000000. If you are in this
|
||||
* situation, you should either update your bootloader (preferred
|
||||
* solution) or the below Device Tree should be adjusted.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include "armada-xp-mv78460.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada XP Development Board DB-MV784MP-GP";
|
||||
compatible = "marvell,axp-gp", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
/*
|
||||
* 8 GB of plug-in RAM modules by default.The amount
|
||||
* of memory available can be changed by the
|
||||
* bootloader according the size of the module
|
||||
* actually plugged. However, memory between
|
||||
* 0xF0000000 to 0xFFFFFFFF cannot be used, as it is
|
||||
* the address range used for I/O (internal registers,
|
||||
* MBus windows).
|
||||
*/
|
||||
reg = <0x00000000 0x00000000 0x00000000 0xf0000000>,
|
||||
<0x00000001 0x00000000 0x00000001 0x00000000>;
|
||||
};
|
||||
|
||||
cpus {
|
||||
pm_pic {
|
||||
ctrl-gpios = <&gpio0 16 GPIO_ACTIVE_LOW>,
|
||||
<&gpio0 17 GPIO_ACTIVE_LOW>,
|
||||
<&gpio0 18 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
|
||||
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
|
||||
MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>;
|
||||
|
||||
devbus-bootcs {
|
||||
status = "okay";
|
||||
|
||||
/* Device Bus parameters are required */
|
||||
|
||||
/* Read parameters */
|
||||
devbus,bus-width = <16>;
|
||||
devbus,turn-off-ps = <60000>;
|
||||
devbus,badr-skew-ps = <0>;
|
||||
devbus,acc-first-ps = <124000>;
|
||||
devbus,acc-next-ps = <248000>;
|
||||
devbus,rd-setup-ps = <0>;
|
||||
devbus,rd-hold-ps = <0>;
|
||||
|
||||
/* Write parameters */
|
||||
devbus,sync-enable = <0>;
|
||||
devbus,wr-high-ps = <60000>;
|
||||
devbus,wr-low-ps = <60000>;
|
||||
devbus,ale-wr-ps = <60000>;
|
||||
|
||||
/* NOR 16 MiB */
|
||||
nor@0 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <0 0x1000000>;
|
||||
bank-width = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie-controller {
|
||||
status = "okay";
|
||||
|
||||
/*
|
||||
* The 3 slots are physically present as
|
||||
* standard PCIe slots on the board.
|
||||
*/
|
||||
pcie@1,0 {
|
||||
/* Port 0, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
pcie@9,0 {
|
||||
/* Port 2, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
pcie@10,0 {
|
||||
/* Port 3, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
internal-regs {
|
||||
serial@12000 {
|
||||
status = "okay";
|
||||
};
|
||||
serial@12100 {
|
||||
status = "okay";
|
||||
};
|
||||
serial@12200 {
|
||||
status = "okay";
|
||||
};
|
||||
serial@12300 {
|
||||
status = "okay";
|
||||
};
|
||||
pinctrl {
|
||||
pinctrl-0 = <&pic_pins>;
|
||||
pinctrl-names = "default";
|
||||
pic_pins: pic-pins-0 {
|
||||
marvell,pins = "mpp16", "mpp17",
|
||||
"mpp18";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
};
|
||||
sata@a0000 {
|
||||
nr-ports = <2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
mdio {
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <16>;
|
||||
};
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <17>;
|
||||
};
|
||||
|
||||
phy2: ethernet-phy@2 {
|
||||
reg = <18>;
|
||||
};
|
||||
|
||||
phy3: ethernet-phy@3 {
|
||||
reg = <19>;
|
||||
};
|
||||
};
|
||||
|
||||
ethernet@70000 {
|
||||
status = "okay";
|
||||
phy = <&phy0>;
|
||||
phy-mode = "qsgmii";
|
||||
};
|
||||
ethernet@74000 {
|
||||
status = "okay";
|
||||
phy = <&phy1>;
|
||||
phy-mode = "qsgmii";
|
||||
};
|
||||
ethernet@30000 {
|
||||
status = "okay";
|
||||
phy = <&phy2>;
|
||||
phy-mode = "qsgmii";
|
||||
};
|
||||
ethernet@34000 {
|
||||
status = "okay";
|
||||
phy = <&phy3>;
|
||||
phy-mode = "qsgmii";
|
||||
};
|
||||
|
||||
/* Front-side USB slot */
|
||||
usb@50000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Back-side USB slot */
|
||||
usb@51000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
spi0: spi@10600 {
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "n25q128a13", "jedec,spi-nor";
|
||||
reg = <0>; /* Chip select 0 */
|
||||
spi-max-frequency = <108000000>;
|
||||
};
|
||||
};
|
||||
|
||||
nand@d0000 {
|
||||
status = "okay";
|
||||
num-cs = <1>;
|
||||
marvell,nand-keep-config;
|
||||
marvell,nand-enable-arbiter;
|
||||
nand-on-flash-bbt;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
231
arch/arm/dts/armada-xp-mv78230.dtsi
Normal file
231
arch/arm/dts/armada-xp-mv78230.dtsi
Normal file
|
|
@ -0,0 +1,231 @@
|
|||
/*
|
||||
* Device Tree Include file for Marvell Armada XP family SoC
|
||||
*
|
||||
* Copyright (C) 2012 Marvell
|
||||
*
|
||||
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Contains definitions specific to the Armada XP MV78230 SoC that are not
|
||||
* common to all Armada XP SoCs.
|
||||
*/
|
||||
|
||||
#include "armada-xp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada XP MV78230 SoC";
|
||||
compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
|
||||
|
||||
aliases {
|
||||
gpio0 = &gpio0;
|
||||
gpio1 = &gpio1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
enable-method = "marvell,armada-xp-smp";
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "marvell,sheeva-v7";
|
||||
reg = <0>;
|
||||
clocks = <&cpuclk 0>;
|
||||
clock-latency = <1000000>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "marvell,sheeva-v7";
|
||||
reg = <1>;
|
||||
clocks = <&cpuclk 1>;
|
||||
clock-latency = <1000000>;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
/*
|
||||
* MV78230 has 2 PCIe units Gen2.0: One unit can be
|
||||
* configured as x4 or quad x1 lanes. One unit is
|
||||
* x1 only.
|
||||
*/
|
||||
pcie-controller {
|
||||
compatible = "marvell,armada-xp-pcie";
|
||||
status = "disabled";
|
||||
device_type = "pci";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
msi-parent = <&mpic>;
|
||||
bus-range = <0x00 0xff>;
|
||||
|
||||
ranges =
|
||||
<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
|
||||
0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
|
||||
0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
|
||||
0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
|
||||
0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
|
||||
0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
|
||||
0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
|
||||
0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
|
||||
0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
|
||||
0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
|
||||
0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
|
||||
0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
|
||||
0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
|
||||
0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
|
||||
0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>;
|
||||
|
||||
pcie@1,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
|
||||
reg = <0x0800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x1 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 58>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 5>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@2,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
|
||||
reg = <0x1000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x2 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 59>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <1>;
|
||||
clocks = <&gateclk 6>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@3,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
|
||||
reg = <0x1800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x3 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 60>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <2>;
|
||||
clocks = <&gateclk 7>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@4,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
|
||||
reg = <0x2000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x4 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 61>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <3>;
|
||||
clocks = <&gateclk 8>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@5,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
|
||||
reg = <0x2800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x5 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 62>;
|
||||
marvell,pcie-port = <1>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 9>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
internal-regs {
|
||||
gpio0: gpio@18100 {
|
||||
compatible = "marvell,orion-gpio";
|
||||
reg = <0x18100 0x40>;
|
||||
ngpios = <32>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <82>, <83>, <84>, <85>;
|
||||
};
|
||||
|
||||
gpio1: gpio@18140 {
|
||||
compatible = "marvell,orion-gpio";
|
||||
reg = <0x18140 0x40>;
|
||||
ngpios = <17>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <87>, <88>, <89>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
compatible = "marvell,mv78230-pinctrl";
|
||||
};
|
||||
333
arch/arm/dts/armada-xp-mv78260.dtsi
Normal file
333
arch/arm/dts/armada-xp-mv78260.dtsi
Normal file
|
|
@ -0,0 +1,333 @@
|
|||
/*
|
||||
* Device Tree Include file for Marvell Armada XP family SoC
|
||||
*
|
||||
* Copyright (C) 2012 Marvell
|
||||
*
|
||||
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Contains definitions specific to the Armada XP MV78260 SoC that are not
|
||||
* common to all Armada XP SoCs.
|
||||
*/
|
||||
|
||||
#include "armada-xp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada XP MV78260 SoC";
|
||||
compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
|
||||
|
||||
aliases {
|
||||
gpio0 = &gpio0;
|
||||
gpio1 = &gpio1;
|
||||
gpio2 = &gpio2;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
enable-method = "marvell,armada-xp-smp";
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "marvell,sheeva-v7";
|
||||
reg = <0>;
|
||||
clocks = <&cpuclk 0>;
|
||||
clock-latency = <1000000>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "marvell,sheeva-v7";
|
||||
reg = <1>;
|
||||
clocks = <&cpuclk 1>;
|
||||
clock-latency = <1000000>;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
/*
|
||||
* MV78260 has 3 PCIe units Gen2.0: Two units can be
|
||||
* configured as x4 or quad x1 lanes. One unit is
|
||||
* x4 only.
|
||||
*/
|
||||
pcie-controller {
|
||||
compatible = "marvell,armada-xp-pcie";
|
||||
status = "disabled";
|
||||
device_type = "pci";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
msi-parent = <&mpic>;
|
||||
bus-range = <0x00 0xff>;
|
||||
|
||||
ranges =
|
||||
<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
|
||||
0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
|
||||
0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
|
||||
0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
|
||||
0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
|
||||
0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
|
||||
0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
|
||||
0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
|
||||
0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
|
||||
0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
|
||||
0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
|
||||
0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
|
||||
0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
|
||||
0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
|
||||
0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
|
||||
0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
|
||||
0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
|
||||
|
||||
0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
|
||||
0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
|
||||
0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
|
||||
0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
|
||||
0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
|
||||
0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
|
||||
0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
|
||||
0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */
|
||||
|
||||
0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
|
||||
0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */>;
|
||||
|
||||
pcie@1,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
|
||||
reg = <0x0800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x1 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 58>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 5>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@2,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
|
||||
reg = <0x1000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x2 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 59>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <1>;
|
||||
clocks = <&gateclk 6>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@3,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
|
||||
reg = <0x1800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x3 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 60>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <2>;
|
||||
clocks = <&gateclk 7>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@4,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
|
||||
reg = <0x2000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x4 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 61>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <3>;
|
||||
clocks = <&gateclk 8>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@5,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
|
||||
reg = <0x2800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x5 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 62>;
|
||||
marvell,pcie-port = <1>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 9>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@6,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x84000 0 0x2000>;
|
||||
reg = <0x3000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x6 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 63>;
|
||||
marvell,pcie-port = <1>;
|
||||
marvell,pcie-lane = <1>;
|
||||
clocks = <&gateclk 10>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@7,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x88000 0 0x2000>;
|
||||
reg = <0x3800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x7 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 64>;
|
||||
marvell,pcie-port = <1>;
|
||||
marvell,pcie-lane = <2>;
|
||||
clocks = <&gateclk 11>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@8,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x8c000 0 0x2000>;
|
||||
reg = <0x4000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x8 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 65>;
|
||||
marvell,pcie-port = <1>;
|
||||
marvell,pcie-lane = <3>;
|
||||
clocks = <&gateclk 12>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@9,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
|
||||
reg = <0x4800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x9 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 99>;
|
||||
marvell,pcie-port = <2>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 26>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
internal-regs {
|
||||
gpio0: gpio@18100 {
|
||||
compatible = "marvell,orion-gpio";
|
||||
reg = <0x18100 0x40>;
|
||||
ngpios = <32>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <82>, <83>, <84>, <85>;
|
||||
};
|
||||
|
||||
gpio1: gpio@18140 {
|
||||
compatible = "marvell,orion-gpio";
|
||||
reg = <0x18140 0x40>;
|
||||
ngpios = <32>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <87>, <88>, <89>, <90>;
|
||||
};
|
||||
|
||||
gpio2: gpio@18180 {
|
||||
compatible = "marvell,orion-gpio";
|
||||
reg = <0x18180 0x40>;
|
||||
ngpios = <3>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <91>;
|
||||
};
|
||||
|
||||
eth3: ethernet@34000 {
|
||||
compatible = "marvell,armada-xp-neta";
|
||||
reg = <0x34000 0x4000>;
|
||||
interrupts = <14>;
|
||||
clocks = <&gateclk 1>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
compatible = "marvell,mv78260-pinctrl";
|
||||
};
|
||||
371
arch/arm/dts/armada-xp-mv78460.dtsi
Normal file
371
arch/arm/dts/armada-xp-mv78460.dtsi
Normal file
|
|
@ -0,0 +1,371 @@
|
|||
/*
|
||||
* Device Tree Include file for Marvell Armada XP family SoC
|
||||
*
|
||||
* Copyright (C) 2012 Marvell
|
||||
*
|
||||
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Contains definitions specific to the Armada XP MV78460 SoC that are not
|
||||
* common to all Armada XP SoCs.
|
||||
*/
|
||||
|
||||
#include "armada-xp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada XP MV78460 SoC";
|
||||
compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
|
||||
|
||||
aliases {
|
||||
gpio0 = &gpio0;
|
||||
gpio1 = &gpio1;
|
||||
gpio2 = &gpio2;
|
||||
};
|
||||
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
enable-method = "marvell,armada-xp-smp";
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "marvell,sheeva-v7";
|
||||
reg = <0>;
|
||||
clocks = <&cpuclk 0>;
|
||||
clock-latency = <1000000>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "marvell,sheeva-v7";
|
||||
reg = <1>;
|
||||
clocks = <&cpuclk 1>;
|
||||
clock-latency = <1000000>;
|
||||
};
|
||||
|
||||
cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "marvell,sheeva-v7";
|
||||
reg = <2>;
|
||||
clocks = <&cpuclk 2>;
|
||||
clock-latency = <1000000>;
|
||||
};
|
||||
|
||||
cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "marvell,sheeva-v7";
|
||||
reg = <3>;
|
||||
clocks = <&cpuclk 3>;
|
||||
clock-latency = <1000000>;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
/*
|
||||
* MV78460 has 4 PCIe units Gen2.0: Two units can be
|
||||
* configured as x4 or quad x1 lanes. Two units are
|
||||
* x4/x1.
|
||||
*/
|
||||
pcie-controller {
|
||||
compatible = "marvell,armada-xp-pcie";
|
||||
status = "disabled";
|
||||
device_type = "pci";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
msi-parent = <&mpic>;
|
||||
bus-range = <0x00 0xff>;
|
||||
|
||||
ranges =
|
||||
<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
|
||||
0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
|
||||
0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
|
||||
0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
|
||||
0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
|
||||
0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
|
||||
0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */
|
||||
0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
|
||||
0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
|
||||
0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
|
||||
0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
|
||||
0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
|
||||
0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
|
||||
0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
|
||||
0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
|
||||
0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
|
||||
0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
|
||||
0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
|
||||
|
||||
0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
|
||||
0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
|
||||
0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
|
||||
0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
|
||||
0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
|
||||
0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
|
||||
0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
|
||||
0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */
|
||||
|
||||
0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
|
||||
0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */
|
||||
|
||||
0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
|
||||
0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>;
|
||||
|
||||
pcie@1,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
|
||||
reg = <0x0800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x1 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 58>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 5>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@2,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
|
||||
reg = <0x1000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x2 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 59>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <1>;
|
||||
clocks = <&gateclk 6>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@3,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
|
||||
reg = <0x1800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x3 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 60>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <2>;
|
||||
clocks = <&gateclk 7>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@4,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
|
||||
reg = <0x2000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x4 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 61>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <3>;
|
||||
clocks = <&gateclk 8>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@5,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
|
||||
reg = <0x2800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x5 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 62>;
|
||||
marvell,pcie-port = <1>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 9>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@6,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
|
||||
reg = <0x3000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x6 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 63>;
|
||||
marvell,pcie-port = <1>;
|
||||
marvell,pcie-lane = <1>;
|
||||
clocks = <&gateclk 10>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@7,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
|
||||
reg = <0x3800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x7 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 64>;
|
||||
marvell,pcie-port = <1>;
|
||||
marvell,pcie-lane = <2>;
|
||||
clocks = <&gateclk 11>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@8,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
|
||||
reg = <0x4000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x8 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 65>;
|
||||
marvell,pcie-port = <1>;
|
||||
marvell,pcie-lane = <3>;
|
||||
clocks = <&gateclk 12>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@9,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
|
||||
reg = <0x4800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x9 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 99>;
|
||||
marvell,pcie-port = <2>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 26>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@10,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
|
||||
reg = <0x5000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
|
||||
0x81000000 0 0 0x81000000 0xa 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 103>;
|
||||
marvell,pcie-port = <3>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 27>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
internal-regs {
|
||||
gpio0: gpio@18100 {
|
||||
compatible = "marvell,orion-gpio";
|
||||
reg = <0x18100 0x40>;
|
||||
ngpios = <32>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <82>, <83>, <84>, <85>;
|
||||
};
|
||||
|
||||
gpio1: gpio@18140 {
|
||||
compatible = "marvell,orion-gpio";
|
||||
reg = <0x18140 0x40>;
|
||||
ngpios = <32>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <87>, <88>, <89>, <90>;
|
||||
};
|
||||
|
||||
gpio2: gpio@18180 {
|
||||
compatible = "marvell,orion-gpio";
|
||||
reg = <0x18180 0x40>;
|
||||
ngpios = <3>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <91>;
|
||||
};
|
||||
|
||||
eth3: ethernet@34000 {
|
||||
compatible = "marvell,armada-xp-neta";
|
||||
reg = <0x34000 0x4000>;
|
||||
interrupts = <14>;
|
||||
clocks = <&gateclk 1>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
compatible = "marvell,mv78460-pinctrl";
|
||||
};
|
||||
320
arch/arm/dts/armada-xp.dtsi
Normal file
320
arch/arm/dts/armada-xp.dtsi
Normal file
|
|
@ -0,0 +1,320 @@
|
|||
/*
|
||||
* Device Tree Include file for Marvell Armada XP family SoC
|
||||
*
|
||||
* Copyright (C) 2012 Marvell
|
||||
*
|
||||
* Lior Amsalem <alior@marvell.com>
|
||||
* Gregory CLEMENT <gregory.clement@free-electrons.com>
|
||||
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
* Ben Dooks <ben.dooks@codethink.co.uk>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Contains definitions specific to the Armada XP SoC that are not
|
||||
* common to all Armada SoCs.
|
||||
*/
|
||||
|
||||
#include "armada-370-xp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada XP family SoC";
|
||||
compatible = "marvell,armadaxp", "marvell,armada-370-xp";
|
||||
|
||||
aliases {
|
||||
serial2 = &uart2;
|
||||
serial3 = &uart3;
|
||||
};
|
||||
|
||||
soc {
|
||||
compatible = "marvell,armadaxp-mbus", "simple-bus";
|
||||
|
||||
bootrom {
|
||||
compatible = "marvell,bootrom";
|
||||
reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
|
||||
};
|
||||
|
||||
internal-regs {
|
||||
sdramc@1400 {
|
||||
compatible = "marvell,armada-xp-sdram-controller";
|
||||
reg = <0x1400 0x500>;
|
||||
};
|
||||
|
||||
L2: l2-cache {
|
||||
compatible = "marvell,aurora-system-cache";
|
||||
reg = <0x08000 0x1000>;
|
||||
cache-id-part = <0x100>;
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
wt-override;
|
||||
};
|
||||
|
||||
spi0: spi@10600 {
|
||||
compatible = "marvell,armada-xp-spi",
|
||||
"marvell,orion-spi";
|
||||
pinctrl-0 = <&spi0_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
spi1: spi@10680 {
|
||||
compatible = "marvell,armada-xp-spi",
|
||||
"marvell,orion-spi";
|
||||
};
|
||||
|
||||
|
||||
i2c0: i2c@11000 {
|
||||
compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
|
||||
reg = <0x11000 0x100>;
|
||||
};
|
||||
|
||||
i2c1: i2c@11100 {
|
||||
compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
|
||||
reg = <0x11100 0x100>;
|
||||
};
|
||||
|
||||
uart2: serial@12200 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
pinctrl-0 = <&uart2_pins>;
|
||||
pinctrl-names = "default";
|
||||
reg = <0x12200 0x100>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <43>;
|
||||
reg-io-width = <1>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@12300 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
pinctrl-0 = <&uart3_pins>;
|
||||
pinctrl-names = "default";
|
||||
reg = <0x12300 0x100>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <44>;
|
||||
reg-io-width = <1>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
system-controller@18200 {
|
||||
compatible = "marvell,armada-370-xp-system-controller";
|
||||
reg = <0x18200 0x500>;
|
||||
};
|
||||
|
||||
gateclk: clock-gating-control@18220 {
|
||||
compatible = "marvell,armada-xp-gating-clock";
|
||||
reg = <0x18220 0x4>;
|
||||
clocks = <&coreclk 0>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
coreclk: mvebu-sar@18230 {
|
||||
compatible = "marvell,armada-xp-core-clock";
|
||||
reg = <0x18230 0x08>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
thermal@182b0 {
|
||||
compatible = "marvell,armadaxp-thermal";
|
||||
reg = <0x182b0 0x4
|
||||
0x184d0 0x4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
cpuclk: clock-complex@18700 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "marvell,armada-xp-cpu-clock";
|
||||
reg = <0x18700 0x24>, <0x1c054 0x10>;
|
||||
clocks = <&coreclk 1>;
|
||||
};
|
||||
|
||||
interrupt-controller@20a00 {
|
||||
reg = <0x20a00 0x2d0>, <0x21070 0x58>;
|
||||
};
|
||||
|
||||
timer@20300 {
|
||||
compatible = "marvell,armada-xp-timer";
|
||||
clocks = <&coreclk 2>, <&refclk>;
|
||||
clock-names = "nbclk", "fixed";
|
||||
};
|
||||
|
||||
watchdog@20300 {
|
||||
compatible = "marvell,armada-xp-wdt";
|
||||
clocks = <&coreclk 2>, <&refclk>;
|
||||
clock-names = "nbclk", "fixed";
|
||||
};
|
||||
|
||||
cpurst@20800 {
|
||||
compatible = "marvell,armada-370-cpu-reset";
|
||||
reg = <0x20800 0x20>;
|
||||
};
|
||||
|
||||
eth2: ethernet@30000 {
|
||||
compatible = "marvell,armada-xp-neta";
|
||||
reg = <0x30000 0x4000>;
|
||||
interrupts = <12>;
|
||||
clocks = <&gateclk 2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb@50000 {
|
||||
clocks = <&gateclk 18>;
|
||||
};
|
||||
|
||||
usb@51000 {
|
||||
clocks = <&gateclk 19>;
|
||||
};
|
||||
|
||||
usb@52000 {
|
||||
compatible = "marvell,orion-ehci";
|
||||
reg = <0x52000 0x500>;
|
||||
interrupts = <47>;
|
||||
clocks = <&gateclk 20>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
xor@60900 {
|
||||
compatible = "marvell,orion-xor";
|
||||
reg = <0x60900 0x100
|
||||
0x60b00 0x100>;
|
||||
clocks = <&gateclk 22>;
|
||||
status = "okay";
|
||||
|
||||
xor10 {
|
||||
interrupts = <51>;
|
||||
dmacap,memcpy;
|
||||
dmacap,xor;
|
||||
};
|
||||
xor11 {
|
||||
interrupts = <52>;
|
||||
dmacap,memcpy;
|
||||
dmacap,xor;
|
||||
dmacap,memset;
|
||||
};
|
||||
};
|
||||
|
||||
ethernet@70000 {
|
||||
compatible = "marvell,armada-xp-neta";
|
||||
};
|
||||
|
||||
ethernet@74000 {
|
||||
compatible = "marvell,armada-xp-neta";
|
||||
};
|
||||
|
||||
xor@f0900 {
|
||||
compatible = "marvell,orion-xor";
|
||||
reg = <0xF0900 0x100
|
||||
0xF0B00 0x100>;
|
||||
clocks = <&gateclk 28>;
|
||||
status = "okay";
|
||||
|
||||
xor00 {
|
||||
interrupts = <94>;
|
||||
dmacap,memcpy;
|
||||
dmacap,xor;
|
||||
};
|
||||
xor01 {
|
||||
interrupts = <95>;
|
||||
dmacap,memcpy;
|
||||
dmacap,xor;
|
||||
dmacap,memset;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
clocks {
|
||||
/* 25 MHz reference crystal */
|
||||
refclk: oscillator {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
ge0_gmii_pins: ge0-gmii-pins {
|
||||
marvell,pins =
|
||||
"mpp0", "mpp1", "mpp2", "mpp3",
|
||||
"mpp4", "mpp5", "mpp6", "mpp7",
|
||||
"mpp8", "mpp9", "mpp10", "mpp11",
|
||||
"mpp12", "mpp13", "mpp14", "mpp15",
|
||||
"mpp16", "mpp17", "mpp18", "mpp19",
|
||||
"mpp20", "mpp21", "mpp22", "mpp23";
|
||||
marvell,function = "ge0";
|
||||
};
|
||||
|
||||
ge0_rgmii_pins: ge0-rgmii-pins {
|
||||
marvell,pins =
|
||||
"mpp0", "mpp1", "mpp2", "mpp3",
|
||||
"mpp4", "mpp5", "mpp6", "mpp7",
|
||||
"mpp8", "mpp9", "mpp10", "mpp11";
|
||||
marvell,function = "ge0";
|
||||
};
|
||||
|
||||
ge1_rgmii_pins: ge1-rgmii-pins {
|
||||
marvell,pins =
|
||||
"mpp12", "mpp13", "mpp14", "mpp15",
|
||||
"mpp16", "mpp17", "mpp18", "mpp19",
|
||||
"mpp20", "mpp21", "mpp22", "mpp23";
|
||||
marvell,function = "ge1";
|
||||
};
|
||||
|
||||
sdio_pins: sdio-pins {
|
||||
marvell,pins = "mpp30", "mpp31", "mpp32",
|
||||
"mpp33", "mpp34", "mpp35";
|
||||
marvell,function = "sd0";
|
||||
};
|
||||
|
||||
spi0_pins: spi0-pins {
|
||||
marvell,pins = "mpp36", "mpp37",
|
||||
"mpp38", "mpp39";
|
||||
marvell,function = "spi0";
|
||||
};
|
||||
|
||||
uart2_pins: uart2-pins {
|
||||
marvell,pins = "mpp42", "mpp43";
|
||||
marvell,function = "uart2";
|
||||
};
|
||||
|
||||
uart3_pins: uart3-pins {
|
||||
marvell,pins = "mpp44", "mpp45";
|
||||
marvell,function = "uart3";
|
||||
};
|
||||
};
|
||||
|
|
@ -89,4 +89,9 @@
|
|||
regulator-name = "ldo5";
|
||||
};
|
||||
};
|
||||
|
||||
usb_power_supply: usb_power_supply {
|
||||
compatible = "x-powers,axp202-usb-power-supply";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
693
arch/arm/dts/dra7-evm.dts
Normal file
693
arch/arm/dts/dra7-evm.dts
Normal file
|
|
@ -0,0 +1,693 @@
|
|||
/*
|
||||
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
/dts-v1/;
|
||||
|
||||
#include "dra74x.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
model = "TI DRA742";
|
||||
compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x60000000>; /* 1536 MB */
|
||||
};
|
||||
|
||||
mmc2_3v3: fixedregulator-mmc2 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "mmc2_3v3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
extcon_usb1: extcon_usb1 {
|
||||
compatible = "linux,extcon-usb-gpio";
|
||||
id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
extcon_usb2: extcon_usb2 {
|
||||
compatible = "linux,extcon-usb-gpio";
|
||||
id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
vtt_fixed: fixedregulator-vtt {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vtt_fixed";
|
||||
regulator-min-microvolt = <1350000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
enable-active-high;
|
||||
gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
&dra7_pmx_core {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vtt_pin>;
|
||||
|
||||
vtt_pin: pinmux_vtt_pin {
|
||||
pinctrl-single,pins = <
|
||||
0x3b4 (PIN_OUTPUT | MUX_MODE14) /* spi1_cs1.gpio7_11 */
|
||||
>;
|
||||
};
|
||||
|
||||
i2c1_pins: pinmux_i2c1_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda */
|
||||
0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl */
|
||||
>;
|
||||
};
|
||||
|
||||
i2c2_pins: pinmux_i2c2_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x408 (PIN_INPUT | MUX_MODE0) /* i2c2_sda */
|
||||
0x40c (PIN_INPUT | MUX_MODE0) /* i2c2_scl */
|
||||
>;
|
||||
};
|
||||
|
||||
i2c3_pins: pinmux_i2c3_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x288 (PIN_INPUT | MUX_MODE9) /* gpio6_14.i2c3_sda */
|
||||
0x28c (PIN_INPUT | MUX_MODE9) /* gpio6_15.i2c3_scl */
|
||||
>;
|
||||
};
|
||||
|
||||
mcspi1_pins: pinmux_mcspi1_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x3a4 (PIN_INPUT | MUX_MODE0) /* spi1_sclk */
|
||||
0x3a8 (PIN_INPUT | MUX_MODE0) /* spi1_d1 */
|
||||
0x3ac (PIN_INPUT | MUX_MODE0) /* spi1_d0 */
|
||||
0x3b0 (PIN_INPUT_SLEW | MUX_MODE0) /* spi1_cs0 */
|
||||
0x3b8 (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs2.hdmi1_hpd */
|
||||
0x3bc (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs3.hdmi1_cec */
|
||||
>;
|
||||
};
|
||||
|
||||
mcspi2_pins: pinmux_mcspi2_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x3c0 (PIN_INPUT | MUX_MODE0) /* spi2_sclk */
|
||||
0x3c4 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
|
||||
0x3c8 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
|
||||
0x3cc (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */
|
||||
>;
|
||||
};
|
||||
|
||||
uart1_pins: pinmux_uart1_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x3e0 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_rxd */
|
||||
0x3e4 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_txd */
|
||||
0x3e8 (PIN_INPUT | MUX_MODE3) /* uart1_ctsn */
|
||||
0x3ec (PIN_INPUT | MUX_MODE3) /* uart1_rtsn */
|
||||
>;
|
||||
};
|
||||
|
||||
uart2_pins: pinmux_uart2_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x3f0 (PIN_INPUT | MUX_MODE0) /* uart2_rxd */
|
||||
0x3f4 (PIN_INPUT | MUX_MODE0) /* uart2_txd */
|
||||
0x3f8 (PIN_INPUT | MUX_MODE0) /* uart2_ctsn */
|
||||
0x3fc (PIN_INPUT | MUX_MODE0) /* uart2_rtsn */
|
||||
>;
|
||||
};
|
||||
|
||||
uart3_pins: pinmux_uart3_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x248 (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */
|
||||
0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
|
||||
>;
|
||||
};
|
||||
|
||||
qspi1_pins: pinmux_qspi1_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x4c (PIN_INPUT | MUX_MODE1) /* gpmc_a3.qspi1_cs2 */
|
||||
0x50 (PIN_INPUT | MUX_MODE1) /* gpmc_a4.qspi1_cs3 */
|
||||
0x74 (PIN_INPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */
|
||||
0x78 (PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */
|
||||
0x7c (PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */
|
||||
0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
|
||||
0x84 (PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */
|
||||
0x88 (PIN_INPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */
|
||||
0xb8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */
|
||||
0xbc (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs3.qspi1_cs1 */
|
||||
>;
|
||||
};
|
||||
|
||||
usb1_pins: pinmux_usb1_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
|
||||
>;
|
||||
};
|
||||
|
||||
usb2_pins: pinmux_usb2_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
|
||||
>;
|
||||
};
|
||||
|
||||
nand_flash_x16: nand_flash_x16 {
|
||||
/* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch
|
||||
* So NAND flash requires following switch settings:
|
||||
* SW5.9 (GPMC_WPN) = LOW
|
||||
* SW5.1 (NAND_BOOTn) = HIGH */
|
||||
pinctrl-single,pins = <
|
||||
0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */
|
||||
0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */
|
||||
0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */
|
||||
0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */
|
||||
0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */
|
||||
0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */
|
||||
0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */
|
||||
0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */
|
||||
0x20 (PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */
|
||||
0x24 (PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */
|
||||
0x28 (PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */
|
||||
0x2c (PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */
|
||||
0x30 (PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */
|
||||
0x34 (PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */
|
||||
0x38 (PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */
|
||||
0x3c (PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */
|
||||
0xd8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0 */
|
||||
0xcc (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
|
||||
0xb4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0 */
|
||||
0xc4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
|
||||
0xc8 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
|
||||
0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle */
|
||||
>;
|
||||
};
|
||||
|
||||
cpsw_default: cpsw_default {
|
||||
pinctrl-single,pins = <
|
||||
/* Slave 1 */
|
||||
0x250 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txc.rgmii0_txc */
|
||||
0x254 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txctl.rgmii0_txctl */
|
||||
0x258 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_td3.rgmii0_txd3 */
|
||||
0x25c (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd2.rgmii0_txd2 */
|
||||
0x260 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd1.rgmii0_txd1 */
|
||||
0x264 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd0.rgmii0_txd0 */
|
||||
0x268 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxc.rgmii0_rxc */
|
||||
0x26c (PIN_INPUT | MUX_MODE0) /* rgmii0_rxctl.rgmii0_rxctl */
|
||||
0x270 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd3.rgmii0_rxd3 */
|
||||
0x274 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd2.rgmii0_rxd2 */
|
||||
0x278 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd1.rgmii0_rxd1 */
|
||||
0x27c (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd0.rgmii0_rxd0 */
|
||||
|
||||
/* Slave 2 */
|
||||
0x198 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */
|
||||
0x19c (PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */
|
||||
0x1a0 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */
|
||||
0x1a4 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */
|
||||
0x1a8 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */
|
||||
0x1ac (PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */
|
||||
0x1b0 (PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */
|
||||
0x1b4 (PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */
|
||||
0x1b8 (PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */
|
||||
0x1bc (PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */
|
||||
0x1c0 (PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */
|
||||
0x1c4 (PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */
|
||||
>;
|
||||
|
||||
};
|
||||
|
||||
cpsw_sleep: cpsw_sleep {
|
||||
pinctrl-single,pins = <
|
||||
/* Slave 1 */
|
||||
0x250 (MUX_MODE15)
|
||||
0x254 (MUX_MODE15)
|
||||
0x258 (MUX_MODE15)
|
||||
0x25c (MUX_MODE15)
|
||||
0x260 (MUX_MODE15)
|
||||
0x264 (MUX_MODE15)
|
||||
0x268 (MUX_MODE15)
|
||||
0x26c (MUX_MODE15)
|
||||
0x270 (MUX_MODE15)
|
||||
0x274 (MUX_MODE15)
|
||||
0x278 (MUX_MODE15)
|
||||
0x27c (MUX_MODE15)
|
||||
|
||||
/* Slave 2 */
|
||||
0x198 (MUX_MODE15)
|
||||
0x19c (MUX_MODE15)
|
||||
0x1a0 (MUX_MODE15)
|
||||
0x1a4 (MUX_MODE15)
|
||||
0x1a8 (MUX_MODE15)
|
||||
0x1ac (MUX_MODE15)
|
||||
0x1b0 (MUX_MODE15)
|
||||
0x1b4 (MUX_MODE15)
|
||||
0x1b8 (MUX_MODE15)
|
||||
0x1bc (MUX_MODE15)
|
||||
0x1c0 (MUX_MODE15)
|
||||
0x1c4 (MUX_MODE15)
|
||||
>;
|
||||
};
|
||||
|
||||
davinci_mdio_default: davinci_mdio_default {
|
||||
pinctrl-single,pins = <
|
||||
0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */
|
||||
0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
|
||||
>;
|
||||
};
|
||||
|
||||
davinci_mdio_sleep: davinci_mdio_sleep {
|
||||
pinctrl-single,pins = <
|
||||
0x23c (MUX_MODE15)
|
||||
0x240 (MUX_MODE15)
|
||||
>;
|
||||
};
|
||||
|
||||
dcan1_pins_default: dcan1_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
|
||||
0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
|
||||
>;
|
||||
};
|
||||
|
||||
dcan1_pins_sleep: dcan1_pins_sleep {
|
||||
pinctrl-single,pins = <
|
||||
0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
|
||||
0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c1_pins>;
|
||||
clock-frequency = <400000>;
|
||||
|
||||
tps659038: tps659038@58 {
|
||||
compatible = "ti,tps659038";
|
||||
reg = <0x58>;
|
||||
|
||||
tps659038_pmic {
|
||||
compatible = "ti,tps659038-pmic";
|
||||
|
||||
regulators {
|
||||
smps123_reg: smps123 {
|
||||
/* VDD_MPU */
|
||||
regulator-name = "smps123";
|
||||
regulator-min-microvolt = < 850000>;
|
||||
regulator-max-microvolt = <1250000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
smps45_reg: smps45 {
|
||||
/* VDD_DSPEVE */
|
||||
regulator-name = "smps45";
|
||||
regulator-min-microvolt = < 850000>;
|
||||
regulator-max-microvolt = <1150000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
smps6_reg: smps6 {
|
||||
/* VDD_GPU - over VDD_SMPS6 */
|
||||
regulator-name = "smps6";
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1250000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
smps7_reg: smps7 {
|
||||
/* CORE_VDD */
|
||||
regulator-name = "smps7";
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1060000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
smps8_reg: smps8 {
|
||||
/* VDD_IVAHD */
|
||||
regulator-name = "smps8";
|
||||
regulator-min-microvolt = < 850000>;
|
||||
regulator-max-microvolt = <1250000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
smps9_reg: smps9 {
|
||||
/* VDDS1V8 */
|
||||
regulator-name = "smps9";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
ldo1_reg: ldo1 {
|
||||
/* LDO1_OUT --> SDIO */
|
||||
regulator-name = "ldo1";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
ldo2_reg: ldo2 {
|
||||
/* VDD_RTCIO */
|
||||
/* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */
|
||||
regulator-name = "ldo2";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
ldo3_reg: ldo3 {
|
||||
/* VDDA_1V8_PHY */
|
||||
regulator-name = "ldo3";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
ldo9_reg: ldo9 {
|
||||
/* VDD_RTC */
|
||||
regulator-name = "ldo9";
|
||||
regulator-min-microvolt = <1050000>;
|
||||
regulator-max-microvolt = <1050000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
ldoln_reg: ldoln {
|
||||
/* VDDA_1V8_PLL */
|
||||
regulator-name = "ldoln";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
ldousb_reg: ldousb {
|
||||
/* VDDA_3V_USB: VDDA_USBHS33 */
|
||||
regulator-name = "ldousb";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pcf_gpio_21: gpio@21 {
|
||||
compatible = "ti,pcf8575";
|
||||
reg = <0x21>;
|
||||
lines-initial-states = <0x1408>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-parent = <&gpio6>;
|
||||
interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c2_pins>;
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c3_pins>;
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
|
||||
&mcspi1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcspi1_pins>;
|
||||
};
|
||||
|
||||
&mcspi2 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcspi2_pins>;
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart1_pins>;
|
||||
interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&dra7_pmx_core 0x3e0>;
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart2_pins>;
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart3_pins>;
|
||||
};
|
||||
|
||||
&mmc1 {
|
||||
status = "okay";
|
||||
vmmc-supply = <&ldo1_reg>;
|
||||
bus-width = <4>;
|
||||
};
|
||||
|
||||
&mmc2 {
|
||||
status = "okay";
|
||||
vmmc-supply = <&mmc2_3v3>;
|
||||
bus-width = <8>;
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu0-supply = <&smps123_reg>;
|
||||
};
|
||||
|
||||
&qspi {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qspi1_pins>;
|
||||
|
||||
spi-max-frequency = <48000000>;
|
||||
m25p80@0 {
|
||||
compatible = "s25fl256s1";
|
||||
spi-max-frequency = <48000000>;
|
||||
reg = <0>;
|
||||
spi-tx-bus-width = <1>;
|
||||
spi-rx-bus-width = <4>;
|
||||
spi-cpol;
|
||||
spi-cpha;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
/* MTD partition table.
|
||||
* The ROM checks the first four physical blocks
|
||||
* for a valid file to boot and the flash here is
|
||||
* 64KiB block size.
|
||||
*/
|
||||
partition@0 {
|
||||
label = "QSPI.SPL";
|
||||
reg = <0x00000000 0x000010000>;
|
||||
};
|
||||
partition@1 {
|
||||
label = "QSPI.SPL.backup1";
|
||||
reg = <0x00010000 0x00010000>;
|
||||
};
|
||||
partition@2 {
|
||||
label = "QSPI.SPL.backup2";
|
||||
reg = <0x00020000 0x00010000>;
|
||||
};
|
||||
partition@3 {
|
||||
label = "QSPI.SPL.backup3";
|
||||
reg = <0x00030000 0x00010000>;
|
||||
};
|
||||
partition@4 {
|
||||
label = "QSPI.u-boot";
|
||||
reg = <0x00040000 0x00100000>;
|
||||
};
|
||||
partition@5 {
|
||||
label = "QSPI.u-boot-spl-os";
|
||||
reg = <0x00140000 0x00080000>;
|
||||
};
|
||||
partition@6 {
|
||||
label = "QSPI.u-boot-env";
|
||||
reg = <0x001c0000 0x00010000>;
|
||||
};
|
||||
partition@7 {
|
||||
label = "QSPI.u-boot-env.backup1";
|
||||
reg = <0x001d0000 0x0010000>;
|
||||
};
|
||||
partition@8 {
|
||||
label = "QSPI.kernel";
|
||||
reg = <0x001e0000 0x0800000>;
|
||||
};
|
||||
partition@9 {
|
||||
label = "QSPI.file-system";
|
||||
reg = <0x009e0000 0x01620000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&omap_dwc3_1 {
|
||||
extcon = <&extcon_usb1>;
|
||||
};
|
||||
|
||||
&omap_dwc3_2 {
|
||||
extcon = <&extcon_usb2>;
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
dr_mode = "peripheral";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usb1_pins>;
|
||||
};
|
||||
|
||||
&usb2 {
|
||||
dr_mode = "host";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usb2_pins>;
|
||||
};
|
||||
|
||||
&elm {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpmc {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&nand_flash_x16>;
|
||||
ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
|
||||
nand@0,0 {
|
||||
reg = <0 0 4>; /* device IO registers */
|
||||
ti,nand-ecc-opt = "bch8";
|
||||
ti,elm-id = <&elm>;
|
||||
nand-bus-width = <16>;
|
||||
gpmc,device-width = <2>;
|
||||
gpmc,sync-clk-ps = <0>;
|
||||
gpmc,cs-on-ns = <0>;
|
||||
gpmc,cs-rd-off-ns = <80>;
|
||||
gpmc,cs-wr-off-ns = <80>;
|
||||
gpmc,adv-on-ns = <0>;
|
||||
gpmc,adv-rd-off-ns = <60>;
|
||||
gpmc,adv-wr-off-ns = <60>;
|
||||
gpmc,we-on-ns = <10>;
|
||||
gpmc,we-off-ns = <50>;
|
||||
gpmc,oe-on-ns = <4>;
|
||||
gpmc,oe-off-ns = <40>;
|
||||
gpmc,access-ns = <40>;
|
||||
gpmc,wr-access-ns = <80>;
|
||||
gpmc,rd-cycle-ns = <80>;
|
||||
gpmc,wr-cycle-ns = <80>;
|
||||
gpmc,bus-turnaround-ns = <0>;
|
||||
gpmc,cycle2cycle-delay-ns = <0>;
|
||||
gpmc,clk-activation-ns = <0>;
|
||||
gpmc,wait-monitoring-ns = <0>;
|
||||
gpmc,wr-data-mux-bus-ns = <0>;
|
||||
/* MTD partition table */
|
||||
/* All SPL-* partitions are sized to minimal length
|
||||
* which can be independently programmable. For
|
||||
* NAND flash this is equal to size of erase-block */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "NAND.SPL";
|
||||
reg = <0x00000000 0x000020000>;
|
||||
};
|
||||
partition@1 {
|
||||
label = "NAND.SPL.backup1";
|
||||
reg = <0x00020000 0x00020000>;
|
||||
};
|
||||
partition@2 {
|
||||
label = "NAND.SPL.backup2";
|
||||
reg = <0x00040000 0x00020000>;
|
||||
};
|
||||
partition@3 {
|
||||
label = "NAND.SPL.backup3";
|
||||
reg = <0x00060000 0x00020000>;
|
||||
};
|
||||
partition@4 {
|
||||
label = "NAND.u-boot-spl-os";
|
||||
reg = <0x00080000 0x00040000>;
|
||||
};
|
||||
partition@5 {
|
||||
label = "NAND.u-boot";
|
||||
reg = <0x000c0000 0x00100000>;
|
||||
};
|
||||
partition@6 {
|
||||
label = "NAND.u-boot-env";
|
||||
reg = <0x001c0000 0x00020000>;
|
||||
};
|
||||
partition@7 {
|
||||
label = "NAND.u-boot-env.backup1";
|
||||
reg = <0x001e0000 0x00020000>;
|
||||
};
|
||||
partition@8 {
|
||||
label = "NAND.kernel";
|
||||
reg = <0x00200000 0x00800000>;
|
||||
};
|
||||
partition@9 {
|
||||
label = "NAND.file-system";
|
||||
reg = <0x00a00000 0x0f600000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&usb2_phy1 {
|
||||
phy-supply = <&ldousb_reg>;
|
||||
};
|
||||
|
||||
&usb2_phy2 {
|
||||
phy-supply = <&ldousb_reg>;
|
||||
};
|
||||
|
||||
&gpio7 {
|
||||
ti,no-reset-on-init;
|
||||
ti,no-idle-on-init;
|
||||
};
|
||||
|
||||
&mac {
|
||||
status = "okay";
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&cpsw_default>;
|
||||
pinctrl-1 = <&cpsw_sleep>;
|
||||
dual_emac;
|
||||
};
|
||||
|
||||
&cpsw_emac0 {
|
||||
phy_id = <&davinci_mdio>, <2>;
|
||||
phy-mode = "rgmii";
|
||||
dual_emac_res_vlan = <1>;
|
||||
};
|
||||
|
||||
&cpsw_emac1 {
|
||||
phy_id = <&davinci_mdio>, <3>;
|
||||
phy-mode = "rgmii";
|
||||
dual_emac_res_vlan = <2>;
|
||||
};
|
||||
|
||||
&davinci_mdio {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&davinci_mdio_default>;
|
||||
pinctrl-1 = <&davinci_mdio_sleep>;
|
||||
};
|
||||
|
||||
&dcan1 {
|
||||
status = "ok";
|
||||
pinctrl-names = "default", "sleep", "active";
|
||||
pinctrl-0 = <&dcan1_pins_sleep>;
|
||||
pinctrl-1 = <&dcan1_pins_sleep>;
|
||||
pinctrl-2 = <&dcan1_pins_default>;
|
||||
};
|
||||
90
arch/arm/dts/dra74x.dtsi
Normal file
90
arch/arm/dts/dra74x.dtsi
Normal file
|
|
@ -0,0 +1,90 @@
|
|||
/*
|
||||
* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
* Based on "omap4.dtsi"
|
||||
*/
|
||||
|
||||
#include "dra7.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "ti,dra742", "ti,dra74", "ti,dra7";
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0>;
|
||||
|
||||
operating-points = <
|
||||
/* kHz uV */
|
||||
1000000 1060000
|
||||
1176000 1160000
|
||||
>;
|
||||
|
||||
clocks = <&dpll_mpu_ck>;
|
||||
clock-names = "cpu";
|
||||
|
||||
clock-latency = <300000>; /* From omap-cpufreq driver */
|
||||
|
||||
/* cooling options */
|
||||
cooling-min-level = <0>;
|
||||
cooling-max-level = <2>;
|
||||
#cooling-cells = <2>; /* min followed by max */
|
||||
};
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,cortex-a15-pmu";
|
||||
interrupt-parent = <&wakeupgen>;
|
||||
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
ocp {
|
||||
omap_dwc3_4: omap_dwc3_4@48940000 {
|
||||
compatible = "ti,dwc3";
|
||||
ti,hwmods = "usb_otg_ss4";
|
||||
reg = <0x48940000 0x10000>;
|
||||
interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
utmi-mode = <2>;
|
||||
ranges;
|
||||
status = "disabled";
|
||||
usb4: usb@48950000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0x48950000 0x17000>;
|
||||
interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
|
||||
tx-fifo-resize;
|
||||
maximum-speed = "high-speed";
|
||||
dr_mode = "otg";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dss {
|
||||
reg = <0x58000000 0x80>,
|
||||
<0x58004054 0x4>,
|
||||
<0x58004300 0x20>,
|
||||
<0x58005054 0x4>,
|
||||
<0x58005300 0x20>;
|
||||
reg-names = "dss", "pll1_clkctrl", "pll1",
|
||||
"pll2_clkctrl", "pll2";
|
||||
|
||||
clocks = <&dss_dss_clk>,
|
||||
<&dss_video1_clk>,
|
||||
<&dss_video2_clk>;
|
||||
clock-names = "fck", "video1_clk", "video2_clk";
|
||||
};
|
||||
77
arch/arm/dts/k2e-clocks.dtsi
Normal file
77
arch/arm/dts/k2e-clocks.dtsi
Normal file
|
|
@ -0,0 +1,77 @@
|
|||
/*
|
||||
* Copyright 2014 Texas Instruments, Inc.
|
||||
*
|
||||
* Keystone 2 Edison SoC specific device tree
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
clocks {
|
||||
mainpllclk: mainpllclk@2310110 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,main-pll-clock";
|
||||
clocks = <&refclksys>;
|
||||
reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
|
||||
reg-names = "control", "multiplier", "post-divider";
|
||||
};
|
||||
|
||||
papllclk: papllclk@2620358 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,pll-clock";
|
||||
clocks = <&refclkpass>;
|
||||
clock-output-names = "papllclk";
|
||||
reg = <0x02620358 4>;
|
||||
reg-names = "control";
|
||||
};
|
||||
|
||||
ddr3apllclk: ddr3apllclk@2620360 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,pll-clock";
|
||||
clocks = <&refclkddr3a>;
|
||||
clock-output-names = "ddr-3a-pll-clk";
|
||||
reg = <0x02620360 4>;
|
||||
reg-names = "control";
|
||||
};
|
||||
|
||||
clkusb1: clkusb1 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk16>;
|
||||
clock-output-names = "usb1";
|
||||
reg = <0x02350004 0xb00>, <0x02350000 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <0>;
|
||||
};
|
||||
|
||||
clkhyperlink0: clkhyperlink0 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk12>;
|
||||
clock-output-names = "hyperlink-0";
|
||||
reg = <0x02350030 0xb00>, <0x02350014 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <5>;
|
||||
};
|
||||
|
||||
clkpcie1: clkpcie1 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk12>;
|
||||
clock-output-names = "pcie1";
|
||||
reg = <0x0235006c 0xb00>, <0x02350048 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <18>;
|
||||
};
|
||||
|
||||
clkxge: clkxge {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk13>;
|
||||
clock-output-names = "xge";
|
||||
reg = <0x023500c8 0xb00>, <0x02350074 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <29>;
|
||||
};
|
||||
};
|
||||
154
arch/arm/dts/k2e-evm.dts
Normal file
154
arch/arm/dts/k2e-evm.dts
Normal file
|
|
@ -0,0 +1,154 @@
|
|||
/*
|
||||
* Copyright 2013-2014 Texas Instruments, Inc.
|
||||
*
|
||||
* Keystone 2 Edison EVM device tree
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
/dts-v1/;
|
||||
|
||||
#include "keystone.dtsi"
|
||||
#include "k2e.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "ti,k2e-evm","ti,keystone";
|
||||
model = "Texas Instruments Keystone 2 Edison EVM";
|
||||
|
||||
soc {
|
||||
|
||||
clocks {
|
||||
refclksys: refclksys {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <100000000>;
|
||||
clock-output-names = "refclk-sys";
|
||||
};
|
||||
|
||||
refclkpass: refclkpass {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <100000000>;
|
||||
clock-output-names = "refclk-pass";
|
||||
};
|
||||
|
||||
refclkddr3a: refclkddr3a {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <100000000>;
|
||||
clock-output-names = "refclk-ddr3a";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&usb_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb1_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
dtt@50 {
|
||||
compatible = "at,24c1024";
|
||||
reg = <0x50>;
|
||||
};
|
||||
};
|
||||
|
||||
&aemif {
|
||||
cs0 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
clock-ranges;
|
||||
ranges;
|
||||
|
||||
ti,cs-chipselect = <0>;
|
||||
/* all timings in nanoseconds */
|
||||
ti,cs-min-turnaround-ns = <12>;
|
||||
ti,cs-read-hold-ns = <6>;
|
||||
ti,cs-read-strobe-ns = <23>;
|
||||
ti,cs-read-setup-ns = <9>;
|
||||
ti,cs-write-hold-ns = <8>;
|
||||
ti,cs-write-strobe-ns = <23>;
|
||||
ti,cs-write-setup-ns = <8>;
|
||||
|
||||
nand@0,0 {
|
||||
compatible = "ti,keystone-nand","ti,davinci-nand";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0 0 0x4000000
|
||||
1 0 0x0000100>;
|
||||
|
||||
ti,davinci-chipselect = <0>;
|
||||
ti,davinci-mask-ale = <0x2000>;
|
||||
ti,davinci-mask-cle = <0x4000>;
|
||||
ti,davinci-mask-chipsel = <0>;
|
||||
nand-ecc-mode = "hw";
|
||||
ti,davinci-ecc-bits = <4>;
|
||||
nand-on-flash-bbt;
|
||||
|
||||
partition@0 {
|
||||
label = "u-boot";
|
||||
reg = <0x0 0x100000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@100000 {
|
||||
label = "params";
|
||||
reg = <0x100000 0x80000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@180000 {
|
||||
label = "ubifs";
|
||||
reg = <0x180000 0x1FE80000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
nor_flash: n25q128a11@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "Micron,n25q128a11";
|
||||
spi-max-frequency = <54000000>;
|
||||
m25p,fast-read;
|
||||
reg = <0>;
|
||||
|
||||
partition@0 {
|
||||
label = "u-boot-spl";
|
||||
reg = <0x0 0x80000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@1 {
|
||||
label = "misc";
|
||||
reg = <0x80000 0xf80000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mdio {
|
||||
status = "ok";
|
||||
ethphy0: ethernet-phy@0 {
|
||||
compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
ethphy1: ethernet-phy@1 {
|
||||
compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22";
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
206
arch/arm/dts/k2e-netcp.dtsi
Normal file
206
arch/arm/dts/k2e-netcp.dtsi
Normal file
|
|
@ -0,0 +1,206 @@
|
|||
/*
|
||||
* Device Tree Source for Keystone 2 Edison Netcp driver
|
||||
*
|
||||
* Copyright 2015 Texas Instruments, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
qmss: qmss@2a40000 {
|
||||
compatible = "ti,keystone-navigator-qmss";
|
||||
dma-coherent;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
clocks = <&chipclk13>;
|
||||
ranges;
|
||||
queue-range = <0 0x2000>;
|
||||
linkram0 = <0x100000 0x4000>;
|
||||
linkram1 = <0 0x10000>;
|
||||
|
||||
qmgrs {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
qmgr0 {
|
||||
managed-queues = <0 0x2000>;
|
||||
reg = <0x2a40000 0x20000>,
|
||||
<0x2a06000 0x400>,
|
||||
<0x2a02000 0x1000>,
|
||||
<0x2a03000 0x1000>,
|
||||
<0x23a80000 0x20000>,
|
||||
<0x2a80000 0x20000>;
|
||||
reg-names = "peek", "status", "config",
|
||||
"region", "push", "pop";
|
||||
};
|
||||
};
|
||||
queue-pools {
|
||||
qpend {
|
||||
qpend-0 {
|
||||
qrange = <658 8>;
|
||||
interrupts =<0 40 0xf04 0 41 0xf04 0 42 0xf04
|
||||
0 43 0xf04 0 44 0xf04 0 45 0xf04
|
||||
0 46 0xf04 0 47 0xf04>;
|
||||
};
|
||||
qpend-1 {
|
||||
qrange = <528 16>;
|
||||
interrupts = <0 48 0xf04 0 49 0xf04 0 50 0xf04
|
||||
0 51 0xf04 0 52 0xf04 0 53 0xf04
|
||||
0 54 0xf04 0 55 0xf04 0 56 0xf04
|
||||
0 57 0xf04 0 58 0xf04 0 59 0xf04
|
||||
0 60 0xf04 0 61 0xf04 0 62 0xf04
|
||||
0 63 0xf04>;
|
||||
qalloc-by-id;
|
||||
};
|
||||
qpend-2 {
|
||||
qrange = <544 16>;
|
||||
interrupts = <0 64 0xf04 0 65 0xf04 0 66 0xf04
|
||||
0 59 0xf04 0 68 0xf04 0 69 0xf04
|
||||
0 70 0xf04 0 71 0xf04 0 72 0xf04
|
||||
0 73 0xf04 0 74 0xf04 0 75 0xf04
|
||||
0 76 0xf04 0 77 0xf04 0 78 0xf04
|
||||
0 79 0xf04>;
|
||||
};
|
||||
};
|
||||
general-purpose {
|
||||
gp-0 {
|
||||
qrange = <4000 64>;
|
||||
};
|
||||
netcp-tx {
|
||||
qrange = <896 128>;
|
||||
qalloc-by-id;
|
||||
};
|
||||
};
|
||||
};
|
||||
descriptor-regions {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
region-12 {
|
||||
id = <12>;
|
||||
region-spec = <8192 128>; /* num_desc desc_size */
|
||||
link-index = <0x4000>;
|
||||
};
|
||||
};
|
||||
}; /* qmss */
|
||||
|
||||
knav_dmas: knav_dmas@0 {
|
||||
compatible = "ti,keystone-navigator-dma";
|
||||
clocks = <&papllclk>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
ti,navigator-cloud-address = <0x23a80000 0x23a90000
|
||||
0x23a80000 0x23a90000>;
|
||||
|
||||
dma_gbe: dma_gbe@0 {
|
||||
reg = <0x24186000 0x100>,
|
||||
<0x24187000 0x2a0>,
|
||||
<0x24188000 0xb60>,
|
||||
<0x24186100 0x80>,
|
||||
<0x24189000 0x1000>;
|
||||
reg-names = "global", "txchan", "rxchan",
|
||||
"txsched", "rxflow";
|
||||
};
|
||||
};
|
||||
|
||||
netcp: netcp@24000000 {
|
||||
reg = <0x2620110 0x8>;
|
||||
reg-names = "efuse";
|
||||
compatible = "ti,netcp-1.0";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
/* NetCP address range */
|
||||
ranges = <0 0x24000000 0x1000000>;
|
||||
|
||||
clocks = <&papllclk>, <&clkcpgmac>, <&chipclk12>;
|
||||
dma-coherent;
|
||||
|
||||
ti,navigator-dmas = <&dma_gbe 0>,
|
||||
<&dma_gbe 8>,
|
||||
<&dma_gbe 0>;
|
||||
ti,navigator-dma-names = "netrx0", "netrx1", "nettx";
|
||||
|
||||
netcp-devices {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
gbe@200000 { /* ETHSS */
|
||||
label = "netcp-gbe";
|
||||
compatible = "ti,netcp-gbe-9";
|
||||
reg = <0x200000 0x900>, <0x220000 0x20000>;
|
||||
/* enable-ale; */
|
||||
tx-queue = <896>;
|
||||
tx-channel = "nettx";
|
||||
|
||||
interfaces {
|
||||
gbe0: interface-0 {
|
||||
slave-port = <0>;
|
||||
link-interface = <1>;
|
||||
phy-handle = <ðphy0>;
|
||||
};
|
||||
gbe1: interface-1 {
|
||||
slave-port = <1>;
|
||||
link-interface = <1>;
|
||||
phy-handle = <ðphy1>;
|
||||
};
|
||||
};
|
||||
|
||||
secondary-slave-ports {
|
||||
port-2 {
|
||||
slave-port = <2>;
|
||||
link-interface = <2>;
|
||||
};
|
||||
port-3 {
|
||||
slave-port = <3>;
|
||||
link-interface = <2>;
|
||||
};
|
||||
port-4 {
|
||||
slave-port = <4>;
|
||||
link-interface = <2>;
|
||||
};
|
||||
port-5 {
|
||||
slave-port = <5>;
|
||||
link-interface = <2>;
|
||||
};
|
||||
port-6 {
|
||||
slave-port = <6>;
|
||||
link-interface = <2>;
|
||||
};
|
||||
port-7 {
|
||||
slave-port = <7>;
|
||||
link-interface = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
netcp-interfaces {
|
||||
interface-0 {
|
||||
rx-channel = "netrx0";
|
||||
rx-pool = <1024 12>;
|
||||
tx-pool = <1024 12>;
|
||||
rx-queue-depth = <128 128 0 0>;
|
||||
rx-buffer-size = <1518 4096 0 0>;
|
||||
rx-queue = <528>;
|
||||
tx-completion-queue = <530>;
|
||||
efuse-mac = <1>;
|
||||
netcp-gbe = <&gbe0>;
|
||||
|
||||
};
|
||||
interface-1 {
|
||||
rx-channel = "netrx1";
|
||||
rx-pool = <1024 12>;
|
||||
tx-pool = <1024 12>;
|
||||
rx-queue-depth = <128 128 0 0>;
|
||||
rx-buffer-size = <1518 4096 0 0>;
|
||||
rx-queue = <529>;
|
||||
tx-completion-queue = <531>;
|
||||
efuse-mac = <0>;
|
||||
local-mac-address = [02 18 31 7e 3e 00];
|
||||
netcp-gbe = <&gbe1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
147
arch/arm/dts/k2e.dtsi
Normal file
147
arch/arm/dts/k2e.dtsi
Normal file
|
|
@ -0,0 +1,147 @@
|
|||
/*
|
||||
* Copyright 2013-2014 Texas Instruments, Inc.
|
||||
*
|
||||
* Keystone 2 Edison soc device tree
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/ {
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
cpu@0 {
|
||||
compatible = "arm,cortex-a15";
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
compatible = "arm,cortex-a15";
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
};
|
||||
|
||||
cpu@2 {
|
||||
compatible = "arm,cortex-a15";
|
||||
device_type = "cpu";
|
||||
reg = <2>;
|
||||
};
|
||||
|
||||
cpu@3 {
|
||||
compatible = "arm,cortex-a15";
|
||||
device_type = "cpu";
|
||||
reg = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
/include/ "k2e-clocks.dtsi"
|
||||
|
||||
usb: usb@2680000 {
|
||||
interrupts = <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>;
|
||||
dwc3@2690000 {
|
||||
interrupts = <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
};
|
||||
|
||||
usb1_phy: usb_phy@2620750 {
|
||||
compatible = "ti,keystone-usbphy";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x2620750 24>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb1: usb@25000000 {
|
||||
compatible = "ti,keystone-dwc3";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x25000000 0x10000>;
|
||||
clocks = <&clkusb1>;
|
||||
clock-names = "usb";
|
||||
interrupts = <GIC_SPI 414 IRQ_TYPE_EDGE_RISING>;
|
||||
ranges;
|
||||
dma-coherent;
|
||||
dma-ranges;
|
||||
status = "disabled";
|
||||
|
||||
dwc3@25010000 {
|
||||
compatible = "synopsys,dwc3";
|
||||
reg = <0x25010000 0x70000>;
|
||||
interrupts = <GIC_SPI 414 IRQ_TYPE_EDGE_RISING>;
|
||||
usb-phy = <&usb1_phy>, <&usb1_phy>;
|
||||
};
|
||||
};
|
||||
|
||||
dspgpio0: keystone_dsp_gpio@02620240 {
|
||||
compatible = "ti,keystone-dsp-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio,syscon-dev = <&devctrl 0x240>;
|
||||
};
|
||||
|
||||
pcie1: pcie@21020000 {
|
||||
compatible = "ti,keystone-pcie","snps,dw-pcie";
|
||||
clocks = <&clkpcie1>;
|
||||
clock-names = "pcie";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
reg = <0x21021000 0x2000>, <0x21020000 0x1000>, <0x02620128 4>;
|
||||
ranges = <0x81000000 0 0 0x23260000 0x4000 0x4000
|
||||
0x82000000 0 0x60000000 0x60000000 0 0x10000000>;
|
||||
|
||||
status = "disabled";
|
||||
device_type = "pci";
|
||||
num-lanes = <2>;
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie_intc1 0>, /* INT A */
|
||||
<0 0 0 2 &pcie_intc1 1>, /* INT B */
|
||||
<0 0 0 3 &pcie_intc1 2>, /* INT C */
|
||||
<0 0 0 4 &pcie_intc1 3>; /* INT D */
|
||||
|
||||
pcie_msi_intc1: msi-interrupt-controller {
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 378 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 379 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 380 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 381 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 382 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 383 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 384 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
|
||||
pcie_intc1: legacy-interrupt-controller {
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 374 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 375 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 376 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
};
|
||||
|
||||
mdio: mdio@24200f00 {
|
||||
compatible = "ti,keystone_mdio", "ti,davinci_mdio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x24200f00 0x100>;
|
||||
status = "disabled";
|
||||
clocks = <&clkcpgmac>;
|
||||
clock-names = "fck";
|
||||
bus_freq = <2500000>;
|
||||
};
|
||||
/include/ "k2e-netcp.dtsi"
|
||||
};
|
||||
};
|
||||
21
arch/arm/dts/k2g-evm.dts
Normal file
21
arch/arm/dts/k2g-evm.dts
Normal file
|
|
@ -0,0 +1,21 @@
|
|||
/*
|
||||
* Copyright 2014 Texas Instruments, Inc.
|
||||
*
|
||||
* Keystone 2 Galileo EVM device tree
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
/dts-v1/;
|
||||
|
||||
#include "k2g.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "ti,k2g-evm","ti,keystone";
|
||||
model = "Texas Instruments Keystone 2 Galileo EVM";
|
||||
|
||||
chosen {
|
||||
stdout-path = &uart0;
|
||||
};
|
||||
};
|
||||
72
arch/arm/dts/k2g.dtsi
Normal file
72
arch/arm/dts/k2g.dtsi
Normal file
|
|
@ -0,0 +1,72 @@
|
|||
/*
|
||||
* Copyright 2014 Texas Instruments, Inc.
|
||||
*
|
||||
* Keystone 2 Galileo soc device tree
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Texas Instruments Keystone 2 SoC";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x80000000>;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
cpu@0 {
|
||||
compatible = "arm,cortex-a15";
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
gic: interrupt-controller {
|
||||
compatible = "arm,cortex-a15-gic";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
reg = <0x0 0x02561000 0x0 0x1000>,
|
||||
<0x0 0x02562000 0x0 0x2000>,
|
||||
<0x0 0x02564000 0x0 0x1000>,
|
||||
<0x0 0x02566000 0x0 0x2000>;
|
||||
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
|
||||
IRQ_TYPE_LEVEL_HIGH)>;
|
||||
};
|
||||
|
||||
soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "ti,keystone","simple-bus";
|
||||
interrupt-parent = <&gic>;
|
||||
ranges;
|
||||
|
||||
uart0: serial@02530c00 {
|
||||
compatible = "ns16550a";
|
||||
current-speed = <115200>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
reg = <0x02530c00 0x100>;
|
||||
clock-names = "uart";
|
||||
interrupts = <GIC_SPI 164 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
425
arch/arm/dts/k2hk-clocks.dtsi
Normal file
425
arch/arm/dts/k2hk-clocks.dtsi
Normal file
|
|
@ -0,0 +1,425 @@
|
|||
/*
|
||||
* Copyright 2013-2014 Texas Instruments, Inc.
|
||||
*
|
||||
* Keystone 2 Kepler/Hawking SoC clock nodes
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
clocks {
|
||||
armpllclk: armpllclk@2620370 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,pll-clock";
|
||||
clocks = <&refclkarm>;
|
||||
clock-output-names = "arm-pll-clk";
|
||||
reg = <0x02620370 4>;
|
||||
reg-names = "control";
|
||||
};
|
||||
|
||||
mainpllclk: mainpllclk@2310110 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,main-pll-clock";
|
||||
clocks = <&refclksys>;
|
||||
reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
|
||||
reg-names = "control", "multiplier", "post-divider";
|
||||
};
|
||||
|
||||
papllclk: papllclk@2620358 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,pll-clock";
|
||||
clocks = <&refclkpass>;
|
||||
clock-output-names = "papllclk";
|
||||
reg = <0x02620358 4>;
|
||||
reg-names = "control";
|
||||
};
|
||||
|
||||
ddr3apllclk: ddr3apllclk@2620360 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,pll-clock";
|
||||
clocks = <&refclkddr3a>;
|
||||
clock-output-names = "ddr-3a-pll-clk";
|
||||
reg = <0x02620360 4>;
|
||||
reg-names = "control";
|
||||
};
|
||||
|
||||
ddr3bpllclk: ddr3bpllclk@2620368 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,pll-clock";
|
||||
clocks = <&refclkddr3b>;
|
||||
clock-output-names = "ddr-3b-pll-clk";
|
||||
reg = <0x02620368 4>;
|
||||
reg-names = "control";
|
||||
};
|
||||
|
||||
clktsip: clktsip {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk16>;
|
||||
clock-output-names = "tsip";
|
||||
reg = <0x02350000 0xb00>, <0x02350000 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <0>;
|
||||
};
|
||||
|
||||
clksrio: clksrio {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk1rstiso13>;
|
||||
clock-output-names = "srio";
|
||||
reg = <0x0235002c 0xb00>, <0x02350010 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <4>;
|
||||
};
|
||||
|
||||
clkhyperlink0: clkhyperlink0 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk12>;
|
||||
clock-output-names = "hyperlink-0";
|
||||
reg = <0x02350030 0xb00>, <0x02350014 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <5>;
|
||||
};
|
||||
|
||||
clkgem1: clkgem1 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk1>;
|
||||
clock-output-names = "gem1";
|
||||
reg = <0x02350040 0xb00>, <0x02350024 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <9>;
|
||||
};
|
||||
|
||||
clkgem2: clkgem2 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk1>;
|
||||
clock-output-names = "gem2";
|
||||
reg = <0x02350044 0xb00>, <0x02350028 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <10>;
|
||||
};
|
||||
|
||||
clkgem3: clkgem3 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk1>;
|
||||
clock-output-names = "gem3";
|
||||
reg = <0x02350048 0xb00>, <0x0235002c 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <11>;
|
||||
};
|
||||
|
||||
clkgem4: clkgem4 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk1>;
|
||||
clock-output-names = "gem4";
|
||||
reg = <0x0235004c 0xb00>, <0x02350030 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <12>;
|
||||
};
|
||||
|
||||
clkgem5: clkgem5 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk1>;
|
||||
clock-output-names = "gem5";
|
||||
reg = <0x02350050 0xb00>, <0x02350034 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <13>;
|
||||
};
|
||||
|
||||
clkgem6: clkgem6 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk1>;
|
||||
clock-output-names = "gem6";
|
||||
reg = <0x02350054 0xb00>, <0x02350038 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <14>;
|
||||
};
|
||||
|
||||
clkgem7: clkgem7 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk1>;
|
||||
clock-output-names = "gem7";
|
||||
reg = <0x02350058 0xb00>, <0x0235003c 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <15>;
|
||||
};
|
||||
|
||||
clkddr31: clkddr31 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk13>;
|
||||
clock-output-names = "ddr3-1";
|
||||
reg = <0x02350060 0xb00>, <0x02350040 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <16>;
|
||||
};
|
||||
|
||||
clktac: clktac {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk13>;
|
||||
clock-output-names = "tac";
|
||||
reg = <0x02350064 0xb00>, <0x02350044 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <17>;
|
||||
};
|
||||
|
||||
clkrac01: clkrac01 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk13>;
|
||||
clock-output-names = "rac-01";
|
||||
reg = <0x02350068 0xb00>, <0x02350044 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <17>;
|
||||
};
|
||||
|
||||
clkrac23: clkrac23 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk13>;
|
||||
clock-output-names = "rac-23";
|
||||
reg = <0x0235006c 0xb00>, <0x02350048 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <18>;
|
||||
};
|
||||
|
||||
clkfftc0: clkfftc0 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk13>;
|
||||
clock-output-names = "fftc-0";
|
||||
reg = <0x02350070 0xb00>, <0x0235004c 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <19>;
|
||||
};
|
||||
|
||||
clkfftc1: clkfftc1 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk13>;
|
||||
clock-output-names = "fftc-1";
|
||||
reg = <0x02350074 0xb00>, <0x0235004c 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <19>;
|
||||
};
|
||||
|
||||
clkfftc2: clkfftc2 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk13>;
|
||||
clock-output-names = "fftc-2";
|
||||
reg = <0x02350078 0xb00>, <0x02350050 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <20>;
|
||||
};
|
||||
|
||||
clkfftc3: clkfftc3 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk13>;
|
||||
clock-output-names = "fftc-3";
|
||||
reg = <0x0235007c 0xb00>, <0x02350050 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <20>;
|
||||
};
|
||||
|
||||
clkfftc4: clkfftc4 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk13>;
|
||||
clock-output-names = "fftc-4";
|
||||
reg = <0x02350080 0xb00>, <0x02350050 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <20>;
|
||||
};
|
||||
|
||||
clkfftc5: clkfftc5 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk13>;
|
||||
clock-output-names = "fftc-5";
|
||||
reg = <0x02350084 0xb00>, <0x02350050 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <20>;
|
||||
};
|
||||
|
||||
clkaif: clkaif {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk13>;
|
||||
clock-output-names = "aif";
|
||||
reg = <0x02350088 0xb00>, <0x02350054 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <21>;
|
||||
};
|
||||
|
||||
clktcp3d0: clktcp3d0 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk13>;
|
||||
clock-output-names = "tcp3d-0";
|
||||
reg = <0x0235008c 0xb00>, <0x02350058 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <22>;
|
||||
};
|
||||
|
||||
clktcp3d1: clktcp3d1 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk13>;
|
||||
clock-output-names = "tcp3d-1";
|
||||
reg = <0x02350090 0xb00>, <0x02350058 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <22>;
|
||||
};
|
||||
|
||||
clktcp3d2: clktcp3d2 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk13>;
|
||||
clock-output-names = "tcp3d-2";
|
||||
reg = <0x02350094 0xb00>, <0x0235005c 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <23>;
|
||||
};
|
||||
|
||||
clktcp3d3: clktcp3d3 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk13>;
|
||||
clock-output-names = "tcp3d-3";
|
||||
reg = <0x02350098 0xb00>, <0x0235005c 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <23>;
|
||||
};
|
||||
|
||||
clkvcp0: clkvcp0 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk13>;
|
||||
clock-output-names = "vcp-0";
|
||||
reg = <0x0235009c 0xb00>, <0x02350060 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <24>;
|
||||
};
|
||||
|
||||
clkvcp1: clkvcp1 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk13>;
|
||||
clock-output-names = "vcp-1";
|
||||
reg = <0x023500a0 0xb00>, <0x02350060 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <24>;
|
||||
};
|
||||
|
||||
clkvcp2: clkvcp2 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk13>;
|
||||
clock-output-names = "vcp-2";
|
||||
reg = <0x023500a4 0xb00>, <0x02350060 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <24>;
|
||||
};
|
||||
|
||||
clkvcp3: clkvcp3 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk13>;
|
||||
clock-output-names = "vcp-3";
|
||||
reg = <0x023500a8 0xb00>, <0x02350060 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <24>;
|
||||
};
|
||||
|
||||
clkvcp4: clkvcp4 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk13>;
|
||||
clock-output-names = "vcp-4";
|
||||
reg = <0x023500ac 0xb00>, <0x02350064 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <25>;
|
||||
};
|
||||
|
||||
clkvcp5: clkvcp5 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk13>;
|
||||
clock-output-names = "vcp-5";
|
||||
reg = <0x023500b0 0xb00>, <0x02350064 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <25>;
|
||||
};
|
||||
|
||||
clkvcp6: clkvcp6 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk13>;
|
||||
clock-output-names = "vcp-6";
|
||||
reg = <0x023500b4 0xb00>, <0x02350064 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <25>;
|
||||
};
|
||||
|
||||
clkvcp7: clkvcp7 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk13>;
|
||||
clock-output-names = "vcp-7";
|
||||
reg = <0x023500b8 0xb00>, <0x02350064 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <25>;
|
||||
};
|
||||
|
||||
clkbcp: clkbcp {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk13>;
|
||||
clock-output-names = "bcp";
|
||||
reg = <0x023500bc 0xb00>, <0x02350068 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <26>;
|
||||
};
|
||||
|
||||
clkdxb: clkdxb {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk13>;
|
||||
clock-output-names = "dxb";
|
||||
reg = <0x023500c0 0xb00>, <0x0235006c 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <27>;
|
||||
};
|
||||
|
||||
clkhyperlink1: clkhyperlink1 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk12>;
|
||||
clock-output-names = "hyperlink-1";
|
||||
reg = <0x023500c4 0xb00>, <0x02350070 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <28>;
|
||||
};
|
||||
|
||||
clkxge: clkxge {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk13>;
|
||||
clock-output-names = "xge";
|
||||
reg = <0x023500c8 0xb00>, <0x02350074 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <29>;
|
||||
};
|
||||
};
|
||||
182
arch/arm/dts/k2hk-evm.dts
Normal file
182
arch/arm/dts/k2hk-evm.dts
Normal file
|
|
@ -0,0 +1,182 @@
|
|||
/*
|
||||
* Copyright 2013-2014 Texas Instruments, Inc.
|
||||
*
|
||||
* Keystone 2 Kepler/Hawking EVM device tree
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
/dts-v1/;
|
||||
|
||||
#include "keystone.dtsi"
|
||||
#include "k2hk.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "ti,k2hk-evm","ti,keystone";
|
||||
model = "Texas Instruments Keystone 2 Kepler/Hawking EVM";
|
||||
|
||||
soc {
|
||||
clocks {
|
||||
refclksys: refclksys {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <122880000>;
|
||||
clock-output-names = "refclk-sys";
|
||||
};
|
||||
|
||||
refclkpass: refclkpass {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <122880000>;
|
||||
clock-output-names = "refclk-pass";
|
||||
};
|
||||
|
||||
refclkarm: refclkarm {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <125000000>;
|
||||
clock-output-names = "refclk-arm";
|
||||
};
|
||||
|
||||
refclkddr3a: refclkddr3a {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <100000000>;
|
||||
clock-output-names = "refclk-ddr3a";
|
||||
};
|
||||
|
||||
refclkddr3b: refclkddr3b {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <100000000>;
|
||||
clock-output-names = "refclk-ddr3b";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
debug1_1 {
|
||||
label = "keystone:green:debug1";
|
||||
gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; /* 12 */
|
||||
};
|
||||
|
||||
debug1_2 {
|
||||
label = "keystone:red:debug1";
|
||||
gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; /* 13 */
|
||||
};
|
||||
|
||||
debug2 {
|
||||
label = "keystone:blue:debug2";
|
||||
gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; /* 14 */
|
||||
};
|
||||
|
||||
debug3 {
|
||||
label = "keystone:blue:debug3";
|
||||
gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; /* 15 */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&usb_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&aemif {
|
||||
cs0 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
clock-ranges;
|
||||
ranges;
|
||||
|
||||
ti,cs-chipselect = <0>;
|
||||
/* all timings in nanoseconds */
|
||||
ti,cs-min-turnaround-ns = <12>;
|
||||
ti,cs-read-hold-ns = <6>;
|
||||
ti,cs-read-strobe-ns = <23>;
|
||||
ti,cs-read-setup-ns = <9>;
|
||||
ti,cs-write-hold-ns = <8>;
|
||||
ti,cs-write-strobe-ns = <23>;
|
||||
ti,cs-write-setup-ns = <8>;
|
||||
|
||||
nand@0,0 {
|
||||
compatible = "ti,keystone-nand","ti,davinci-nand";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0 0 0x4000000
|
||||
1 0 0x0000100>;
|
||||
|
||||
ti,davinci-chipselect = <0>;
|
||||
ti,davinci-mask-ale = <0x2000>;
|
||||
ti,davinci-mask-cle = <0x4000>;
|
||||
ti,davinci-mask-chipsel = <0>;
|
||||
nand-ecc-mode = "hw";
|
||||
ti,davinci-ecc-bits = <4>;
|
||||
nand-on-flash-bbt;
|
||||
|
||||
partition@0 {
|
||||
label = "u-boot";
|
||||
reg = <0x0 0x100000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@100000 {
|
||||
label = "params";
|
||||
reg = <0x100000 0x80000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@180000 {
|
||||
label = "ubifs";
|
||||
reg = <0x180000 0x1fe80000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
dtt@50 {
|
||||
compatible = "at,24c1024";
|
||||
reg = <0x50>;
|
||||
};
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
nor_flash: n25q128a11@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "Micron,n25q128a11";
|
||||
spi-max-frequency = <54000000>;
|
||||
m25p,fast-read;
|
||||
reg = <0>;
|
||||
|
||||
partition@0 {
|
||||
label = "u-boot-spl";
|
||||
reg = <0x0 0x80000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@1 {
|
||||
label = "misc";
|
||||
reg = <0x80000 0xf80000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mdio {
|
||||
status = "ok";
|
||||
ethphy0: ethernet-phy@0 {
|
||||
compatible = "marvell,88E1111", "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
ethphy1: ethernet-phy@1 {
|
||||
compatible = "marvell,88E1111", "ethernet-phy-ieee802.3-c22";
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
208
arch/arm/dts/k2hk-netcp.dtsi
Normal file
208
arch/arm/dts/k2hk-netcp.dtsi
Normal file
|
|
@ -0,0 +1,208 @@
|
|||
/*
|
||||
* Device Tree Source for Keystone 2 Hawking Netcp driver
|
||||
*
|
||||
* Copyright 2015 Texas Instruments, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
qmss: qmss@2a40000 {
|
||||
compatible = "ti,keystone-navigator-qmss";
|
||||
dma-coherent;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
clocks = <&chipclk13>;
|
||||
ranges;
|
||||
queue-range = <0 0x4000>;
|
||||
linkram0 = <0x100000 0x8000>;
|
||||
linkram1 = <0x0 0x10000>;
|
||||
|
||||
qmgrs {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
qmgr0 {
|
||||
managed-queues = <0 0x2000>;
|
||||
reg = <0x2a40000 0x20000>,
|
||||
<0x2a06000 0x400>,
|
||||
<0x2a02000 0x1000>,
|
||||
<0x2a03000 0x1000>,
|
||||
<0x23a80000 0x20000>,
|
||||
<0x2a80000 0x20000>;
|
||||
reg-names = "peek", "status", "config",
|
||||
"region", "push", "pop";
|
||||
};
|
||||
|
||||
qmgr1 {
|
||||
managed-queues = <0x2000 0x2000>;
|
||||
reg = <0x2a60000 0x20000>,
|
||||
<0x2a06400 0x400>,
|
||||
<0x2a04000 0x1000>,
|
||||
<0x2a05000 0x1000>,
|
||||
<0x23aa0000 0x20000>,
|
||||
<0x2aa0000 0x20000>;
|
||||
reg-names = "peek", "status", "config",
|
||||
"region", "push", "pop";
|
||||
};
|
||||
};
|
||||
queue-pools {
|
||||
qpend {
|
||||
qpend-0 {
|
||||
qrange = <658 8>;
|
||||
interrupts =<0 40 0xf04 0 41 0xf04 0 42 0xf04
|
||||
0 43 0xf04 0 44 0xf04 0 45 0xf04
|
||||
0 46 0xf04 0 47 0xf04>;
|
||||
};
|
||||
qpend-1 {
|
||||
qrange = <8704 16>;
|
||||
interrupts = <0 48 0xf04 0 49 0xf04 0 50 0xf04
|
||||
0 51 0xf04 0 52 0xf04 0 53 0xf04
|
||||
0 54 0xf04 0 55 0xf04 0 56 0xf04
|
||||
0 57 0xf04 0 58 0xf04 0 59 0xf04
|
||||
0 60 0xf04 0 61 0xf04 0 62 0xf04
|
||||
0 63 0xf04>;
|
||||
qalloc-by-id;
|
||||
};
|
||||
qpend-2 {
|
||||
qrange = <8720 16>;
|
||||
interrupts = <0 64 0xf04 0 65 0xf04 0 66 0xf04
|
||||
0 59 0xf04 0 68 0xf04 0 69 0xf04
|
||||
0 70 0xf04 0 71 0xf04 0 72 0xf04
|
||||
0 73 0xf04 0 74 0xf04 0 75 0xf04
|
||||
0 76 0xf04 0 77 0xf04 0 78 0xf04
|
||||
0 79 0xf04>;
|
||||
};
|
||||
};
|
||||
general-purpose {
|
||||
gp-0 {
|
||||
qrange = <4000 64>;
|
||||
};
|
||||
netcp-tx {
|
||||
qrange = <640 9>;
|
||||
qalloc-by-id;
|
||||
};
|
||||
netcpx-tx {
|
||||
qrange = <8752 8>;
|
||||
qalloc-by-id;
|
||||
};
|
||||
};
|
||||
};
|
||||
descriptor-regions {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
region-12 {
|
||||
id = <12>;
|
||||
region-spec = <8192 128>; /* num_desc desc_size */
|
||||
link-index = <0x4000>;
|
||||
};
|
||||
};
|
||||
}; /* qmss */
|
||||
|
||||
knav_dmas: knav_dmas@0 {
|
||||
compatible = "ti,keystone-navigator-dma";
|
||||
clocks = <&papllclk>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
ti,navigator-cloud-address = <0x23a80000 0x23a90000
|
||||
0x23aa0000 0x23ab0000>;
|
||||
|
||||
dma_gbe: dma_gbe@0 {
|
||||
reg = <0x2004000 0x100>,
|
||||
<0x2004400 0x120>,
|
||||
<0x2004800 0x300>,
|
||||
<0x2004c00 0x120>,
|
||||
<0x2005000 0x400>;
|
||||
reg-names = "global", "txchan", "rxchan",
|
||||
"txsched", "rxflow";
|
||||
};
|
||||
};
|
||||
|
||||
netcp: netcp@2000000 {
|
||||
reg = <0x2620110 0x8>;
|
||||
reg-names = "efuse";
|
||||
compatible = "ti,netcp-1.0";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
/* NetCP address range */
|
||||
ranges = <0 0x2000000 0x100000>;
|
||||
|
||||
clocks = <&papllclk>, <&clkcpgmac>, <&chipclk12>;
|
||||
dma-coherent;
|
||||
|
||||
ti,navigator-dmas = <&dma_gbe 22>,
|
||||
<&dma_gbe 23>,
|
||||
<&dma_gbe 8>;
|
||||
ti,navigator-dma-names = "netrx0", "netrx1", "nettx";
|
||||
|
||||
netcp-devices {
|
||||
ranges;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
gbe@90000 { /* ETHSS */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
label = "netcp-gbe";
|
||||
compatible = "ti,netcp-gbe";
|
||||
reg = <0x90000 0x300>, <0x90400 0x400>, <0x90800 0x700>;
|
||||
/* enable-ale; */
|
||||
tx-queue = <648>;
|
||||
tx-channel = "nettx";
|
||||
|
||||
interfaces {
|
||||
gbe0: interface-0 {
|
||||
slave-port = <0>;
|
||||
link-interface = <1>;
|
||||
phy-handle = <ðphy0>;
|
||||
};
|
||||
gbe1: interface-1 {
|
||||
slave-port = <1>;
|
||||
link-interface = <1>;
|
||||
phy-handle = <ðphy1>;
|
||||
};
|
||||
};
|
||||
|
||||
secondary-slave-ports {
|
||||
port-2 {
|
||||
slave-port = <2>;
|
||||
link-interface = <2>;
|
||||
};
|
||||
port-3 {
|
||||
slave-port = <3>;
|
||||
link-interface = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
netcp-interfaces {
|
||||
interface-0 {
|
||||
rx-channel = "netrx0";
|
||||
rx-pool = <1024 12>;
|
||||
tx-pool = <1024 12>;
|
||||
rx-queue-depth = <128 128 0 0>;
|
||||
rx-buffer-size = <1518 4096 0 0>;
|
||||
rx-queue = <8704>;
|
||||
tx-completion-queue = <8706>;
|
||||
efuse-mac = <1>;
|
||||
netcp-gbe = <&gbe0>;
|
||||
|
||||
};
|
||||
interface-1 {
|
||||
rx-channel = "netrx1";
|
||||
rx-pool = <1024 12>;
|
||||
tx-pool = <1024 12>;
|
||||
rx-queue-depth = <128 128 0 0>;
|
||||
rx-buffer-size = <1518 4096 0 0>;
|
||||
rx-queue = <8705>;
|
||||
tx-completion-queue = <8707>;
|
||||
efuse-mac = <0>;
|
||||
local-mac-address = [02 18 31 7e 3e 6f];
|
||||
netcp-gbe = <&gbe1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
114
arch/arm/dts/k2hk.dtsi
Normal file
114
arch/arm/dts/k2hk.dtsi
Normal file
|
|
@ -0,0 +1,114 @@
|
|||
/*
|
||||
* Copyright 2013-2014 Texas Instruments, Inc.
|
||||
*
|
||||
* Keystone 2 Kepler/Hawking soc specific device tree
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/ {
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
cpu@0 {
|
||||
compatible = "arm,cortex-a15";
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
compatible = "arm,cortex-a15";
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
};
|
||||
|
||||
cpu@2 {
|
||||
compatible = "arm,cortex-a15";
|
||||
device_type = "cpu";
|
||||
reg = <2>;
|
||||
};
|
||||
|
||||
cpu@3 {
|
||||
compatible = "arm,cortex-a15";
|
||||
device_type = "cpu";
|
||||
reg = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
/include/ "k2hk-clocks.dtsi"
|
||||
|
||||
dspgpio0: keystone_dsp_gpio@02620240 {
|
||||
compatible = "ti,keystone-dsp-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio,syscon-dev = <&devctrl 0x240>;
|
||||
};
|
||||
|
||||
dspgpio1: keystone_dsp_gpio@2620244 {
|
||||
compatible = "ti,keystone-dsp-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio,syscon-dev = <&devctrl 0x244>;
|
||||
};
|
||||
|
||||
dspgpio2: keystone_dsp_gpio@2620248 {
|
||||
compatible = "ti,keystone-dsp-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio,syscon-dev = <&devctrl 0x248>;
|
||||
};
|
||||
|
||||
dspgpio3: keystone_dsp_gpio@262024c {
|
||||
compatible = "ti,keystone-dsp-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio,syscon-dev = <&devctrl 0x24c>;
|
||||
};
|
||||
|
||||
dspgpio4: keystone_dsp_gpio@2620250 {
|
||||
compatible = "ti,keystone-dsp-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio,syscon-dev = <&devctrl 0x250>;
|
||||
};
|
||||
|
||||
dspgpio5: keystone_dsp_gpio@2620254 {
|
||||
compatible = "ti,keystone-dsp-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio,syscon-dev = <&devctrl 0x254>;
|
||||
};
|
||||
|
||||
dspgpio6: keystone_dsp_gpio@2620258 {
|
||||
compatible = "ti,keystone-dsp-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio,syscon-dev = <&devctrl 0x258>;
|
||||
};
|
||||
|
||||
dspgpio7: keystone_dsp_gpio@262025c {
|
||||
compatible = "ti,keystone-dsp-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio,syscon-dev = <&devctrl 0x25c>;
|
||||
};
|
||||
|
||||
mdio: mdio@02090300 {
|
||||
compatible = "ti,keystone_mdio", "ti,davinci_mdio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x02090300 0x100>;
|
||||
status = "disabled";
|
||||
clocks = <&clkcpgmac>;
|
||||
clock-names = "fck";
|
||||
bus_freq = <2500000>;
|
||||
};
|
||||
/include/ "k2hk-netcp.dtsi"
|
||||
};
|
||||
};
|
||||
266
arch/arm/dts/k2l-clocks.dtsi
Normal file
266
arch/arm/dts/k2l-clocks.dtsi
Normal file
|
|
@ -0,0 +1,266 @@
|
|||
/*
|
||||
* Copyright 2013-2014 Texas Instruments, Inc.
|
||||
*
|
||||
* Keystone 2 lamarr SoC clock nodes
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
clocks {
|
||||
armpllclk: armpllclk@2620370 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,pll-clock";
|
||||
clocks = <&refclksys>;
|
||||
clock-output-names = "arm-pll-clk";
|
||||
reg = <0x02620370 4>;
|
||||
reg-names = "control";
|
||||
};
|
||||
|
||||
mainpllclk: mainpllclk@2310110 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,main-pll-clock";
|
||||
clocks = <&refclksys>;
|
||||
reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
|
||||
reg-names = "control", "multiplier", "post-divider";
|
||||
};
|
||||
|
||||
papllclk: papllclk@2620358 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,pll-clock";
|
||||
clocks = <&refclksys>;
|
||||
clock-output-names = "papllclk";
|
||||
reg = <0x02620358 4>;
|
||||
reg-names = "control";
|
||||
};
|
||||
|
||||
ddr3apllclk: ddr3apllclk@2620360 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,pll-clock";
|
||||
clocks = <&refclksys>;
|
||||
clock-output-names = "ddr-3a-pll-clk";
|
||||
reg = <0x02620360 4>;
|
||||
reg-names = "control";
|
||||
};
|
||||
|
||||
clkdfeiqnsys: clkdfeiqnsys {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk12>;
|
||||
clock-output-names = "dfe";
|
||||
reg-names = "control", "domain";
|
||||
reg = <0x02350004 0xb00>, <0x02350000 0x400>;
|
||||
domain-id = <0>;
|
||||
};
|
||||
|
||||
clkpcie1: clkpcie1 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk12>;
|
||||
clock-output-names = "pcie";
|
||||
reg = <0x0235002c 0xb00>, <0x02350000 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <4>;
|
||||
};
|
||||
|
||||
clkgem1: clkgem1 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk1>;
|
||||
clock-output-names = "gem1";
|
||||
reg = <0x02350040 0xb00>, <0x02350024 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <9>;
|
||||
};
|
||||
|
||||
clkgem2: clkgem2 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk1>;
|
||||
clock-output-names = "gem2";
|
||||
reg = <0x02350044 0xb00>, <0x02350028 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <10>;
|
||||
};
|
||||
|
||||
clkgem3: clkgem3 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk1>;
|
||||
clock-output-names = "gem3";
|
||||
reg = <0x02350048 0xb00>, <0x0235002c 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <11>;
|
||||
};
|
||||
|
||||
clktac: clktac {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk13>;
|
||||
clock-output-names = "tac";
|
||||
reg = <0x02350064 0xb00>, <0x02350044 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <17>;
|
||||
};
|
||||
|
||||
clkrac: clkrac {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk13>;
|
||||
clock-output-names = "rac";
|
||||
reg = <0x02350068 0xb00>, <0x02350044 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <17>;
|
||||
};
|
||||
|
||||
clkdfepd0: clkdfepd0 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk13>;
|
||||
clock-output-names = "dfe-pd0";
|
||||
reg = <0x0235006c 0xb00>, <0x02350044 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <18>;
|
||||
};
|
||||
|
||||
clkfftc0: clkfftc0 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk13>;
|
||||
clock-output-names = "fftc-0";
|
||||
reg = <0x02350070 0xb00>, <0x0235004c 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <19>;
|
||||
};
|
||||
|
||||
clkosr: clkosr {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk13>;
|
||||
clock-output-names = "osr";
|
||||
reg = <0x02350088 0xb00>, <0x0235004c 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <21>;
|
||||
};
|
||||
|
||||
clktcp3d0: clktcp3d0 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk13>;
|
||||
clock-output-names = "tcp3d-0";
|
||||
reg = <0x0235008c 0xb00>, <0x02350058 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <22>;
|
||||
};
|
||||
|
||||
clktcp3d1: clktcp3d1 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk13>;
|
||||
clock-output-names = "tcp3d-1";
|
||||
reg = <0x02350094 0xb00>, <0x02350058 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <23>;
|
||||
};
|
||||
|
||||
clkvcp0: clkvcp0 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk13>;
|
||||
clock-output-names = "vcp-0";
|
||||
reg = <0x0235009c 0xb00>, <0x02350060 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <24>;
|
||||
};
|
||||
|
||||
clkvcp1: clkvcp1 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk13>;
|
||||
clock-output-names = "vcp-1";
|
||||
reg = <0x023500a0 0xb00>, <0x02350060 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <24>;
|
||||
};
|
||||
|
||||
clkvcp2: clkvcp2 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk13>;
|
||||
clock-output-names = "vcp-2";
|
||||
reg = <0x023500a4 0xb00>, <0x02350060 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <24>;
|
||||
};
|
||||
|
||||
clkvcp3: clkvcp3 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk13>;
|
||||
clock-output-names = "vcp-3";
|
||||
reg = <0x023500a8 0xb00>, <0x02350060 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <24>;
|
||||
};
|
||||
|
||||
clkbcp: clkbcp {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk13>;
|
||||
clock-output-names = "bcp";
|
||||
reg = <0x023500bc 0xb00>, <0x02350068 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <26>;
|
||||
};
|
||||
|
||||
clkdfepd1: clkdfepd1 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk13>;
|
||||
clock-output-names = "dfe-pd1";
|
||||
reg = <0x023500c0 0xb00>, <0x02350044 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <27>;
|
||||
};
|
||||
|
||||
clkfftc1: clkfftc1 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk13>;
|
||||
clock-output-names = "fftc-1";
|
||||
reg = <0x023500c4 0xb00>, <0x023504c0 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <28>;
|
||||
};
|
||||
|
||||
clkiqnail: clkiqnail {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk13>;
|
||||
clock-output-names = "iqn-ail";
|
||||
reg = <0x023500c8 0xb00>, <0x0235004c 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <29>;
|
||||
};
|
||||
|
||||
clkuart2: clkuart2 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&clkmodrst0>;
|
||||
clock-output-names = "uart2";
|
||||
reg = <0x02350000 0xb00>, <0x02350000 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <0>;
|
||||
};
|
||||
|
||||
clkuart3: clkuart3 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&clkmodrst0>;
|
||||
clock-output-names = "uart3";
|
||||
reg = <0x02350000 0xb00>, <0x02350000 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <0>;
|
||||
};
|
||||
};
|
||||
131
arch/arm/dts/k2l-evm.dts
Normal file
131
arch/arm/dts/k2l-evm.dts
Normal file
|
|
@ -0,0 +1,131 @@
|
|||
/*
|
||||
* Copyright 2014 Texas Instruments, Inc.
|
||||
*
|
||||
* Keystone 2 Lamarr EVM device tree
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
/dts-v1/;
|
||||
|
||||
#include "keystone.dtsi"
|
||||
#include "k2l.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "ti,k2l-evm","ti,keystone";
|
||||
model = "Texas Instruments Keystone 2 Lamarr EVM";
|
||||
|
||||
soc {
|
||||
clocks {
|
||||
refclksys: refclksys {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <122880000>;
|
||||
clock-output-names = "refclk-sys";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&usb_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
dtt@50 {
|
||||
compatible = "at,24c1024";
|
||||
reg = <0x50>;
|
||||
};
|
||||
};
|
||||
|
||||
&aemif {
|
||||
cs0 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
clock-ranges;
|
||||
ranges;
|
||||
|
||||
ti,cs-chipselect = <0>;
|
||||
/* all timings in nanoseconds */
|
||||
ti,cs-min-turnaround-ns = <12>;
|
||||
ti,cs-read-hold-ns = <6>;
|
||||
ti,cs-read-strobe-ns = <23>;
|
||||
ti,cs-read-setup-ns = <9>;
|
||||
ti,cs-write-hold-ns = <8>;
|
||||
ti,cs-write-strobe-ns = <23>;
|
||||
ti,cs-write-setup-ns = <8>;
|
||||
|
||||
nand@0,0 {
|
||||
compatible = "ti,keystone-nand","ti,davinci-nand";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0 0 0x4000000
|
||||
1 0 0x0000100>;
|
||||
|
||||
ti,davinci-chipselect = <0>;
|
||||
ti,davinci-mask-ale = <0x2000>;
|
||||
ti,davinci-mask-cle = <0x4000>;
|
||||
ti,davinci-mask-chipsel = <0>;
|
||||
nand-ecc-mode = "hw";
|
||||
ti,davinci-ecc-bits = <4>;
|
||||
nand-on-flash-bbt;
|
||||
|
||||
partition@0 {
|
||||
label = "u-boot";
|
||||
reg = <0x0 0x100000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@100000 {
|
||||
label = "params";
|
||||
reg = <0x100000 0x80000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@180000 {
|
||||
label = "ubifs";
|
||||
reg = <0x180000 0x7FE80000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
nor_flash: n25q128a11@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "Micron,n25q128a11";
|
||||
spi-max-frequency = <54000000>;
|
||||
m25p,fast-read;
|
||||
reg = <0>;
|
||||
|
||||
partition@0 {
|
||||
label = "u-boot-spl";
|
||||
reg = <0x0 0x80000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@1 {
|
||||
label = "misc";
|
||||
reg = <0x80000 0xf80000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mdio {
|
||||
status = "ok";
|
||||
ethphy0: ethernet-phy@0 {
|
||||
compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
ethphy1: ethernet-phy@1 {
|
||||
compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22";
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
189
arch/arm/dts/k2l-netcp.dtsi
Normal file
189
arch/arm/dts/k2l-netcp.dtsi
Normal file
|
|
@ -0,0 +1,189 @@
|
|||
/*
|
||||
* Device Tree Source for Keystone 2 Lamarr Netcp driver
|
||||
*
|
||||
* Copyright 2015 Texas Instruments, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
qmss: qmss@2a40000 {
|
||||
compatible = "ti,keystone-navigator-qmss";
|
||||
dma-coherent;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
clocks = <&chipclk13>;
|
||||
ranges;
|
||||
queue-range = <0 0x2000>;
|
||||
linkram0 = <0x100000 0x4000>;
|
||||
linkram1 = <0x70000000 0x10000>; /* 1MB OSR mem */
|
||||
|
||||
qmgrs {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
qmgr0 {
|
||||
managed-queues = <0 0x2000>;
|
||||
reg = <0x2a40000 0x20000>,
|
||||
<0x2a06000 0x400>,
|
||||
<0x2a02000 0x1000>,
|
||||
<0x2a03000 0x1000>,
|
||||
<0x23a80000 0x20000>,
|
||||
<0x2a80000 0x20000>;
|
||||
reg-names = "peek", "status", "config",
|
||||
"region", "push", "pop";
|
||||
};
|
||||
};
|
||||
queue-pools {
|
||||
qpend {
|
||||
qpend-0 {
|
||||
qrange = <658 8>;
|
||||
interrupts =<0 40 0xf04 0 41 0xf04 0 42 0xf04
|
||||
0 43 0xf04 0 44 0xf04 0 45 0xf04
|
||||
0 46 0xf04 0 47 0xf04>;
|
||||
};
|
||||
qpend-1 {
|
||||
qrange = <528 16>;
|
||||
interrupts = <0 48 0xf04 0 49 0xf04 0 50 0xf04
|
||||
0 51 0xf04 0 52 0xf04 0 53 0xf04
|
||||
0 54 0xf04 0 55 0xf04 0 56 0xf04
|
||||
0 57 0xf04 0 58 0xf04 0 59 0xf04
|
||||
0 60 0xf04 0 61 0xf04 0 62 0xf04
|
||||
0 63 0xf04>;
|
||||
qalloc-by-id;
|
||||
};
|
||||
qpend-2 {
|
||||
qrange = <544 16>;
|
||||
interrupts = <0 64 0xf04 0 65 0xf04 0 66 0xf04
|
||||
0 59 0xf04 0 68 0xf04 0 69 0xf04
|
||||
0 70 0xf04 0 71 0xf04 0 72 0xf04
|
||||
0 73 0xf04 0 74 0xf04 0 75 0xf04
|
||||
0 76 0xf04 0 77 0xf04 0 78 0xf04
|
||||
0 79 0xf04>;
|
||||
};
|
||||
};
|
||||
general-purpose {
|
||||
gp-0 {
|
||||
qrange = <4000 64>;
|
||||
};
|
||||
netcp-tx {
|
||||
qrange = <896 128>;
|
||||
qalloc-by-id;
|
||||
};
|
||||
};
|
||||
};
|
||||
descriptor-regions {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
region-12 {
|
||||
id = <12>;
|
||||
region-spec = <8192 128>; /* num_desc desc_size */
|
||||
link-index = <0x4000>;
|
||||
};
|
||||
};
|
||||
}; /* qmss */
|
||||
|
||||
knav_dmas: knav_dmas@0 {
|
||||
compatible = "ti,keystone-navigator-dma";
|
||||
clocks = <&papllclk>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
ti,navigator-cloud-address = <0x23a80000 0x23a90000>;
|
||||
|
||||
dma_gbe: dma_gbe@0 {
|
||||
reg = <0x26186000 0x100>,
|
||||
<0x26187000 0x2a0>,
|
||||
<0x26188000 0xb60>,
|
||||
<0x26186100 0x80>,
|
||||
<0x26189000 0x1000>;
|
||||
reg-names = "global", "txchan", "rxchan",
|
||||
"txsched", "rxflow";
|
||||
};
|
||||
};
|
||||
|
||||
netcp: netcp@26000000 {
|
||||
reg = <0x2620110 0x8>;
|
||||
reg-names = "efuse";
|
||||
compatible = "ti,netcp-1.0";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
/* NetCP address range */
|
||||
ranges = <0 0x26000000 0x1000000>;
|
||||
|
||||
clocks = <&papllclk>, <&clkcpgmac>, <&chipclk12>;
|
||||
dma-coherent;
|
||||
|
||||
ti,navigator-dmas = <&dma_gbe 0>,
|
||||
<&dma_gbe 8>,
|
||||
<&dma_gbe 0>;
|
||||
ti,navigator-dma-names = "netrx0", "netrx1", "nettx";
|
||||
|
||||
netcp-devices {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
gbe@200000 { /* ETHSS */
|
||||
label = "netcp-gbe";
|
||||
compatible = "ti,netcp-gbe-5";
|
||||
reg = <0x200000 0x900>, <0x220000 0x20000>;
|
||||
/* enable-ale; */
|
||||
tx-queue = <896>;
|
||||
tx-channel = "nettx";
|
||||
|
||||
interfaces {
|
||||
gbe0: interface-0 {
|
||||
slave-port = <0>;
|
||||
link-interface = <1>;
|
||||
phy-handle = <ðphy0>;
|
||||
};
|
||||
gbe1: interface-1 {
|
||||
slave-port = <1>;
|
||||
link-interface = <1>;
|
||||
phy-handle = <ðphy1>;
|
||||
};
|
||||
};
|
||||
|
||||
secondary-slave-ports {
|
||||
port-2 {
|
||||
slave-port = <2>;
|
||||
link-interface = <2>;
|
||||
};
|
||||
port-3 {
|
||||
slave-port = <3>;
|
||||
link-interface = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
netcp-interfaces {
|
||||
interface-0 {
|
||||
rx-channel = "netrx0";
|
||||
rx-pool = <1024 12>;
|
||||
tx-pool = <1024 12>;
|
||||
rx-queue-depth = <128 128 0 0>;
|
||||
rx-buffer-size = <1518 4096 0 0>;
|
||||
rx-queue = <528>;
|
||||
tx-completion-queue = <530>;
|
||||
efuse-mac = <1>;
|
||||
netcp-gbe = <&gbe0>;
|
||||
|
||||
};
|
||||
interface-1 {
|
||||
rx-channel = "netrx1";
|
||||
rx-pool = <1024 12>;
|
||||
tx-pool = <1024 12>;
|
||||
rx-queue-depth = <128 128 0 0>;
|
||||
rx-buffer-size = <1518 4096 0 0>;
|
||||
rx-queue = <529>;
|
||||
tx-completion-queue = <531>;
|
||||
efuse-mac = <0>;
|
||||
local-mac-address = [02 18 31 7e 3e 7f];
|
||||
netcp-gbe = <&gbe1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
108
arch/arm/dts/k2l.dtsi
Normal file
108
arch/arm/dts/k2l.dtsi
Normal file
|
|
@ -0,0 +1,108 @@
|
|||
/*
|
||||
* Copyright 2014 Texas Instruments, Inc.
|
||||
*
|
||||
* Keystone 2 Lamarr SoC specific device tree
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/ {
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
cpu@0 {
|
||||
compatible = "arm,cortex-a15";
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
compatible = "arm,cortex-a15";
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
/include/ "k2l-clocks.dtsi"
|
||||
|
||||
uart2: serial@02348400 {
|
||||
compatible = "ns16550a";
|
||||
current-speed = <115200>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
reg = <0x02348400 0x100>;
|
||||
clocks = <&clkuart2>;
|
||||
interrupts = <GIC_SPI 432 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
|
||||
uart3: serial@02348800 {
|
||||
compatible = "ns16550a";
|
||||
current-speed = <115200>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
reg = <0x02348800 0x100>;
|
||||
clocks = <&clkuart3>;
|
||||
interrupts = <GIC_SPI 435 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
|
||||
dspgpio0: keystone_dsp_gpio@02620240 {
|
||||
compatible = "ti,keystone-dsp-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio,syscon-dev = <&devctrl 0x240>;
|
||||
};
|
||||
|
||||
dspgpio1: keystone_dsp_gpio@2620244 {
|
||||
compatible = "ti,keystone-dsp-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio,syscon-dev = <&devctrl 0x244>;
|
||||
};
|
||||
|
||||
dspgpio2: keystone_dsp_gpio@2620248 {
|
||||
compatible = "ti,keystone-dsp-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio,syscon-dev = <&devctrl 0x248>;
|
||||
};
|
||||
|
||||
dspgpio3: keystone_dsp_gpio@262024c {
|
||||
compatible = "ti,keystone-dsp-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio,syscon-dev = <&devctrl 0x24c>;
|
||||
};
|
||||
|
||||
mdio: mdio@26200f00 {
|
||||
compatible = "ti,keystone_mdio", "ti,davinci_mdio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x26200f00 0x100>;
|
||||
status = "disabled";
|
||||
clocks = <&clkcpgmac>;
|
||||
clock-names = "fck";
|
||||
bus_freq = <2500000>;
|
||||
};
|
||||
/include/ "k2l-netcp.dtsi"
|
||||
};
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
ti,davinci-spi-num-cs = <5>;
|
||||
};
|
||||
|
||||
&spi1 {
|
||||
ti,davinci-spi-num-cs = <3>;
|
||||
};
|
||||
|
||||
&spi2 {
|
||||
ti,davinci-spi-num-cs = <5>;
|
||||
/* Pin muxed. Enabled and configured by Bootloader */
|
||||
status = "disabled";
|
||||
};
|
||||
414
arch/arm/dts/keystone-clocks.dtsi
Normal file
414
arch/arm/dts/keystone-clocks.dtsi
Normal file
|
|
@ -0,0 +1,414 @@
|
|||
/*
|
||||
* Device Tree Source for Keystone 2 clock tree
|
||||
*
|
||||
* Copyright (C) 2013 Texas Instruments, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
mainmuxclk: mainmuxclk@2310108 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,pll-mux-clock";
|
||||
clocks = <&mainpllclk>, <&refclksys>;
|
||||
reg = <0x02310108 4>;
|
||||
bit-shift = <23>;
|
||||
bit-mask = <1>;
|
||||
clock-output-names = "mainmuxclk";
|
||||
};
|
||||
|
||||
chipclk1: chipclk1 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&mainmuxclk>;
|
||||
clock-div = <1>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "chipclk1";
|
||||
};
|
||||
|
||||
chipclk1rstiso: chipclk1rstiso {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&mainmuxclk>;
|
||||
clock-div = <1>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "chipclk1rstiso";
|
||||
};
|
||||
|
||||
gemtraceclk: gemtraceclk@2310120 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,pll-divider-clock";
|
||||
clocks = <&mainmuxclk>;
|
||||
reg = <0x02310120 4>;
|
||||
bit-shift = <0>;
|
||||
bit-mask = <8>;
|
||||
clock-output-names = "gemtraceclk";
|
||||
};
|
||||
|
||||
chipstmxptclk: chipstmxptclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,pll-divider-clock";
|
||||
clocks = <&mainmuxclk>;
|
||||
reg = <0x02310164 4>;
|
||||
bit-shift = <0>;
|
||||
bit-mask = <8>;
|
||||
clock-output-names = "chipstmxptclk";
|
||||
};
|
||||
|
||||
chipclk12: chipclk12 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&chipclk1>;
|
||||
clock-div = <2>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "chipclk12";
|
||||
};
|
||||
|
||||
chipclk13: chipclk13 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&chipclk1>;
|
||||
clock-div = <3>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "chipclk13";
|
||||
};
|
||||
|
||||
paclk13: paclk13 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&papllclk>;
|
||||
clock-div = <3>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "paclk13";
|
||||
};
|
||||
|
||||
chipclk14: chipclk14 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&chipclk1>;
|
||||
clock-div = <4>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "chipclk14";
|
||||
};
|
||||
|
||||
chipclk16: chipclk16 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&chipclk1>;
|
||||
clock-div = <6>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "chipclk16";
|
||||
};
|
||||
|
||||
chipclk112: chipclk112 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&chipclk1>;
|
||||
clock-div = <12>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "chipclk112";
|
||||
};
|
||||
|
||||
chipclk124: chipclk124 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&chipclk1>;
|
||||
clock-div = <24>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "chipclk114";
|
||||
};
|
||||
|
||||
chipclk1rstiso13: chipclk1rstiso13 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&chipclk1rstiso>;
|
||||
clock-div = <3>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "chipclk1rstiso13";
|
||||
};
|
||||
|
||||
chipclk1rstiso14: chipclk1rstiso14 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&chipclk1rstiso>;
|
||||
clock-div = <4>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "chipclk1rstiso14";
|
||||
};
|
||||
|
||||
chipclk1rstiso16: chipclk1rstiso16 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&chipclk1rstiso>;
|
||||
clock-div = <6>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "chipclk1rstiso16";
|
||||
};
|
||||
|
||||
chipclk1rstiso112: chipclk1rstiso112 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&chipclk1rstiso>;
|
||||
clock-div = <12>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "chipclk1rstiso112";
|
||||
};
|
||||
|
||||
clkmodrst0: clkmodrst0 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk16>;
|
||||
clock-output-names = "modrst0";
|
||||
reg = <0x02350000 0xb00>, <0x02350000 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <0>;
|
||||
};
|
||||
|
||||
|
||||
clkusb: clkusb {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk16>;
|
||||
clock-output-names = "usb";
|
||||
reg = <0x02350008 0xb00>, <0x02350000 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <0>;
|
||||
};
|
||||
|
||||
clkaemifspi: clkaemifspi {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk16>;
|
||||
clock-output-names = "aemif-spi";
|
||||
reg = <0x0235000c 0xb00>, <0x02350000 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <0>;
|
||||
};
|
||||
|
||||
|
||||
clkdebugsstrc: clkdebugsstrc {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk13>;
|
||||
clock-output-names = "debugss-trc";
|
||||
reg = <0x02350014 0xb00>, <0x02350000 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <1>;
|
||||
};
|
||||
|
||||
clktetbtrc: clktetbtrc {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk13>;
|
||||
clock-output-names = "tetb-trc";
|
||||
reg = <0x02350018 0xb00>, <0x02350004 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <1>;
|
||||
};
|
||||
|
||||
clkpa: clkpa {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&paclk13>;
|
||||
clock-output-names = "pa";
|
||||
reg = <0x0235001c 0xb00>, <0x02350008 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <2>;
|
||||
};
|
||||
|
||||
clkcpgmac: clkcpgmac {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&clkpa>;
|
||||
clock-output-names = "cpgmac";
|
||||
reg = <0x02350020 0xb00>, <0x02350008 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <2>;
|
||||
};
|
||||
|
||||
clksa: clksa {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&clkpa>;
|
||||
clock-output-names = "sa";
|
||||
reg = <0x02350024 0xb00>, <0x02350008 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <2>;
|
||||
};
|
||||
|
||||
clkpcie: clkpcie {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk12>;
|
||||
clock-output-names = "pcie";
|
||||
reg = <0x02350028 0xb00>, <0x0235000c 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <3>;
|
||||
};
|
||||
|
||||
clksr: clksr {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk1rstiso112>;
|
||||
clock-output-names = "sr";
|
||||
reg = <0x02350034 0xb00>, <0x02350018 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <6>;
|
||||
};
|
||||
|
||||
clkgem0: clkgem0 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk1>;
|
||||
clock-output-names = "gem0";
|
||||
reg = <0x0235003c 0xb00>, <0x02350020 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <8>;
|
||||
};
|
||||
|
||||
clkddr30: clkddr30 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk12>;
|
||||
clock-output-names = "ddr3-0";
|
||||
reg = <0x0235005c 0xb00>, <0x02350040 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <16>;
|
||||
};
|
||||
|
||||
clkwdtimer0: clkwdtimer0 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&clkmodrst0>;
|
||||
clock-output-names = "timer0";
|
||||
reg = <0x02350000 0xb00>, <0x02350000 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <0>;
|
||||
};
|
||||
|
||||
clkwdtimer1: clkwdtimer1 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&clkmodrst0>;
|
||||
clock-output-names = "timer1";
|
||||
reg = <0x02350000 0xb00>, <0x02350000 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <0>;
|
||||
};
|
||||
|
||||
clkwdtimer2: clkwdtimer2 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&clkmodrst0>;
|
||||
clock-output-names = "timer2";
|
||||
reg = <0x02350000 0xb00>, <0x02350000 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <0>;
|
||||
};
|
||||
|
||||
clkwdtimer3: clkwdtimer3 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&clkmodrst0>;
|
||||
clock-output-names = "timer3";
|
||||
reg = <0x02350000 0xb00>, <0x02350000 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <0>;
|
||||
};
|
||||
|
||||
clktimer15: clktimer15 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&clkmodrst0>;
|
||||
clock-output-names = "timer15";
|
||||
reg = <0x02350000 0xb00>, <0x02350000 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <0>;
|
||||
};
|
||||
|
||||
clkuart0: clkuart0 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&clkmodrst0>;
|
||||
clock-output-names = "uart0";
|
||||
reg = <0x02350000 0xb00>, <0x02350000 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <0>;
|
||||
};
|
||||
|
||||
clkuart1: clkuart1 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&clkmodrst0>;
|
||||
clock-output-names = "uart1";
|
||||
reg = <0x02350000 0xb00>, <0x02350000 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <0>;
|
||||
};
|
||||
|
||||
clkaemif: clkaemif {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&clkaemifspi>;
|
||||
clock-output-names = "aemif";
|
||||
reg = <0x02350000 0xb00>, <0x02350000 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <0>;
|
||||
};
|
||||
|
||||
clkusim: clkusim {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&clkmodrst0>;
|
||||
clock-output-names = "usim";
|
||||
reg = <0x02350000 0xb00>, <0x02350000 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <0>;
|
||||
};
|
||||
|
||||
clki2c: clki2c {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&clkmodrst0>;
|
||||
clock-output-names = "i2c";
|
||||
reg = <0x02350000 0xb00>, <0x02350000 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <0>;
|
||||
};
|
||||
|
||||
clkspi: clkspi {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&clkaemifspi>;
|
||||
clock-output-names = "spi";
|
||||
reg = <0x02350000 0xb00>, <0x02350000 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <0>;
|
||||
};
|
||||
|
||||
clkgpio: clkgpio {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&clkmodrst0>;
|
||||
clock-output-names = "gpio";
|
||||
reg = <0x02350000 0xb00>, <0x02350000 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <0>;
|
||||
};
|
||||
|
||||
clkkeymgr: clkkeymgr {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&clkmodrst0>;
|
||||
clock-output-names = "keymgr";
|
||||
reg = <0x02350000 0xb00>, <0x02350000 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <0>;
|
||||
};
|
||||
};
|
||||
327
arch/arm/dts/keystone.dtsi
Normal file
327
arch/arm/dts/keystone.dtsi
Normal file
|
|
@ -0,0 +1,327 @@
|
|||
/*
|
||||
* Copyright 2013 Texas Instruments, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
#include "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Texas Instruments Keystone 2 SoC";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = &uart0;
|
||||
};
|
||||
|
||||
memory {
|
||||
reg = <0x80000000 0x40000000>;
|
||||
};
|
||||
|
||||
gic: interrupt-controller {
|
||||
compatible = "arm,cortex-a15-gic";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
reg = <0x02561000 0x1000>,
|
||||
<0x02562000 0x2000>,
|
||||
<0x02564000 0x1000>,
|
||||
<0x02566000 0x2000>;
|
||||
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
|
||||
IRQ_TYPE_LEVEL_HIGH)>;
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv7-timer";
|
||||
interrupts =
|
||||
<GIC_PPI 13
|
||||
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14
|
||||
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11
|
||||
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10
|
||||
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,cortex-a15-pmu";
|
||||
interrupts = <GIC_SPI 20 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 22 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 23 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
|
||||
soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "ti,keystone","simple-bus";
|
||||
interrupt-parent = <&gic>;
|
||||
ranges;
|
||||
|
||||
pllctrl: pll-controller@02310000 {
|
||||
compatible = "ti,keystone-pllctrl", "syscon";
|
||||
reg = <0x02310000 0x200>;
|
||||
};
|
||||
|
||||
devctrl: device-state-control@02620000 {
|
||||
compatible = "ti,keystone-devctrl", "syscon";
|
||||
reg = <0x02620000 0x1000>;
|
||||
};
|
||||
|
||||
rstctrl: reset-controller {
|
||||
compatible = "ti,keystone-reset";
|
||||
ti,syscon-pll = <&pllctrl 0xe4>;
|
||||
ti,syscon-dev = <&devctrl 0x328>;
|
||||
ti,wdt-list = <0>;
|
||||
};
|
||||
|
||||
/include/ "keystone-clocks.dtsi"
|
||||
|
||||
uart0: serial@02530c00 {
|
||||
compatible = "ns16550a";
|
||||
current-speed = <115200>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
reg = <0x02530c00 0x100>;
|
||||
clocks = <&clkuart0>;
|
||||
interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
|
||||
uart1: serial@02531000 {
|
||||
compatible = "ns16550a";
|
||||
current-speed = <115200>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
reg = <0x02531000 0x100>;
|
||||
clocks = <&clkuart1>;
|
||||
interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
|
||||
i2c0: i2c@2530000 {
|
||||
compatible = "ti,davinci-i2c";
|
||||
reg = <0x02530000 0x400>;
|
||||
clock-frequency = <100000>;
|
||||
clocks = <&clki2c>;
|
||||
interrupts = <GIC_SPI 283 IRQ_TYPE_EDGE_RISING>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
i2c1: i2c@2530400 {
|
||||
compatible = "ti,davinci-i2c";
|
||||
reg = <0x02530400 0x400>;
|
||||
clock-frequency = <100000>;
|
||||
clocks = <&clki2c>;
|
||||
interrupts = <GIC_SPI 286 IRQ_TYPE_EDGE_RISING>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
i2c2: i2c@2530800 {
|
||||
compatible = "ti,davinci-i2c";
|
||||
reg = <0x02530800 0x400>;
|
||||
clock-frequency = <100000>;
|
||||
clocks = <&clki2c>;
|
||||
interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
spi0: spi@21000400 {
|
||||
compatible = "ti,dm6441-spi";
|
||||
reg = <0x21000400 0x200>;
|
||||
num-cs = <4>;
|
||||
ti,davinci-spi-intr-line = <0>;
|
||||
interrupts = <GIC_SPI 292 IRQ_TYPE_EDGE_RISING>;
|
||||
clocks = <&clkspi>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
spi1: spi@21000600 {
|
||||
compatible = "ti,dm6441-spi";
|
||||
reg = <0x21000600 0x200>;
|
||||
num-cs = <4>;
|
||||
ti,davinci-spi-intr-line = <0>;
|
||||
interrupts = <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>;
|
||||
clocks = <&clkspi>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
spi2: spi@21000800 {
|
||||
compatible = "ti,dm6441-spi";
|
||||
reg = <0x21000800 0x200>;
|
||||
num-cs = <4>;
|
||||
ti,davinci-spi-intr-line = <0>;
|
||||
interrupts = <GIC_SPI 300 IRQ_TYPE_EDGE_RISING>;
|
||||
clocks = <&clkspi>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
usb_phy: usb_phy@2620738 {
|
||||
compatible = "ti,keystone-usbphy";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x2620738 24>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb: usb@2680000 {
|
||||
compatible = "ti,keystone-dwc3";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x2680000 0x10000>;
|
||||
clocks = <&clkusb>;
|
||||
clock-names = "usb";
|
||||
interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>;
|
||||
ranges;
|
||||
dma-coherent;
|
||||
dma-ranges;
|
||||
status = "disabled";
|
||||
|
||||
dwc3@2690000 {
|
||||
compatible = "synopsys,dwc3";
|
||||
reg = <0x2690000 0x70000>;
|
||||
interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>;
|
||||
usb-phy = <&usb_phy>, <&usb_phy>;
|
||||
};
|
||||
};
|
||||
|
||||
wdt: wdt@022f0080 {
|
||||
compatible = "ti,keystone-wdt","ti,davinci-wdt";
|
||||
reg = <0x022f0080 0x80>;
|
||||
clocks = <&clkwdtimer0>;
|
||||
};
|
||||
|
||||
clock_event: timer@22f0000 {
|
||||
compatible = "ti,keystone-timer";
|
||||
reg = <0x022f0000 0x80>;
|
||||
interrupts = <GIC_SPI 110 IRQ_TYPE_EDGE_RISING>;
|
||||
clocks = <&clktimer15>;
|
||||
};
|
||||
|
||||
gpio0: gpio@260bf00 {
|
||||
compatible = "ti,keystone-gpio";
|
||||
reg = <0x0260bf00 0x100>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
/* HW Interrupts mapped to GPIO pins */
|
||||
interrupts = <GIC_SPI 120 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 121 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 123 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 124 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 140 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 142 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 143 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 144 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 145 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 146 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 147 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 148 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 150 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 151 IRQ_TYPE_EDGE_RISING>;
|
||||
clocks = <&clkgpio>;
|
||||
clock-names = "gpio";
|
||||
ti,ngpio = <32>;
|
||||
ti,davinci-gpio-unbanked = <32>;
|
||||
};
|
||||
|
||||
aemif: aemif@21000A00 {
|
||||
compatible = "ti,keystone-aemif", "ti,davinci-aemif";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
clocks = <&clkaemif>;
|
||||
clock-names = "aemif";
|
||||
clock-ranges;
|
||||
|
||||
reg = <0x21000A00 0x00000100>;
|
||||
ranges = <0 0 0x30000000 0x10000000
|
||||
1 0 0x21000A00 0x00000100>;
|
||||
};
|
||||
|
||||
kirq0: keystone_irq@26202a0 {
|
||||
compatible = "ti,keystone-irq";
|
||||
interrupts = <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
ti,syscon-dev = <&devctrl 0x2a0>;
|
||||
};
|
||||
|
||||
pcie0: pcie@21800000 {
|
||||
compatible = "ti,keystone-pcie", "snps,dw-pcie";
|
||||
clocks = <&clkpcie>;
|
||||
clock-names = "pcie";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
reg = <0x21801000 0x2000>, <0x21800000 0x1000>, <0x02620128 4>;
|
||||
ranges = <0x81000000 0 0 0x23250000 0 0x4000
|
||||
0x82000000 0 0x50000000 0x50000000 0 0x10000000>;
|
||||
|
||||
status = "disabled";
|
||||
device_type = "pci";
|
||||
num-lanes = <2>;
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie_intc0 0>, /* INT A */
|
||||
<0 0 0 2 &pcie_intc0 1>, /* INT B */
|
||||
<0 0 0 3 &pcie_intc0 2>, /* INT C */
|
||||
<0 0 0 4 &pcie_intc0 3>; /* INT D */
|
||||
|
||||
pcie_msi_intc0: msi-interrupt-controller {
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 31 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 37 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
|
||||
pcie_intc0: legacy-interrupt-controller {
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 27 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 28 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 29 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -69,6 +69,9 @@
|
|||
};
|
||||
|
||||
&mmc0 {
|
||||
status = "okay";
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
cd-gpios = <&portb 18 0>;
|
||||
vmmc-supply = <®ulator_3_3v>;
|
||||
vqmmc-supply = <®ulator_3_3v>;
|
||||
|
|
|
|||
|
|
@ -77,6 +77,15 @@
|
|||
clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
framebuffer@2 {
|
||||
compatible = "allwinner,simple-framebuffer",
|
||||
"simple-framebuffer";
|
||||
allwinner,pipeline = "de_be0-lcd0-tve0";
|
||||
clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>,
|
||||
<&ahb_gates 44>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
clocks {
|
||||
|
|
@ -85,6 +94,17 @@
|
|||
compatible = "allwinner,sun5i-a10s-ahb-gates-clk";
|
||||
reg = <0x01c20060 0x8>;
|
||||
clocks = <&ahb>;
|
||||
clock-indices = <0>, <1>,
|
||||
<2>, <5>, <6>,
|
||||
<7>, <8>, <9>,
|
||||
<10>, <13>,
|
||||
<14>, <17>, <18>,
|
||||
<20>, <21>, <22>,
|
||||
<26>, <28>, <32>,
|
||||
<34>, <36>, <40>,
|
||||
<43>, <44>,
|
||||
<46>, <51>,
|
||||
<52>;
|
||||
clock-output-names = "ahb_usbotg", "ahb_ehci",
|
||||
"ahb_ohci", "ahb_ss", "ahb_dma",
|
||||
"ahb_bist", "ahb_mmc0", "ahb_mmc1",
|
||||
|
|
@ -103,6 +123,9 @@
|
|||
compatible = "allwinner,sun5i-a10s-apb0-gates-clk";
|
||||
reg = <0x01c20068 0x4>;
|
||||
clocks = <&apb0>;
|
||||
clock-indices = <0>, <3>,
|
||||
<5>, <6>,
|
||||
<10>;
|
||||
clock-output-names = "apb0_codec", "apb0_iis",
|
||||
"apb0_pio", "apb0_ir",
|
||||
"apb0_keypad";
|
||||
|
|
@ -113,9 +136,14 @@
|
|||
compatible = "allwinner,sun5i-a10s-apb1-gates-clk";
|
||||
reg = <0x01c2006c 0x4>;
|
||||
clocks = <&apb1>;
|
||||
clock-indices = <0>, <1>,
|
||||
<2>, <16>,
|
||||
<17>, <18>,
|
||||
<19>;
|
||||
clock-output-names = "apb1_i2c0", "apb1_i2c1",
|
||||
"apb1_i2c2", "apb1_uart0", "apb1_uart1",
|
||||
"apb1_uart2", "apb1_uart3";
|
||||
"apb1_i2c2", "apb1_uart0",
|
||||
"apb1_uart1", "apb1_uart2",
|
||||
"apb1_uart3";
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -137,6 +165,14 @@
|
|||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
pwm: pwm@01c20e00 {
|
||||
compatible = "allwinner,sun5i-a10s-pwm";
|
||||
reg = <0x01c20e00 0xc>;
|
||||
clocks = <&osc24M>;
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart0: serial@01c28000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x01c28000 0x400>;
|
||||
|
|
@ -176,13 +212,6 @@
|
|||
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
||||
};
|
||||
|
||||
uart3_pins_a: uart3@0 {
|
||||
allwinner,pins = "PG9", "PG10";
|
||||
allwinner,function = "uart3";
|
||||
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
||||
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
||||
};
|
||||
|
||||
emac_pins_a: emac0@0 {
|
||||
allwinner,pins = "PA0", "PA1", "PA2",
|
||||
"PA3", "PA4", "PA5", "PA6",
|
||||
|
|
|
|||
|
|
@ -1,29 +0,0 @@
|
|||
/*
|
||||
* Copyright 2015 Hans de Goede <hdegoede@redhat.com>
|
||||
*
|
||||
* Minimal dts file for the Forfun Q88db for u-boot only
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+ or X11
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "sun5i-a13.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Forfun Q88db";
|
||||
compatible = "forfun,q88db", "allwinner,sun5i-a13";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart1;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart1_pins_b>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -1,29 +0,0 @@
|
|||
/*
|
||||
* Copyright 2015 Hans de Goede <hdegoede@redhat.com>
|
||||
*
|
||||
* Minimal dts file for the TZX Q8 713b7 for u-boot only
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+ or X11
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "sun5i-a13.dtsi"
|
||||
|
||||
/ {
|
||||
model = "TZX Q8 713b7";
|
||||
compatible = "tzx,q8-713b7", "allwinner,sun5i-a13";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart1;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart1_pins_b>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -104,6 +104,16 @@
|
|||
compatible = "allwinner,sun5i-a13-ahb-gates-clk";
|
||||
reg = <0x01c20060 0x8>;
|
||||
clocks = <&ahb>;
|
||||
clock-indices = <0>, <1>,
|
||||
<2>, <5>, <6>,
|
||||
<7>, <8>, <9>,
|
||||
<10>, <13>,
|
||||
<14>, <20>,
|
||||
<21>, <22>,
|
||||
<28>, <32>, <36>,
|
||||
<40>, <44>,
|
||||
<46>, <51>,
|
||||
<52>;
|
||||
clock-output-names = "ahb_usbotg", "ahb_ehci",
|
||||
"ahb_ohci", "ahb_ss", "ahb_dma",
|
||||
"ahb_bist", "ahb_mmc0", "ahb_mmc1",
|
||||
|
|
@ -121,6 +131,8 @@
|
|||
compatible = "allwinner,sun5i-a13-apb0-gates-clk";
|
||||
reg = <0x01c20068 0x4>;
|
||||
clocks = <&apb0>;
|
||||
clock-indices = <0>, <5>,
|
||||
<6>;
|
||||
clock-output-names = "apb0_codec", "apb0_pio",
|
||||
"apb0_ir";
|
||||
};
|
||||
|
|
@ -130,8 +142,22 @@
|
|||
compatible = "allwinner,sun5i-a13-apb1-gates-clk";
|
||||
reg = <0x01c2006c 0x4>;
|
||||
clocks = <&apb1>;
|
||||
clock-indices = <0>, <1>,
|
||||
<2>, <17>,
|
||||
<19>;
|
||||
clock-output-names = "apb1_i2c0", "apb1_i2c1",
|
||||
"apb1_i2c2", "apb1_uart1", "apb1_uart3";
|
||||
"apb1_i2c2", "apb1_uart1",
|
||||
"apb1_uart3";
|
||||
};
|
||||
};
|
||||
|
||||
soc@01c00000 {
|
||||
pwm: pwm@01c20e00 {
|
||||
compatible = "allwinner,sun5i-a13-pwm";
|
||||
reg = <0x01c20e00 0xc>;
|
||||
clocks = <&osc24M>;
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1,7 +1,8 @@
|
|||
/*
|
||||
* Copyright 2014 Chen-Yu Tsai
|
||||
* Copyright 2015 Free Electrons
|
||||
* Copyright 2015 NextThing Co
|
||||
*
|
||||
* Chen-Yu Tsai <wens@csie.org>
|
||||
* Maxime Ripard <maxime.ripard@free-electrons.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
|
|
@ -43,19 +44,21 @@
|
|||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "sun8i-a23.dtsi"
|
||||
#include "sun5i-r8.dtsi"
|
||||
#include "sunxi-common-regulators.dtsi"
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/pinctrl/sun4i-a10.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
/ {
|
||||
model = "Ippo Q8H Dual Core Tablet (v5)";
|
||||
compatible = "ippo,q8h-v5", "allwinner,sun8i-a23";
|
||||
model = "NextThing C.H.I.P.";
|
||||
compatible = "nextthing,chip", "allwinner,sun5i-r8";
|
||||
|
||||
aliases {
|
||||
serial0 = &r_uart;
|
||||
i2c0 = &i2c0;
|
||||
i2c2 = &i2c2;
|
||||
serial0 = &uart1;
|
||||
serial1 = &uart3;
|
||||
};
|
||||
|
||||
chosen {
|
||||
|
|
@ -63,74 +66,149 @@
|
|||
};
|
||||
};
|
||||
|
||||
&ehci0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c0_pins_a>;
|
||||
status = "okay";
|
||||
|
||||
axp209: pmic@34 {
|
||||
reg = <0x34>;
|
||||
|
||||
/*
|
||||
* The interrupt is routed through the "External Fast
|
||||
* Interrupt Request" pin (ball G13 of the module)
|
||||
* directly to the main interrupt controller, without
|
||||
* any other controller interfering.
|
||||
*/
|
||||
interrupts = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c1_pins_a>;
|
||||
status = "okay";
|
||||
};
|
||||
#include "axp209.dtsi"
|
||||
|
||||
&i2c2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c2_pins_a>;
|
||||
/* pull-ups and devices require PMIC regulator */
|
||||
status = "failed";
|
||||
};
|
||||
|
||||
&lradc {
|
||||
vref-supply = <®_vcc3v0>;
|
||||
status = "okay";
|
||||
|
||||
button@200 {
|
||||
label = "Volume Up";
|
||||
linux,code = <KEY_VOLUMEUP>;
|
||||
channel = <0>;
|
||||
voltage = <200000>;
|
||||
};
|
||||
xio: gpio@38 {
|
||||
compatible = "nxp,pcf8574a";
|
||||
reg = <0x38>;
|
||||
|
||||
button@400 {
|
||||
label = "Volume Down";
|
||||
linux,code = <KEY_VOLUMEDOWN>;
|
||||
channel = <0>;
|
||||
voltage = <400000>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-parent = <&pio>;
|
||||
interrupts = <6 0 IRQ_TYPE_EDGE_FALLING>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
&mmc0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_q8h>;
|
||||
vmmc-supply = <®_vcc3v0>;
|
||||
pinctrl-0 = <&mmc0_pins_a>;
|
||||
vmmc-supply = <®_vcc3v3>;
|
||||
bus-width = <4>;
|
||||
cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
|
||||
cd-inverted;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ohci0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&otg_sram {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pio {
|
||||
mmc0_cd_pin_q8h: mmc0_cd_pin@0 {
|
||||
allwinner,pins = "PB4";
|
||||
chip_vbus_pin: chip_vbus_pin@0 {
|
||||
allwinner,pins = "PB10";
|
||||
allwinner,function = "gpio_out";
|
||||
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
||||
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
||||
};
|
||||
|
||||
chip_id_det_pin: chip_id_det_pin@0 {
|
||||
allwinner,pins = "PG2";
|
||||
allwinner,function = "gpio_in";
|
||||
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
||||
allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
|
||||
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
||||
};
|
||||
};
|
||||
|
||||
&r_uart {
|
||||
®_dcdc2 {
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1400000>;
|
||||
regulator-name = "cpuvdd";
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
®_dcdc3 {
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1300000>;
|
||||
regulator-name = "corevdd";
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
®_ldo1 {
|
||||
regulator-name = "rtcvdd";
|
||||
};
|
||||
|
||||
®_ldo2 {
|
||||
regulator-min-microvolt = <2700000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "avcc";
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
®_ldo5 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcc-1v8";
|
||||
};
|
||||
|
||||
®_usb0_vbus {
|
||||
pinctrl-0 = <&chip_vbus_pin>;
|
||||
vin-supply = <®_vcc5v0>;
|
||||
gpio = <&pio 1 10 GPIO_ACTIVE_HIGH>; /* PB10 */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&r_uart_pins_a>;
|
||||
pinctrl-0 = <&uart1_pins_b>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart3_pins_a>,
|
||||
<&uart3_pins_cts_rts_a>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_otg {
|
||||
dr_mode = "host";
|
||||
dr_mode = "otg";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_power_supply {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbphy {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&chip_id_det_pin>;
|
||||
status = "okay";
|
||||
|
||||
usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */
|
||||
usb0_vbus_power-supply = <&usb_power_supply>;
|
||||
usb0_vbus-supply = <®_usb0_vbus>;
|
||||
usb1_vbus-supply = <®_vcc5v0>;
|
||||
};
|
||||
|
|
@ -1,5 +1,8 @@
|
|||
/*
|
||||
* Copyright 2015 Hans de Goede <hdegoede@redhat.com>
|
||||
* Copyright 2015 Free Electrons
|
||||
* Copyright 2015 NextThing Co
|
||||
*
|
||||
* Maxime Ripard <maxime.ripard@free-electrons.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
|
|
@ -40,15 +43,17 @@
|
|||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The Ippo Q8H v1.2 is almost identical to the v5, still it needs a separate
|
||||
* dtb file since some gpio-s surrounding the wlan/bluetooth are different,
|
||||
* and it uses different camera sensors.
|
||||
*/
|
||||
|
||||
#include "sun8i-a23-ippo-q8h-v5.dts"
|
||||
#include "sun5i-a13.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Ippo Q8H Dual Core Tablet (v1.2)";
|
||||
compatible = "ippo,q8h-v1.2", "allwinner,sun8i-a23";
|
||||
chosen {
|
||||
framebuffer@1 {
|
||||
compatible = "allwinner,simple-framebuffer",
|
||||
"simple-framebuffer";
|
||||
allwinner,pipeline = "de_be0-lcd0-tve0";
|
||||
clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>,
|
||||
<&ahb_gates 44>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -178,6 +178,7 @@
|
|||
compatible = "allwinner,sun4i-a10-axi-gates-clk";
|
||||
reg = <0x01c2005c 0x4>;
|
||||
clocks = <&axi>;
|
||||
clock-indices = <0>;
|
||||
clock-output-names = "axi_dram";
|
||||
};
|
||||
|
||||
|
|
@ -528,6 +529,27 @@
|
|||
allwinner,drive = <SUN4I_PINCTRL_30_MA>;
|
||||
allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
|
||||
};
|
||||
|
||||
uart3_pins_a: uart3@0 {
|
||||
allwinner,pins = "PG9", "PG10";
|
||||
allwinner,function = "uart3";
|
||||
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
||||
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
||||
};
|
||||
|
||||
uart3_pins_cts_rts_a: uart3-cts-rts@0 {
|
||||
allwinner,pins = "PG11", "PG12";
|
||||
allwinner,function = "uart3";
|
||||
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
||||
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
||||
};
|
||||
|
||||
pwm0_pins: pwm0 {
|
||||
allwinner,pins = "PB2";
|
||||
allwinner,function = "pwm";
|
||||
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
||||
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
||||
};
|
||||
};
|
||||
|
||||
timer@01c20c00 {
|
||||
|
|
|
|||
|
|
@ -659,6 +659,24 @@
|
|||
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
||||
};
|
||||
|
||||
mmc2_pins_a: mmc2@0 {
|
||||
allwinner,pins = "PC6", "PC7", "PC8", "PC9",
|
||||
"PC10", "PC11";
|
||||
allwinner,function = "mmc2";
|
||||
allwinner,drive = <SUN4I_PINCTRL_30_MA>;
|
||||
allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
|
||||
};
|
||||
|
||||
mmc2_8bit_emmc_pins: mmc2@1 {
|
||||
allwinner,pins = "PC6", "PC7", "PC8", "PC9",
|
||||
"PC10", "PC11", "PC12",
|
||||
"PC13", "PC14", "PC15",
|
||||
"PC24";
|
||||
allwinner,function = "mmc2";
|
||||
allwinner,drive = <SUN4I_PINCTRL_30_MA>;
|
||||
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
||||
};
|
||||
|
||||
gmac_pins_mii_a: gmac_mii@0 {
|
||||
allwinner,pins = "PA0", "PA1", "PA2", "PA3",
|
||||
"PA8", "PA9", "PA11",
|
||||
|
|
|
|||
|
|
@ -6,12 +6,12 @@
|
|||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* a) This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful,
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
|
|
@ -41,90 +41,151 @@
|
|||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "sun8i-a33.dtsi"
|
||||
#include "sun6i-a31s.dtsi"
|
||||
#include "sunxi-common-regulators.dtsi"
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/pinctrl/sun4i-a10.h>
|
||||
|
||||
/ {
|
||||
model = "Ippo Q8H Quad Core Tablet (v1.2)";
|
||||
compatible = "ippo,a33-q8h-v1.2", "allwinner,sun8i-a33";
|
||||
model = "Sinovoip BPI-M2";
|
||||
compatible = "sinovoip,bpi-m2", "allwinner,sun6i-a31s";
|
||||
|
||||
aliases {
|
||||
serial0 = &r_uart;
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c0_pins_a>;
|
||||
status = "okay";
|
||||
};
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&led_pins_bpi_m2>;
|
||||
|
||||
&i2c1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c1_pins_a>;
|
||||
status = "okay";
|
||||
};
|
||||
blue {
|
||||
label = "bpi-m2:blue:usr";
|
||||
gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */
|
||||
};
|
||||
|
||||
&lradc {
|
||||
vref-supply = <®_vcc3v0>;
|
||||
status = "okay";
|
||||
green {
|
||||
label = "bpi-m2:green:usr";
|
||||
gpios = <&pio 6 10 GPIO_ACTIVE_HIGH>; /* PG10 */
|
||||
};
|
||||
|
||||
button@200 {
|
||||
label = "Volume Up";
|
||||
linux,code = <KEY_VOLUMEUP>;
|
||||
channel = <0>;
|
||||
voltage = <200000>;
|
||||
red {
|
||||
label = "bpi-m2:red:usr";
|
||||
gpios = <&pio 6 5 GPIO_ACTIVE_HIGH>; /* PG5 */
|
||||
};
|
||||
};
|
||||
|
||||
button@400 {
|
||||
label = "Volume Down";
|
||||
linux,code = <KEY_VOLUMEDOWN>;
|
||||
channel = <0>;
|
||||
voltage = <400000>;
|
||||
mmc2_pwrseq: mmc2_pwrseq {
|
||||
compatible = "mmc-pwrseq-simple";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mmc2_pwrseq_pin_bpi_m2>;
|
||||
reset-gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>; /* PL8 WIFI_EN */
|
||||
};
|
||||
};
|
||||
|
||||
&ehci0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmac {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac_pins_rgmii_a>, <&gmac_phy_reset_pin_bpi_m2>;
|
||||
phy = <&phy1>;
|
||||
phy-mode = "rgmii";
|
||||
snps,reset-gpio = <&pio 0 21 GPIO_ACTIVE_HIGH>; /* PA21 */
|
||||
snps,reset-active-low;
|
||||
snps,reset-delays-us = <0 10000 30000>;
|
||||
status = "okay";
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&ir {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ir_pins_a>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mmc0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_q8h>;
|
||||
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bpi_m2>;
|
||||
vmmc-supply = <®_vcc3v0>;
|
||||
bus-width = <4>;
|
||||
cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
|
||||
cd-gpios = <&pio 0 4 GPIO_ACTIVE_HIGH>; /* PA4 */
|
||||
cd-inverted;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mmc0_pins_a {
|
||||
allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
|
||||
};
|
||||
|
||||
&mmc2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mmc2_pins_a>;
|
||||
vmmc-supply = <®_vcc3v0>;
|
||||
mmc-pwrseq = <&mmc2_pwrseq>;
|
||||
bus-width = <4>;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
|
||||
brcmf: bcrmf@1 {
|
||||
reg = <1>;
|
||||
compatible = "brcm,bcm4329-fmac";
|
||||
interrupt-parent = <&r_pio>;
|
||||
interrupts = <0 5 IRQ_TYPE_LEVEL_LOW>; /* PL5 */
|
||||
interrupt-names = "host-wake";
|
||||
};
|
||||
};
|
||||
|
||||
&mmc2_pins_a {
|
||||
allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
|
||||
};
|
||||
|
||||
&ohci0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pio {
|
||||
mmc0_cd_pin_q8h: mmc0_cd_pin@0 {
|
||||
allwinner,pins = "PB4";
|
||||
gmac_phy_reset_pin_bpi_m2: gmac_phy_reset_pin@0 {
|
||||
allwinner,pins = "PA21";
|
||||
allwinner,function = "gpio_out";
|
||||
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
||||
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
||||
};
|
||||
|
||||
led_pins_bpi_m2: led_pins@0 {
|
||||
allwinner,pins = "PG5", "PG10", "PG11";
|
||||
allwinner,function = "gpio_out";
|
||||
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
||||
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
||||
};
|
||||
|
||||
mmc0_cd_pin_bpi_m2: mmc0_cd_pin@0 {
|
||||
allwinner,pins = "PA4";
|
||||
allwinner,function = "gpio_in";
|
||||
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
||||
allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
|
||||
};
|
||||
};
|
||||
|
||||
&r_uart {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&r_uart_pins_a>;
|
||||
status = "okay";
|
||||
&r_pio {
|
||||
mmc2_pwrseq_pin_bpi_m2: mmc2_pwrseq_pin@0 {
|
||||
allwinner,pins = "PL8";
|
||||
allwinner,function = "gpio_out";
|
||||
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
||||
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* FIXME for now we only support host mode and rely on u-boot to have
|
||||
* turned on Vbus which is controlled by the axp223 pmic on the board.
|
||||
*
|
||||
* Once we have axp223 support we should switch to fully supporting otg.
|
||||
*/
|
||||
&usb_otg {
|
||||
dr_mode = "host";
|
||||
&uart0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_pins_a>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
@ -18,6 +18,8 @@
|
|||
#define IOMUXC_GPR1_REF_SSP_EN (1 << 16)
|
||||
#define IOMUXC_GPR1_TEST_POWERDOWN (1 << 18)
|
||||
|
||||
#define IOMUXC_GPR1_PCIE_SW_RST (1 << 29)
|
||||
|
||||
/*
|
||||
* IOMUXC_GPR5 bit fields
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -69,8 +69,6 @@ void sdelay(unsigned long);
|
|||
void make_cs1_contiguous(void);
|
||||
void omap_nand_switch_ecc(uint32_t, uint32_t);
|
||||
void power_init_r(void);
|
||||
void dieid_num_r(void);
|
||||
void get_dieid(u32 *id);
|
||||
void do_omap3_emu_romcode_call(u32 service_id, u32 parameters);
|
||||
void omap3_set_aux_cr_secure(u32 acr);
|
||||
u32 warm_reset(void);
|
||||
|
|
|
|||
|
|
@ -33,10 +33,6 @@
|
|||
|
||||
/* CONTROL_ID_CODE */
|
||||
#define CONTROL_ID_CODE 0x4A002204
|
||||
#define STD_FUSE_DIE_ID_0 0x4A002200
|
||||
#define STD_FUSE_DIE_ID_1 0x4A002208
|
||||
#define STD_FUSE_DIE_ID_2 0x4A00220c
|
||||
#define STD_FUSE_DIE_ID_3 0x4A002210
|
||||
|
||||
#define OMAP4_CONTROL_ID_CODE_ES1_0 0x0B85202F
|
||||
#define OMAP4_CONTROL_ID_CODE_ES2_0 0x1B85202F
|
||||
|
|
|
|||
|
|
@ -103,13 +103,17 @@
|
|||
#define TCR_EL2_IPS_BITS (3 << 16) /* 42 bits physical address */
|
||||
#define TCR_EL3_IPS_BITS (3 << 16) /* 42 bits physical address */
|
||||
|
||||
/* PTWs cacheable, inner/outer WBWA and non-shareable */
|
||||
/* PTWs cacheable, inner/outer WBWA and inner shareable */
|
||||
#define TCR_FLAGS (TCR_TG0_64K | \
|
||||
TCR_SHARED_NON | \
|
||||
TCR_SHARED_INNER | \
|
||||
TCR_ORGN_WBWA | \
|
||||
TCR_IRGN_WBWA | \
|
||||
TCR_T0SZ(VA_BITS))
|
||||
|
||||
#define TCR_EL1_RSVD (1 << 31)
|
||||
#define TCR_EL2_RSVD (1 << 31 | 1 << 23)
|
||||
#define TCR_EL3_RSVD (1 << 31 | 1 << 23)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
void set_pgtable_section(u64 *page_table, u64 index,
|
||||
|
|
|
|||
|
|
@ -603,8 +603,11 @@ void abb_setup(u32 fuse, u32 ldovbb, u32 setup, u32 control,
|
|||
u32 txdone, u32 txdone_mask, u32 opp);
|
||||
s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb);
|
||||
|
||||
void usb_fake_mac_from_die_id(u32 *id);
|
||||
void usb_set_serial_num_from_die_id(u32 *id);
|
||||
void omap_die_id_serial(void);
|
||||
void omap_die_id_get_board_serial(struct tag_serialnr *serialnr);
|
||||
void omap_die_id_usbethaddr(void);
|
||||
void omap_die_id_display(void);
|
||||
|
||||
void recalibrate_iodelay(void);
|
||||
|
||||
void omap_smc1(u32 service, u32 val);
|
||||
|
|
@ -612,6 +615,8 @@ void omap_smc1(u32 service, u32 val);
|
|||
void enable_edma3_clocks(void);
|
||||
void disable_edma3_clocks(void);
|
||||
|
||||
void omap_die_id(unsigned int *die_id);
|
||||
|
||||
/* ABB */
|
||||
#define OMAP_ABB_NOMINAL_OPP 0
|
||||
#define OMAP_ABB_FAST_OPP 1
|
||||
|
|
|
|||
|
|
@ -26,6 +26,9 @@
|
|||
#define OMAP_MMC_H_
|
||||
|
||||
struct hsmmc {
|
||||
#ifdef CONFIG_DM_MMC
|
||||
unsigned char res0[0x100];
|
||||
#endif
|
||||
unsigned char res1[0x10];
|
||||
unsigned int sysconfig; /* 0x10 */
|
||||
unsigned int sysstatus; /* 0x14 */
|
||||
|
|
|
|||
|
|
@ -17,6 +17,8 @@
|
|||
#define L2X0_CTRL_EN 1
|
||||
|
||||
#define L310_SHARED_ATT_OVERRIDE_ENABLE (1 << 22)
|
||||
#define L310_AUX_CTRL_DATA_PREFETCH_MASK (1 << 28)
|
||||
#define L310_AUX_CTRL_INST_PREFETCH_MASK (1 << 29)
|
||||
|
||||
struct pl310_regs {
|
||||
u32 pl310_cache_id;
|
||||
|
|
|
|||
|
|
@ -194,7 +194,7 @@ void save_boot_params_ret(void);
|
|||
static inline unsigned int get_cr(void)
|
||||
{
|
||||
unsigned int val;
|
||||
asm("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) : : "cc");
|
||||
asm volatile("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) : : "cc");
|
||||
return val;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -11,6 +11,7 @@
|
|||
#define _KEYSTONE_NET_H_
|
||||
|
||||
#include <asm/io.h>
|
||||
#include <phy.h>
|
||||
|
||||
/* EMAC */
|
||||
#ifdef CONFIG_KSNET_NETCP_V1_0
|
||||
|
|
@ -49,7 +50,11 @@
|
|||
#define MAC_ID_BASE_ADDR CONFIG_KSNET_MAC_ID_BASE
|
||||
|
||||
/* MDIO module input frequency */
|
||||
#ifdef CONFIG_SOC_K2G
|
||||
#define EMAC_MDIO_BUS_FREQ (clk_get_rate(sys_clk0_3_clk))
|
||||
#else
|
||||
#define EMAC_MDIO_BUS_FREQ (clk_get_rate(pass_pll_clk))
|
||||
#endif
|
||||
/* MDIO clock output frequency */
|
||||
#define EMAC_MDIO_CLOCK_FREQ 2500000 /* 2.5 MHz */
|
||||
|
||||
|
|
@ -188,6 +193,11 @@ struct mac_sl_cfg {
|
|||
#define SGMII_RXCFG_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x034)
|
||||
#define SGMII_AUXCFG_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x038)
|
||||
|
||||
/* RGMII */
|
||||
#define RGMII_REG_STATUS_LINK BIT(0)
|
||||
|
||||
#define RGMII_STATUS_REG (GBETH_BASE + 0x18)
|
||||
|
||||
/* PSS */
|
||||
#ifdef CONFIG_KSNET_NETCP_V1_0
|
||||
|
||||
|
|
@ -239,6 +249,7 @@ struct eth_priv_t {
|
|||
int phy_addr;
|
||||
int slave_port;
|
||||
int sgmii_link_type;
|
||||
phy_interface_t phy_if;
|
||||
struct phy_device *phy_dev;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -25,7 +25,8 @@
|
|||
* the GD ('global data') structure, both located in some readily
|
||||
* available RAM (SRAM, locked cache...). In this context, VARIABLE
|
||||
* global data, initialized or not (BSS), are UNAVAILABLE; only
|
||||
* CONSTANT initialized data are available.
|
||||
* CONSTANT initialized data are available. GD should be zeroed
|
||||
* before board_init_f() is called.
|
||||
*
|
||||
* 2. Call board_init_f(). This function prepares the hardware for
|
||||
* execution from system RAM (DRAM, DDR...) As system RAM may not
|
||||
|
|
@ -34,24 +35,29 @@
|
|||
* data include the relocation destination, the future stack, and
|
||||
* the future GD location.
|
||||
*
|
||||
* (the following applies only to non-SPL builds)
|
||||
*
|
||||
* 3. Set up intermediate environment where the stack and GD are the
|
||||
* ones allocated by board_init_f() in system RAM, but BSS and
|
||||
* initialized non-const data are still not available.
|
||||
*
|
||||
* 4. Call relocate_code(). This function relocates U-Boot from its
|
||||
* current location into the relocation destination computed by
|
||||
* board_init_f().
|
||||
* 4a.For U-Boot proper (not SPL), call relocate_code(). This function
|
||||
* relocates U-Boot from its current location into the relocation
|
||||
* destination computed by board_init_f().
|
||||
*
|
||||
* 4b.For SPL, board_init_f() just returns (to crt0). There is no
|
||||
* code relocation in SPL.
|
||||
*
|
||||
* 5. Set up final environment for calling board_init_r(). This
|
||||
* environment has BSS (initialized to 0), initialized non-const
|
||||
* data (initialized to their intended value), and stack in system
|
||||
* RAM. GD has retained values set by board_init_f(). Some CPUs
|
||||
* have some work left to do at this point regarding memory, so
|
||||
* call c_runtime_cpu_setup.
|
||||
* RAM (for SPL moving the stack and GD into RAM is optional - see
|
||||
* CONFIG_SPL_STACK_R). GD has retained values set by board_init_f().
|
||||
*
|
||||
* 6. Branch to board_init_r().
|
||||
* 6. For U-Boot proper (not SPL), some CPUs have some work left to do
|
||||
* at this point regarding memory, so call c_runtime_cpu_setup.
|
||||
*
|
||||
* 7. Branch to board_init_r().
|
||||
*
|
||||
* For more information see 'Board Initialisation Flow in README.
|
||||
*/
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -27,7 +27,8 @@
|
|||
* the GD ('global data') structure, both located in some readily
|
||||
* available RAM (SRAM, locked cache...). In this context, VARIABLE
|
||||
* global data, initialized or not (BSS), are UNAVAILABLE; only
|
||||
* CONSTANT initialized data are available.
|
||||
* CONSTANT initialized data are available. GD should be zeroed
|
||||
* before board_init_f() is called.
|
||||
*
|
||||
* 2. Call board_init_f(). This function prepares the hardware for
|
||||
* execution from system RAM (DRAM, DDR...) As system RAM may not
|
||||
|
|
@ -36,24 +37,31 @@
|
|||
* data include the relocation destination, the future stack, and
|
||||
* the future GD location.
|
||||
*
|
||||
* (the following applies only to non-SPL builds)
|
||||
*
|
||||
* 3. Set up intermediate environment where the stack and GD are the
|
||||
* ones allocated by board_init_f() in system RAM, but BSS and
|
||||
* initialized non-const data are still not available.
|
||||
*
|
||||
* 4. Call relocate_code(). This function relocates U-Boot from its
|
||||
* current location into the relocation destination computed by
|
||||
* board_init_f().
|
||||
* 4a.For U-Boot proper (not SPL), call relocate_code(). This function
|
||||
* relocates U-Boot from its current location into the relocation
|
||||
* destination computed by board_init_f().
|
||||
*
|
||||
* 4b.For SPL, board_init_f() just returns (to crt0). There is no
|
||||
* code relocation in SPL.
|
||||
*
|
||||
* 5. Set up final environment for calling board_init_r(). This
|
||||
* environment has BSS (initialized to 0), initialized non-const
|
||||
* data (initialized to their intended value), and stack in system
|
||||
* RAM. GD has retained values set by board_init_f(). Some CPUs
|
||||
* have some work left to do at this point regarding memory, so
|
||||
* call c_runtime_cpu_setup.
|
||||
* RAM (for SPL moving the stack and GD into RAM is optional - see
|
||||
* CONFIG_SPL_STACK_R). GD has retained values set by board_init_f().
|
||||
*
|
||||
* 6. Branch to board_init_r().
|
||||
* TODO: For SPL, implement stack relocation on AArch64.
|
||||
*
|
||||
* 6. For U-Boot proper (not SPL), some CPUs have some work left to do
|
||||
* at this point regarding memory, so call c_runtime_cpu_setup.
|
||||
*
|
||||
* 7. Branch to board_init_r().
|
||||
*
|
||||
* For more information see 'Board Initialisation Flow in README.
|
||||
*/
|
||||
|
||||
ENTRY(_main)
|
||||
|
|
@ -106,6 +114,8 @@ relocation_return:
|
|||
*/
|
||||
bl c_runtime_cpu_setup /* still call old routine */
|
||||
|
||||
/* TODO: For SPL, call spl_relocate_stack_gd() to alloc stack relocation */
|
||||
|
||||
/*
|
||||
* Clear BSS section
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -46,11 +46,19 @@ ENTRY(gic_init_secure)
|
|||
ldr w9, [x0, GICD_TYPER]
|
||||
and w10, w9, #0x1f /* ITLinesNumber */
|
||||
cbz w10, 1f /* No SPIs */
|
||||
add x11, x0, (GICD_IGROUPRn + 4)
|
||||
add x11, x0, GICD_IGROUPRn
|
||||
mov w9, #~0 /* Config SPIs as Grp1 */
|
||||
str w9, [x11], #0x4
|
||||
0: str w9, [x11], #0x4
|
||||
sub w10, w10, #0x1
|
||||
cbnz w10, 0b
|
||||
|
||||
ldr x1, =GICC_BASE /* GICC_CTLR */
|
||||
mov w0, #3 /* EnableGrp0 | EnableGrp1 */
|
||||
str w0, [x1]
|
||||
|
||||
mov w0, #1 << 7 /* allow NS access to GICC_PMR */
|
||||
str w0, [x1, #4] /* GICC_PMR */
|
||||
#endif
|
||||
1:
|
||||
ret
|
||||
|
|
|
|||
|
|
@ -150,6 +150,7 @@ struct bcm2835_mbox_tag_hdr {
|
|||
#define BCM2835_BOARD_REV_A_PLUS 0x12
|
||||
#define BCM2835_BOARD_REV_B_PLUS_13 0x13
|
||||
#define BCM2835_BOARD_REV_CM_14 0x14
|
||||
#define BCM2835_BOARD_REV_A_PLUS_15 0x15
|
||||
#endif
|
||||
|
||||
struct bcm2835_mbox_tag_get_board_rev {
|
||||
|
|
|
|||
|
|
@ -13,6 +13,9 @@ config TARGET_K2E_EVM
|
|||
config TARGET_K2L_EVM
|
||||
bool "TI Keystone 2 Lamar EVM"
|
||||
|
||||
config TARGET_K2G_EVM
|
||||
bool "TI Keystone 2 Galileo EVM"
|
||||
|
||||
endchoice
|
||||
|
||||
config SYS_SOC
|
||||
|
|
|
|||
|
|
@ -31,8 +31,14 @@ const struct keystone_pll_regs keystone_pll_regs[] = {
|
|||
[TETRIS_PLL] = {KS2_ARMPLLCTL0, KS2_ARMPLLCTL1},
|
||||
[DDR3A_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
|
||||
[DDR3B_PLL] = {KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1},
|
||||
[UART_PLL] = {KS2_UARTPLLCTL0, KS2_UARTPLLCTL1},
|
||||
};
|
||||
|
||||
inline void pll_pa_clk_sel(void)
|
||||
{
|
||||
setbits_le32(keystone_pll_regs[PASS_PLL].reg1, CFG_PLLCTL1_PAPLL_MASK);
|
||||
}
|
||||
|
||||
static void wait_for_completion(const struct pll_init_data *data)
|
||||
{
|
||||
int i;
|
||||
|
|
@ -180,9 +186,8 @@ void configure_secondary_pll(const struct pll_init_data *data)
|
|||
sdelay(21000);
|
||||
|
||||
/* Select the Output of PASS PLL as input to PASS */
|
||||
if (data->pll == PASS_PLL)
|
||||
setbits_le32(keystone_pll_regs[data->pll].reg1,
|
||||
CFG_PLLCTL1_PAPLL_MASK);
|
||||
if (data->pll == PASS_PLL && cpu_is_k2hk())
|
||||
pll_pa_clk_sel();
|
||||
|
||||
/* Select the Output of ARM PLL as input to ARM */
|
||||
if (data->pll == TETRIS_PLL)
|
||||
|
|
@ -309,6 +314,10 @@ static unsigned long pll_freq_get(int pll)
|
|||
ret = external_clk[ddr3b_clk];
|
||||
reg = KS2_DDR3BPLLCTL0;
|
||||
break;
|
||||
case UART_PLL:
|
||||
ret = external_clk[uart_clk];
|
||||
reg = KS2_UARTPLLCTL0;
|
||||
break;
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -351,6 +360,10 @@ unsigned long clk_get_rate(unsigned int clk)
|
|||
if (cpu_is_k2hk())
|
||||
freq = pll_freq_get(DDR3B_PLL);
|
||||
break;
|
||||
case uart_pll_clk:
|
||||
if (cpu_is_k2g())
|
||||
freq = pll_freq_get(UART_PLL);
|
||||
break;
|
||||
case sys_clk0_1_clk:
|
||||
case sys_clk0_clk:
|
||||
freq = pll_freq_get(CORE_PLL) / pll0div_read(1);
|
||||
|
|
|
|||
|
|
@ -37,7 +37,7 @@ static int do_mon_install(cmd_tbl_t *cmdtp, int flag, int argc,
|
|||
if (argc < 2)
|
||||
return CMD_RET_USAGE;
|
||||
|
||||
freq = clk_get_rate(sys_clk0_6_clk);
|
||||
freq = CONFIG_SYS_HZ_CLOCK;
|
||||
|
||||
addr = simple_strtoul(argv[1], NULL, 16);
|
||||
|
||||
|
|
|
|||
|
|
@ -16,13 +16,13 @@ spl/u-boot-spl.gph: spl/u-boot-spl.bin FORCE
|
|||
|
||||
OBJCOPYFLAGS_u-boot-spi.gph = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) \
|
||||
--gap-fill=0
|
||||
u-boot-spi.gph: spl/u-boot-spl.gph u-boot.img FORCE
|
||||
u-boot-spi.gph: spl/u-boot-spl.gph u-boot-dtb.img FORCE
|
||||
$(call if_changed,pad_cat)
|
||||
|
||||
ifndef CONFIG_SPL_BUILD
|
||||
MKIMAGEFLAGS_MLO = -A $(ARCH) -T gpimage -C none \
|
||||
-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) -n U-Boot
|
||||
MLO: u-boot.bin FORCE
|
||||
MLO: u-boot-dtb.bin FORCE
|
||||
$(call if_changed,mkimage)
|
||||
@dd if=/dev/zero bs=8 count=1 2>/dev/null >> $@
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -52,7 +52,8 @@ void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
|
|||
__raw_writel(phy_cfg->dtpr2, base + KS2_DDRPHY_DTPR2_OFFSET);
|
||||
__raw_writel(phy_cfg->mr0, base + KS2_DDRPHY_MR0_OFFSET);
|
||||
__raw_writel(phy_cfg->mr1, base + KS2_DDRPHY_MR1_OFFSET);
|
||||
__raw_writel(phy_cfg->mr2, base + KS2_DDRPHY_MR2_OFFSET);
|
||||
if (!cpu_is_k2g())
|
||||
__raw_writel(phy_cfg->mr2, base + KS2_DDRPHY_MR2_OFFSET);
|
||||
__raw_writel(phy_cfg->dtcr, base + KS2_DDRPHY_DTCR_OFFSET);
|
||||
__raw_writel(phy_cfg->pgcr2, base + KS2_DDRPHY_PGCR2_OFFSET);
|
||||
|
||||
|
|
@ -64,6 +65,15 @@ void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
|
|||
while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1)
|
||||
;
|
||||
|
||||
/* Disable ECC for K2G */
|
||||
if (cpu_is_k2g()) {
|
||||
clrbits_le32(base + KS2_DDRPHY_DATX8_4_OFFSET, 0x1);
|
||||
clrbits_le32(base + KS2_DDRPHY_DATX8_5_OFFSET, 0x1);
|
||||
clrbits_le32(base + KS2_DDRPHY_DATX8_6_OFFSET, 0x1);
|
||||
clrbits_le32(base + KS2_DDRPHY_DATX8_7_OFFSET, 0x1);
|
||||
clrbits_le32(base + KS2_DDRPHY_DATX8_8_OFFSET, 0x1);
|
||||
}
|
||||
|
||||
__raw_writel(phy_cfg->pir_v2, base + KS2_DDRPHY_PIR_OFFSET);
|
||||
while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1)
|
||||
;
|
||||
|
|
|
|||
20
arch/arm/mach-keystone/include/mach/clock-k2g.h
Normal file
20
arch/arm/mach-keystone/include/mach/clock-k2g.h
Normal file
|
|
@ -0,0 +1,20 @@
|
|||
/*
|
||||
* K2G: Clock data
|
||||
*
|
||||
* (C) Copyright 2015
|
||||
* Texas Instruments Incorporated, <www.ti.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_CLOCK_K2G_H
|
||||
#define __ASM_ARCH_CLOCK_K2G_H
|
||||
|
||||
#define PLLSET_CMD_LIST "<pa|arm|ddr3>"
|
||||
|
||||
#define DEV_SUPPORTED_SPEEDS 0xfff
|
||||
#define ARM_SUPPORTED_SPEEDS 0xfff
|
||||
|
||||
#define KS2_CLK1_6 sys_clk0_6_clk
|
||||
|
||||
#endif
|
||||
|
|
@ -24,8 +24,13 @@
|
|||
#include <asm/arch/clock-k2l.h>
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SOC_K2G
|
||||
#include <asm/arch/clock-k2g.h>
|
||||
#endif
|
||||
|
||||
#define CORE_PLL MAIN_PLL
|
||||
#define DDR3_PLL DDR3A_PLL
|
||||
#define NSS_PLL PASS_PLL
|
||||
|
||||
#define CLK_LIST(CLK)\
|
||||
CLK(0, core_pll_clk)\
|
||||
|
|
@ -48,7 +53,8 @@
|
|||
CLK(17, sys_clk1_6_clk)\
|
||||
CLK(18, sys_clk1_12_clk)\
|
||||
CLK(19, sys_clk2_clk)\
|
||||
CLK(20, sys_clk3_clk)
|
||||
CLK(20, sys_clk3_clk)\
|
||||
CLK(21, uart_pll_clk)
|
||||
|
||||
#include <asm/types.h>
|
||||
|
||||
|
|
@ -75,6 +81,7 @@ enum {
|
|||
PASS_PLL,
|
||||
DDR3A_PLL,
|
||||
DDR3B_PLL,
|
||||
UART_PLL,
|
||||
MAX_PLL_COUNT,
|
||||
};
|
||||
|
||||
|
|
@ -85,6 +92,7 @@ enum ext_clk_e {
|
|||
tetris_clk,
|
||||
ddr3a_clk,
|
||||
ddr3b_clk,
|
||||
uart_clk,
|
||||
ext_clk_count /* number of external clocks */
|
||||
};
|
||||
|
||||
|
|
@ -118,6 +126,7 @@ unsigned long clk_round_rate(unsigned int clk, unsigned long hz);
|
|||
int clk_set_rate(unsigned int clk, unsigned long hz);
|
||||
int get_max_dev_speed(void);
|
||||
int get_max_arm_speed(void);
|
||||
void pll_pa_clk_sel(void);
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
|
|
|||
74
arch/arm/mach-keystone/include/mach/hardware-k2g.h
Normal file
74
arch/arm/mach-keystone/include/mach/hardware-k2g.h
Normal file
|
|
@ -0,0 +1,74 @@
|
|||
/*
|
||||
* K2G: SoC definitions
|
||||
*
|
||||
* (C) Copyright 2015
|
||||
* Texas Instruments Incorporated, <www.ti.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_HARDWARE_K2G_H
|
||||
#define __ASM_ARCH_HARDWARE_K2G_H
|
||||
|
||||
#define KS2_NUM_DSPS 0
|
||||
|
||||
/* Power and Sleep Controller (PSC) Domains */
|
||||
#define KS2_LPSC_ALWAYSON 0
|
||||
#define KS2_LPSC_PMMC 1
|
||||
#define KS2_LPSC_DEBUG 2
|
||||
#define KS2_LPSC_NSS 3
|
||||
#define KS2_LPSC_SA 4
|
||||
#define KS2_LPSC_TERANET 5
|
||||
#define KS2_LPSC_SYS_COMP 6
|
||||
#define KS2_LPSC_QSPI 7
|
||||
#define KS2_LPSC_MMC 8
|
||||
#define KS2_LPSC_GPMC 9
|
||||
#define KS2_LPSC_MLB 11
|
||||
#define KS2_LPSC_EHRPWM 12
|
||||
#define KS2_LPSC_EQEP 13
|
||||
#define KS2_LPSC_ECAP 14
|
||||
#define KS2_LPSC_MCASP 15
|
||||
#define KS2_LPSC_SR 16
|
||||
#define KS2_LPSC_MSMC 17
|
||||
#define KS2_LPSC_GEM 18
|
||||
#define KS2_LPSC_ARM 19
|
||||
#define KS2_LPSC_ASRC 20
|
||||
#define KS2_LPSC_ICSS 21
|
||||
#define KS2_LPSC_DSS 23
|
||||
#define KS2_LPSC_PCIE 24
|
||||
#define KS2_LPSC_USB_0 25
|
||||
#define KS2_LPSC_USB KS2_LPSC_USB_0
|
||||
#define KS2_LPSC_USB_1 26
|
||||
#define KS2_LPSC_DDR3 27
|
||||
#define KS2_LPSC_SPARE0_LPSC0 28
|
||||
#define KS2_LPSC_SPARE0_LPSC1 29
|
||||
#define KS2_LPSC_SPARE1_LPSC0 30
|
||||
#define KS2_LPSC_SPARE1_LPSC1 31
|
||||
|
||||
#define KS2_LPSC_CPGMAC KS2_LPSC_NSS
|
||||
#define KS2_LPSC_CRYPTO KS2_LPSC_SA
|
||||
|
||||
/* SGMII SerDes */
|
||||
#define KS2_LANES_PER_SGMII_SERDES 4
|
||||
|
||||
/* NETCP pktdma */
|
||||
#define KS2_NETCP_PDMA_CTRL_BASE 0x04010000
|
||||
#define KS2_NETCP_PDMA_TX_BASE 0x04011000
|
||||
#define KS2_NETCP_PDMA_TX_CH_NUM 21
|
||||
#define KS2_NETCP_PDMA_RX_BASE 0x04012000
|
||||
#define KS2_NETCP_PDMA_RX_CH_NUM 32
|
||||
#define KS2_NETCP_PDMA_SCHED_BASE 0x04010100
|
||||
#define KS2_NETCP_PDMA_RX_FLOW_BASE 0x04013000
|
||||
#define KS2_NETCP_PDMA_RX_FLOW_NUM 32
|
||||
#define KS2_NETCP_PDMA_TX_SND_QUEUE 5
|
||||
|
||||
/* NETCP */
|
||||
#define KS2_NETCP_BASE 0x04000000
|
||||
|
||||
#define K2G_GPIO0_BASE 0X02603000
|
||||
#define K2G_GPIO1_BASE 0X0260a000
|
||||
#define K2G_GPIO1_BANK2_BASE K2G_GPIO1_BASE + 0x38
|
||||
#define K2G_GPIO_DIR_OFFSET 0x0
|
||||
#define K2G_GPIO_SETDATA_OFFSET 0x8
|
||||
|
||||
#endif /* __ASM_ARCH_HARDWARE_K2G_H */
|
||||
|
|
@ -52,6 +52,10 @@ typedef volatile unsigned int *dv_reg_p;
|
|||
#define KS2_DDRPHY_ZQ2CR1_OFFSET 0x1A4
|
||||
#define KS2_DDRPHY_ZQ3CR1_OFFSET 0x1B4
|
||||
|
||||
#define KS2_DDRPHY_DATX8_4_OFFSET 0x2C0
|
||||
#define KS2_DDRPHY_DATX8_5_OFFSET 0x300
|
||||
#define KS2_DDRPHY_DATX8_6_OFFSET 0x340
|
||||
#define KS2_DDRPHY_DATX8_7_OFFSET 0x380
|
||||
#define KS2_DDRPHY_DATX8_8_OFFSET 0x3C0
|
||||
|
||||
#define IODDRM_MASK 0x00000180
|
||||
|
|
@ -121,8 +125,13 @@ typedef volatile unsigned int *dv_reg_p;
|
|||
#define KS2_EDMA_PARAM_1(x) (0x4020 + (4 * x))
|
||||
|
||||
/* NETCP pktdma */
|
||||
#ifdef CONFIG_SOC_K2G
|
||||
#define KS2_NETCP_PDMA_RX_FREE_QUEUE 113
|
||||
#define KS2_NETCP_PDMA_RX_RCV_QUEUE 114
|
||||
#else
|
||||
#define KS2_NETCP_PDMA_RX_FREE_QUEUE 4001
|
||||
#define KS2_NETCP_PDMA_RX_RCV_QUEUE 4002
|
||||
#endif
|
||||
|
||||
/* Chip Interrupt Controller */
|
||||
#define KS2_CIC2_BASE 0x02608000
|
||||
|
|
@ -143,6 +152,8 @@ typedef volatile unsigned int *dv_reg_p;
|
|||
#define KS2_JTAG_ID_REG (KS2_DEVICE_STATE_CTRL_BASE + 0x18)
|
||||
#define KS2_DEVSTAT (KS2_DEVICE_STATE_CTRL_BASE + 0x20)
|
||||
#define KS2_DEVCFG (KS2_DEVICE_STATE_CTRL_BASE + 0x14c)
|
||||
#define KS2_ETHERNET_CFG (KS2_DEVICE_STATE_CTRL_BASE + 0xe20)
|
||||
#define KS2_ETHERNET_RGMII 2
|
||||
|
||||
/* PSC */
|
||||
#define KS2_PSC_BASE 0x02350000
|
||||
|
|
@ -167,6 +178,8 @@ typedef volatile unsigned int *dv_reg_p;
|
|||
#define KS2_DDR3BPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x36C)
|
||||
#define KS2_ARMPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x370)
|
||||
#define KS2_ARMPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x374)
|
||||
#define KS2_UARTPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x390)
|
||||
#define KS2_UARTPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x394)
|
||||
|
||||
#define KS2_PLL_CNTRL_BASE 0x02310000
|
||||
#define KS2_CLOCK_BASE KS2_PLL_CNTRL_BASE
|
||||
|
|
@ -179,10 +192,17 @@ typedef volatile unsigned int *dv_reg_p;
|
|||
#define KS2_RSTYPE_PLL_SOFT BIT(13)
|
||||
|
||||
/* SPI */
|
||||
#ifdef CONFIG_SOC_K2G
|
||||
#define KS2_SPI0_BASE 0x21805400
|
||||
#define KS2_SPI1_BASE 0x21805800
|
||||
#define KS2_SPI2_BASE 0x21805c00
|
||||
#define KS2_SPI3_BASE 0x21806000
|
||||
#else
|
||||
#define KS2_SPI0_BASE 0x21000400
|
||||
#define KS2_SPI1_BASE 0x21000600
|
||||
#define KS2_SPI2_BASE 0x21000800
|
||||
#define KS2_SPI_BASE KS2_SPI0_BASE
|
||||
#endif
|
||||
|
||||
/* AEMIF */
|
||||
#define KS2_AEMIF_CNTRL_BASE 0x21000a00
|
||||
|
|
@ -194,10 +214,16 @@ typedef volatile unsigned int *dv_reg_p;
|
|||
/* MSMC control */
|
||||
#define KS2_MSMC_CTRL_BASE 0x0bc00000
|
||||
#define KS2_MSMC_DATA_BASE 0x0c000000
|
||||
#ifndef CONFIG_SOC_K2G
|
||||
#define KS2_MSMC_SEGMENT_TETRIS 8
|
||||
#define KS2_MSMC_SEGMENT_NETCP 9
|
||||
#define KS2_MSMC_SEGMENT_QM_PDSP 10
|
||||
#define KS2_MSMC_SEGMENT_PCIE0 11
|
||||
#else
|
||||
#define KS2_MSMC_SEGMENT_TETRIS 1
|
||||
#define KS2_MSMC_SEGMENT_NETCP 4
|
||||
#define KS2_MSMC_SEGMENT_PCIE0 5
|
||||
#endif
|
||||
|
||||
/* MSMC segment size shift bits */
|
||||
#define KS2_MSMC_SEG_SIZE_SHIFT 12
|
||||
|
|
@ -211,6 +237,22 @@ typedef volatile unsigned int *dv_reg_p;
|
|||
#define KS2_MISC_CTRL (KS2_DEVICE_STATE_CTRL_BASE + 0xc7c)
|
||||
|
||||
/* Queue manager */
|
||||
#ifdef CONFIG_SOC_K2G
|
||||
#define KS2_QM_BASE_ADDRESS 0x040C0000
|
||||
#define KS2_QM_CONF_BASE 0x04040000
|
||||
#define KS2_QM_DESC_SETUP_BASE 0x04080000
|
||||
#define KS2_QM_STATUS_RAM_BASE 0x0 /* K2G doesn't have it */
|
||||
#define KS2_QM_INTD_CONF_BASE 0x0
|
||||
#define KS2_QM_PDSP1_CMD_BASE 0x0
|
||||
#define KS2_QM_PDSP1_CTRL_BASE 0x0
|
||||
#define KS2_QM_PDSP1_IRAM_BASE 0x0
|
||||
#define KS2_QM_MANAGER_QUEUES_BASE 0x040c0000
|
||||
#define KS2_QM_MANAGER_Q_PROXY_BASE 0x04040200
|
||||
#define KS2_QM_QUEUE_STATUS_BASE 0x04100000
|
||||
#define KS2_QM_LINK_RAM_BASE 0x04020000
|
||||
#define KS2_QM_REGION_NUM 8
|
||||
#define KS2_QM_QPOOL_NUM 112
|
||||
#else
|
||||
#define KS2_QM_BASE_ADDRESS 0x23a80000
|
||||
#define KS2_QM_CONF_BASE 0x02a02000
|
||||
#define KS2_QM_DESC_SETUP_BASE 0x02a03000
|
||||
|
|
@ -225,6 +267,7 @@ typedef volatile unsigned int *dv_reg_p;
|
|||
#define KS2_QM_LINK_RAM_BASE 0x00100000
|
||||
#define KS2_QM_REGION_NUM 64
|
||||
#define KS2_QM_QPOOL_NUM 4000
|
||||
#endif
|
||||
|
||||
/* USB */
|
||||
#define KS2_USB_SS_BASE 0x02680000
|
||||
|
|
@ -247,6 +290,7 @@ typedef volatile unsigned int *dv_reg_p;
|
|||
#define CPU_66AK2Hx 0xb981
|
||||
#define CPU_66AK2Ex 0xb9a6
|
||||
#define CPU_66AK2Lx 0xb9a7
|
||||
#define CPU_66AK2Gx 0xbb06
|
||||
|
||||
/* DEVSPEED register */
|
||||
#define DEVSPEED_DEVSPEED_SHIFT 16
|
||||
|
|
@ -267,6 +311,10 @@ typedef volatile unsigned int *dv_reg_p;
|
|||
#include <asm/arch/hardware-k2l.h>
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SOC_K2G
|
||||
#include <asm/arch/hardware-k2g.h>
|
||||
#endif
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
static inline u16 get_part_number(void)
|
||||
|
|
@ -291,6 +339,11 @@ static inline u8 cpu_is_k2l(void)
|
|||
return get_part_number() == CPU_66AK2Lx;
|
||||
}
|
||||
|
||||
static inline u8 cpu_is_k2g(void)
|
||||
{
|
||||
return get_part_number() == CPU_66AK2Gx;
|
||||
}
|
||||
|
||||
static inline u8 cpu_revision(void)
|
||||
{
|
||||
u32 jtag_id = __raw_readl(KS2_JTAG_ID_REG);
|
||||
|
|
|
|||
22
arch/arm/mach-keystone/include/mach/mmc_host_def.h
Normal file
22
arch/arm/mach-keystone/include/mach/mmc_host_def.h
Normal file
|
|
@ -0,0 +1,22 @@
|
|||
/*
|
||||
* K2G: MMC
|
||||
*
|
||||
* (C) Copyright 2015
|
||||
* Texas Instruments Incorporated, <www.ti.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef K2G_MMC_HOST_DEF_H
|
||||
#define K2G_MMC_HOST_DEF_H
|
||||
|
||||
#include <asm/omap_mmc.h>
|
||||
|
||||
/*
|
||||
* OMAP HSMMC register definitions
|
||||
*/
|
||||
|
||||
#define OMAP_HSMMC1_BASE 0x23000100
|
||||
#define OMAP_HSMMC2_BASE 0x23100100
|
||||
|
||||
#endif /* K2G_MMC_HOST_DEF_H */
|
||||
58
arch/arm/mach-keystone/include/mach/mux-k2g.h
Normal file
58
arch/arm/mach-keystone/include/mach/mux-k2g.h
Normal file
|
|
@ -0,0 +1,58 @@
|
|||
/*
|
||||
* K2G: Pinmux configuration
|
||||
*
|
||||
* (C) Copyright 2015
|
||||
* Texas Instruments Incorporated, <www.ti.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_MUX_K2G_H
|
||||
#define __ASM_ARCH_MUX_K2G_H
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#define K2G_PADCFG_REG (KS2_DEVICE_STATE_CTRL_BASE + 0x1000)
|
||||
|
||||
/*
|
||||
* 20:19 - buffer class RW fixed
|
||||
* 18 - rxactive (Input enabled for the pad ) 0 - Di; 1 - En;
|
||||
* 17 - pulltypesel (0 - PULLDOWN; 1 - PULLUP);
|
||||
* 16 - pulluden (0 - PULLUP/DOWN EN; 1 - DI);
|
||||
* 3:0 - muxmode (available modes 0:5)
|
||||
*/
|
||||
|
||||
#define PIN_IEN (1 << 18) /* pin input enabled */
|
||||
#define PIN_PDIS (1 << 16) /* pull up/down disabled */
|
||||
#define PIN_PTU (1 << 17) /* pull up */
|
||||
#define PIN_PTD (0 << 17) /* pull down */
|
||||
|
||||
#define MODE(m) ((m) & 0x7)
|
||||
#define MAX_PIN_N 260
|
||||
|
||||
#define MUX_CFG(value, index) \
|
||||
__raw_writel(\
|
||||
(value) | \
|
||||
(__raw_readl(K2G_PADCFG_REG + (index << 2)) & \
|
||||
(0x3 << 19)),\
|
||||
(K2G_PADCFG_REG + (index << 2))\
|
||||
);
|
||||
|
||||
struct pin_cfg {
|
||||
int reg_inx;
|
||||
u32 val;
|
||||
};
|
||||
|
||||
static inline void configure_pin_mux(struct pin_cfg *pin_mux)
|
||||
{
|
||||
if (!pin_mux)
|
||||
return;
|
||||
|
||||
while ((pin_mux->reg_inx >= 0) && (pin_mux->reg_inx < MAX_PIN_N)) {
|
||||
MUX_CFG(pin_mux->val, pin_mux->reg_inx);
|
||||
pin_mux++;
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* __ASM_ARCH_MUX_K2G_H */
|
||||
|
|
@ -103,7 +103,9 @@ int arch_cpu_init(void)
|
|||
|
||||
msmc_share_all_segments(KS2_MSMC_SEGMENT_TETRIS);
|
||||
msmc_share_all_segments(KS2_MSMC_SEGMENT_NETCP);
|
||||
#ifdef KS2_MSMC_SEGMENT_QM_PDSP
|
||||
msmc_share_all_segments(KS2_MSMC_SEGMENT_QM_PDSP);
|
||||
#endif
|
||||
msmc_share_all_segments(KS2_MSMC_SEGMENT_PCIE0);
|
||||
|
||||
/* Initialize the PCIe-0 to work as Root Complex */
|
||||
|
|
@ -122,8 +124,10 @@ int arch_cpu_init(void)
|
|||
* UART register PWREMU_MGMT is initialized. Linux UART
|
||||
* driver doesn't handle this.
|
||||
*/
|
||||
#ifndef CONFIG_DM_SERIAL
|
||||
NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM2),
|
||||
CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -167,6 +171,9 @@ int print_cpuinfo(void)
|
|||
case CPU_66AK2Ex:
|
||||
puts("66AK2Ex SR");
|
||||
break;
|
||||
case CPU_66AK2Gx:
|
||||
puts("66AK2Gx SR");
|
||||
break;
|
||||
default:
|
||||
puts("Unknown\n");
|
||||
}
|
||||
|
|
|
|||
31
arch/arm/mach-mvebu/Kconfig
Normal file
31
arch/arm/mach-mvebu/Kconfig
Normal file
|
|
@ -0,0 +1,31 @@
|
|||
if ARCH_MVEBU
|
||||
|
||||
choice
|
||||
prompt "Marvell MVEBU (Armada XP/38x) board select"
|
||||
optional
|
||||
|
||||
config TARGET_DB_88F6820_GP
|
||||
bool "Support DB-88F6820-GP"
|
||||
|
||||
config TARGET_DB_MV784MP_GP
|
||||
bool "Support db-mv784mp-gp"
|
||||
|
||||
config TARGET_MAXBCM
|
||||
bool "Support maxbcm"
|
||||
|
||||
endchoice
|
||||
|
||||
config SYS_SOC
|
||||
default "mvebu"
|
||||
|
||||
config MVEBU_BOOTROM_UARTBOOT
|
||||
bool "Use kwboot to boot via BootROM xmodem protocol"
|
||||
help
|
||||
This option provides support for booting via the Marvell
|
||||
xmodem protocol, used by the kwboot tool.
|
||||
|
||||
Please don't forget to configure the boot device in
|
||||
the board specific kwbimage.cfg file this way:
|
||||
BOOT_FROM uart
|
||||
|
||||
endif
|
||||
|
|
@ -27,6 +27,14 @@ static struct mbus_win windows[] = {
|
|||
CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_BOOTROM },
|
||||
};
|
||||
|
||||
void lowlevel_init(void)
|
||||
{
|
||||
/*
|
||||
* Dummy implementation, we only need LOWLEVEL_INIT
|
||||
* on Armada to configure CP15 in start.S / cpu_init_cp15()
|
||||
*/
|
||||
}
|
||||
|
||||
void reset_cpu(unsigned long ignored)
|
||||
{
|
||||
struct mvebu_system_registers *reg =
|
||||
|
|
@ -214,7 +222,10 @@ static void setup_usb_phys(void)
|
|||
|
||||
int arch_cpu_init(void)
|
||||
{
|
||||
#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_ARMADA_38X)
|
||||
#if !defined(CONFIG_SPL_BUILD)
|
||||
struct pl310_regs *const pl310 =
|
||||
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
|
||||
|
||||
/*
|
||||
* Only with disabled MMU its possible to switch the base
|
||||
* register address on Armada 38x. Without this the SDRAM
|
||||
|
|
@ -234,18 +245,14 @@ int arch_cpu_init(void)
|
|||
* configured the internal register base to the value used
|
||||
* in the macros / defines in the U-Boot header (soc.h).
|
||||
*/
|
||||
if (mvebu_soc_family() == MVEBU_SOC_A38X) {
|
||||
struct pl310_regs *const pl310 =
|
||||
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
|
||||
|
||||
/*
|
||||
* To fully release / unlock this area from cache, we need
|
||||
* to flush all caches and disable the L2 cache.
|
||||
*/
|
||||
icache_disable();
|
||||
dcache_disable();
|
||||
clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
|
||||
}
|
||||
/*
|
||||
* To fully release / unlock this area from cache, we need
|
||||
* to flush all caches and disable the L2 cache.
|
||||
*/
|
||||
icache_disable();
|
||||
dcache_disable();
|
||||
clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
|
||||
#endif
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -119,6 +119,8 @@ int mvebu_mbus_probe(struct mbus_win windows[], int count);
|
|||
int mvebu_soc_family(void);
|
||||
u32 mvebu_get_nand_clock(void);
|
||||
|
||||
void return_to_bootrom(void);
|
||||
|
||||
int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks);
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -31,7 +31,7 @@
|
|||
/* SOC specific definations */
|
||||
#define INTREG_BASE 0xd0000000
|
||||
#define INTREG_BASE_ADDR_REG (INTREG_BASE + 0x20080)
|
||||
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SYS_MVEBU_DDR_A38X)
|
||||
#if defined(CONFIG_SPL_BUILD)
|
||||
/*
|
||||
* On A38x switching the regs base address without running from
|
||||
* SDRAM doesn't seem to work. So let the SPL still use the
|
||||
|
|
|
|||
|
|
@ -5,9 +5,25 @@
|
|||
#include <config.h>
|
||||
#include <linux/linkage.h>
|
||||
|
||||
#ifdef CONFIG_MVEBU_BOOTROM_UARTBOOT
|
||||
ENTRY(save_boot_params)
|
||||
stmfd sp!, {r0 - r12, lr} /* @ save registers on stack */
|
||||
ldr r12, =CONFIG_SPL_BOOTROM_SAVE
|
||||
str sp, [r12]
|
||||
b save_boot_params_ret
|
||||
ENDPROC(save_boot_params)
|
||||
|
||||
ENTRY(return_to_bootrom)
|
||||
ldr r12, =CONFIG_SPL_BOOTROM_SAVE
|
||||
ldr sp, [r12]
|
||||
mov r0, #0x0 /* @ return value: 0x0 NO_ERR */
|
||||
ldmfd sp!, {r0 - r12, pc} /* @ restore regs and return */
|
||||
ENDPROC(return_to_bootrom)
|
||||
#else
|
||||
ENTRY(save_boot_params)
|
||||
b save_boot_params_ret
|
||||
ENDPROC(save_boot_params)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* cache_inv - invalidate Cache line
|
||||
|
|
|
|||
|
|
@ -31,11 +31,18 @@ u32 spl_boot_mode(void)
|
|||
|
||||
void board_init_f(ulong dummy)
|
||||
{
|
||||
/* Set global data pointer */
|
||||
gd = &gdata;
|
||||
#ifndef CONFIG_MVEBU_BOOTROM_UARTBOOT
|
||||
/*
|
||||
* Only call arch_cpu_init() when not returning to the
|
||||
* Marvell BootROM, which is done when booting via
|
||||
* the xmodem protocol (kwboot tool). Otherwise the
|
||||
* internal register will get remapped and the BootROM
|
||||
* can't continue to run correctly.
|
||||
*/
|
||||
|
||||
/* Linux expects the internal registers to be at 0xf1000000 */
|
||||
arch_cpu_init();
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Pin muxing needs to be done before UART output, since
|
||||
|
|
@ -54,5 +61,18 @@ void board_init_f(ulong dummy)
|
|||
/* Setup DDR */
|
||||
ddr3_init();
|
||||
|
||||
board_init_r(NULL, 0);
|
||||
#ifdef CONFIG_MVEBU_BOOTROM_UARTBOOT
|
||||
/*
|
||||
* Return to the BootROM to continue the Marvell xmodem
|
||||
* UART boot protocol. As initiated by the kwboot tool.
|
||||
*
|
||||
* This can only be done by the BootROM and not by the
|
||||
* U-Boot SPL infrastructure, since the beginning of the
|
||||
* image is already read and interpreted by the BootROM.
|
||||
* SPL has no chance to receive this information. So we
|
||||
* need to return to the BootROM to enable this xmodem
|
||||
* UART download.
|
||||
*/
|
||||
return_to_bootrom();
|
||||
#endif
|
||||
}
|
||||
|
|
|
|||
|
|
@ -52,6 +52,18 @@ void enable_caches(void)
|
|||
#endif
|
||||
}
|
||||
|
||||
void v7_outer_cache_enable(void)
|
||||
{
|
||||
/* disable the L2 cache */
|
||||
writel(0, &pl310->pl310_ctrl);
|
||||
|
||||
/* enable BRESP, instruction and data prefetch, full line of zeroes */
|
||||
setbits_le32(&pl310->pl310_aux_ctrl,
|
||||
L310_AUX_CTRL_DATA_PREFETCH_MASK |
|
||||
L310_AUX_CTRL_INST_PREFETCH_MASK |
|
||||
L310_SHARED_ATT_OVERRIDE_ENABLE);
|
||||
}
|
||||
|
||||
/*
|
||||
* DesignWare Ethernet initialization
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -15,7 +15,8 @@ LDFLAGS_FINAL += --bss-plt
|
|||
PLATFORM_RELFLAGS += -fpic -mrelocatable -ffunction-sections \
|
||||
-fdata-sections -mcall-linux
|
||||
|
||||
PLATFORM_CPPFLAGS += -D__powerpc__ -ffixed-r2 -m32
|
||||
PF_CPPFLAGS_POWERPC := $(call cc-option,-fno-ira-hoist-pressure,)
|
||||
PLATFORM_CPPFLAGS += -D__powerpc__ -ffixed-r2 -m32 $(PF_CPPFLAGS_POWERPC)
|
||||
PLATFORM_LDFLAGS += -m32 -melf32ppclinux
|
||||
|
||||
#
|
||||
|
|
|
|||
|
|
@ -1,986 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2000-2011
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <watchdog.h>
|
||||
#include <command.h>
|
||||
#include <malloc.h>
|
||||
#include <stdio_dev.h>
|
||||
#ifdef CONFIG_8xx
|
||||
#include <mpc8xx.h>
|
||||
#endif
|
||||
#ifdef CONFIG_5xx
|
||||
#include <mpc5xx.h>
|
||||
#endif
|
||||
#ifdef CONFIG_MPC5xxx
|
||||
#include <mpc5xxx.h>
|
||||
#endif
|
||||
#if defined(CONFIG_CMD_IDE)
|
||||
#include <ide.h>
|
||||
#endif
|
||||
#if defined(CONFIG_CMD_SCSI)
|
||||
#include <scsi.h>
|
||||
#endif
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#include <kgdb.h>
|
||||
#endif
|
||||
#ifdef CONFIG_STATUS_LED
|
||||
#include <status_led.h>
|
||||
#endif
|
||||
#include <net.h>
|
||||
#ifdef CONFIG_GENERIC_MMC
|
||||
#include <mmc.h>
|
||||
#endif
|
||||
#include <serial.h>
|
||||
#ifdef CONFIG_SYS_ALLOC_DPRAM
|
||||
#if !defined(CONFIG_CPM2)
|
||||
#include <commproc.h>
|
||||
#endif
|
||||
#endif
|
||||
#include <version.h>
|
||||
#if defined(CONFIG_BAB7xx)
|
||||
#include <w83c553f.h>
|
||||
#endif
|
||||
#include <dtt.h>
|
||||
#if defined(CONFIG_POST)
|
||||
#include <post.h>
|
||||
#endif
|
||||
#if defined(CONFIG_LOGBUFFER)
|
||||
#include <logbuff.h>
|
||||
#endif
|
||||
#if defined(CONFIG_SYS_INIT_RAM_LOCK) && defined(CONFIG_E500)
|
||||
#include <asm/cache.h>
|
||||
#endif
|
||||
#ifdef CONFIG_PS2KBD
|
||||
#include <keyboard.h>
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ADDR_MAP
|
||||
#include <asm/mmu.h>
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MP
|
||||
#include <asm/mp.h>
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_BITBANGMII
|
||||
#include <miiphy.h>
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_UPDATE_FLASH_SIZE
|
||||
extern int update_flash_size(int flash_size);
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CMD_DOC)
|
||||
void doc_init(void);
|
||||
#endif
|
||||
#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C)
|
||||
#include <i2c.h>
|
||||
#endif
|
||||
#include <spi.h>
|
||||
#include <nand.h>
|
||||
|
||||
static char *failed = "*** failed ***\n";
|
||||
|
||||
#if defined(CONFIG_OXC) || defined(CONFIG_RMU)
|
||||
extern flash_info_t flash_info[];
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_START_IDE)
|
||||
extern int board_start_ide(void);
|
||||
#endif
|
||||
#include <environment.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#if !defined(CONFIG_SYS_MEM_TOP_HIDE)
|
||||
#define CONFIG_SYS_MEM_TOP_HIDE 0
|
||||
#endif
|
||||
|
||||
extern ulong __init_end;
|
||||
extern ulong __bss_end;
|
||||
ulong monitor_flash_len;
|
||||
|
||||
#if defined(CONFIG_CMD_BEDBUG)
|
||||
#include <bedbug/type.h>
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Utilities
|
||||
*/
|
||||
|
||||
/*
|
||||
* All attempts to come up with a "common" initialization sequence
|
||||
* that works for all boards and architectures failed: some of the
|
||||
* requirements are just _too_ different. To get rid of the resulting
|
||||
* mess of board dependend #ifdef'ed code we now make the whole
|
||||
* initialization sequence configurable to the user.
|
||||
*
|
||||
* The requirements for any new initalization function is simple: it
|
||||
* receives a pointer to the "global data" structure as it's only
|
||||
* argument, and returns an integer return code, where 0 means
|
||||
* "continue" and != 0 means "fatal error, hang the system".
|
||||
*/
|
||||
typedef int (init_fnc_t)(void);
|
||||
|
||||
/*
|
||||
* Init Utilities
|
||||
*
|
||||
* Some of this code should be moved into the core functions,
|
||||
* but let's get it working (again) first...
|
||||
*/
|
||||
|
||||
static int init_baudrate(void)
|
||||
{
|
||||
gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/***********************************************************************/
|
||||
|
||||
static void __board_add_ram_info(int use_default)
|
||||
{
|
||||
/* please define platform specific board_add_ram_info() */
|
||||
}
|
||||
|
||||
void board_add_ram_info(int)
|
||||
__attribute__ ((weak, alias("__board_add_ram_info")));
|
||||
|
||||
static int __board_flash_wp_on(void)
|
||||
{
|
||||
/*
|
||||
* Most flashes can't be detected when write protection is enabled,
|
||||
* so provide a way to let U-Boot gracefully ignore write protected
|
||||
* devices.
|
||||
*/
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_flash_wp_on(void)
|
||||
__attribute__ ((weak, alias("__board_flash_wp_on")));
|
||||
|
||||
static void __cpu_secondary_init_r(void)
|
||||
{
|
||||
}
|
||||
|
||||
void cpu_secondary_init_r(void)
|
||||
__attribute__ ((weak, alias("__cpu_secondary_init_r")));
|
||||
|
||||
static int init_func_ram(void)
|
||||
{
|
||||
#ifdef CONFIG_BOARD_TYPES
|
||||
int board_type = gd->board_type;
|
||||
#else
|
||||
int board_type = 0; /* use dummy arg */
|
||||
#endif
|
||||
puts("DRAM: ");
|
||||
|
||||
gd->ram_size = initdram(board_type);
|
||||
|
||||
if (gd->ram_size > 0) {
|
||||
print_size(gd->ram_size, "");
|
||||
board_add_ram_info(0);
|
||||
putc('\n');
|
||||
return 0;
|
||||
}
|
||||
puts(failed);
|
||||
return 1;
|
||||
}
|
||||
|
||||
/***********************************************************************/
|
||||
|
||||
#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C)
|
||||
static int init_func_i2c(void)
|
||||
{
|
||||
puts("I2C: ");
|
||||
#ifdef CONFIG_SYS_I2C
|
||||
i2c_init_all();
|
||||
#else
|
||||
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
|
||||
#endif
|
||||
puts("ready\n");
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_HARD_SPI)
|
||||
static int init_func_spi(void)
|
||||
{
|
||||
puts("SPI: ");
|
||||
spi_init();
|
||||
puts("ready\n");
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
/***********************************************************************/
|
||||
|
||||
#if defined(CONFIG_WATCHDOG)
|
||||
int init_func_watchdog_init(void)
|
||||
{
|
||||
#if defined(CONFIG_MPC85xx)
|
||||
init_85xx_watchdog();
|
||||
#endif
|
||||
puts(" Watchdog enabled\n");
|
||||
WATCHDOG_RESET();
|
||||
return 0;
|
||||
}
|
||||
|
||||
int init_func_watchdog_reset(void)
|
||||
{
|
||||
WATCHDOG_RESET();
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_WATCHDOG */
|
||||
|
||||
/*
|
||||
* Initialization sequence
|
||||
*/
|
||||
|
||||
static init_fnc_t *init_sequence[] = {
|
||||
#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
|
||||
probecpu,
|
||||
#endif
|
||||
#if defined(CONFIG_BOARD_EARLY_INIT_F)
|
||||
board_early_init_f,
|
||||
#endif
|
||||
#if !defined(CONFIG_8xx_CPUCLK_DEFAULT)
|
||||
get_clocks, /* get CPU and bus clocks (etc.) */
|
||||
#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \
|
||||
&& !defined(CONFIG_TQM885D)
|
||||
adjust_sdram_tbs_8xx,
|
||||
#endif
|
||||
init_timebase,
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_ALLOC_DPRAM
|
||||
#if !defined(CONFIG_CPM2)
|
||||
dpram_init,
|
||||
#endif
|
||||
#endif
|
||||
#if defined(CONFIG_BOARD_POSTCLK_INIT)
|
||||
board_postclk_init,
|
||||
#endif
|
||||
env_init,
|
||||
#if defined(CONFIG_8xx_CPUCLK_DEFAULT)
|
||||
/* get CPU and bus clocks according to the environment variable */
|
||||
get_clocks_866,
|
||||
/* adjust sdram refresh rate according to the new clock */
|
||||
sdram_adjust_866,
|
||||
init_timebase,
|
||||
#endif
|
||||
init_baudrate,
|
||||
serial_init,
|
||||
console_init_f,
|
||||
display_options,
|
||||
#if defined(CONFIG_MPC8260)
|
||||
prt_8260_rsr,
|
||||
prt_8260_clks,
|
||||
#endif /* CONFIG_MPC8260 */
|
||||
#if defined(CONFIG_MPC83xx)
|
||||
prt_83xx_rsr,
|
||||
#endif
|
||||
checkcpu,
|
||||
#if defined(CONFIG_MPC5xxx)
|
||||
prt_mpc5xxx_clks,
|
||||
#endif /* CONFIG_MPC5xxx */
|
||||
checkboard,
|
||||
INIT_FUNC_WATCHDOG_INIT
|
||||
#if defined(CONFIG_MISC_INIT_F)
|
||||
misc_init_f,
|
||||
#endif
|
||||
INIT_FUNC_WATCHDOG_RESET
|
||||
#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C)
|
||||
init_func_i2c,
|
||||
#endif
|
||||
#if defined(CONFIG_HARD_SPI)
|
||||
init_func_spi,
|
||||
#endif
|
||||
#ifdef CONFIG_POST
|
||||
post_init_f,
|
||||
#endif
|
||||
INIT_FUNC_WATCHDOG_RESET
|
||||
init_func_ram,
|
||||
#if defined(CONFIG_SYS_DRAM_TEST)
|
||||
testdram,
|
||||
#endif /* CONFIG_SYS_DRAM_TEST */
|
||||
INIT_FUNC_WATCHDOG_RESET
|
||||
NULL, /* Terminate this list */
|
||||
};
|
||||
|
||||
static int __fixup_cpu(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int fixup_cpu(void) __attribute__((weak, alias("__fixup_cpu")));
|
||||
|
||||
/*
|
||||
* This is the first part of the initialization sequence that is
|
||||
* implemented in C, but still running from ROM.
|
||||
*
|
||||
* The main purpose is to provide a (serial) console interface as
|
||||
* soon as possible (so we can see any error messages), and to
|
||||
* initialize the RAM so that we can relocate the monitor code to
|
||||
* RAM.
|
||||
*
|
||||
* Be aware of the restrictions: global data is read-only, BSS is not
|
||||
* initialized, and stack space is limited to a few kB.
|
||||
*/
|
||||
|
||||
void board_init_f(ulong bootflag)
|
||||
{
|
||||
bd_t *bd;
|
||||
ulong len, addr, addr_sp;
|
||||
ulong *s;
|
||||
gd_t *id;
|
||||
init_fnc_t **init_fnc_ptr;
|
||||
|
||||
#ifdef CONFIG_PRAM
|
||||
ulong reg;
|
||||
#endif
|
||||
|
||||
/* Pointer is writable since we allocated a register for it */
|
||||
gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
|
||||
/* compiler optimization barrier needed for GCC >= 3.4 */
|
||||
__asm__ __volatile__("":::"memory");
|
||||
|
||||
#if !defined(CONFIG_CPM2) && !defined(CONFIG_MPC512X) && \
|
||||
!defined(CONFIG_MPC83xx) && !defined(CONFIG_MPC85xx) && \
|
||||
!defined(CONFIG_MPC86xx)
|
||||
/* Clear initial global data */
|
||||
memset((void *) gd, 0, sizeof(gd_t));
|
||||
#endif
|
||||
|
||||
gd->flags = bootflag;
|
||||
|
||||
for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr)
|
||||
if ((*init_fnc_ptr) () != 0)
|
||||
hang();
|
||||
|
||||
#ifdef CONFIG_POST
|
||||
post_bootmode_init();
|
||||
post_run(NULL, POST_ROM | post_bootmode_get(NULL));
|
||||
#endif
|
||||
|
||||
WATCHDOG_RESET();
|
||||
|
||||
/*
|
||||
* Now that we have DRAM mapped and working, we can
|
||||
* relocate the code and continue running from DRAM.
|
||||
*
|
||||
* Reserve memory at end of RAM for (top down in that order):
|
||||
* - area that won't get touched by U-Boot and Linux (optional)
|
||||
* - kernel log buffer
|
||||
* - protected RAM
|
||||
* - LCD framebuffer
|
||||
* - monitor code
|
||||
* - board info struct
|
||||
*/
|
||||
len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE;
|
||||
|
||||
/*
|
||||
* Subtract specified amount of memory to hide so that it won't
|
||||
* get "touched" at all by U-Boot. By fixing up gd->ram_size
|
||||
* the Linux kernel should now get passed the now "corrected"
|
||||
* memory size and won't touch it either. This should work
|
||||
* for arch/ppc and arch/powerpc. Only Linux board ports in
|
||||
* arch/powerpc with bootwrapper support, that recalculate the
|
||||
* memory size from the SDRAM controller setup will have to
|
||||
* get fixed.
|
||||
*/
|
||||
gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE;
|
||||
|
||||
addr = CONFIG_SYS_SDRAM_BASE + get_effective_memsize();
|
||||
|
||||
#if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500))
|
||||
/*
|
||||
* We need to make sure the location we intend to put secondary core
|
||||
* boot code is reserved and not used by any part of u-boot
|
||||
*/
|
||||
if (addr > determine_mp_bootpg(NULL)) {
|
||||
addr = determine_mp_bootpg(NULL);
|
||||
debug("Reserving MP boot page to %08lx\n", addr);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_LOGBUFFER
|
||||
#ifndef CONFIG_ALT_LB_ADDR
|
||||
/* reserve kernel log buffer */
|
||||
addr -= (LOGBUFF_RESERVE);
|
||||
debug("Reserving %dk for kernel logbuffer at %08lx\n", LOGBUFF_LEN,
|
||||
addr);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PRAM
|
||||
/*
|
||||
* reserve protected RAM
|
||||
*/
|
||||
reg = getenv_ulong("pram", 10, CONFIG_PRAM);
|
||||
addr -= (reg << 10); /* size is in kB */
|
||||
debug("Reserving %ldk for protected RAM at %08lx\n", reg, addr);
|
||||
#endif /* CONFIG_PRAM */
|
||||
|
||||
/* round down to next 4 kB limit */
|
||||
addr &= ~(4096 - 1);
|
||||
debug("Top of RAM usable for U-Boot at: %08lx\n", addr);
|
||||
|
||||
#ifdef CONFIG_LCD
|
||||
#ifdef CONFIG_FB_ADDR
|
||||
gd->fb_base = CONFIG_FB_ADDR;
|
||||
#else
|
||||
/* reserve memory for LCD display (always full pages) */
|
||||
addr = lcd_setmem(addr);
|
||||
gd->fb_base = addr;
|
||||
#endif /* CONFIG_FB_ADDR */
|
||||
#endif /* CONFIG_LCD */
|
||||
|
||||
#if defined(CONFIG_VIDEO) && defined(CONFIG_8xx)
|
||||
/* reserve memory for video display (always full pages) */
|
||||
addr = video_setmem(addr);
|
||||
gd->fb_base = addr;
|
||||
#endif /* CONFIG_VIDEO */
|
||||
|
||||
/*
|
||||
* reserve memory for U-Boot code, data & bss
|
||||
* round down to next 4 kB limit
|
||||
*/
|
||||
addr -= len;
|
||||
addr &= ~(4096 - 1);
|
||||
#ifdef CONFIG_E500
|
||||
/* round down to next 64 kB limit so that IVPR stays aligned */
|
||||
addr &= ~(65536 - 1);
|
||||
#endif
|
||||
|
||||
debug("Reserving %ldk for U-Boot at: %08lx\n", len >> 10, addr);
|
||||
|
||||
/*
|
||||
* reserve memory for malloc() arena
|
||||
*/
|
||||
addr_sp = addr - TOTAL_MALLOC_LEN;
|
||||
debug("Reserving %dk for malloc() at: %08lx\n",
|
||||
TOTAL_MALLOC_LEN >> 10, addr_sp);
|
||||
|
||||
/*
|
||||
* (permanently) allocate a Board Info struct
|
||||
* and a permanent copy of the "global" data
|
||||
*/
|
||||
addr_sp -= sizeof(bd_t);
|
||||
bd = (bd_t *) addr_sp;
|
||||
memset(bd, 0, sizeof(bd_t));
|
||||
gd->bd = bd;
|
||||
debug("Reserving %zu Bytes for Board Info at: %08lx\n",
|
||||
sizeof(bd_t), addr_sp);
|
||||
addr_sp -= sizeof(gd_t);
|
||||
id = (gd_t *) addr_sp;
|
||||
debug("Reserving %zu Bytes for Global Data at: %08lx\n",
|
||||
sizeof(gd_t), addr_sp);
|
||||
|
||||
/*
|
||||
* Finally, we set up a new (bigger) stack.
|
||||
*
|
||||
* Leave some safety gap for SP, force alignment on 16 byte boundary
|
||||
* Clear initial stack frame
|
||||
*/
|
||||
addr_sp -= 16;
|
||||
addr_sp &= ~0xF;
|
||||
s = (ulong *) addr_sp;
|
||||
*s = 0; /* Terminate back chain */
|
||||
*++s = 0; /* NULL return address */
|
||||
debug("Stack Pointer at: %08lx\n", addr_sp);
|
||||
|
||||
/*
|
||||
* Save local variables to board info struct
|
||||
*/
|
||||
|
||||
bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of memory */
|
||||
bd->bi_memsize = gd->ram_size; /* size in bytes */
|
||||
|
||||
#ifdef CONFIG_SYS_SRAM_BASE
|
||||
bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */
|
||||
bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_8xx) || defined(CONFIG_MPC8260) || defined(CONFIG_5xx) || \
|
||||
defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
|
||||
bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */
|
||||
#endif
|
||||
#if defined(CONFIG_MPC5xxx)
|
||||
bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */
|
||||
#endif
|
||||
#if defined(CONFIG_MPC83xx)
|
||||
bd->bi_immrbar = CONFIG_SYS_IMMR;
|
||||
#endif
|
||||
|
||||
WATCHDOG_RESET();
|
||||
bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */
|
||||
bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */
|
||||
#if defined(CONFIG_CPM2)
|
||||
bd->bi_cpmfreq = gd->arch.cpm_clk;
|
||||
bd->bi_brgfreq = gd->arch.brg_clk;
|
||||
bd->bi_sccfreq = gd->arch.scc_clk;
|
||||
bd->bi_vco = gd->arch.vco_out;
|
||||
#endif /* CONFIG_CPM2 */
|
||||
#if defined(CONFIG_MPC512X)
|
||||
bd->bi_ipsfreq = gd->arch.ips_clk;
|
||||
#endif /* CONFIG_MPC512X */
|
||||
#if defined(CONFIG_MPC5xxx)
|
||||
bd->bi_ipbfreq = gd->arch.ipb_clk;
|
||||
bd->bi_pcifreq = gd->pci_clk;
|
||||
#endif /* CONFIG_MPC5xxx */
|
||||
|
||||
#ifdef CONFIG_SYS_EXTBDINFO
|
||||
strncpy((char *) bd->bi_s_version, "1.2", sizeof(bd->bi_s_version));
|
||||
strncpy((char *) bd->bi_r_version, U_BOOT_VERSION,
|
||||
sizeof(bd->bi_r_version));
|
||||
|
||||
bd->bi_procfreq = gd->cpu_clk; /* Processor Speed, In Hz */
|
||||
bd->bi_plb_busfreq = gd->bus_clk;
|
||||
#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \
|
||||
defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
|
||||
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
|
||||
bd->bi_pci_busfreq = get_PCI_freq();
|
||||
bd->bi_opbfreq = get_OPB_freq();
|
||||
#elif defined(CONFIG_XILINX_405)
|
||||
bd->bi_pci_busfreq = get_PCI_freq();
|
||||
#endif
|
||||
#endif
|
||||
|
||||
debug("New Stack Pointer is: %08lx\n", addr_sp);
|
||||
|
||||
WATCHDOG_RESET();
|
||||
|
||||
gd->relocaddr = addr; /* Store relocation addr, useful for debug */
|
||||
|
||||
memcpy(id, (void *) gd, sizeof(gd_t));
|
||||
|
||||
relocate_code(addr_sp, id, addr);
|
||||
|
||||
/* NOTREACHED - relocate_code() does not return */
|
||||
}
|
||||
|
||||
/*
|
||||
* This is the next part if the initialization sequence: we are now
|
||||
* running from RAM and have a "normal" C environment, i. e. global
|
||||
* data can be written, BSS has been cleared, the stack size in not
|
||||
* that critical any more, etc.
|
||||
*/
|
||||
void board_init_r(gd_t *id, ulong dest_addr)
|
||||
{
|
||||
bd_t *bd;
|
||||
ulong malloc_start;
|
||||
|
||||
#ifndef CONFIG_SYS_NO_FLASH
|
||||
ulong flash_size;
|
||||
#endif
|
||||
|
||||
gd = id; /* initialize RAM version of global data */
|
||||
bd = gd->bd;
|
||||
|
||||
gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
|
||||
|
||||
/* The Malloc area is immediately below the monitor copy in DRAM */
|
||||
malloc_start = dest_addr - TOTAL_MALLOC_LEN;
|
||||
|
||||
#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
|
||||
/*
|
||||
* The gd->arch.cpu pointer is set to an address in flash before
|
||||
* relocation. We need to update it to point to the same CPU entry
|
||||
* in RAM.
|
||||
*/
|
||||
gd->arch.cpu += dest_addr - CONFIG_SYS_MONITOR_BASE;
|
||||
|
||||
/*
|
||||
* If we didn't know the cpu mask & # cores, we can save them of
|
||||
* now rather than 'computing' them constantly
|
||||
*/
|
||||
fixup_cpu();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_EXTRA_ENV_RELOC
|
||||
/*
|
||||
* Some systems need to relocate the env_addr pointer early because the
|
||||
* location it points to will get invalidated before env_relocate is
|
||||
* called. One example is on systems that might use a L2 or L3 cache
|
||||
* in SRAM mode and initialize that cache from SRAM mode back to being
|
||||
* a cache in cpu_init_r.
|
||||
*/
|
||||
gd->env_addr += dest_addr - CONFIG_SYS_MONITOR_BASE;
|
||||
#endif
|
||||
|
||||
serial_initialize();
|
||||
|
||||
debug("Now running in RAM - U-Boot at: %08lx\n", dest_addr);
|
||||
|
||||
WATCHDOG_RESET();
|
||||
|
||||
/*
|
||||
* Setup trap handlers
|
||||
*/
|
||||
trap_init(dest_addr);
|
||||
|
||||
#ifdef CONFIG_ADDR_MAP
|
||||
init_addr_map();
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_BOARD_EARLY_INIT_R)
|
||||
board_early_init_r();
|
||||
#endif
|
||||
|
||||
monitor_flash_len = (ulong)&__init_end - dest_addr;
|
||||
|
||||
WATCHDOG_RESET();
|
||||
|
||||
#ifdef CONFIG_LOGBUFFER
|
||||
logbuff_init_ptrs();
|
||||
#endif
|
||||
#ifdef CONFIG_POST
|
||||
post_output_backlog();
|
||||
#endif
|
||||
|
||||
WATCHDOG_RESET();
|
||||
|
||||
#if defined(CONFIG_SYS_DELAYED_ICACHE)
|
||||
icache_enable(); /* it's time to enable the instruction cache */
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SYS_INIT_RAM_LOCK) && defined(CONFIG_E500)
|
||||
unlock_ram_in_cache(); /* it's time to unlock D-cache in e500 */
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_EARLY_PCI_INIT)
|
||||
/*
|
||||
* Do early PCI configuration _before_ the flash gets initialised,
|
||||
* because PCU ressources are crucial for flash access on some boards.
|
||||
*/
|
||||
pci_init();
|
||||
#endif
|
||||
#if defined(CONFIG_WINBOND_83C553)
|
||||
/*
|
||||
* Initialise the ISA bridge
|
||||
*/
|
||||
initialise_w83c553f();
|
||||
#endif
|
||||
|
||||
asm("sync ; isync");
|
||||
|
||||
mem_malloc_init(malloc_start, TOTAL_MALLOC_LEN);
|
||||
|
||||
#if !defined(CONFIG_SYS_NO_FLASH)
|
||||
puts("Flash: ");
|
||||
|
||||
if (board_flash_wp_on()) {
|
||||
printf("Uninitialized - Write Protect On\n");
|
||||
/* Since WP is on, we can't find real size. Set to 0 */
|
||||
flash_size = 0;
|
||||
} else if ((flash_size = flash_init()) > 0) {
|
||||
#ifdef CONFIG_SYS_FLASH_CHECKSUM
|
||||
print_size(flash_size, "");
|
||||
/*
|
||||
* Compute and print flash CRC if flashchecksum is set to 'y'
|
||||
*
|
||||
* NOTE: Maybe we should add some WATCHDOG_RESET()? XXX
|
||||
*/
|
||||
if (getenv_yesno("flashchecksum") == 1) {
|
||||
printf(" CRC: %08X",
|
||||
crc32(0,
|
||||
(const unsigned char *)
|
||||
CONFIG_SYS_FLASH_BASE, flash_size)
|
||||
);
|
||||
}
|
||||
putc('\n');
|
||||
#else /* !CONFIG_SYS_FLASH_CHECKSUM */
|
||||
print_size(flash_size, "\n");
|
||||
#endif /* CONFIG_SYS_FLASH_CHECKSUM */
|
||||
} else {
|
||||
puts(failed);
|
||||
hang();
|
||||
}
|
||||
|
||||
/* update start of FLASH memory */
|
||||
bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
|
||||
/* size of FLASH memory (final value) */
|
||||
bd->bi_flashsize = flash_size;
|
||||
|
||||
#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
|
||||
/* Make a update of the Memctrl. */
|
||||
update_flash_size(flash_size);
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(CONFIG_OXC) || defined(CONFIG_RMU)
|
||||
/* flash mapped at end of memory map */
|
||||
bd->bi_flashoffset = CONFIG_SYS_TEXT_BASE + flash_size;
|
||||
#elif CONFIG_SYS_MONITOR_BASE == CONFIG_SYS_FLASH_BASE
|
||||
bd->bi_flashoffset = monitor_flash_len; /* reserved area for monitor */
|
||||
#endif
|
||||
#endif /* !CONFIG_SYS_NO_FLASH */
|
||||
|
||||
WATCHDOG_RESET();
|
||||
|
||||
/* initialize higher level parts of CPU like time base and timers */
|
||||
cpu_init_r();
|
||||
|
||||
WATCHDOG_RESET();
|
||||
|
||||
#ifdef CONFIG_SPI
|
||||
#if !defined(CONFIG_ENV_IS_IN_EEPROM)
|
||||
spi_init_f();
|
||||
#endif
|
||||
spi_init_r();
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CMD_NAND)
|
||||
WATCHDOG_RESET();
|
||||
puts("NAND: ");
|
||||
nand_init(); /* go init the NAND */
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_GENERIC_MMC
|
||||
/*
|
||||
* MMC initialization is called before relocating env.
|
||||
* Thus It is required that operations like pin multiplexer
|
||||
* be put in board_init.
|
||||
*/
|
||||
WATCHDOG_RESET();
|
||||
puts("MMC: ");
|
||||
mmc_initialize(bd);
|
||||
#endif
|
||||
|
||||
/* relocate environment function pointers etc. */
|
||||
env_relocate();
|
||||
|
||||
/*
|
||||
* after non-volatile devices & environment is setup and cpu code have
|
||||
* another round to deal with any initialization that might require
|
||||
* full access to the environment or loading of some image (firmware)
|
||||
* from a non-volatile device
|
||||
*/
|
||||
cpu_secondary_init_r();
|
||||
|
||||
/*
|
||||
* Fill in missing fields of bd_info.
|
||||
* We do this here, where we have "normal" access to the
|
||||
* environment; we used to do this still running from ROM,
|
||||
* where had to use getenv_f(), which can be pretty slow when
|
||||
* the environment is in EEPROM.
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_SYS_EXTBDINFO)
|
||||
#if defined(CONFIG_405GP) || defined(CONFIG_405EP)
|
||||
#if defined(CONFIG_I2CFAST)
|
||||
/*
|
||||
* set bi_iic_fast for linux taking environment variable
|
||||
* "i2cfast" into account
|
||||
*/
|
||||
{
|
||||
if (getenv_yesno("i2cfast") == 1) {
|
||||
bd->bi_iic_fast[0] = 1;
|
||||
bd->bi_iic_fast[1] = 1;
|
||||
}
|
||||
}
|
||||
#endif /* CONFIG_I2CFAST */
|
||||
#endif /* CONFIG_405GP, CONFIG_405EP */
|
||||
#endif /* CONFIG_SYS_EXTBDINFO */
|
||||
|
||||
#if defined(CONFIG_ID_EEPROM) || defined(CONFIG_SYS_I2C_MAC_OFFSET)
|
||||
mac_read_from_eeprom();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CMD_NET
|
||||
/* kept around for legacy kernels only ... ignore the next section */
|
||||
eth_getenv_enetaddr("ethaddr", bd->bi_enetaddr);
|
||||
#ifdef CONFIG_HAS_ETH1
|
||||
eth_getenv_enetaddr("eth1addr", bd->bi_enet1addr);
|
||||
#endif
|
||||
#ifdef CONFIG_HAS_ETH2
|
||||
eth_getenv_enetaddr("eth2addr", bd->bi_enet2addr);
|
||||
#endif
|
||||
#ifdef CONFIG_HAS_ETH3
|
||||
eth_getenv_enetaddr("eth3addr", bd->bi_enet3addr);
|
||||
#endif
|
||||
#ifdef CONFIG_HAS_ETH4
|
||||
eth_getenv_enetaddr("eth4addr", bd->bi_enet4addr);
|
||||
#endif
|
||||
#ifdef CONFIG_HAS_ETH5
|
||||
eth_getenv_enetaddr("eth5addr", bd->bi_enet5addr);
|
||||
#endif
|
||||
#endif /* CONFIG_CMD_NET */
|
||||
|
||||
WATCHDOG_RESET();
|
||||
|
||||
#if defined(CONFIG_PCI) && !defined(CONFIG_SYS_EARLY_PCI_INIT)
|
||||
/*
|
||||
* Do pci configuration
|
||||
*/
|
||||
pci_init();
|
||||
#endif
|
||||
|
||||
/** leave this here (after malloc(), environment and PCI are working) **/
|
||||
/* Initialize stdio devices */
|
||||
stdio_init();
|
||||
|
||||
/* Initialize the jump table for applications */
|
||||
jumptable_init();
|
||||
|
||||
#if defined(CONFIG_API)
|
||||
/* Initialize API */
|
||||
api_init();
|
||||
#endif
|
||||
|
||||
/* Initialize the console (after the relocation and devices init) */
|
||||
console_init_r();
|
||||
|
||||
#if defined(CONFIG_MISC_INIT_R)
|
||||
/* miscellaneous platform dependent initialisations */
|
||||
misc_init_r();
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
WATCHDOG_RESET();
|
||||
puts("KGDB: ");
|
||||
kgdb_init();
|
||||
#endif
|
||||
|
||||
debug("U-Boot relocated to %08lx\n", dest_addr);
|
||||
|
||||
/*
|
||||
* Enable Interrupts
|
||||
*/
|
||||
interrupt_init();
|
||||
|
||||
#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
|
||||
status_led_set(STATUS_LED_BOOT, STATUS_LED_BLINKING);
|
||||
#endif
|
||||
|
||||
udelay(20);
|
||||
|
||||
/* Initialize from environment */
|
||||
load_addr = getenv_ulong("loadaddr", 16, load_addr);
|
||||
|
||||
WATCHDOG_RESET();
|
||||
|
||||
#if defined(CONFIG_CMD_SCSI)
|
||||
WATCHDOG_RESET();
|
||||
puts("SCSI: ");
|
||||
scsi_init();
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CMD_DOC)
|
||||
WATCHDOG_RESET();
|
||||
puts("DOC: ");
|
||||
doc_init();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_BITBANGMII
|
||||
bb_miiphy_init();
|
||||
#endif
|
||||
#if defined(CONFIG_CMD_NET)
|
||||
WATCHDOG_RESET();
|
||||
puts("Net: ");
|
||||
eth_initialize();
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
|
||||
WATCHDOG_RESET();
|
||||
debug("Reset Ethernet PHY\n");
|
||||
reset_phy();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_POST
|
||||
post_run(NULL, POST_RAM | post_bootmode_get(0));
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CMD_PCMCIA) \
|
||||
&& !defined(CONFIG_CMD_IDE)
|
||||
WATCHDOG_RESET();
|
||||
puts("PCMCIA:");
|
||||
pcmcia_init();
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CMD_IDE)
|
||||
WATCHDOG_RESET();
|
||||
#ifdef CONFIG_IDE_8xx_PCCARD
|
||||
puts("PCMCIA:");
|
||||
#else
|
||||
puts("IDE: ");
|
||||
#endif
|
||||
#if defined(CONFIG_START_IDE)
|
||||
if (board_start_ide())
|
||||
ide_init();
|
||||
#else
|
||||
ide_init();
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_LAST_STAGE_INIT
|
||||
WATCHDOG_RESET();
|
||||
/*
|
||||
* Some parts can be only initialized if all others (like
|
||||
* Interrupts) are up and running (i.e. the PC-style ISA
|
||||
* keyboard).
|
||||
*/
|
||||
last_stage_init();
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CMD_BEDBUG)
|
||||
WATCHDOG_RESET();
|
||||
bedbug_init();
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_PRAM) || defined(CONFIG_LOGBUFFER)
|
||||
/*
|
||||
* Export available size of memory for Linux,
|
||||
* taking into account the protected RAM at top of memory
|
||||
*/
|
||||
{
|
||||
ulong pram = 0;
|
||||
char memsz[32];
|
||||
|
||||
#ifdef CONFIG_PRAM
|
||||
pram = getenv_ulong("pram", 10, CONFIG_PRAM);
|
||||
#endif
|
||||
#ifdef CONFIG_LOGBUFFER
|
||||
#ifndef CONFIG_ALT_LB_ADDR
|
||||
/* Also take the logbuffer into account (pram is in kB) */
|
||||
pram += (LOGBUFF_LEN + LOGBUFF_OVERHEAD) / 1024;
|
||||
#endif
|
||||
#endif
|
||||
sprintf(memsz, "%ldk", (ulong) (bd->bi_memsize / 1024) - pram);
|
||||
setenv("mem", memsz);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PS2KBD
|
||||
puts("PS/2: ");
|
||||
kbd_init();
|
||||
#endif
|
||||
|
||||
/* Initialization complete - start the monitor */
|
||||
|
||||
/* main_loop() can return to retry autoboot, if so just run it again. */
|
||||
for (;;) {
|
||||
WATCHDOG_RESET();
|
||||
main_loop();
|
||||
}
|
||||
|
||||
/* NOTREACHED - no way out of command loop except booting */
|
||||
}
|
||||
|
||||
#if 0 /* We could use plain global data, but the resulting code is bigger */
|
||||
/*
|
||||
* Pointer to initial global data area
|
||||
*
|
||||
* Here we initialize it.
|
||||
*/
|
||||
#undef XTRN_DECLARE_GLOBAL_DATA_PTR
|
||||
#define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */
|
||||
DECLARE_GLOBAL_DATA_PTR =
|
||||
(gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
|
||||
#endif /* 0 */
|
||||
|
||||
/************************************************************************/
|
||||
|
|
@ -13,6 +13,8 @@
|
|||
eth5 = ð_5;
|
||||
i2c0 = "/i2c@0";
|
||||
pci0 = &pci;
|
||||
remoteproc1 = &rproc_1;
|
||||
remoteproc2 = &rproc_2;
|
||||
rtc0 = &rtc_0;
|
||||
rtc1 = &rtc_1;
|
||||
spi0 = "/spi@0";
|
||||
|
|
@ -233,6 +235,17 @@
|
|||
compatible = "sandbox,reset";
|
||||
};
|
||||
|
||||
rproc_1: rproc@1 {
|
||||
compatible = "sandbox,test-processor";
|
||||
remoteproc-name = "remoteproc-test-dev1";
|
||||
};
|
||||
|
||||
rproc_2: rproc@2 {
|
||||
compatible = "sandbox,test-processor";
|
||||
internal-memory-mapped;
|
||||
remoteproc-name = "remoteproc-test-dev2";
|
||||
};
|
||||
|
||||
spi@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
|
|||
|
|
@ -239,6 +239,14 @@ config FSP_SYS_MALLOC_F_LEN
|
|||
help
|
||||
Additional size of malloc() pool before relocation.
|
||||
|
||||
config ENABLE_MRC_CACHE
|
||||
bool "Enable MRC cache"
|
||||
depends on !EFI && !SYS_COREBOOT
|
||||
help
|
||||
Enable this feature to cause MRC data to be cached in NV storage
|
||||
to be used for speeding up boot time on future reboots and/or
|
||||
power cycles.
|
||||
|
||||
config SMP
|
||||
bool "Enable Symmetric Multiprocessing"
|
||||
default n
|
||||
|
|
@ -358,6 +366,17 @@ config GENERATE_ACPI_TABLE
|
|||
by the operating system. It defines platform-independent interfaces
|
||||
for configuration and power management monitoring.
|
||||
|
||||
config GENERATE_SMBIOS_TABLE
|
||||
bool "Generate an SMBIOS (System Management BIOS) table"
|
||||
default y
|
||||
help
|
||||
The System Management BIOS (SMBIOS) specification addresses how
|
||||
motherboard and system vendors present management information about
|
||||
their products in a standard format by extending the BIOS interface
|
||||
on Intel architecture systems.
|
||||
|
||||
Check http://www.dmtf.org/standards/smbios for details.
|
||||
|
||||
endmenu
|
||||
|
||||
config MAX_PIRQ_LINKS
|
||||
|
|
|
|||
|
|
@ -8,6 +8,7 @@
|
|||
#include <mmc.h>
|
||||
#include <pci_ids.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/mrccache.h>
|
||||
#include <asm/post.h>
|
||||
|
||||
static struct pci_device_id mmc_supported[] = {
|
||||
|
|
@ -43,6 +44,30 @@ int arch_misc_init(void)
|
|||
if (!ll_boot_init())
|
||||
return 0;
|
||||
|
||||
#ifdef CONFIG_ENABLE_MRC_CACHE
|
||||
/*
|
||||
* We intend not to check any return value here, as even MRC cache
|
||||
* is not saved successfully, it is not a severe error that will
|
||||
* prevent system from continuing to boot.
|
||||
*/
|
||||
mrccache_save();
|
||||
#endif
|
||||
|
||||
return pirq_init();
|
||||
}
|
||||
|
||||
int reserve_arch(void)
|
||||
{
|
||||
#ifdef CONFIG_ENABLE_MRC_CACHE
|
||||
return mrccache_reserve();
|
||||
#else
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
void reset_cpu(ulong addr)
|
||||
{
|
||||
/* cold reset */
|
||||
x86_full_reset();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -142,7 +142,12 @@ void arch_setup_gd(gd_t *new_gd)
|
|||
|
||||
gdt_addr = new_gd->arch.gdt;
|
||||
|
||||
/* CS: code, read/execute, 4 GB, base 0 */
|
||||
/*
|
||||
* CS: code, read/execute, 4 GB, base 0
|
||||
*
|
||||
* Some OS (like VxWorks) requires GDT entry 1 to be the 32-bit CS
|
||||
*/
|
||||
gdt_addr[X86_GDT_ENTRY_UNUSED] = GDT_ENTRY(0xc09b, 0, 0xfffff);
|
||||
gdt_addr[X86_GDT_ENTRY_32BIT_CS] = GDT_ENTRY(0xc09b, 0, 0xfffff);
|
||||
|
||||
/* DS: data, read/write, 4 GB, base 0 */
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show more
Loading…
Reference in a new issue