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clk/qcom: move from mach-snapdragon
Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
This commit is contained in:
parent
697758e7c8
commit
a623c14f43
13 changed files with 66 additions and 10 deletions
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@ -575,6 +575,7 @@ M: Neil Armstrong <neil.armstrong@linaro.org>
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R: Sumit Garg <sumit.garg@linaro.org>
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S: Maintained
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F: arch/arm/mach-snapdragon/
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F: drivers/clk/qcom/
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F: drivers/gpio/msm_gpio.c
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F: drivers/mmc/msm_sdhci.c
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F: drivers/phy/msm8916-usbh-phy.c
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@ -15,6 +15,7 @@ config SPL_SYS_MALLOC_F_LEN
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config SDM845
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bool "Qualcomm Snapdragon 845 SoC"
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select LINUX_KERNEL_IMAGE_HEADER
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imply CLK_QCOM_SDM845
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config LNX_KRNL_IMG_TEXT_OFFSET_BASE
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default 0x80000000
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@ -26,6 +27,7 @@ config TARGET_DRAGONBOARD410C
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bool "96Boards Dragonboard 410C"
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select BOARD_LATE_INIT
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select ENABLE_ARM_SOC_BOOT0_HOOK
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imply CLK_QCOM_APQ8016
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help
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Support for 96Boards Dragonboard 410C. This board complies with
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96Board Open Platform Specifications. Features:
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@ -39,6 +41,7 @@ config TARGET_DRAGONBOARD410C
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config TARGET_DRAGONBOARD820C
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bool "96Boards Dragonboard 820C"
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imply CLK_QCOM_APQ8096
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help
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Support for 96Boards Dragonboard 820C. This board complies with
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96Board Open Platform Specifications. Features:
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@ -72,6 +75,7 @@ config TARGET_STARQLTECHN
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config TARGET_QCS404EVB
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bool "Qualcomm Technologies, Inc. QCS404 EVB"
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select LINUX_KERNEL_IMAGE_HEADER
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imply CLK_QCOM_QCS404
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help
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Support for Qualcomm Technologies, Inc. QCS404 evaluation board.
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Features:
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@ -2,20 +2,15 @@
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#
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# (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
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obj-$(CONFIG_SDM845) += clock-sdm845.o
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obj-$(CONFIG_SDM845) += sysmap-sdm845.o
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obj-$(CONFIG_SDM845) += init_sdm845.o
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obj-$(CONFIG_TARGET_DRAGONBOARD820C) += clock-apq8096.o
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obj-$(CONFIG_TARGET_DRAGONBOARD820C) += sysmap-apq8096.o
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obj-$(CONFIG_TARGET_DRAGONBOARD410C) += clock-apq8016.o
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obj-$(CONFIG_TARGET_DRAGONBOARD410C) += sysmap-apq8016.o
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obj-y += misc.o
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obj-y += clock-snapdragon.o
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obj-y += dram.o
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obj-y += pinctrl-snapdragon.o
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obj-y += pinctrl-apq8016.o
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obj-y += pinctrl-apq8096.o
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obj-y += pinctrl-qcs404.o
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obj-y += pinctrl-sdm845.o
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obj-$(CONFIG_TARGET_QCS404EVB) += clock-qcs404.o
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obj-$(CONFIG_TARGET_QCS404EVB) += sysmap-qcs404.o
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@ -254,6 +254,7 @@ source "drivers/clk/meson/Kconfig"
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source "drivers/clk/microchip/Kconfig"
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source "drivers/clk/mvebu/Kconfig"
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source "drivers/clk/owl/Kconfig"
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source "drivers/clk/qcom/Kconfig"
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source "drivers/clk/renesas/Kconfig"
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source "drivers/clk/sunxi/Kconfig"
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source "drivers/clk/sifive/Kconfig"
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@ -39,6 +39,7 @@ obj-$(CONFIG_CLK_MPFS) += microchip/
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obj-$(CONFIG_CLK_MVEBU) += mvebu/
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obj-$(CONFIG_CLK_OCTEON) += clk_octeon.o
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obj-$(CONFIG_CLK_OWL) += owl/
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obj-$(CONFIG_CLK_QCOM) += qcom/
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obj-$(CONFIG_CLK_RENESAS) += renesas/
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obj-$(CONFIG_$(SPL_TPL_)CLK_SCMI) += clk_scmi.o
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obj-$(CONFIG_CLK_SIFIVE) += sifive/
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44
drivers/clk/qcom/Kconfig
Normal file
44
drivers/clk/qcom/Kconfig
Normal file
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@ -0,0 +1,44 @@
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if ARCH_SNAPDRAGON || ARCH_IPQ40XX
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config CLK_QCOM
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bool
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depends on CLK && DM_RESET
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def_bool n
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menu "Qualcomm clock drivers"
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config CLK_QCOM_APQ8016
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bool "Qualcomm APQ8016 GCC"
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select CLK_QCOM
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help
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Say Y here to enable support for the Global Clock Controller
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on the Snapdragon APQ8016 SoC. This driver supports the clocks
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and resets exposed by the GCC hardware block.
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config CLK_QCOM_APQ8096
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bool "Qualcomm APQ8096 GCC"
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select CLK_QCOM
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help
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Say Y here to enable support for the Global Clock Controller
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on the Snapdragon APQ8096 SoC. This driver supports the clocks
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and resets exposed by the GCC hardware block.
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config CLK_QCOM_QCS404
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bool "Qualcomm QCS404 GCC"
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select CLK_QCOM
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help
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Say Y here to enable support for the Global Clock Controller
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on the Snapdragon QCS404 SoC. This driver supports the clocks
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and resets exposed by the GCC hardware block.
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config CLK_QCOM_SDM845
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bool "Qualcomm SDM845 GCC"
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select CLK_QCOM
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help
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Say Y here to enable support for the Global Clock Controller
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on the Snapdragon 845 SoC. This driver supports the clocks
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and resets exposed by the GCC hardware block.
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endmenu
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endif
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9
drivers/clk/qcom/Makefile
Normal file
9
drivers/clk/qcom/Makefile
Normal file
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@ -0,0 +1,9 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# (C) Copyright 2023 Linaro
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obj-y += clock-qcom.o
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obj-$(CONFIG_CLK_QCOM_SDM845) += clock-sdm845.o
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obj-$(CONFIG_CLK_QCOM_APQ8016) += clock-apq8016.o
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obj-$(CONFIG_CLK_QCOM_APQ8096) += clock-apq8096.o
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obj-$(CONFIG_CLK_QCOM_QCS404) += clock-qcs404.o
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@ -13,7 +13,7 @@
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#include <errno.h>
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#include <asm/io.h>
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#include <linux/bitops.h>
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#include "clock-snapdragon.h"
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#include "clock-qcom.h"
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/* GPLL0 clock control registers */
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#define GPLL0_STATUS_ACTIVE BIT(17)
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@ -13,7 +13,8 @@
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#include <errno.h>
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#include <asm/io.h>
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#include <linux/bitops.h>
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#include "clock-snapdragon.h"
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#include "clock-qcom.h"
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/* GPLL0 clock control registers */
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#define GPLL0_STATUS_ACTIVE BIT(30)
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@ -13,7 +13,7 @@
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#include <errno.h>
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#include <asm/io.h>
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#include <linux/bitops.h>
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#include "clock-snapdragon.h"
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#include "clock-qcom.h"
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/* CBCR register fields */
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#define CBCR_BRANCH_ENABLE_BIT BIT(0)
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@ -11,7 +11,7 @@
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#include <errno.h>
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#include <asm/io.h>
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#include <linux/bitops.h>
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#include "clock-snapdragon.h"
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#include "clock-qcom.h"
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#include <dt-bindings/clock/qcom,gcc-qcs404.h>
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@ -15,7 +15,7 @@
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#include <asm/io.h>
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#include <linux/bitops.h>
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#include <dt-bindings/clock/qcom,gcc-sdm845.h>
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#include "clock-snapdragon.h"
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#include "clock-qcom.h"
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#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
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