mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-24 13:43:28 +00:00
clk/qcom: move from mach-snapdragon
Clock drivers don't belong here, move them to the right place and declutter mach-snapdragon a bit. To de-couple these drivers from specific "target" platforms, add additional config options to enable each clock driver gated behind a common CLK_QCOM option and enable them by default for the respective targets. This will make future work easier as we move towards a generic Qualcomm target. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
This commit is contained in:
parent
697758e7c8
commit
a623c14f43
13 changed files with 66 additions and 10 deletions
|
@ -575,6 +575,7 @@ M: Neil Armstrong <neil.armstrong@linaro.org>
|
|||
R: Sumit Garg <sumit.garg@linaro.org>
|
||||
S: Maintained
|
||||
F: arch/arm/mach-snapdragon/
|
||||
F: drivers/clk/qcom/
|
||||
F: drivers/gpio/msm_gpio.c
|
||||
F: drivers/mmc/msm_sdhci.c
|
||||
F: drivers/phy/msm8916-usbh-phy.c
|
||||
|
|
|
@ -15,6 +15,7 @@ config SPL_SYS_MALLOC_F_LEN
|
|||
config SDM845
|
||||
bool "Qualcomm Snapdragon 845 SoC"
|
||||
select LINUX_KERNEL_IMAGE_HEADER
|
||||
imply CLK_QCOM_SDM845
|
||||
|
||||
config LNX_KRNL_IMG_TEXT_OFFSET_BASE
|
||||
default 0x80000000
|
||||
|
@ -26,6 +27,7 @@ config TARGET_DRAGONBOARD410C
|
|||
bool "96Boards Dragonboard 410C"
|
||||
select BOARD_LATE_INIT
|
||||
select ENABLE_ARM_SOC_BOOT0_HOOK
|
||||
imply CLK_QCOM_APQ8016
|
||||
help
|
||||
Support for 96Boards Dragonboard 410C. This board complies with
|
||||
96Board Open Platform Specifications. Features:
|
||||
|
@ -39,6 +41,7 @@ config TARGET_DRAGONBOARD410C
|
|||
|
||||
config TARGET_DRAGONBOARD820C
|
||||
bool "96Boards Dragonboard 820C"
|
||||
imply CLK_QCOM_APQ8096
|
||||
help
|
||||
Support for 96Boards Dragonboard 820C. This board complies with
|
||||
96Board Open Platform Specifications. Features:
|
||||
|
@ -72,6 +75,7 @@ config TARGET_STARQLTECHN
|
|||
config TARGET_QCS404EVB
|
||||
bool "Qualcomm Technologies, Inc. QCS404 EVB"
|
||||
select LINUX_KERNEL_IMAGE_HEADER
|
||||
imply CLK_QCOM_QCS404
|
||||
help
|
||||
Support for Qualcomm Technologies, Inc. QCS404 evaluation board.
|
||||
Features:
|
||||
|
|
|
@ -2,20 +2,15 @@
|
|||
#
|
||||
# (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
|
||||
|
||||
obj-$(CONFIG_SDM845) += clock-sdm845.o
|
||||
obj-$(CONFIG_SDM845) += sysmap-sdm845.o
|
||||
obj-$(CONFIG_SDM845) += init_sdm845.o
|
||||
obj-$(CONFIG_TARGET_DRAGONBOARD820C) += clock-apq8096.o
|
||||
obj-$(CONFIG_TARGET_DRAGONBOARD820C) += sysmap-apq8096.o
|
||||
obj-$(CONFIG_TARGET_DRAGONBOARD410C) += clock-apq8016.o
|
||||
obj-$(CONFIG_TARGET_DRAGONBOARD410C) += sysmap-apq8016.o
|
||||
obj-y += misc.o
|
||||
obj-y += clock-snapdragon.o
|
||||
obj-y += dram.o
|
||||
obj-y += pinctrl-snapdragon.o
|
||||
obj-y += pinctrl-apq8016.o
|
||||
obj-y += pinctrl-apq8096.o
|
||||
obj-y += pinctrl-qcs404.o
|
||||
obj-y += pinctrl-sdm845.o
|
||||
obj-$(CONFIG_TARGET_QCS404EVB) += clock-qcs404.o
|
||||
obj-$(CONFIG_TARGET_QCS404EVB) += sysmap-qcs404.o
|
||||
|
|
|
@ -254,6 +254,7 @@ source "drivers/clk/meson/Kconfig"
|
|||
source "drivers/clk/microchip/Kconfig"
|
||||
source "drivers/clk/mvebu/Kconfig"
|
||||
source "drivers/clk/owl/Kconfig"
|
||||
source "drivers/clk/qcom/Kconfig"
|
||||
source "drivers/clk/renesas/Kconfig"
|
||||
source "drivers/clk/sunxi/Kconfig"
|
||||
source "drivers/clk/sifive/Kconfig"
|
||||
|
|
|
@ -39,6 +39,7 @@ obj-$(CONFIG_CLK_MPFS) += microchip/
|
|||
obj-$(CONFIG_CLK_MVEBU) += mvebu/
|
||||
obj-$(CONFIG_CLK_OCTEON) += clk_octeon.o
|
||||
obj-$(CONFIG_CLK_OWL) += owl/
|
||||
obj-$(CONFIG_CLK_QCOM) += qcom/
|
||||
obj-$(CONFIG_CLK_RENESAS) += renesas/
|
||||
obj-$(CONFIG_$(SPL_TPL_)CLK_SCMI) += clk_scmi.o
|
||||
obj-$(CONFIG_CLK_SIFIVE) += sifive/
|
||||
|
|
44
drivers/clk/qcom/Kconfig
Normal file
44
drivers/clk/qcom/Kconfig
Normal file
|
@ -0,0 +1,44 @@
|
|||
if ARCH_SNAPDRAGON || ARCH_IPQ40XX
|
||||
|
||||
config CLK_QCOM
|
||||
bool
|
||||
depends on CLK && DM_RESET
|
||||
def_bool n
|
||||
|
||||
menu "Qualcomm clock drivers"
|
||||
|
||||
config CLK_QCOM_APQ8016
|
||||
bool "Qualcomm APQ8016 GCC"
|
||||
select CLK_QCOM
|
||||
help
|
||||
Say Y here to enable support for the Global Clock Controller
|
||||
on the Snapdragon APQ8016 SoC. This driver supports the clocks
|
||||
and resets exposed by the GCC hardware block.
|
||||
|
||||
config CLK_QCOM_APQ8096
|
||||
bool "Qualcomm APQ8096 GCC"
|
||||
select CLK_QCOM
|
||||
help
|
||||
Say Y here to enable support for the Global Clock Controller
|
||||
on the Snapdragon APQ8096 SoC. This driver supports the clocks
|
||||
and resets exposed by the GCC hardware block.
|
||||
|
||||
config CLK_QCOM_QCS404
|
||||
bool "Qualcomm QCS404 GCC"
|
||||
select CLK_QCOM
|
||||
help
|
||||
Say Y here to enable support for the Global Clock Controller
|
||||
on the Snapdragon QCS404 SoC. This driver supports the clocks
|
||||
and resets exposed by the GCC hardware block.
|
||||
|
||||
config CLK_QCOM_SDM845
|
||||
bool "Qualcomm SDM845 GCC"
|
||||
select CLK_QCOM
|
||||
help
|
||||
Say Y here to enable support for the Global Clock Controller
|
||||
on the Snapdragon 845 SoC. This driver supports the clocks
|
||||
and resets exposed by the GCC hardware block.
|
||||
|
||||
endmenu
|
||||
|
||||
endif
|
9
drivers/clk/qcom/Makefile
Normal file
9
drivers/clk/qcom/Makefile
Normal file
|
@ -0,0 +1,9 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# (C) Copyright 2023 Linaro
|
||||
|
||||
obj-y += clock-qcom.o
|
||||
obj-$(CONFIG_CLK_QCOM_SDM845) += clock-sdm845.o
|
||||
obj-$(CONFIG_CLK_QCOM_APQ8016) += clock-apq8016.o
|
||||
obj-$(CONFIG_CLK_QCOM_APQ8096) += clock-apq8096.o
|
||||
obj-$(CONFIG_CLK_QCOM_QCS404) += clock-qcs404.o
|
|
@ -13,7 +13,7 @@
|
|||
#include <errno.h>
|
||||
#include <asm/io.h>
|
||||
#include <linux/bitops.h>
|
||||
#include "clock-snapdragon.h"
|
||||
#include "clock-qcom.h"
|
||||
|
||||
/* GPLL0 clock control registers */
|
||||
#define GPLL0_STATUS_ACTIVE BIT(17)
|
|
@ -13,7 +13,8 @@
|
|||
#include <errno.h>
|
||||
#include <asm/io.h>
|
||||
#include <linux/bitops.h>
|
||||
#include "clock-snapdragon.h"
|
||||
|
||||
#include "clock-qcom.h"
|
||||
|
||||
/* GPLL0 clock control registers */
|
||||
#define GPLL0_STATUS_ACTIVE BIT(30)
|
|
@ -13,7 +13,7 @@
|
|||
#include <errno.h>
|
||||
#include <asm/io.h>
|
||||
#include <linux/bitops.h>
|
||||
#include "clock-snapdragon.h"
|
||||
#include "clock-qcom.h"
|
||||
|
||||
/* CBCR register fields */
|
||||
#define CBCR_BRANCH_ENABLE_BIT BIT(0)
|
|
@ -11,7 +11,7 @@
|
|||
#include <errno.h>
|
||||
#include <asm/io.h>
|
||||
#include <linux/bitops.h>
|
||||
#include "clock-snapdragon.h"
|
||||
#include "clock-qcom.h"
|
||||
|
||||
#include <dt-bindings/clock/qcom,gcc-qcs404.h>
|
||||
|
|
@ -15,7 +15,7 @@
|
|||
#include <asm/io.h>
|
||||
#include <linux/bitops.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sdm845.h>
|
||||
#include "clock-snapdragon.h"
|
||||
#include "clock-qcom.h"
|
||||
|
||||
#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
|
||||
|
Loading…
Reference in a new issue