mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-10 23:24:38 +00:00
Merge git://git.denx.de/u-boot-socfpga
This commit is contained in:
commit
a6003397f7
42 changed files with 4851 additions and 31 deletions
|
@ -539,6 +539,8 @@ config ARCH_SOCFPGA
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bool "Altera SOCFPGA family"
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select CPU_V7
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select SUPPORT_SPL
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select OF_CONTROL
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select SPL_OF_CONTROL
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select DM
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select DM_SPI_FLASH
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select DM_SPI
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|
|
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@ -60,7 +60,10 @@ dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-evm.dtb
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dtb-$(CONFIG_ARCH_SOCFPGA) += \
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socfpga_arria5_socdk.dtb \
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socfpga_cyclone5_mcvevk.dtb \
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socfpga_cyclone5_socdk.dtb \
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socfpga_cyclone5_de0_nano_soc.dtb \
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socfpga_cyclone5_sockit.dtb \
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socfpga_cyclone5_socrates.dtb
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dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb
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dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb
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61
arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts
Normal file
61
arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts
Normal file
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@ -0,0 +1,61 @@
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/*
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* Copyright Altera Corporation (C) 2015
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include "socfpga_cyclone5.dtsi"
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/ {
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model = "Terasic DE0-Nano(Atlas)";
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compatible = "altr,socfpga-cyclone5", "altr,socfpga";
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chosen {
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bootargs = "console=ttyS0,115200";
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};
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aliases {
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ethernet0 = &gmac1;
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};
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memory {
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name = "memory";
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device_type = "memory";
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reg = <0x0 0x40000000>; /* 1GB */
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};
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soc {
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u-boot,dm-pre-reloc;
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};
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};
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&gmac1 {
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status = "okay";
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phy-mode = "rgmii";
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rxd0-skew-ps = <420>;
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rxd1-skew-ps = <420>;
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rxd2-skew-ps = <420>;
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rxd3-skew-ps = <420>;
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txen-skew-ps = <0>;
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txc-skew-ps = <1860>;
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rxdv-skew-ps = <420>;
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rxc-skew-ps = <1680>;
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};
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&gpio0 {
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status = "okay";
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};
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&gpio1 {
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status = "okay";
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};
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&gpio2 {
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status = "okay";
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};
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&mmc0 {
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status = "okay";
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u-boot,dm-pre-reloc;
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};
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53
arch/arm/dts/socfpga_cyclone5_mcvevk.dts
Normal file
53
arch/arm/dts/socfpga_cyclone5_mcvevk.dts
Normal file
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@ -0,0 +1,53 @@
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/*
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* Copyright (C) 2015 Marek Vasut <marex@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include "socfpga_cyclone5.dtsi"
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/ {
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model = "DENX MCVEVK";
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compatible = "altr,socfpga-cyclone5", "altr,socfpga";
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chosen {
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bootargs = "console=ttyS0,115200";
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};
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aliases {
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ethernet0 = &gmac0;
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};
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memory {
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name = "memory";
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device_type = "memory";
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reg = <0x0 0x40000000>; /* 1GB */
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};
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soc {
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u-boot,dm-pre-reloc;
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};
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};
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&gmac0 {
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status = "okay";
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phy-mode = "rgmii";
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};
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&gpio0 {
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status = "okay";
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};
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&gpio1 {
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status = "okay";
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};
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&gpio2 {
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status = "okay";
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};
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&mmc0 {
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status = "okay";
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bus-width = <8>;
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u-boot,dm-pre-reloc;
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};
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92
arch/arm/dts/socfpga_cyclone5_sockit.dts
Normal file
92
arch/arm/dts/socfpga_cyclone5_sockit.dts
Normal file
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@ -0,0 +1,92 @@
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/*
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* Copyright (C) 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include "socfpga_cyclone5.dtsi"
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/ {
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model = "Terasic SoCkit";
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compatible = "altr,socfpga-cyclone5", "altr,socfpga";
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chosen {
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bootargs = "console=ttyS0,115200";
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};
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aliases {
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ethernet0 = &gmac1;
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};
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memory {
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name = "memory";
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device_type = "memory";
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reg = <0x0 0x40000000>; /* 1GB */
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};
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soc {
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u-boot,dm-pre-reloc;
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};
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};
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&gmac1 {
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status = "okay";
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phy-mode = "rgmii";
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rxd0-skew-ps = <0>;
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rxd1-skew-ps = <0>;
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rxd2-skew-ps = <0>;
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rxd3-skew-ps = <0>;
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txen-skew-ps = <0>;
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txc-skew-ps = <2600>;
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rxdv-skew-ps = <0>;
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rxc-skew-ps = <2000>;
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};
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&gpio0 {
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status = "okay";
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};
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&gpio1 {
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status = "okay";
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};
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&gpio2 {
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status = "okay";
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};
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&i2c0 {
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status = "okay";
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rtc: rtc@68 {
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compatible = "stm,m41t82";
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reg = <0x68>;
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};
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};
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&mmc0 {
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status = "okay";
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u-boot,dm-pre-reloc;
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};
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&qspi {
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status = "okay";
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u-boot,dm-pre-reloc;
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flash0: n25q00@0 {
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u-boot,dm-pre-reloc;
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "n25q00", "spi-flash";
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reg = <0>; /* chip select */
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spi-max-frequency = <50000000>;
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m25p,fast-read;
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page-size = <256>;
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block-size = <16>; /* 2^16, 64KB */
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read-delay = <4>; /* delay value in read data capture register */
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tshsl-ns = <50>;
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tsd2d-ns = <50>;
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tchsh-ns = <4>;
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tslch-ns = <4>;
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};
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};
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@ -18,15 +18,33 @@ config TARGET_SOCFPGA_CYCLONE5_SOCDK
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bool "Altera SOCFPGA SoCDK (Cyclone V)"
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select TARGET_SOCFPGA_CYCLONE5
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config TARGET_SOCFPGA_DENX_MCVEVK
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bool "DENX MCVEVK (Cyclone V)"
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select TARGET_SOCFPGA_CYCLONE5
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config TARGET_SOCFPGA_TERASIC_DE0_NANO
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bool "Terasic DE0-Nano-Atlas (Cyclone V)"
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select TARGET_SOCFPGA_CYCLONE5
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config TARGET_SOCFPGA_TERASIC_SOCKIT
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bool "Terasic SoCkit (Cyclone V)"
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select TARGET_SOCFPGA_CYCLONE5
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endchoice
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config SYS_BOARD
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default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
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default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
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default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
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default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
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default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
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config SYS_VENDOR
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default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
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default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
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default "denx" if TARGET_SOCFPGA_DENX_MCVEVK
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default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
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default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
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config SYS_SOC
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default "socfpga"
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@ -34,5 +52,8 @@ config SYS_SOC
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config SYS_CONFIG_NAME
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default "socfpga_arria5" if TARGET_SOCFPGA_ARRIA5_SOCDK
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default "socfpga_cyclone5" if TARGET_SOCFPGA_CYCLONE5_SOCDK
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default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
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default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
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default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
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endif
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|
|
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@ -7,6 +7,6 @@
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#ifndef _SOCFPGA_DWMMC_H_
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#define _SOCFPGA_DWMMC_H_
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extern int socfpga_dwmmc_init(u32 regbase, int bus_width, int index);
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int socfpga_dwmmc_init(const void *blob);
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#endif /* _SOCFPGA_SDMMC_H_ */
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|
|
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@ -125,14 +125,7 @@ int cpu_eth_init(bd_t *bis)
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*/
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int cpu_mmc_init(bd_t *bis)
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{
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/*
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* FIXME: Temporarily define CONFIG_HPS_SDMMC_BUSWIDTH to prevent breakage
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* due to missing patches in u-boot/master . The upcoming patch will
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* switch this to OF probing, so this whole block will go away.
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*/
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#define CONFIG_HPS_SDMMC_BUSWIDTH 8
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return socfpga_dwmmc_init(SOCFPGA_SDMMC_ADDRESS,
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CONFIG_HPS_SDMMC_BUSWIDTH, 0);
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return socfpga_dwmmc_init(gd->fdt_blob);
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}
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#endif
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|
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|
|
|
@ -7,13 +7,16 @@
|
|||
|
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#include <common.h>
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#include <asm/io.h>
|
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#include <asm/arch/reset_manager.h>
|
||||
#include <asm/arch/fpga_manager.h>
|
||||
#include <asm/arch/reset_manager.h>
|
||||
#include <asm/arch/system_manager.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
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|
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static const struct socfpga_reset_manager *reset_manager_base =
|
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(void *)SOCFPGA_RSTMGR_ADDRESS;
|
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static struct socfpga_system_manager *sysmgr_regs =
|
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(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
|
||||
|
||||
/* Assert or de-assert SoCFPGA reset manager reset. */
|
||||
void socfpga_per_reset(u32 reset, int set)
|
||||
|
@ -97,6 +100,9 @@ void socfpga_bridges_reset(int enable)
|
|||
/* brdmodrst */
|
||||
writel(0xffffffff, &reset_manager_base->brg_mod_reset);
|
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} else {
|
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writel(0, &sysmgr_regs->iswgrp_handoff[0]);
|
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writel(l3mask, &sysmgr_regs->iswgrp_handoff[1]);
|
||||
|
||||
/* Check signal from FPGA. */
|
||||
if (!fpgamgr_test_fpga_ready()) {
|
||||
/* FPGA not ready, do nothing. */
|
||||
|
|
|
@ -180,6 +180,4 @@ void board_init_f(ulong dummy)
|
|||
|
||||
/* Configure simple malloc base pointer into RAM. */
|
||||
gd->malloc_base = CONFIG_SYS_TEXT_BASE + (1024 * 1024);
|
||||
|
||||
board_init_r(NULL, 0);
|
||||
}
|
||||
|
|
5
board/denx/mcvevk/MAINTAINERS
Normal file
5
board/denx/mcvevk/MAINTAINERS
Normal file
|
@ -0,0 +1,5 @@
|
|||
SOCKIT BOARD
|
||||
M: Marek Vasut <marex@denx.de>
|
||||
S: Maintained
|
||||
F: include/configs/socfpga_mcvevk.h
|
||||
F: configs/socfpga_mcvevk_defconfig
|
9
board/denx/mcvevk/Makefile
Normal file
9
board/denx/mcvevk/Makefile
Normal file
|
@ -0,0 +1,9 @@
|
|||
#
|
||||
# (C) Copyright 2001-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y := socfpga.o
|
660
board/denx/mcvevk/qts/iocsr_config.h
Normal file
660
board/denx/mcvevk/qts/iocsr_config.h
Normal file
|
@ -0,0 +1,660 @@
|
|||
/*
|
||||
* Altera SoCFPGA IOCSR configuration
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef __SOCFPGA_IOCSR_CONFIG_H__
|
||||
#define __SOCFPGA_IOCSR_CONFIG_H__
|
||||
|
||||
#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764
|
||||
#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
|
||||
#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955
|
||||
#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
|
||||
|
||||
const unsigned long iocsr_scan_chain0_table[] = {
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x0FF00000,
|
||||
0xC0000000,
|
||||
0x0000003F,
|
||||
0x00008000,
|
||||
0x00000000,
|
||||
0x18060000,
|
||||
0x00000060,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00004000,
|
||||
0x0C0300C0,
|
||||
0x00000000,
|
||||
0x0C000000,
|
||||
0x0000C030,
|
||||
0x0000C030,
|
||||
0x00002000,
|
||||
0x06018060,
|
||||
0x06018000,
|
||||
0x06000018,
|
||||
0x00006018,
|
||||
0x01806018,
|
||||
0x00001000,
|
||||
};
|
||||
|
||||
const unsigned long iocsr_scan_chain1_table[] = {
|
||||
0x000C0300,
|
||||
0x300C0000,
|
||||
0x300000C0,
|
||||
0x000000C0,
|
||||
0x000300C0,
|
||||
0x00008000,
|
||||
0x00060180,
|
||||
0x18060000,
|
||||
0x18000000,
|
||||
0x00000060,
|
||||
0x00018060,
|
||||
0x00004000,
|
||||
0x000300C0,
|
||||
0x0C030000,
|
||||
0x0C000000,
|
||||
0x00000030,
|
||||
0x0000C030,
|
||||
0x00002000,
|
||||
0x00018060,
|
||||
0x06018000,
|
||||
0x01FE0000,
|
||||
0xF8000000,
|
||||
0x00000007,
|
||||
0x00001000,
|
||||
0x0300C030,
|
||||
0x00000000,
|
||||
0x03000000,
|
||||
0x0000000C,
|
||||
0x00000000,
|
||||
0x00000800,
|
||||
0x00006018,
|
||||
0x01806000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00001806,
|
||||
0x00000400,
|
||||
0x0000300C,
|
||||
0x00C03000,
|
||||
0x00C00000,
|
||||
0x00000003,
|
||||
0x00000C03,
|
||||
0x00000200,
|
||||
0x00001806,
|
||||
0x00601800,
|
||||
0x80600000,
|
||||
0x80000001,
|
||||
0x00000601,
|
||||
0x00000100,
|
||||
0x00001000,
|
||||
0x00300C00,
|
||||
0xC0300000,
|
||||
0xC0000000,
|
||||
0x00000300,
|
||||
0x00000080,
|
||||
};
|
||||
|
||||
const unsigned long iocsr_scan_chain2_table[] = {
|
||||
0x300C0300,
|
||||
0x00000000,
|
||||
0x0FF00000,
|
||||
0x00000000,
|
||||
0x0C0300C0,
|
||||
0x00008000,
|
||||
0x00060180,
|
||||
0x00000000,
|
||||
0x18000000,
|
||||
0x00018060,
|
||||
0x06018060,
|
||||
0x00004000,
|
||||
0x200300C0,
|
||||
0x0C030000,
|
||||
0x0C000000,
|
||||
0x00000030,
|
||||
0x0000C030,
|
||||
0x00002000,
|
||||
0x00018060,
|
||||
0x00000000,
|
||||
0x06000000,
|
||||
0x00010018,
|
||||
0x01806018,
|
||||
0x00001000,
|
||||
0x0000C030,
|
||||
0x00000000,
|
||||
0x03000000,
|
||||
0x0000000C,
|
||||
0x00C0300C,
|
||||
0x00000800,
|
||||
};
|
||||
|
||||
const unsigned long iocsr_scan_chain3_table[] = {
|
||||
0x0CC20D80,
|
||||
0x0C3000FF,
|
||||
0x0A804001,
|
||||
0x07900000,
|
||||
0x08020000,
|
||||
0x00100000,
|
||||
0x0A800000,
|
||||
0x07900000,
|
||||
0x08020000,
|
||||
0x00100000,
|
||||
0x20430000,
|
||||
0x0C003001,
|
||||
0x00C00481,
|
||||
0x00000000,
|
||||
0x00000021,
|
||||
0x82000004,
|
||||
0x05400000,
|
||||
0x03C80000,
|
||||
0x04010000,
|
||||
0x00080000,
|
||||
0x05400000,
|
||||
0x03C80000,
|
||||
0x05400000,
|
||||
0x03C80000,
|
||||
0x90218000,
|
||||
0x86001800,
|
||||
0x00600240,
|
||||
0x80090218,
|
||||
0x00000001,
|
||||
0x40000002,
|
||||
0x02A00000,
|
||||
0x01E40000,
|
||||
0x02A00000,
|
||||
0x01E40000,
|
||||
0x02A00000,
|
||||
0x01E40000,
|
||||
0x02A00000,
|
||||
0x01E40000,
|
||||
0x4810C000,
|
||||
0x43000C00,
|
||||
0x00300120,
|
||||
0xC004810C,
|
||||
0x12043000,
|
||||
0x20000300,
|
||||
0x00040000,
|
||||
0x50670000,
|
||||
0x00000010,
|
||||
0x24590000,
|
||||
0x00001000,
|
||||
0xA0000034,
|
||||
0x0D000001,
|
||||
0xC0680618,
|
||||
0x45034071,
|
||||
0x1A681A01,
|
||||
0x806180D0,
|
||||
0x34071C06,
|
||||
0x01A034D0,
|
||||
0x380D0000,
|
||||
0x0820680E,
|
||||
0x034D0340,
|
||||
0xD000001A,
|
||||
0x0680E380,
|
||||
0x10040000,
|
||||
0x00200000,
|
||||
0x10040000,
|
||||
0x00200000,
|
||||
0x15000000,
|
||||
0x0F200000,
|
||||
0x15000000,
|
||||
0x0F200000,
|
||||
0x01FE0000,
|
||||
0x18000000,
|
||||
0x01800902,
|
||||
0x00240860,
|
||||
0x007F8006,
|
||||
0x00000000,
|
||||
0x0A800001,
|
||||
0x07900000,
|
||||
0x0A800000,
|
||||
0x07900000,
|
||||
0x0A800000,
|
||||
0x07900000,
|
||||
0x08020000,
|
||||
0x00100000,
|
||||
0x20430000,
|
||||
0x0C003001,
|
||||
0x00C00481,
|
||||
0x00000FF0,
|
||||
0x4810C000,
|
||||
0x80000C00,
|
||||
0x05400000,
|
||||
0x02480000,
|
||||
0x04000000,
|
||||
0x00080000,
|
||||
0x05400000,
|
||||
0x03C80000,
|
||||
0x05400000,
|
||||
0x03C80000,
|
||||
0x90218000,
|
||||
0x86001800,
|
||||
0x00600240,
|
||||
0x80090218,
|
||||
0x24086001,
|
||||
0x40000600,
|
||||
0x02A00040,
|
||||
0x01E40000,
|
||||
0x02A00000,
|
||||
0x01E40000,
|
||||
0x02A00000,
|
||||
0x01E40000,
|
||||
0x02A00000,
|
||||
0x01E40000,
|
||||
0x4810C000,
|
||||
0x43000C00,
|
||||
0x00300120,
|
||||
0xC004810C,
|
||||
0x12043000,
|
||||
0x20000300,
|
||||
0x00040000,
|
||||
0x50670000,
|
||||
0x00000010,
|
||||
0x24590000,
|
||||
0x00001000,
|
||||
0xA0000034,
|
||||
0x0D000001,
|
||||
0xC0680618,
|
||||
0x45034071,
|
||||
0x1A681A01,
|
||||
0x80E380D0,
|
||||
0x34071C06,
|
||||
0x01A00040,
|
||||
0x380D0002,
|
||||
0x71C0680E,
|
||||
0x034D0340,
|
||||
0xD01A681A,
|
||||
0x06806180,
|
||||
0x10040000,
|
||||
0x00200000,
|
||||
0x10040000,
|
||||
0x00200000,
|
||||
0x15000000,
|
||||
0x0F200000,
|
||||
0x15000000,
|
||||
0x0F200000,
|
||||
0x01FE0000,
|
||||
0x18000000,
|
||||
0x01800902,
|
||||
0x00240860,
|
||||
0x007F8006,
|
||||
0x00000000,
|
||||
0x99300001,
|
||||
0x34343400,
|
||||
0xAA0D4000,
|
||||
0x01C3A800,
|
||||
0xAA0D4000,
|
||||
0x01C3A800,
|
||||
0xAA0D4000,
|
||||
0x01C3A800,
|
||||
0x00040100,
|
||||
0x00000800,
|
||||
0x00000000,
|
||||
0x00001208,
|
||||
0x00482000,
|
||||
0x01000000,
|
||||
0x00000000,
|
||||
0x00410482,
|
||||
0x0006A000,
|
||||
0x0001B400,
|
||||
0x00020000,
|
||||
0x00000400,
|
||||
0x0002A000,
|
||||
0x0001E400,
|
||||
0x5506A000,
|
||||
0x00E1D400,
|
||||
0x00000000,
|
||||
0x2043090C,
|
||||
0x00003001,
|
||||
0x90400000,
|
||||
0x00000000,
|
||||
0x2020C243,
|
||||
0x2A835000,
|
||||
0x0070EA00,
|
||||
0x2A835000,
|
||||
0x0070EA00,
|
||||
0x2A835000,
|
||||
0x0070EA00,
|
||||
0x00010040,
|
||||
0x00000200,
|
||||
0x00000000,
|
||||
0x00000482,
|
||||
0x00120800,
|
||||
0x00002000,
|
||||
0x80000000,
|
||||
0x00104120,
|
||||
0x00000200,
|
||||
0xAC0D5F80,
|
||||
0xFFFFFFFF,
|
||||
0x14F3690D,
|
||||
0x1A041414,
|
||||
0x00D00000,
|
||||
0x04864000,
|
||||
0x69A47A01,
|
||||
0x932CA3DA,
|
||||
0xF459651E,
|
||||
0x03549248,
|
||||
0x821A0000,
|
||||
0x0000D000,
|
||||
0x030C0680,
|
||||
0xDA69A47A,
|
||||
0x1E9228A3,
|
||||
0x48F45965,
|
||||
0x000354D3,
|
||||
0x00080000,
|
||||
0x00001000,
|
||||
0x00080200,
|
||||
0x00001000,
|
||||
0x000A8000,
|
||||
0x00075000,
|
||||
0x541A8000,
|
||||
0x03875001,
|
||||
0x00000000,
|
||||
0x00000010,
|
||||
0x0080C000,
|
||||
0x41000000,
|
||||
0x00003FC2,
|
||||
0x00820000,
|
||||
0xAA0D4000,
|
||||
0x01C3A800,
|
||||
0xAA0D4000,
|
||||
0x01C3A800,
|
||||
0xAA0D4000,
|
||||
0x01C3A800,
|
||||
0x00040000,
|
||||
0x00000800,
|
||||
0x00000000,
|
||||
0x00001208,
|
||||
0x00482000,
|
||||
0x00800000,
|
||||
0x00000000,
|
||||
0x00410482,
|
||||
0x0006A000,
|
||||
0x0001B400,
|
||||
0x00020000,
|
||||
0x00000400,
|
||||
0x00020080,
|
||||
0x00000400,
|
||||
0x5506A000,
|
||||
0x00E1D400,
|
||||
0x00000000,
|
||||
0x0000090C,
|
||||
0x00000010,
|
||||
0x90400000,
|
||||
0x00000000,
|
||||
0x2020C243,
|
||||
0x2A835000,
|
||||
0x0070EA00,
|
||||
0x2A835000,
|
||||
0x0070EA00,
|
||||
0x2A835000,
|
||||
0x0070EA00,
|
||||
0x00015000,
|
||||
0x0000F200,
|
||||
0x00000000,
|
||||
0x00000482,
|
||||
0x86120800,
|
||||
0x00600240,
|
||||
0x80000000,
|
||||
0x00104120,
|
||||
0x00000200,
|
||||
0xAC0D5F80,
|
||||
0xFFFFFFFF,
|
||||
0x14F3690D,
|
||||
0x1A041414,
|
||||
0x00D00000,
|
||||
0x14864000,
|
||||
0x59647A05,
|
||||
0xE228A3D6,
|
||||
0xF459651E,
|
||||
0x034CD348,
|
||||
0x821A0041,
|
||||
0x0000D000,
|
||||
0x00000680,
|
||||
0xD669A47A,
|
||||
0x1E9228A3,
|
||||
0x48F45965,
|
||||
0x00034492,
|
||||
0x00080000,
|
||||
0x00001000,
|
||||
0x00080000,
|
||||
0x00001000,
|
||||
0x000A8000,
|
||||
0x00075000,
|
||||
0x541A8000,
|
||||
0x03875001,
|
||||
0x00000000,
|
||||
0x00000010,
|
||||
0x0080C000,
|
||||
0x41000000,
|
||||
0x00000002,
|
||||
0x00820004,
|
||||
0xAA0D4000,
|
||||
0x01C3A800,
|
||||
0xAA0D4000,
|
||||
0x01C3A800,
|
||||
0xAA0D4000,
|
||||
0x01C3A800,
|
||||
0x00040000,
|
||||
0x00000800,
|
||||
0x00000000,
|
||||
0x00001208,
|
||||
0x00482000,
|
||||
0x00800000,
|
||||
0x00000000,
|
||||
0x00410482,
|
||||
0x0006A000,
|
||||
0x0001B400,
|
||||
0x00020000,
|
||||
0x00000400,
|
||||
0x0002A000,
|
||||
0x0001E400,
|
||||
0x5506A000,
|
||||
0x00E1D400,
|
||||
0x00000000,
|
||||
0x2043090C,
|
||||
0x00003001,
|
||||
0x90400000,
|
||||
0x00000000,
|
||||
0x2020C243,
|
||||
0x2A835000,
|
||||
0x0070EA00,
|
||||
0x2A835000,
|
||||
0x0070EA00,
|
||||
0x2A835000,
|
||||
0x0070EA00,
|
||||
0x00010000,
|
||||
0x00000200,
|
||||
0x00000000,
|
||||
0x00000482,
|
||||
0x00120800,
|
||||
0x00200000,
|
||||
0x80000000,
|
||||
0x00104120,
|
||||
0x00000200,
|
||||
0xAC0D5F80,
|
||||
0xFFFFFFFF,
|
||||
0x14F3690D,
|
||||
0x1A041414,
|
||||
0x00D00000,
|
||||
0x14864000,
|
||||
0x59647A05,
|
||||
0x9228A3D6,
|
||||
0xF459651E,
|
||||
0x034CD348,
|
||||
0x821A0000,
|
||||
0x0000D000,
|
||||
0x00000680,
|
||||
0xD659647A,
|
||||
0x1E932CA3,
|
||||
0x48F65965,
|
||||
0x00034CD3,
|
||||
0x00080000,
|
||||
0x00001000,
|
||||
0x00080000,
|
||||
0x00001000,
|
||||
0x000A8000,
|
||||
0x00075000,
|
||||
0x541A8000,
|
||||
0x03875001,
|
||||
0x00000000,
|
||||
0x00000010,
|
||||
0x0080C000,
|
||||
0x41000000,
|
||||
0x00000002,
|
||||
0x00820004,
|
||||
0xAA0D4000,
|
||||
0x01C3A800,
|
||||
0xAA0D4000,
|
||||
0x01C3A800,
|
||||
0xAA0D4000,
|
||||
0x01C3A800,
|
||||
0x00040000,
|
||||
0x00000800,
|
||||
0x00000000,
|
||||
0x00001208,
|
||||
0x00482000,
|
||||
0x00800000,
|
||||
0x00000000,
|
||||
0x00410482,
|
||||
0x0006A000,
|
||||
0x0001B400,
|
||||
0x00020000,
|
||||
0x00000400,
|
||||
0x00020000,
|
||||
0x00000400,
|
||||
0x5506A000,
|
||||
0x00E1D400,
|
||||
0x00000000,
|
||||
0x0000090C,
|
||||
0x00001000,
|
||||
0x90400000,
|
||||
0x00000000,
|
||||
0x2020C243,
|
||||
0x2A835000,
|
||||
0x0070EA00,
|
||||
0x2A835000,
|
||||
0x0070EA00,
|
||||
0x2A835000,
|
||||
0x0070EA00,
|
||||
0x00010040,
|
||||
0x00000200,
|
||||
0x00000000,
|
||||
0x00000482,
|
||||
0x00120800,
|
||||
0x00400000,
|
||||
0x80000000,
|
||||
0x00104120,
|
||||
0x00000200,
|
||||
0xAC0D5F80,
|
||||
0xFFFFFFFF,
|
||||
0x14F1690D,
|
||||
0x1A041414,
|
||||
0x00D00000,
|
||||
0x14864000,
|
||||
0x59647A05,
|
||||
0x932CA3D6,
|
||||
0xF659651E,
|
||||
0x034CD348,
|
||||
0x821A0000,
|
||||
0x0000D000,
|
||||
0x00000680,
|
||||
0xD669A47A,
|
||||
0x1E9228A3,
|
||||
0x48F45965,
|
||||
0x00034CD3,
|
||||
0x00080000,
|
||||
0x00001000,
|
||||
0x00080000,
|
||||
0x00001000,
|
||||
0x000A8000,
|
||||
0x00075000,
|
||||
0x541A8000,
|
||||
0x03875001,
|
||||
0x00000000,
|
||||
0x00000010,
|
||||
0x0080C000,
|
||||
0x41000000,
|
||||
0x00000002,
|
||||
0x00820004,
|
||||
0x00489800,
|
||||
0x801A1A1A,
|
||||
0x00000200,
|
||||
0x80000004,
|
||||
0x00000200,
|
||||
0x80000004,
|
||||
0x00000200,
|
||||
0x00000004,
|
||||
0x00000200,
|
||||
0x00000004,
|
||||
0x00040000,
|
||||
0x10000000,
|
||||
0x00000000,
|
||||
0x00004000,
|
||||
0x00010000,
|
||||
0x40002080,
|
||||
0x00000100,
|
||||
0x40000002,
|
||||
0x00000100,
|
||||
0x00000002,
|
||||
0x00000100,
|
||||
0x40000002,
|
||||
0x00000100,
|
||||
0x00000002,
|
||||
0x00020000,
|
||||
0x00000000,
|
||||
0x00000008,
|
||||
0x00000020,
|
||||
0x00008000,
|
||||
0x20001040,
|
||||
0x00000080,
|
||||
0x20000001,
|
||||
0x00000080,
|
||||
0x20000001,
|
||||
0x00000080,
|
||||
0x20000001,
|
||||
0x00000080,
|
||||
0x00000001,
|
||||
0x00010000,
|
||||
0x04000000,
|
||||
0x00FF0000,
|
||||
0x00000000,
|
||||
0x00004000,
|
||||
0x00000800,
|
||||
0xC0000001,
|
||||
0x00041419,
|
||||
0x40000000,
|
||||
0x04000816,
|
||||
0x000D0000,
|
||||
0x00006800,
|
||||
0x00000340,
|
||||
0xD000001A,
|
||||
0x06800000,
|
||||
0x00340000,
|
||||
0x0001A000,
|
||||
0x00000D00,
|
||||
0x40000068,
|
||||
0x1A000003,
|
||||
0x00D00000,
|
||||
0x00068000,
|
||||
0x00003400,
|
||||
0x000001A0,
|
||||
0x00000401,
|
||||
0x00000008,
|
||||
0x00000401,
|
||||
0x00000008,
|
||||
0x00000401,
|
||||
0x00000008,
|
||||
0x00000401,
|
||||
0x80000008,
|
||||
0x0000007F,
|
||||
0x20000000,
|
||||
0x00000000,
|
||||
0xE0000080,
|
||||
0x0000001F,
|
||||
0x00004000,
|
||||
};
|
||||
|
||||
|
||||
#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */
|
219
board/denx/mcvevk/qts/pinmux_config.h
Normal file
219
board/denx/mcvevk/qts/pinmux_config.h
Normal file
|
@ -0,0 +1,219 @@
|
|||
/*
|
||||
* Altera SoCFPGA PinMux configuration
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef __SOCFPGA_PINMUX_CONFIG_H__
|
||||
#define __SOCFPGA_PINMUX_CONFIG_H__
|
||||
|
||||
const u8 sys_mgr_init_table[] = {
|
||||
3, /* EMACIO0 */
|
||||
3, /* EMACIO1 */
|
||||
3, /* EMACIO2 */
|
||||
3, /* EMACIO3 */
|
||||
3, /* EMACIO4 */
|
||||
3, /* EMACIO5 */
|
||||
3, /* EMACIO6 */
|
||||
3, /* EMACIO7 */
|
||||
3, /* EMACIO8 */
|
||||
3, /* EMACIO9 */
|
||||
3, /* EMACIO10 */
|
||||
3, /* EMACIO11 */
|
||||
3, /* EMACIO12 */
|
||||
3, /* EMACIO13 */
|
||||
0, /* EMACIO14 */
|
||||
0, /* EMACIO15 */
|
||||
0, /* EMACIO16 */
|
||||
0, /* EMACIO17 */
|
||||
0, /* EMACIO18 */
|
||||
0, /* EMACIO19 */
|
||||
3, /* FLASHIO0 */
|
||||
0, /* FLASHIO1 */
|
||||
3, /* FLASHIO2 */
|
||||
3, /* FLASHIO3 */
|
||||
3, /* FLASHIO4 */
|
||||
3, /* FLASHIO5 */
|
||||
3, /* FLASHIO6 */
|
||||
3, /* FLASHIO7 */
|
||||
0, /* FLASHIO8 */
|
||||
3, /* FLASHIO9 */
|
||||
3, /* FLASHIO10 */
|
||||
3, /* FLASHIO11 */
|
||||
0, /* GENERALIO0 */
|
||||
1, /* GENERALIO1 */
|
||||
1, /* GENERALIO2 */
|
||||
0, /* GENERALIO3 */
|
||||
0, /* GENERALIO4 */
|
||||
1, /* GENERALIO5 */
|
||||
1, /* GENERALIO6 */
|
||||
1, /* GENERALIO7 */
|
||||
1, /* GENERALIO8 */
|
||||
0, /* GENERALIO9 */
|
||||
0, /* GENERALIO10 */
|
||||
0, /* GENERALIO11 */
|
||||
0, /* GENERALIO12 */
|
||||
2, /* GENERALIO13 */
|
||||
2, /* GENERALIO14 */
|
||||
1, /* GENERALIO15 */
|
||||
1, /* GENERALIO16 */
|
||||
1, /* GENERALIO17 */
|
||||
1, /* GENERALIO18 */
|
||||
0, /* GENERALIO19 */
|
||||
0, /* GENERALIO20 */
|
||||
0, /* GENERALIO21 */
|
||||
0, /* GENERALIO22 */
|
||||
0, /* GENERALIO23 */
|
||||
0, /* GENERALIO24 */
|
||||
0, /* GENERALIO25 */
|
||||
0, /* GENERALIO26 */
|
||||
0, /* GENERALIO27 */
|
||||
0, /* GENERALIO28 */
|
||||
0, /* GENERALIO29 */
|
||||
0, /* GENERALIO30 */
|
||||
0, /* GENERALIO31 */
|
||||
0, /* MIXED1IO0 */
|
||||
1, /* MIXED1IO1 */
|
||||
1, /* MIXED1IO2 */
|
||||
1, /* MIXED1IO3 */
|
||||
1, /* MIXED1IO4 */
|
||||
0, /* MIXED1IO5 */
|
||||
0, /* MIXED1IO6 */
|
||||
0, /* MIXED1IO7 */
|
||||
1, /* MIXED1IO8 */
|
||||
1, /* MIXED1IO9 */
|
||||
1, /* MIXED1IO10 */
|
||||
1, /* MIXED1IO11 */
|
||||
0, /* MIXED1IO12 */
|
||||
0, /* MIXED1IO13 */
|
||||
0, /* MIXED1IO14 */
|
||||
1, /* MIXED1IO15 */
|
||||
1, /* MIXED1IO16 */
|
||||
1, /* MIXED1IO17 */
|
||||
1, /* MIXED1IO18 */
|
||||
0, /* MIXED1IO19 */
|
||||
0, /* MIXED1IO20 */
|
||||
0, /* MIXED1IO21 */
|
||||
0, /* MIXED2IO0 */
|
||||
0, /* MIXED2IO1 */
|
||||
0, /* MIXED2IO2 */
|
||||
0, /* MIXED2IO3 */
|
||||
0, /* MIXED2IO4 */
|
||||
0, /* MIXED2IO5 */
|
||||
0, /* MIXED2IO6 */
|
||||
0, /* MIXED2IO7 */
|
||||
0, /* GPLINMUX48 */
|
||||
0, /* GPLINMUX49 */
|
||||
0, /* GPLINMUX50 */
|
||||
0, /* GPLINMUX51 */
|
||||
0, /* GPLINMUX52 */
|
||||
0, /* GPLINMUX53 */
|
||||
0, /* GPLINMUX54 */
|
||||
0, /* GPLINMUX55 */
|
||||
0, /* GPLINMUX56 */
|
||||
0, /* GPLINMUX57 */
|
||||
0, /* GPLINMUX58 */
|
||||
0, /* GPLINMUX59 */
|
||||
0, /* GPLINMUX60 */
|
||||
0, /* GPLINMUX61 */
|
||||
0, /* GPLINMUX62 */
|
||||
0, /* GPLINMUX63 */
|
||||
0, /* GPLINMUX64 */
|
||||
0, /* GPLINMUX65 */
|
||||
0, /* GPLINMUX66 */
|
||||
0, /* GPLINMUX67 */
|
||||
0, /* GPLINMUX68 */
|
||||
0, /* GPLINMUX69 */
|
||||
0, /* GPLINMUX70 */
|
||||
1, /* GPLMUX0 */
|
||||
1, /* GPLMUX1 */
|
||||
1, /* GPLMUX2 */
|
||||
1, /* GPLMUX3 */
|
||||
1, /* GPLMUX4 */
|
||||
1, /* GPLMUX5 */
|
||||
1, /* GPLMUX6 */
|
||||
1, /* GPLMUX7 */
|
||||
1, /* GPLMUX8 */
|
||||
1, /* GPLMUX9 */
|
||||
1, /* GPLMUX10 */
|
||||
1, /* GPLMUX11 */
|
||||
1, /* GPLMUX12 */
|
||||
1, /* GPLMUX13 */
|
||||
1, /* GPLMUX14 */
|
||||
1, /* GPLMUX15 */
|
||||
1, /* GPLMUX16 */
|
||||
1, /* GPLMUX17 */
|
||||
1, /* GPLMUX18 */
|
||||
1, /* GPLMUX19 */
|
||||
1, /* GPLMUX20 */
|
||||
1, /* GPLMUX21 */
|
||||
1, /* GPLMUX22 */
|
||||
1, /* GPLMUX23 */
|
||||
1, /* GPLMUX24 */
|
||||
1, /* GPLMUX25 */
|
||||
1, /* GPLMUX26 */
|
||||
1, /* GPLMUX27 */
|
||||
1, /* GPLMUX28 */
|
||||
1, /* GPLMUX29 */
|
||||
1, /* GPLMUX30 */
|
||||
1, /* GPLMUX31 */
|
||||
1, /* GPLMUX32 */
|
||||
1, /* GPLMUX33 */
|
||||
1, /* GPLMUX34 */
|
||||
1, /* GPLMUX35 */
|
||||
1, /* GPLMUX36 */
|
||||
1, /* GPLMUX37 */
|
||||
1, /* GPLMUX38 */
|
||||
1, /* GPLMUX39 */
|
||||
1, /* GPLMUX40 */
|
||||
1, /* GPLMUX41 */
|
||||
1, /* GPLMUX42 */
|
||||
1, /* GPLMUX43 */
|
||||
1, /* GPLMUX44 */
|
||||
1, /* GPLMUX45 */
|
||||
1, /* GPLMUX46 */
|
||||
1, /* GPLMUX47 */
|
||||
1, /* GPLMUX48 */
|
||||
1, /* GPLMUX49 */
|
||||
1, /* GPLMUX50 */
|
||||
1, /* GPLMUX51 */
|
||||
1, /* GPLMUX52 */
|
||||
1, /* GPLMUX53 */
|
||||
1, /* GPLMUX54 */
|
||||
1, /* GPLMUX55 */
|
||||
1, /* GPLMUX56 */
|
||||
1, /* GPLMUX57 */
|
||||
1, /* GPLMUX58 */
|
||||
1, /* GPLMUX59 */
|
||||
1, /* GPLMUX60 */
|
||||
1, /* GPLMUX61 */
|
||||
1, /* GPLMUX62 */
|
||||
1, /* GPLMUX63 */
|
||||
1, /* GPLMUX64 */
|
||||
1, /* GPLMUX65 */
|
||||
1, /* GPLMUX66 */
|
||||
1, /* GPLMUX67 */
|
||||
1, /* GPLMUX68 */
|
||||
1, /* GPLMUX69 */
|
||||
1, /* GPLMUX70 */
|
||||
0, /* NANDUSEFPGA */
|
||||
0, /* UART0USEFPGA */
|
||||
0, /* RGMII1USEFPGA */
|
||||
0, /* SPIS0USEFPGA */
|
||||
0, /* CAN0USEFPGA */
|
||||
0, /* I2C0USEFPGA */
|
||||
0, /* SDMMCUSEFPGA */
|
||||
0, /* QSPIUSEFPGA */
|
||||
0, /* SPIS1USEFPGA */
|
||||
0, /* RGMII0USEFPGA */
|
||||
1, /* UART1USEFPGA */
|
||||
0, /* CAN1USEFPGA */
|
||||
0, /* USB1USEFPGA */
|
||||
0, /* I2C3USEFPGA */
|
||||
0, /* I2C2USEFPGA */
|
||||
0, /* I2C1USEFPGA */
|
||||
0, /* SPIM1USEFPGA */
|
||||
0, /* USB0USEFPGA */
|
||||
0 /* SPIM0USEFPGA */
|
||||
};
|
||||
#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */
|
85
board/denx/mcvevk/qts/pll_config.h
Normal file
85
board/denx/mcvevk/qts/pll_config.h
Normal file
|
@ -0,0 +1,85 @@
|
|||
/*
|
||||
* Altera SoCFPGA Clock and PLL configuration
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef __SOCFPGA_PLL_CONFIG_H__
|
||||
#define __SOCFPGA_PLL_CONFIG_H__
|
||||
|
||||
#define CONFIG_HPS_DBCTRL_STAYOSC1 1
|
||||
|
||||
#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
|
||||
#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63
|
||||
#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
|
||||
#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
|
||||
#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
|
||||
#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
|
||||
#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
|
||||
#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
|
||||
#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
|
||||
#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
|
||||
|
||||
#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
|
||||
#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
|
||||
#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
|
||||
#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
|
||||
#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 511
|
||||
#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
|
||||
#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
|
||||
#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
|
||||
#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
|
||||
#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
|
||||
#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
|
||||
#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 1
|
||||
#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 1
|
||||
#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
|
||||
#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
|
||||
#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
|
||||
#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
|
||||
|
||||
#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 2
|
||||
#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 79
|
||||
#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
|
||||
#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
|
||||
#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
|
||||
#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
|
||||
#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
|
||||
#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
|
||||
#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
|
||||
#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
|
||||
#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
|
||||
|
||||
#define CONFIG_HPS_CLK_OSC1_HZ 25000000
|
||||
#define CONFIG_HPS_CLK_OSC2_HZ 25000000
|
||||
#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
|
||||
#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
|
||||
#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
|
||||
#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
|
||||
#define CONFIG_HPS_CLK_SDRVCO_HZ 666666666
|
||||
#define CONFIG_HPS_CLK_EMAC0_HZ 250000000
|
||||
#define CONFIG_HPS_CLK_EMAC1_HZ 1953125
|
||||
#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
|
||||
#define CONFIG_HPS_CLK_NAND_HZ 50000000
|
||||
#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
|
||||
#define CONFIG_HPS_CLK_QSPI_HZ 3125000
|
||||
#define CONFIG_HPS_CLK_SPIM_HZ 200000000
|
||||
#define CONFIG_HPS_CLK_CAN0_HZ 100000000
|
||||
#define CONFIG_HPS_CLK_CAN1_HZ 100000000
|
||||
#define CONFIG_HPS_CLK_GPIODB_HZ 32000
|
||||
#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
|
||||
#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
|
||||
|
||||
#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
|
||||
#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
|
||||
#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
|
||||
|
||||
|
||||
#endif /* __SOCFPGA_PLL_CONFIG_H__ */
|
341
board/denx/mcvevk/qts/sdram_config.h
Normal file
341
board/denx/mcvevk/qts/sdram_config.h
Normal file
|
@ -0,0 +1,341 @@
|
|||
/*
|
||||
* Altera SoCFPGA SDRAM configuration
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef __SOCFPGA_SDRAM_CONFIG_H__
|
||||
#define __SOCFPGA_SDRAM_CONFIG_H__
|
||||
|
||||
/* SDRAM configuration */
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 14
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 117
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 5
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1300
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 5
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 5
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 12
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 17
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
|
||||
|
||||
/* Sequencer auto configuration */
|
||||
#define RW_MGR_ACTIVATE_0_AND_1 0x0D
|
||||
#define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E
|
||||
#define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10
|
||||
#define RW_MGR_ACTIVATE_1 0x0F
|
||||
#define RW_MGR_CLEAR_DQS_ENABLE 0x49
|
||||
#define RW_MGR_GUARANTEED_READ 0x4C
|
||||
#define RW_MGR_GUARANTEED_READ_CONT 0x54
|
||||
#define RW_MGR_GUARANTEED_WRITE 0x18
|
||||
#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1B
|
||||
#define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1F
|
||||
#define RW_MGR_GUARANTEED_WRITE_WAIT2 0x19
|
||||
#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1D
|
||||
#define RW_MGR_IDLE 0x00
|
||||
#define RW_MGR_IDLE_LOOP1 0x7B
|
||||
#define RW_MGR_IDLE_LOOP2 0x7A
|
||||
#define RW_MGR_INIT_RESET_0_CKE_0 0x6F
|
||||
#define RW_MGR_INIT_RESET_1_CKE_0 0x74
|
||||
#define RW_MGR_LFSR_WR_RD_BANK_0 0x22
|
||||
#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x25
|
||||
#define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x24
|
||||
#define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x23
|
||||
#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x32
|
||||
#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x21
|
||||
#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x36
|
||||
#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x39
|
||||
#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x38
|
||||
#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x37
|
||||
#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x46
|
||||
#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x35
|
||||
#define RW_MGR_MRS0_DLL_RESET 0x02
|
||||
#define RW_MGR_MRS0_DLL_RESET_MIRR 0x08
|
||||
#define RW_MGR_MRS0_USER 0x07
|
||||
#define RW_MGR_MRS0_USER_MIRR 0x0C
|
||||
#define RW_MGR_MRS1 0x03
|
||||
#define RW_MGR_MRS1_MIRR 0x09
|
||||
#define RW_MGR_MRS2 0x04
|
||||
#define RW_MGR_MRS2_MIRR 0x0A
|
||||
#define RW_MGR_MRS3 0x05
|
||||
#define RW_MGR_MRS3_MIRR 0x0B
|
||||
#define RW_MGR_PRECHARGE_ALL 0x12
|
||||
#define RW_MGR_READ_B2B 0x59
|
||||
#define RW_MGR_READ_B2B_WAIT1 0x61
|
||||
#define RW_MGR_READ_B2B_WAIT2 0x6B
|
||||
#define RW_MGR_REFRESH_ALL 0x14
|
||||
#define RW_MGR_RETURN 0x01
|
||||
#define RW_MGR_SGLE_READ 0x7D
|
||||
#define RW_MGR_ZQCL 0x06
|
||||
|
||||
/* Sequencer defines configuration */
|
||||
#define AFI_RATE_RATIO 1
|
||||
#define CALIB_LFIFO_OFFSET 7
|
||||
#define CALIB_VFIFO_OFFSET 5
|
||||
#define ENABLE_SUPER_QUICK_CALIBRATION 0
|
||||
#define IO_DELAY_PER_DCHAIN_TAP 25
|
||||
#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25
|
||||
#define IO_DELAY_PER_OPA_TAP 375
|
||||
#define IO_DLL_CHAIN_LENGTH 8
|
||||
#define IO_DQDQS_OUT_PHASE_MAX 0
|
||||
#define IO_DQS_EN_DELAY_MAX 31
|
||||
#define IO_DQS_EN_DELAY_OFFSET 0
|
||||
#define IO_DQS_EN_PHASE_MAX 7
|
||||
#define IO_DQS_IN_DELAY_MAX 31
|
||||
#define IO_DQS_IN_RESERVE 4
|
||||
#define IO_DQS_OUT_RESERVE 4
|
||||
#define IO_IO_IN_DELAY_MAX 31
|
||||
#define IO_IO_OUT1_DELAY_MAX 31
|
||||
#define IO_IO_OUT2_DELAY_MAX 0
|
||||
#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0
|
||||
#define MAX_LATENCY_COUNT_WIDTH 5
|
||||
#define READ_VALID_FIFO_SIZE 16
|
||||
#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048d
|
||||
#define RW_MGR_MEM_ADDRESS_MIRRORING 0
|
||||
#define RW_MGR_MEM_DATA_MASK_WIDTH 4
|
||||
#define RW_MGR_MEM_DATA_WIDTH 32
|
||||
#define RW_MGR_MEM_DQ_PER_READ_DQS 8
|
||||
#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8
|
||||
#define RW_MGR_MEM_IF_READ_DQS_WIDTH 4
|
||||
#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 4
|
||||
#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1
|
||||
#define RW_MGR_MEM_NUMBER_OF_RANKS 1
|
||||
#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1
|
||||
#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1
|
||||
#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 4
|
||||
#define TINIT_CNTR0_VAL 82
|
||||
#define TINIT_CNTR1_VAL 32
|
||||
#define TINIT_CNTR2_VAL 32
|
||||
#define TRESET_CNTR0_VAL 82
|
||||
#define TRESET_CNTR1_VAL 99
|
||||
#define TRESET_CNTR2_VAL 10
|
||||
|
||||
/* Sequencer ac_rom_init configuration */
|
||||
const u32 ac_rom_init[] = {
|
||||
0x20700000,
|
||||
0x20780000,
|
||||
0x10080221,
|
||||
0x10080320,
|
||||
0x10090044,
|
||||
0x100a0008,
|
||||
0x100b0000,
|
||||
0x10380400,
|
||||
0x10080241,
|
||||
0x100802c0,
|
||||
0x100a0024,
|
||||
0x10090010,
|
||||
0x100b0000,
|
||||
0x30780000,
|
||||
0x38780000,
|
||||
0x30780000,
|
||||
0x10680000,
|
||||
0x106b0000,
|
||||
0x10280400,
|
||||
0x10480000,
|
||||
0x1c980000,
|
||||
0x1c9b0000,
|
||||
0x1c980008,
|
||||
0x1c9b0008,
|
||||
0x38f80000,
|
||||
0x3cf80000,
|
||||
0x38780000,
|
||||
0x18180000,
|
||||
0x18980000,
|
||||
0x13580000,
|
||||
0x135b0000,
|
||||
0x13580008,
|
||||
0x135b0008,
|
||||
0x33780000,
|
||||
0x10580008,
|
||||
0x10780000
|
||||
};
|
||||
|
||||
/* Sequencer inst_rom_init configuration */
|
||||
const u32 inst_rom_init[] = {
|
||||
0x80000,
|
||||
0x80680,
|
||||
0x8180,
|
||||
0x8200,
|
||||
0x8280,
|
||||
0x8300,
|
||||
0x8380,
|
||||
0x8100,
|
||||
0x8480,
|
||||
0x8500,
|
||||
0x8580,
|
||||
0x8600,
|
||||
0x8400,
|
||||
0x800,
|
||||
0x8680,
|
||||
0x880,
|
||||
0xa680,
|
||||
0x80680,
|
||||
0x900,
|
||||
0x80680,
|
||||
0x980,
|
||||
0xa680,
|
||||
0x8680,
|
||||
0x80680,
|
||||
0xb68,
|
||||
0xcce8,
|
||||
0xae8,
|
||||
0x8ce8,
|
||||
0xb88,
|
||||
0xec88,
|
||||
0xa08,
|
||||
0xac88,
|
||||
0x80680,
|
||||
0xce00,
|
||||
0xcd80,
|
||||
0xe700,
|
||||
0xc00,
|
||||
0x20ce0,
|
||||
0x20ce0,
|
||||
0x20ce0,
|
||||
0x20ce0,
|
||||
0xd00,
|
||||
0x680,
|
||||
0x680,
|
||||
0x680,
|
||||
0x680,
|
||||
0x60e80,
|
||||
0x61080,
|
||||
0x61080,
|
||||
0x61080,
|
||||
0xa680,
|
||||
0x8680,
|
||||
0x80680,
|
||||
0xce00,
|
||||
0xcd80,
|
||||
0xe700,
|
||||
0xc00,
|
||||
0x30ce0,
|
||||
0x30ce0,
|
||||
0x30ce0,
|
||||
0x30ce0,
|
||||
0xd00,
|
||||
0x680,
|
||||
0x680,
|
||||
0x680,
|
||||
0x680,
|
||||
0x70e80,
|
||||
0x71080,
|
||||
0x71080,
|
||||
0x71080,
|
||||
0xa680,
|
||||
0x8680,
|
||||
0x80680,
|
||||
0x1158,
|
||||
0x6d8,
|
||||
0x80680,
|
||||
0x1168,
|
||||
0x7e8,
|
||||
0x7e8,
|
||||
0x87e8,
|
||||
0x40fe8,
|
||||
0x410e8,
|
||||
0x410e8,
|
||||
0x410e8,
|
||||
0x1168,
|
||||
0x7e8,
|
||||
0x7e8,
|
||||
0xa7e8,
|
||||
0x80680,
|
||||
0x40e88,
|
||||
0x41088,
|
||||
0x41088,
|
||||
0x41088,
|
||||
0x40f68,
|
||||
0x410e8,
|
||||
0x410e8,
|
||||
0x410e8,
|
||||
0xa680,
|
||||
0x40fe8,
|
||||
0x410e8,
|
||||
0x410e8,
|
||||
0x410e8,
|
||||
0x41008,
|
||||
0x41088,
|
||||
0x41088,
|
||||
0x41088,
|
||||
0x1100,
|
||||
0xc680,
|
||||
0x8680,
|
||||
0xe680,
|
||||
0x80680,
|
||||
0x0,
|
||||
0x8000,
|
||||
0xa000,
|
||||
0xc000,
|
||||
0x80000,
|
||||
0x80,
|
||||
0x8080,
|
||||
0xa080,
|
||||
0xc080,
|
||||
0x80080,
|
||||
0x9180,
|
||||
0x8680,
|
||||
0xa680,
|
||||
0x80680,
|
||||
0x40f08,
|
||||
0x80680
|
||||
};
|
||||
|
||||
#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */
|
45
board/denx/mcvevk/socfpga.c
Normal file
45
board/denx/mcvevk/socfpga.c
Normal file
|
@ -0,0 +1,45 @@
|
|||
/*
|
||||
* Copyright (C) 2015 Marek Vasut <marex@denx.de>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/reset_manager.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#include <usb.h>
|
||||
#include <usb/s3c_udc.h>
|
||||
#include <usb_mass_storage.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
void s_init(void) {}
|
||||
|
||||
/*
|
||||
* Miscellaneous platform dependent initialisations
|
||||
*/
|
||||
int board_init(void)
|
||||
{
|
||||
/* Address of boot parameters for ATAG (if ATAG is used) */
|
||||
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_USB_GADGET
|
||||
struct s3c_plat_otg_data socfpga_otg_data = {
|
||||
.regs_otg = CONFIG_USB_DWC2_REG_ADDR,
|
||||
.usb_gusbcfg = 0x1417,
|
||||
};
|
||||
|
||||
int board_usb_init(int index, enum usb_init_type init)
|
||||
{
|
||||
return s3c_udc_probe(&socfpga_otg_data);
|
||||
}
|
||||
|
||||
int g_dnl_board_usb_cable_connected(void)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
#endif
|
5
board/terasic/de0-nano-soc/MAINTAINERS
Normal file
5
board/terasic/de0-nano-soc/MAINTAINERS
Normal file
|
@ -0,0 +1,5 @@
|
|||
SOCFPGA ATLAS BOARD
|
||||
M: Dinh Nguyen <dinguyen@opensource.altera.com>
|
||||
S: Maintained
|
||||
F: include/configs/socfpga_de0_nano_soc.h
|
||||
F: configs/socfpga_de0_nano_soc_defconfig
|
9
board/terasic/de0-nano-soc/Makefile
Normal file
9
board/terasic/de0-nano-soc/Makefile
Normal file
|
@ -0,0 +1,9 @@
|
|||
#
|
||||
# (C) Copyright 2001-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y := socfpga.o
|
658
board/terasic/de0-nano-soc/qts/iocsr_config.h
Normal file
658
board/terasic/de0-nano-soc/qts/iocsr_config.h
Normal file
|
@ -0,0 +1,658 @@
|
|||
/*
|
||||
* Altera SoCFPGA IOCSR configuration
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef __SOCFPGA_IOCSR_CONFIG_H__
|
||||
#define __SOCFPGA_IOCSR_CONFIG_H__
|
||||
|
||||
#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764
|
||||
#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
|
||||
#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955
|
||||
#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
|
||||
|
||||
const unsigned long iocsr_scan_chain0_table[] = {
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x0FF00000,
|
||||
0xC0000000,
|
||||
0x0000003F,
|
||||
0x00008000,
|
||||
0x00020080,
|
||||
0x18060000,
|
||||
0x08000000,
|
||||
0x00018020,
|
||||
0x00000000,
|
||||
0x00004000,
|
||||
0x00010040,
|
||||
0x04010000,
|
||||
0x04000000,
|
||||
0x00000010,
|
||||
0x00004010,
|
||||
0x00002000,
|
||||
0x00020000,
|
||||
0x02008000,
|
||||
0x02000000,
|
||||
0x00000008,
|
||||
0x00002008,
|
||||
0x00001000,
|
||||
};
|
||||
|
||||
const unsigned long iocsr_scan_chain1_table[] = {
|
||||
0x00100000,
|
||||
0x10040000,
|
||||
0x100000C0,
|
||||
0x00000040,
|
||||
0x00010040,
|
||||
0x00008000,
|
||||
0x00060180,
|
||||
0x20000000,
|
||||
0x00000000,
|
||||
0x00000080,
|
||||
0x00020000,
|
||||
0x00004000,
|
||||
0x00010040,
|
||||
0x10000000,
|
||||
0x04000000,
|
||||
0x00000010,
|
||||
0x00004010,
|
||||
0x00002000,
|
||||
0x00020000,
|
||||
0x06018000,
|
||||
0x01FE0000,
|
||||
0xF8000000,
|
||||
0x00000007,
|
||||
0x00001000,
|
||||
0x00010000,
|
||||
0x04000000,
|
||||
0x00000000,
|
||||
0x00000010,
|
||||
0x00004000,
|
||||
0x00000800,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000008,
|
||||
0x00002000,
|
||||
0x00000400,
|
||||
0x00000000,
|
||||
0x00401000,
|
||||
0x00000003,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000200,
|
||||
0x00600802,
|
||||
0x00000000,
|
||||
0x80200000,
|
||||
0x80000600,
|
||||
0x00000200,
|
||||
0x00000100,
|
||||
0x00300401,
|
||||
0xC0100400,
|
||||
0x40100000,
|
||||
0x40000300,
|
||||
0x000C0100,
|
||||
0x00000080,
|
||||
};
|
||||
|
||||
const unsigned long iocsr_scan_chain2_table[] = {
|
||||
0x300C0300,
|
||||
0x00000000,
|
||||
0x0FF00000,
|
||||
0x00000000,
|
||||
0x0C0300C0,
|
||||
0x00008000,
|
||||
0x00080000,
|
||||
0x18060000,
|
||||
0x18000000,
|
||||
0x00018060,
|
||||
0x00020000,
|
||||
0x00004000,
|
||||
0x200300C0,
|
||||
0x10000000,
|
||||
0x00000000,
|
||||
0x00000040,
|
||||
0x00010000,
|
||||
0x00002000,
|
||||
0x10018060,
|
||||
0x06018000,
|
||||
0x06000000,
|
||||
0x00010018,
|
||||
0x00006018,
|
||||
0x00001000,
|
||||
0x00010000,
|
||||
0x00000000,
|
||||
0x03000000,
|
||||
0x0000800C,
|
||||
0x00C01004,
|
||||
0x00000800,
|
||||
};
|
||||
|
||||
const unsigned long iocsr_scan_chain3_table[] = {
|
||||
0x0C420D80,
|
||||
0x082000FF,
|
||||
0x0A804001,
|
||||
0x07900000,
|
||||
0x08020000,
|
||||
0x00100000,
|
||||
0x0A800000,
|
||||
0x07900000,
|
||||
0x08020000,
|
||||
0x00100000,
|
||||
0xC8800000,
|
||||
0x00003001,
|
||||
0x00C00722,
|
||||
0x00000000,
|
||||
0x00000021,
|
||||
0x82000004,
|
||||
0x05400000,
|
||||
0x03C80000,
|
||||
0x04010000,
|
||||
0x00080000,
|
||||
0x05400000,
|
||||
0x03C80000,
|
||||
0x05400000,
|
||||
0x03C80000,
|
||||
0xE4400000,
|
||||
0x00001800,
|
||||
0x00600391,
|
||||
0x800E4400,
|
||||
0x00000001,
|
||||
0x40000002,
|
||||
0x02A00000,
|
||||
0x01E40000,
|
||||
0x02A00000,
|
||||
0x01E40000,
|
||||
0x02A00000,
|
||||
0x01E40000,
|
||||
0x02A00000,
|
||||
0x01E40000,
|
||||
0x72200000,
|
||||
0x80000C00,
|
||||
0x003001C8,
|
||||
0xC0072200,
|
||||
0x1C880000,
|
||||
0x20000300,
|
||||
0x00040000,
|
||||
0x50670000,
|
||||
0x00000010,
|
||||
0x24590000,
|
||||
0x00001000,
|
||||
0xA0000034,
|
||||
0x0D000001,
|
||||
0xC0680618,
|
||||
0x4D034071,
|
||||
0x1A681A03,
|
||||
0x806180D0,
|
||||
0x34071C06,
|
||||
0x01A034D0,
|
||||
0x380D0000,
|
||||
0x0820680E,
|
||||
0x034D0340,
|
||||
0xD000001A,
|
||||
0x0680E380,
|
||||
0x10040000,
|
||||
0x00200000,
|
||||
0x10040000,
|
||||
0x00200000,
|
||||
0x15000000,
|
||||
0x0F200000,
|
||||
0x15000000,
|
||||
0x0F200000,
|
||||
0x01FE0000,
|
||||
0x00000000,
|
||||
0x01800E44,
|
||||
0x00391000,
|
||||
0x007F8006,
|
||||
0x00000000,
|
||||
0x0A800001,
|
||||
0x07900000,
|
||||
0x0A800000,
|
||||
0x07900000,
|
||||
0x0A800000,
|
||||
0x07900000,
|
||||
0x08020000,
|
||||
0x00100000,
|
||||
0xC8800000,
|
||||
0x00003001,
|
||||
0x00C00722,
|
||||
0x00000FF0,
|
||||
0x72200000,
|
||||
0x80000C00,
|
||||
0x05400000,
|
||||
0x02480000,
|
||||
0x04000000,
|
||||
0x00080000,
|
||||
0x05400000,
|
||||
0x03C80000,
|
||||
0x05400000,
|
||||
0x03C80000,
|
||||
0x6A1C0000,
|
||||
0x00001800,
|
||||
0x00600391,
|
||||
0x800E4400,
|
||||
0x1A870001,
|
||||
0x40000600,
|
||||
0x02A00040,
|
||||
0x01E40000,
|
||||
0x02A00000,
|
||||
0x01E40000,
|
||||
0x02A00000,
|
||||
0x01E40000,
|
||||
0x02A00000,
|
||||
0x01E40000,
|
||||
0x72200000,
|
||||
0x80000C00,
|
||||
0x003001C8,
|
||||
0xC0072200,
|
||||
0x1C880000,
|
||||
0x20000300,
|
||||
0x00040000,
|
||||
0x50670000,
|
||||
0x00000010,
|
||||
0x24590000,
|
||||
0x00001000,
|
||||
0xA0000034,
|
||||
0x0D000001,
|
||||
0xC0680618,
|
||||
0x4D034071,
|
||||
0x1A681A03,
|
||||
0x806180D0,
|
||||
0x34071C06,
|
||||
0x01A00040,
|
||||
0x180D0002,
|
||||
0x71C06806,
|
||||
0x034D0340,
|
||||
0xD01A681A,
|
||||
0x06806180,
|
||||
0x10040000,
|
||||
0x00200000,
|
||||
0x10040000,
|
||||
0x00200000,
|
||||
0x15000000,
|
||||
0x0F200000,
|
||||
0x15000000,
|
||||
0x0F200000,
|
||||
0x01FE0000,
|
||||
0x00000000,
|
||||
0x01800E44,
|
||||
0x00391000,
|
||||
0x007F8006,
|
||||
0x00000000,
|
||||
0x99300001,
|
||||
0x34343400,
|
||||
0xAA0D4000,
|
||||
0x01C3A800,
|
||||
0xAA0D4000,
|
||||
0x01C3A800,
|
||||
0xAA0D4000,
|
||||
0x01C3A800,
|
||||
0x00040100,
|
||||
0x00000800,
|
||||
0x00000000,
|
||||
0x00001208,
|
||||
0x00482000,
|
||||
0x01000000,
|
||||
0x00000000,
|
||||
0x00410482,
|
||||
0x0006A000,
|
||||
0x0001B400,
|
||||
0x00020000,
|
||||
0x00000400,
|
||||
0x0002A000,
|
||||
0x0001E400,
|
||||
0x5506A000,
|
||||
0x00E1D400,
|
||||
0x00000000,
|
||||
0xC880090C,
|
||||
0x00003001,
|
||||
0x90400000,
|
||||
0x00000000,
|
||||
0x2020C243,
|
||||
0x2A835000,
|
||||
0x0070EA00,
|
||||
0x2A835000,
|
||||
0x0070EA00,
|
||||
0x2A835000,
|
||||
0x0070EA00,
|
||||
0x00010040,
|
||||
0x00000200,
|
||||
0x00000000,
|
||||
0x00000482,
|
||||
0x00120800,
|
||||
0x00002000,
|
||||
0x80000000,
|
||||
0x00104120,
|
||||
0x00000200,
|
||||
0xAC0D5F80,
|
||||
0xFFFFFFFF,
|
||||
0x14F3690D,
|
||||
0x1A041414,
|
||||
0x00D00000,
|
||||
0x14864000,
|
||||
0x59647A05,
|
||||
0xD32CA3D6,
|
||||
0xF551451E,
|
||||
0x034CD348,
|
||||
0x821A0000,
|
||||
0x0000D000,
|
||||
0x030C0680,
|
||||
0xD659647A,
|
||||
0x1ED32CA3,
|
||||
0x48F55145,
|
||||
0x00034CD3,
|
||||
0x00080200,
|
||||
0x00001000,
|
||||
0x00080200,
|
||||
0x00001000,
|
||||
0x000A8000,
|
||||
0x00075000,
|
||||
0x541A8000,
|
||||
0x03875001,
|
||||
0x10000000,
|
||||
0x00000000,
|
||||
0x0080C000,
|
||||
0x41000000,
|
||||
0x00003FC2,
|
||||
0x00820000,
|
||||
0xAA0D4000,
|
||||
0x01C3A800,
|
||||
0xAA0D4000,
|
||||
0x01C3A800,
|
||||
0xAA0D4000,
|
||||
0x01C3A800,
|
||||
0x00040100,
|
||||
0x00000800,
|
||||
0x00000000,
|
||||
0x00001208,
|
||||
0x00482000,
|
||||
0x00008000,
|
||||
0x00000000,
|
||||
0x00410482,
|
||||
0x0006A000,
|
||||
0x0001B400,
|
||||
0x00020000,
|
||||
0x00000400,
|
||||
0x00020080,
|
||||
0x00000400,
|
||||
0x5506A000,
|
||||
0x00E1D400,
|
||||
0x00000000,
|
||||
0x0000090C,
|
||||
0x00000010,
|
||||
0x90400000,
|
||||
0x00000000,
|
||||
0x2020C243,
|
||||
0x2A835000,
|
||||
0x0070EA00,
|
||||
0x2A835000,
|
||||
0x0070EA00,
|
||||
0x2A835000,
|
||||
0x0070EA00,
|
||||
0x00015000,
|
||||
0x0000F200,
|
||||
0x00000000,
|
||||
0x00000482,
|
||||
0x00120800,
|
||||
0x00600391,
|
||||
0x80000000,
|
||||
0x00104120,
|
||||
0x00000200,
|
||||
0xAC0D5F80,
|
||||
0xFFFFFFFF,
|
||||
0x14F3690D,
|
||||
0x1A041414,
|
||||
0x00D00000,
|
||||
0x0C864000,
|
||||
0x59647A03,
|
||||
0x932CA3DE,
|
||||
0xF651451E,
|
||||
0x035CD348,
|
||||
0x821A0041,
|
||||
0x0000D000,
|
||||
0x00000680,
|
||||
0xDE59647A,
|
||||
0x1ED32CA3,
|
||||
0x48F55145,
|
||||
0x00035492,
|
||||
0x00080200,
|
||||
0x00001000,
|
||||
0x00080200,
|
||||
0x00001000,
|
||||
0x000A8000,
|
||||
0x00075000,
|
||||
0x541A8000,
|
||||
0x03875001,
|
||||
0x10000000,
|
||||
0x00000000,
|
||||
0x0080C000,
|
||||
0x41000000,
|
||||
0x04000002,
|
||||
0x00820000,
|
||||
0xAA0D4000,
|
||||
0x01C3A800,
|
||||
0xAA0D4000,
|
||||
0x01C3A800,
|
||||
0xAA0D4000,
|
||||
0x01C3A800,
|
||||
0x00040100,
|
||||
0x00000800,
|
||||
0x00000000,
|
||||
0x00001208,
|
||||
0x00482000,
|
||||
0x00008000,
|
||||
0x00000000,
|
||||
0x00410482,
|
||||
0x0006A000,
|
||||
0x0001B400,
|
||||
0x00020000,
|
||||
0x00000400,
|
||||
0x0002A000,
|
||||
0x0001E400,
|
||||
0x5506A000,
|
||||
0x00E1D400,
|
||||
0x00000000,
|
||||
0xC880090C,
|
||||
0x00003001,
|
||||
0x90400000,
|
||||
0x00000000,
|
||||
0x2020C243,
|
||||
0x2A835000,
|
||||
0x0070EA00,
|
||||
0x2A835000,
|
||||
0x0070EA00,
|
||||
0x2A835000,
|
||||
0x0070EA00,
|
||||
0x00010040,
|
||||
0x00000200,
|
||||
0x00000000,
|
||||
0x00000482,
|
||||
0x00120800,
|
||||
0x00002000,
|
||||
0x80000000,
|
||||
0x00104120,
|
||||
0x00000200,
|
||||
0xAC0D5F80,
|
||||
0xFFFFFFFF,
|
||||
0x14F3690D,
|
||||
0x1A041414,
|
||||
0x00D00000,
|
||||
0x0C864000,
|
||||
0x59647A03,
|
||||
0xD32CA3DE,
|
||||
0xF551451E,
|
||||
0x035CB2C8,
|
||||
0x821A0000,
|
||||
0x0000D000,
|
||||
0x00000680,
|
||||
0xDE59647A,
|
||||
0x1ED2AAA3,
|
||||
0xC8F55965,
|
||||
0x00035CB2,
|
||||
0x00080200,
|
||||
0x00001000,
|
||||
0x00080200,
|
||||
0x00001000,
|
||||
0x000A8000,
|
||||
0x00075000,
|
||||
0x541A8000,
|
||||
0x03875001,
|
||||
0x10000000,
|
||||
0x00000000,
|
||||
0x0080C000,
|
||||
0x41000000,
|
||||
0x04000002,
|
||||
0x00820000,
|
||||
0xAA0D4000,
|
||||
0x01C3A800,
|
||||
0xAA0D4000,
|
||||
0x01C3A800,
|
||||
0xAA0D4000,
|
||||
0x01C3A800,
|
||||
0x00040100,
|
||||
0x00000800,
|
||||
0x00000000,
|
||||
0x00001208,
|
||||
0x00482000,
|
||||
0x00008000,
|
||||
0x00000000,
|
||||
0x00410482,
|
||||
0x0006A000,
|
||||
0x0001B400,
|
||||
0x00020000,
|
||||
0x00000400,
|
||||
0x00020080,
|
||||
0x00000400,
|
||||
0x5506A000,
|
||||
0x00E1D400,
|
||||
0x00000000,
|
||||
0x0000090C,
|
||||
0x00000010,
|
||||
0x90400000,
|
||||
0x00000000,
|
||||
0x2020C243,
|
||||
0x2A835000,
|
||||
0x0070EA00,
|
||||
0x2A835000,
|
||||
0x0070EA00,
|
||||
0x2A835000,
|
||||
0x0070EA00,
|
||||
0x00010040,
|
||||
0x00000200,
|
||||
0x00000000,
|
||||
0x00000482,
|
||||
0x00120800,
|
||||
0x00400000,
|
||||
0x80000000,
|
||||
0x00104120,
|
||||
0x00000200,
|
||||
0xAC0D5F80,
|
||||
0xFFFFFFFF,
|
||||
0x14F1690D,
|
||||
0x1A041414,
|
||||
0x00D00000,
|
||||
0x14864000,
|
||||
0x59647A05,
|
||||
0xD32CA3DE,
|
||||
0xF551451E,
|
||||
0x035CD348,
|
||||
0x821A0000,
|
||||
0x0000D000,
|
||||
0x00000680,
|
||||
0xDE59647A,
|
||||
0x1ED32CA3,
|
||||
0x48F55145,
|
||||
0x00035CD3,
|
||||
0x00080200,
|
||||
0x00001000,
|
||||
0x00080200,
|
||||
0x00001000,
|
||||
0x000A8000,
|
||||
0x00075000,
|
||||
0x541A8000,
|
||||
0x03875001,
|
||||
0x10000000,
|
||||
0x00000000,
|
||||
0x0080C000,
|
||||
0x41000000,
|
||||
0x04000002,
|
||||
0x00820000,
|
||||
0x00489800,
|
||||
0x801A1A1A,
|
||||
0x00000200,
|
||||
0x80000004,
|
||||
0x00000200,
|
||||
0x80000004,
|
||||
0x00000200,
|
||||
0x80000004,
|
||||
0x00000200,
|
||||
0x00000004,
|
||||
0x00040000,
|
||||
0x10000000,
|
||||
0x00000000,
|
||||
0x00000040,
|
||||
0x00010000,
|
||||
0x40002000,
|
||||
0x00000100,
|
||||
0x40000002,
|
||||
0x00000100,
|
||||
0x40000002,
|
||||
0x00000100,
|
||||
0x40000002,
|
||||
0x00000100,
|
||||
0x00000002,
|
||||
0x00020000,
|
||||
0x08000000,
|
||||
0x00000000,
|
||||
0x00000020,
|
||||
0x00008000,
|
||||
0x20001000,
|
||||
0x00000080,
|
||||
0x20000001,
|
||||
0x00000080,
|
||||
0x20000001,
|
||||
0x00000080,
|
||||
0x20000001,
|
||||
0x00000080,
|
||||
0x00000001,
|
||||
0x00010000,
|
||||
0x04000000,
|
||||
0x00FF0000,
|
||||
0x00000000,
|
||||
0x00004000,
|
||||
0x00000800,
|
||||
0xC0000001,
|
||||
0x00041419,
|
||||
0x40000000,
|
||||
0x04000816,
|
||||
0x000D0000,
|
||||
0x00006800,
|
||||
0x00000340,
|
||||
0xD000001A,
|
||||
0x06800000,
|
||||
0x00340000,
|
||||
0x0001A000,
|
||||
0x00000D00,
|
||||
0x40000068,
|
||||
0x1A000003,
|
||||
0x00D00000,
|
||||
0x00068000,
|
||||
0x00003400,
|
||||
0x000001A0,
|
||||
0x00000401,
|
||||
0x00000008,
|
||||
0x00000401,
|
||||
0x00000008,
|
||||
0x00000401,
|
||||
0x00000008,
|
||||
0x00000401,
|
||||
0x80000008,
|
||||
0x0000007F,
|
||||
0x20000000,
|
||||
0x00000000,
|
||||
0xE0000080,
|
||||
0x0000001F,
|
||||
0x00004000,
|
||||
};
|
||||
#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */
|
220
board/terasic/de0-nano-soc/qts/pinmux_config.h
Normal file
220
board/terasic/de0-nano-soc/qts/pinmux_config.h
Normal file
|
@ -0,0 +1,220 @@
|
|||
/*
|
||||
* Altera SoCFPGA PinMux configuration
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef __SOCFPGA_PINMUX_CONFIG_H__
|
||||
#define __SOCFPGA_PINMUX_CONFIG_H__
|
||||
|
||||
/* pin MUX configuration data */
|
||||
const u8 sys_mgr_init_table[] = {
|
||||
0, /* EMACIO0 */
|
||||
2, /* EMACIO1 */
|
||||
2, /* EMACIO2 */
|
||||
2, /* EMACIO3 */
|
||||
2, /* EMACIO4 */
|
||||
2, /* EMACIO5 */
|
||||
2, /* EMACIO6 */
|
||||
2, /* EMACIO7 */
|
||||
2, /* EMACIO8 */
|
||||
0, /* EMACIO9 */
|
||||
2, /* EMACIO10 */
|
||||
2, /* EMACIO11 */
|
||||
2, /* EMACIO12 */
|
||||
2, /* EMACIO13 */
|
||||
0, /* EMACIO14 */
|
||||
0, /* EMACIO15 */
|
||||
0, /* EMACIO16 */
|
||||
0, /* EMACIO17 */
|
||||
0, /* EMACIO18 */
|
||||
0, /* EMACIO19 */
|
||||
3, /* FLASHIO0 */
|
||||
0, /* FLASHIO1 */
|
||||
3, /* FLASHIO2 */
|
||||
3, /* FLASHIO3 */
|
||||
0, /* FLASHIO4 */
|
||||
0, /* FLASHIO5 */
|
||||
0, /* FLASHIO6 */
|
||||
0, /* FLASHIO7 */
|
||||
0, /* FLASHIO8 */
|
||||
3, /* FLASHIO9 */
|
||||
3, /* FLASHIO10 */
|
||||
3, /* FLASHIO11 */
|
||||
0, /* GENERALIO0 */
|
||||
1, /* GENERALIO1 */
|
||||
1, /* GENERALIO2 */
|
||||
1, /* GENERALIO3 */
|
||||
1, /* GENERALIO4 */
|
||||
0, /* GENERALIO5 */
|
||||
0, /* GENERALIO6 */
|
||||
1, /* GENERALIO7 */
|
||||
1, /* GENERALIO8 */
|
||||
0, /* GENERALIO9 */
|
||||
0, /* GENERALIO10 */
|
||||
0, /* GENERALIO11 */
|
||||
0, /* GENERALIO12 */
|
||||
0, /* GENERALIO13 */
|
||||
0, /* GENERALIO14 */
|
||||
1, /* GENERALIO15 */
|
||||
1, /* GENERALIO16 */
|
||||
1, /* GENERALIO17 */
|
||||
1, /* GENERALIO18 */
|
||||
0, /* GENERALIO19 */
|
||||
0, /* GENERALIO20 */
|
||||
0, /* GENERALIO21 */
|
||||
0, /* GENERALIO22 */
|
||||
0, /* GENERALIO23 */
|
||||
0, /* GENERALIO24 */
|
||||
0, /* GENERALIO25 */
|
||||
0, /* GENERALIO26 */
|
||||
0, /* GENERALIO27 */
|
||||
0, /* GENERALIO28 */
|
||||
0, /* GENERALIO29 */
|
||||
0, /* GENERALIO30 */
|
||||
0, /* GENERALIO31 */
|
||||
2, /* MIXED1IO0 */
|
||||
2, /* MIXED1IO1 */
|
||||
2, /* MIXED1IO2 */
|
||||
2, /* MIXED1IO3 */
|
||||
2, /* MIXED1IO4 */
|
||||
2, /* MIXED1IO5 */
|
||||
2, /* MIXED1IO6 */
|
||||
2, /* MIXED1IO7 */
|
||||
2, /* MIXED1IO8 */
|
||||
2, /* MIXED1IO9 */
|
||||
2, /* MIXED1IO10 */
|
||||
2, /* MIXED1IO11 */
|
||||
2, /* MIXED1IO12 */
|
||||
2, /* MIXED1IO13 */
|
||||
0, /* MIXED1IO14 */
|
||||
0, /* MIXED1IO15 */
|
||||
0, /* MIXED1IO16 */
|
||||
0, /* MIXED1IO17 */
|
||||
0, /* MIXED1IO18 */
|
||||
0, /* MIXED1IO19 */
|
||||
0, /* MIXED1IO20 */
|
||||
0, /* MIXED1IO21 */
|
||||
0, /* MIXED2IO0 */
|
||||
0, /* MIXED2IO1 */
|
||||
0, /* MIXED2IO2 */
|
||||
0, /* MIXED2IO3 */
|
||||
0, /* MIXED2IO4 */
|
||||
0, /* MIXED2IO5 */
|
||||
0, /* MIXED2IO6 */
|
||||
0, /* MIXED2IO7 */
|
||||
0, /* GPLINMUX48 */
|
||||
0, /* GPLINMUX49 */
|
||||
0, /* GPLINMUX50 */
|
||||
0, /* GPLINMUX51 */
|
||||
0, /* GPLINMUX52 */
|
||||
0, /* GPLINMUX53 */
|
||||
0, /* GPLINMUX54 */
|
||||
0, /* GPLINMUX55 */
|
||||
0, /* GPLINMUX56 */
|
||||
0, /* GPLINMUX57 */
|
||||
0, /* GPLINMUX58 */
|
||||
0, /* GPLINMUX59 */
|
||||
0, /* GPLINMUX60 */
|
||||
0, /* GPLINMUX61 */
|
||||
0, /* GPLINMUX62 */
|
||||
0, /* GPLINMUX63 */
|
||||
0, /* GPLINMUX64 */
|
||||
0, /* GPLINMUX65 */
|
||||
0, /* GPLINMUX66 */
|
||||
0, /* GPLINMUX67 */
|
||||
0, /* GPLINMUX68 */
|
||||
0, /* GPLINMUX69 */
|
||||
0, /* GPLINMUX70 */
|
||||
1, /* GPLMUX0 */
|
||||
1, /* GPLMUX1 */
|
||||
1, /* GPLMUX2 */
|
||||
1, /* GPLMUX3 */
|
||||
1, /* GPLMUX4 */
|
||||
1, /* GPLMUX5 */
|
||||
1, /* GPLMUX6 */
|
||||
1, /* GPLMUX7 */
|
||||
1, /* GPLMUX8 */
|
||||
1, /* GPLMUX9 */
|
||||
1, /* GPLMUX10 */
|
||||
1, /* GPLMUX11 */
|
||||
1, /* GPLMUX12 */
|
||||
1, /* GPLMUX13 */
|
||||
1, /* GPLMUX14 */
|
||||
1, /* GPLMUX15 */
|
||||
1, /* GPLMUX16 */
|
||||
1, /* GPLMUX17 */
|
||||
1, /* GPLMUX18 */
|
||||
1, /* GPLMUX19 */
|
||||
1, /* GPLMUX20 */
|
||||
1, /* GPLMUX21 */
|
||||
1, /* GPLMUX22 */
|
||||
1, /* GPLMUX23 */
|
||||
1, /* GPLMUX24 */
|
||||
1, /* GPLMUX25 */
|
||||
1, /* GPLMUX26 */
|
||||
1, /* GPLMUX27 */
|
||||
1, /* GPLMUX28 */
|
||||
1, /* GPLMUX29 */
|
||||
1, /* GPLMUX30 */
|
||||
1, /* GPLMUX31 */
|
||||
1, /* GPLMUX32 */
|
||||
1, /* GPLMUX33 */
|
||||
1, /* GPLMUX34 */
|
||||
1, /* GPLMUX35 */
|
||||
1, /* GPLMUX36 */
|
||||
1, /* GPLMUX37 */
|
||||
1, /* GPLMUX38 */
|
||||
1, /* GPLMUX39 */
|
||||
1, /* GPLMUX40 */
|
||||
1, /* GPLMUX41 */
|
||||
1, /* GPLMUX42 */
|
||||
1, /* GPLMUX43 */
|
||||
1, /* GPLMUX44 */
|
||||
1, /* GPLMUX45 */
|
||||
1, /* GPLMUX46 */
|
||||
1, /* GPLMUX47 */
|
||||
1, /* GPLMUX48 */
|
||||
1, /* GPLMUX49 */
|
||||
1, /* GPLMUX50 */
|
||||
1, /* GPLMUX51 */
|
||||
1, /* GPLMUX52 */
|
||||
1, /* GPLMUX53 */
|
||||
1, /* GPLMUX54 */
|
||||
1, /* GPLMUX55 */
|
||||
1, /* GPLMUX56 */
|
||||
1, /* GPLMUX57 */
|
||||
1, /* GPLMUX58 */
|
||||
1, /* GPLMUX59 */
|
||||
1, /* GPLMUX60 */
|
||||
1, /* GPLMUX61 */
|
||||
1, /* GPLMUX62 */
|
||||
1, /* GPLMUX63 */
|
||||
1, /* GPLMUX64 */
|
||||
1, /* GPLMUX65 */
|
||||
1, /* GPLMUX66 */
|
||||
1, /* GPLMUX67 */
|
||||
1, /* GPLMUX68 */
|
||||
1, /* GPLMUX69 */
|
||||
1, /* GPLMUX70 */
|
||||
0, /* NANDUSEFPGA */
|
||||
0, /* UART0USEFPGA */
|
||||
0, /* RGMII1USEFPGA */
|
||||
0, /* SPIS0USEFPGA */
|
||||
0, /* CAN0USEFPGA */
|
||||
0, /* I2C0USEFPGA */
|
||||
0, /* SDMMCUSEFPGA */
|
||||
0, /* QSPIUSEFPGA */
|
||||
0, /* SPIS1USEFPGA */
|
||||
0, /* RGMII0USEFPGA */
|
||||
0, /* UART1USEFPGA */
|
||||
0, /* CAN1USEFPGA */
|
||||
0, /* USB1USEFPGA */
|
||||
0, /* I2C3USEFPGA */
|
||||
0, /* I2C2USEFPGA */
|
||||
0, /* I2C1USEFPGA */
|
||||
0, /* SPIM1USEFPGA */
|
||||
0, /* USB0USEFPGA */
|
||||
0 /* SPIM0USEFPGA */
|
||||
};
|
||||
#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */
|
85
board/terasic/de0-nano-soc/qts/pll_config.h
Normal file
85
board/terasic/de0-nano-soc/qts/pll_config.h
Normal file
|
@ -0,0 +1,85 @@
|
|||
/*
|
||||
* Altera SoCFPGA Clock and PLL configuration
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef _PRELOADER_PLL_CONFIG_H_
|
||||
#define _PRELOADER_PLL_CONFIG_H_
|
||||
|
||||
#define CONFIG_HPS_DBCTRL_STAYOSC1 1
|
||||
|
||||
#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
|
||||
#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 73
|
||||
#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
|
||||
#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
|
||||
#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 18
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
|
||||
#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
|
||||
#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
|
||||
#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
|
||||
#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
|
||||
#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
|
||||
|
||||
#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
|
||||
#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
|
||||
#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
|
||||
#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
|
||||
#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
|
||||
#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
|
||||
#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
|
||||
#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
|
||||
#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 19
|
||||
#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
|
||||
#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
|
||||
#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4
|
||||
#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
|
||||
#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
|
||||
#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
|
||||
#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
|
||||
#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
|
||||
|
||||
#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
|
||||
#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
|
||||
#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
|
||||
#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
|
||||
#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
|
||||
#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
|
||||
#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
|
||||
#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
|
||||
#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
|
||||
#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
|
||||
#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
|
||||
|
||||
#define CONFIG_HPS_CLK_OSC1_HZ 25000000
|
||||
#define CONFIG_HPS_CLK_OSC2_HZ 25000000
|
||||
#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
|
||||
#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
|
||||
#define CONFIG_HPS_CLK_MAINVCO_HZ 1850000000
|
||||
#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
|
||||
#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
|
||||
#define CONFIG_HPS_CLK_EMAC0_HZ 1953125
|
||||
#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
|
||||
#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
|
||||
#define CONFIG_HPS_CLK_NAND_HZ 50000000
|
||||
#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
|
||||
#define CONFIG_HPS_CLK_QSPI_HZ 3613281
|
||||
#define CONFIG_HPS_CLK_SPIM_HZ 200000000
|
||||
#define CONFIG_HPS_CLK_CAN0_HZ 12500000
|
||||
#define CONFIG_HPS_CLK_CAN1_HZ 12500000
|
||||
#define CONFIG_HPS_CLK_GPIODB_HZ 32000
|
||||
#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
|
||||
#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
|
||||
|
||||
#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
|
||||
#define CONFIG_HPS_ALTERAGRP_MAINCLK 4
|
||||
#define CONFIG_HPS_ALTERAGRP_DBGATCLK 4
|
||||
|
||||
#endif /* _PRELOADER_PLL_CONFIG_H_ */
|
||||
|
342
board/terasic/de0-nano-soc/qts/sdram_config.h
Normal file
342
board/terasic/de0-nano-soc/qts/sdram_config.h
Normal file
|
@ -0,0 +1,342 @@
|
|||
/*
|
||||
* Altera SoCFPGA SDRAM configuration
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef __SDRAM_CONFIG_H
|
||||
#define __SDRAM_CONFIG_H
|
||||
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 7
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 15
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 120
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
|
||||
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_READ_PORT_USED 0x1
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_WRITE_PORT_USED 0x1
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_COMMAND_PORT_USED 0x3
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x311
|
||||
|
||||
/* Sequencer auto configuration */
|
||||
#define RW_MGR_ACTIVATE_0_AND_1 0x0D
|
||||
#define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E
|
||||
#define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10
|
||||
#define RW_MGR_ACTIVATE_1 0x0F
|
||||
#define RW_MGR_CLEAR_DQS_ENABLE 0x49
|
||||
#define RW_MGR_GUARANTEED_READ 0x4C
|
||||
#define RW_MGR_GUARANTEED_READ_CONT 0x54
|
||||
#define RW_MGR_GUARANTEED_WRITE 0x18
|
||||
#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1B
|
||||
#define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1F
|
||||
#define RW_MGR_GUARANTEED_WRITE_WAIT2 0x19
|
||||
#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1D
|
||||
#define RW_MGR_IDLE 0x00
|
||||
#define RW_MGR_IDLE_LOOP1 0x7B
|
||||
#define RW_MGR_IDLE_LOOP2 0x7A
|
||||
#define RW_MGR_INIT_RESET_0_CKE_0 0x6F
|
||||
#define RW_MGR_INIT_RESET_1_CKE_0 0x74
|
||||
#define RW_MGR_LFSR_WR_RD_BANK_0 0x22
|
||||
#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x25
|
||||
#define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x24
|
||||
#define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x23
|
||||
#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x32
|
||||
#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x21
|
||||
#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x36
|
||||
#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x39
|
||||
#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x38
|
||||
#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x37
|
||||
#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x46
|
||||
#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x35
|
||||
#define RW_MGR_MRS0_DLL_RESET 0x02
|
||||
#define RW_MGR_MRS0_DLL_RESET_MIRR 0x08
|
||||
#define RW_MGR_MRS0_USER 0x07
|
||||
#define RW_MGR_MRS0_USER_MIRR 0x0C
|
||||
#define RW_MGR_MRS1 0x03
|
||||
#define RW_MGR_MRS1_MIRR 0x09
|
||||
#define RW_MGR_MRS2 0x04
|
||||
#define RW_MGR_MRS2_MIRR 0x0A
|
||||
#define RW_MGR_MRS3 0x05
|
||||
#define RW_MGR_MRS3_MIRR 0x0B
|
||||
#define RW_MGR_PRECHARGE_ALL 0x12
|
||||
#define RW_MGR_READ_B2B 0x59
|
||||
#define RW_MGR_READ_B2B_WAIT1 0x61
|
||||
#define RW_MGR_READ_B2B_WAIT2 0x6B
|
||||
#define RW_MGR_REFRESH_ALL 0x14
|
||||
#define RW_MGR_RETURN 0x01
|
||||
#define RW_MGR_SGLE_READ 0x7D
|
||||
#define RW_MGR_ZQCL 0x06
|
||||
|
||||
/* Sequencer defines configuration */
|
||||
#define AFI_RATE_RATIO 1
|
||||
#define CALIB_LFIFO_OFFSET 8
|
||||
#define CALIB_VFIFO_OFFSET 6
|
||||
#define ENABLE_SUPER_QUICK_CALIBRATION 0
|
||||
#define IO_DELAY_PER_DCHAIN_TAP 25
|
||||
#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25
|
||||
#define IO_DELAY_PER_OPA_TAP 312
|
||||
#define IO_DLL_CHAIN_LENGTH 8
|
||||
#define IO_DQDQS_OUT_PHASE_MAX 0
|
||||
#define IO_DQS_EN_DELAY_MAX 31
|
||||
#define IO_DQS_EN_DELAY_OFFSET 0
|
||||
#define IO_DQS_EN_PHASE_MAX 7
|
||||
#define IO_DQS_IN_DELAY_MAX 31
|
||||
#define IO_DQS_IN_RESERVE 4
|
||||
#define IO_DQS_OUT_RESERVE 4
|
||||
#define IO_IO_IN_DELAY_MAX 31
|
||||
#define IO_IO_OUT1_DELAY_MAX 31
|
||||
#define IO_IO_OUT2_DELAY_MAX 0
|
||||
#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0
|
||||
#define MAX_LATENCY_COUNT_WIDTH 5
|
||||
#define READ_VALID_FIFO_SIZE 16
|
||||
#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048d
|
||||
#define RW_MGR_MEM_ADDRESS_MIRRORING 0
|
||||
#define RW_MGR_MEM_DATA_MASK_WIDTH 4
|
||||
#define RW_MGR_MEM_DATA_WIDTH 32
|
||||
#define RW_MGR_MEM_DQ_PER_READ_DQS 8
|
||||
#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8
|
||||
#define RW_MGR_MEM_IF_READ_DQS_WIDTH 4
|
||||
#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 4
|
||||
#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1
|
||||
#define RW_MGR_MEM_NUMBER_OF_RANKS 1
|
||||
#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1
|
||||
#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1
|
||||
#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 4
|
||||
#define TINIT_CNTR0_VAL 99
|
||||
#define TINIT_CNTR1_VAL 32
|
||||
#define TINIT_CNTR2_VAL 32
|
||||
#define TRESET_CNTR0_VAL 99
|
||||
#define TRESET_CNTR1_VAL 99
|
||||
#define TRESET_CNTR2_VAL 10
|
||||
|
||||
/* Sequencer ac_rom_init configuration */
|
||||
const u32 ac_rom_init[] = {
|
||||
0x20700000,
|
||||
0x20780000,
|
||||
0x10080431,
|
||||
0x10080530,
|
||||
0x10090044,
|
||||
0x100a0010,
|
||||
0x100b0000,
|
||||
0x10380400,
|
||||
0x10080449,
|
||||
0x100804c8,
|
||||
0x100a0024,
|
||||
0x10090008,
|
||||
0x100b0000,
|
||||
0x30780000,
|
||||
0x38780000,
|
||||
0x30780000,
|
||||
0x10680000,
|
||||
0x106b0000,
|
||||
0x10280400,
|
||||
0x10480000,
|
||||
0x1c980000,
|
||||
0x1c9b0000,
|
||||
0x1c980008,
|
||||
0x1c9b0008,
|
||||
0x38f80000,
|
||||
0x3cf80000,
|
||||
0x38780000,
|
||||
0x18180000,
|
||||
0x18980000,
|
||||
0x13580000,
|
||||
0x135b0000,
|
||||
0x13580008,
|
||||
0x135b0008,
|
||||
0x33780000,
|
||||
0x10580008,
|
||||
0x10780000
|
||||
};
|
||||
|
||||
/* Sequencer inst_rom_init configuration */
|
||||
const u32 inst_rom_init[] = {
|
||||
0x80000,
|
||||
0x80680,
|
||||
0x8180,
|
||||
0x8200,
|
||||
0x8280,
|
||||
0x8300,
|
||||
0x8380,
|
||||
0x8100,
|
||||
0x8480,
|
||||
0x8500,
|
||||
0x8580,
|
||||
0x8600,
|
||||
0x8400,
|
||||
0x800,
|
||||
0x8680,
|
||||
0x880,
|
||||
0xa680,
|
||||
0x80680,
|
||||
0x900,
|
||||
0x80680,
|
||||
0x980,
|
||||
0xa680,
|
||||
0x8680,
|
||||
0x80680,
|
||||
0xb68,
|
||||
0xcce8,
|
||||
0xae8,
|
||||
0x8ce8,
|
||||
0xb88,
|
||||
0xec88,
|
||||
0xa08,
|
||||
0xac88,
|
||||
0x80680,
|
||||
0xce00,
|
||||
0xcd80,
|
||||
0xe700,
|
||||
0xc00,
|
||||
0x20ce0,
|
||||
0x20ce0,
|
||||
0x20ce0,
|
||||
0x20ce0,
|
||||
0xd00,
|
||||
0x680,
|
||||
0x680,
|
||||
0x680,
|
||||
0x680,
|
||||
0x60e80,
|
||||
0x61080,
|
||||
0x61080,
|
||||
0x61080,
|
||||
0xa680,
|
||||
0x8680,
|
||||
0x80680,
|
||||
0xce00,
|
||||
0xcd80,
|
||||
0xe700,
|
||||
0xc00,
|
||||
0x30ce0,
|
||||
0x30ce0,
|
||||
0x30ce0,
|
||||
0x30ce0,
|
||||
0xd00,
|
||||
0x680,
|
||||
0x680,
|
||||
0x680,
|
||||
0x680,
|
||||
0x70e80,
|
||||
0x71080,
|
||||
0x71080,
|
||||
0x71080,
|
||||
0xa680,
|
||||
0x8680,
|
||||
0x80680,
|
||||
0x1158,
|
||||
0x6d8,
|
||||
0x80680,
|
||||
0x1168,
|
||||
0x7e8,
|
||||
0x7e8,
|
||||
0x87e8,
|
||||
0x40fe8,
|
||||
0x410e8,
|
||||
0x410e8,
|
||||
0x410e8,
|
||||
0x1168,
|
||||
0x7e8,
|
||||
0x7e8,
|
||||
0xa7e8,
|
||||
0x80680,
|
||||
0x40e88,
|
||||
0x41088,
|
||||
0x41088,
|
||||
0x41088,
|
||||
0x40f68,
|
||||
0x410e8,
|
||||
0x410e8,
|
||||
0x410e8,
|
||||
0xa680,
|
||||
0x40fe8,
|
||||
0x410e8,
|
||||
0x410e8,
|
||||
0x410e8,
|
||||
0x41008,
|
||||
0x41088,
|
||||
0x41088,
|
||||
0x41088,
|
||||
0x1100,
|
||||
0xc680,
|
||||
0x8680,
|
||||
0xe680,
|
||||
0x80680,
|
||||
0x0,
|
||||
0x8000,
|
||||
0xa000,
|
||||
0xc000,
|
||||
0x80000,
|
||||
0x80,
|
||||
0x8080,
|
||||
0xa080,
|
||||
0xc080,
|
||||
0x80080,
|
||||
0x9180,
|
||||
0x8680,
|
||||
0xa680,
|
||||
0x80680,
|
||||
0x40f08,
|
||||
0x80680
|
||||
};
|
||||
#endif /*#ifndef__SDRAM_CONFIG_H */
|
72
board/terasic/de0-nano-soc/socfpga.c
Normal file
72
board/terasic/de0-nano-soc/socfpga.c
Normal file
|
@ -0,0 +1,72 @@
|
|||
/*
|
||||
* Copyright (C) 2012 Altera Corporation <www.altera.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
|
||||
#include <micrel.h>
|
||||
#include <netdev.h>
|
||||
#include <phy.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
void s_init(void) {}
|
||||
|
||||
/*
|
||||
* Miscellaneous platform dependent initialisations
|
||||
*/
|
||||
int board_init(void)
|
||||
{
|
||||
/* Address of boot parameters for ATAG (if ATAG is used) */
|
||||
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* PHY configuration
|
||||
*/
|
||||
#ifdef CONFIG_PHY_MICREL_KSZ9031
|
||||
int board_phy_config(struct phy_device *phydev)
|
||||
{
|
||||
int ret;
|
||||
/*
|
||||
* These skew settings for the KSZ9021 ethernet phy is required for ethernet
|
||||
* to work reliably on most flavors of cyclone5 boards.
|
||||
*/
|
||||
ret = ksz9031_phy_extended_write(phydev, 0x2,
|
||||
MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
|
||||
MII_KSZ9031_MOD_DATA_NO_POST_INC,
|
||||
0x70);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = ksz9031_phy_extended_write(phydev, 0x2,
|
||||
MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
|
||||
MII_KSZ9031_MOD_DATA_NO_POST_INC,
|
||||
0x7777);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = ksz9031_phy_extended_write(phydev, 0x2,
|
||||
MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
|
||||
MII_KSZ9031_MOD_DATA_NO_POST_INC,
|
||||
0);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = ksz9031_phy_extended_write(phydev, 0x2,
|
||||
MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
|
||||
MII_KSZ9031_MOD_DATA_NO_POST_INC,
|
||||
0x03FC);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (phydev->drv->config)
|
||||
return phydev->drv->config(phydev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
5
board/terasic/sockit/MAINTAINERS
Normal file
5
board/terasic/sockit/MAINTAINERS
Normal file
|
@ -0,0 +1,5 @@
|
|||
SOCKIT BOARD
|
||||
M: Marek Vasut <marex@denx.de>
|
||||
S: Maintained
|
||||
F: include/configs/socfpga_sockit.h
|
||||
F: configs/socfpga_sockit_defconfig
|
9
board/terasic/sockit/Makefile
Normal file
9
board/terasic/sockit/Makefile
Normal file
|
@ -0,0 +1,9 @@
|
|||
#
|
||||
# (C) Copyright 2001-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y := socfpga.o
|
660
board/terasic/sockit/qts/iocsr_config.h
Normal file
660
board/terasic/sockit/qts/iocsr_config.h
Normal file
|
@ -0,0 +1,660 @@
|
|||
/*
|
||||
* Altera SoCFPGA IOCSR configuration
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef __SOCFPGA_IOCSR_CONFIG_H__
|
||||
#define __SOCFPGA_IOCSR_CONFIG_H__
|
||||
|
||||
#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764
|
||||
#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
|
||||
#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955
|
||||
#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
|
||||
|
||||
const unsigned long iocsr_scan_chain0_table[] = {
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x0FF00000,
|
||||
0xC0000000,
|
||||
0x0000003F,
|
||||
0x00008000,
|
||||
0x00060180,
|
||||
0x18060000,
|
||||
0x18000000,
|
||||
0x00018060,
|
||||
0x00000000,
|
||||
0x00004000,
|
||||
0x000300C0,
|
||||
0x0C030000,
|
||||
0x0C000000,
|
||||
0x00000030,
|
||||
0x0000C030,
|
||||
0x00002000,
|
||||
0x00018060,
|
||||
0x06018000,
|
||||
0x06000000,
|
||||
0x00000018,
|
||||
0x00006018,
|
||||
0x00001000,
|
||||
};
|
||||
|
||||
const unsigned long iocsr_scan_chain1_table[] = {
|
||||
0x00100000,
|
||||
0x300C0000,
|
||||
0x300000C0,
|
||||
0x000000C0,
|
||||
0x000300C0,
|
||||
0x00008000,
|
||||
0x00080000,
|
||||
0x20000000,
|
||||
0x00000000,
|
||||
0x00000080,
|
||||
0x00020000,
|
||||
0x00004000,
|
||||
0x000300C0,
|
||||
0x10000000,
|
||||
0x0C000000,
|
||||
0x00000030,
|
||||
0x0000C030,
|
||||
0x00002000,
|
||||
0x06018060,
|
||||
0x06018000,
|
||||
0x01FE0000,
|
||||
0xF8000000,
|
||||
0x00000007,
|
||||
0x00001000,
|
||||
0x0000C030,
|
||||
0x0300C000,
|
||||
0x03000000,
|
||||
0x0000300C,
|
||||
0x0000300C,
|
||||
0x00000800,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x01800000,
|
||||
0x00000006,
|
||||
0x00002000,
|
||||
0x00000400,
|
||||
0x00000000,
|
||||
0x00C03000,
|
||||
0x00000003,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000200,
|
||||
0x00601806,
|
||||
0x00000000,
|
||||
0x80600000,
|
||||
0x80000601,
|
||||
0x00000601,
|
||||
0x00000100,
|
||||
0x00300C03,
|
||||
0xC0300C00,
|
||||
0xC0300000,
|
||||
0xC0000300,
|
||||
0x000C0300,
|
||||
0x00000080,
|
||||
};
|
||||
|
||||
const unsigned long iocsr_scan_chain2_table[] = {
|
||||
0x300C0300,
|
||||
0x00000000,
|
||||
0x0FF00000,
|
||||
0x00000000,
|
||||
0x0C0300C0,
|
||||
0x00008000,
|
||||
0x18060180,
|
||||
0x18060000,
|
||||
0x18000000,
|
||||
0x00018060,
|
||||
0x00018060,
|
||||
0x00004000,
|
||||
0x000300C0,
|
||||
0x0C030000,
|
||||
0x00000030,
|
||||
0x00000000,
|
||||
0x0300C030,
|
||||
0x00002000,
|
||||
0x00018060,
|
||||
0x06018000,
|
||||
0x06000000,
|
||||
0x00000018,
|
||||
0x00006018,
|
||||
0x00001000,
|
||||
0x0000C030,
|
||||
0x00000000,
|
||||
0x03000000,
|
||||
0x0000000C,
|
||||
0x00C0300C,
|
||||
0x00000800,
|
||||
};
|
||||
|
||||
const unsigned long iocsr_scan_chain3_table[] = {
|
||||
0x0C420D80,
|
||||
0x082000FF,
|
||||
0x0A804001,
|
||||
0x07900000,
|
||||
0x08020000,
|
||||
0x00100000,
|
||||
0x0A800000,
|
||||
0x07900000,
|
||||
0x08020000,
|
||||
0x00100000,
|
||||
0xC8800000,
|
||||
0x00003001,
|
||||
0x00C00722,
|
||||
0x00000000,
|
||||
0x00000021,
|
||||
0x82000004,
|
||||
0x05400000,
|
||||
0x03C80000,
|
||||
0x04010000,
|
||||
0x00080000,
|
||||
0x05400000,
|
||||
0x03C80000,
|
||||
0x05400000,
|
||||
0x03C80000,
|
||||
0xE4400000,
|
||||
0x00001800,
|
||||
0x00600391,
|
||||
0x800E4400,
|
||||
0x00000001,
|
||||
0x40000002,
|
||||
0x02A00000,
|
||||
0x01E40000,
|
||||
0x02A00000,
|
||||
0x01E40000,
|
||||
0x02A00000,
|
||||
0x01E40000,
|
||||
0x02A00000,
|
||||
0x01E40000,
|
||||
0x72200000,
|
||||
0x80000C00,
|
||||
0x003001C8,
|
||||
0xC0072200,
|
||||
0x1C880000,
|
||||
0x20000300,
|
||||
0x00040000,
|
||||
0x50670000,
|
||||
0x00000010,
|
||||
0x24590000,
|
||||
0x00001000,
|
||||
0xA0000034,
|
||||
0x0D000001,
|
||||
0x40680208,
|
||||
0x41034051,
|
||||
0x12481A00,
|
||||
0x802080D0,
|
||||
0x34051406,
|
||||
0x01A02490,
|
||||
0x080D0000,
|
||||
0x51406802,
|
||||
0x02490340,
|
||||
0xD000001A,
|
||||
0x0680A280,
|
||||
0x10040000,
|
||||
0x00200000,
|
||||
0x10040000,
|
||||
0x00200000,
|
||||
0x15000000,
|
||||
0x0F200000,
|
||||
0x15000000,
|
||||
0x0F200000,
|
||||
0x01FE0000,
|
||||
0x00000000,
|
||||
0x01800E44,
|
||||
0x00391000,
|
||||
0x007F8006,
|
||||
0x00000000,
|
||||
0x0A800001,
|
||||
0x07900000,
|
||||
0x0A800000,
|
||||
0x07900000,
|
||||
0x0A800000,
|
||||
0x07900000,
|
||||
0x08020000,
|
||||
0x00100000,
|
||||
0xC8800000,
|
||||
0x00003001,
|
||||
0x00C00722,
|
||||
0x00000FF0,
|
||||
0x72200000,
|
||||
0x80000C00,
|
||||
0x05400000,
|
||||
0x02480000,
|
||||
0x04000000,
|
||||
0x00080000,
|
||||
0x05400000,
|
||||
0x03C80000,
|
||||
0x05400000,
|
||||
0x03C80000,
|
||||
0x6A1C0000,
|
||||
0x00001800,
|
||||
0x00600391,
|
||||
0x800E4400,
|
||||
0x1A870001,
|
||||
0x40000600,
|
||||
0x02A00040,
|
||||
0x01E40000,
|
||||
0x02A00000,
|
||||
0x01E40000,
|
||||
0x02A00000,
|
||||
0x01E40000,
|
||||
0x02A00000,
|
||||
0x01E40000,
|
||||
0x72200000,
|
||||
0x80000C00,
|
||||
0x003001C8,
|
||||
0xC0072200,
|
||||
0x1C880000,
|
||||
0x20000300,
|
||||
0x00040000,
|
||||
0x50670000,
|
||||
0x00000010,
|
||||
0x24590000,
|
||||
0x00001000,
|
||||
0xA0000034,
|
||||
0x0D000001,
|
||||
0x40680208,
|
||||
0x49034051,
|
||||
0x12481A02,
|
||||
0x80A280D0,
|
||||
0x34030C06,
|
||||
0x01A00040,
|
||||
0x280D0002,
|
||||
0x5140680A,
|
||||
0x02490340,
|
||||
0xD012481A,
|
||||
0x0680A280,
|
||||
0x10040000,
|
||||
0x00200000,
|
||||
0x10040000,
|
||||
0x00200000,
|
||||
0x15000000,
|
||||
0x0F200000,
|
||||
0x15000000,
|
||||
0x0F200000,
|
||||
0x01FE0000,
|
||||
0x00000000,
|
||||
0x01800E44,
|
||||
0x00391000,
|
||||
0x007F8006,
|
||||
0x00000000,
|
||||
0x99300001,
|
||||
0x34343400,
|
||||
0xAA0D4000,
|
||||
0x01C3A800,
|
||||
0xAA0D4000,
|
||||
0x01C3A800,
|
||||
0xAA0D4000,
|
||||
0x01C3A800,
|
||||
0x00040100,
|
||||
0x00000800,
|
||||
0x00000000,
|
||||
0x00001208,
|
||||
0x00482000,
|
||||
0x01000000,
|
||||
0x00000000,
|
||||
0x00410482,
|
||||
0x0006A000,
|
||||
0x0001B400,
|
||||
0x00020000,
|
||||
0x00000400,
|
||||
0x0002A000,
|
||||
0x0001E400,
|
||||
0x5506A000,
|
||||
0x00E1D400,
|
||||
0x00000000,
|
||||
0xC880090C,
|
||||
0x00003001,
|
||||
0x90400000,
|
||||
0x00000000,
|
||||
0x2020C243,
|
||||
0x2A835000,
|
||||
0x0070EA00,
|
||||
0x2A835000,
|
||||
0x0070EA00,
|
||||
0x2A835000,
|
||||
0x0070EA00,
|
||||
0x00010040,
|
||||
0x00000200,
|
||||
0x00000000,
|
||||
0x00000482,
|
||||
0x00120800,
|
||||
0x00002000,
|
||||
0x80000000,
|
||||
0x00104120,
|
||||
0x00000200,
|
||||
0xAC0D5F80,
|
||||
0xFFFFFFFF,
|
||||
0x14F3690D,
|
||||
0x1A041414,
|
||||
0x00D00000,
|
||||
0x04864000,
|
||||
0x59647A01,
|
||||
0xD32CA3DE,
|
||||
0xF551451E,
|
||||
0x034CD348,
|
||||
0x821A0000,
|
||||
0x0000D000,
|
||||
0x05140680,
|
||||
0xD669A47A,
|
||||
0x1ED32CA3,
|
||||
0x48F55E79,
|
||||
0x00034C92,
|
||||
0x00080200,
|
||||
0x00001000,
|
||||
0x00080200,
|
||||
0x00001000,
|
||||
0x000A8000,
|
||||
0x00075000,
|
||||
0x541A8000,
|
||||
0x03875001,
|
||||
0x10000000,
|
||||
0x00000000,
|
||||
0x0080C000,
|
||||
0x41000000,
|
||||
0x00003FC2,
|
||||
0x00820000,
|
||||
0xAA0D4000,
|
||||
0x01C3A800,
|
||||
0xAA0D4000,
|
||||
0x01C3A800,
|
||||
0xAA0D4000,
|
||||
0x01C3A800,
|
||||
0x00040100,
|
||||
0x00000800,
|
||||
0x00000000,
|
||||
0x00001208,
|
||||
0x00482000,
|
||||
0x00008000,
|
||||
0x00000000,
|
||||
0x00410482,
|
||||
0x0006A000,
|
||||
0x0001B400,
|
||||
0x00020000,
|
||||
0x00000400,
|
||||
0x00020080,
|
||||
0x00000400,
|
||||
0x5506A000,
|
||||
0x00E1D400,
|
||||
0x00000000,
|
||||
0x0000090C,
|
||||
0x00000010,
|
||||
0x90400000,
|
||||
0x00000000,
|
||||
0x2020C243,
|
||||
0x2A835000,
|
||||
0x0070EA00,
|
||||
0x2A835000,
|
||||
0x0070EA00,
|
||||
0x2A835000,
|
||||
0x0070EA00,
|
||||
0x00015000,
|
||||
0x0000F200,
|
||||
0x00000000,
|
||||
0x00000482,
|
||||
0x00120800,
|
||||
0x00600391,
|
||||
0x80000000,
|
||||
0x00104120,
|
||||
0x00000200,
|
||||
0xAC0D5F80,
|
||||
0xFFFFFFFF,
|
||||
0x14F3690D,
|
||||
0x1A041414,
|
||||
0x00D00000,
|
||||
0x14864000,
|
||||
0x59647A05,
|
||||
0x9228A3DE,
|
||||
0xF65E791E,
|
||||
0x034CD348,
|
||||
0x821A0186,
|
||||
0x0000D000,
|
||||
0x00000680,
|
||||
0xD669A47A,
|
||||
0x1E9228A3,
|
||||
0x48F65E79,
|
||||
0x00034CD3,
|
||||
0x00080200,
|
||||
0x00001000,
|
||||
0x00080200,
|
||||
0x00001000,
|
||||
0x000A8000,
|
||||
0x00075000,
|
||||
0x541A8000,
|
||||
0x03875001,
|
||||
0x10000000,
|
||||
0x00000000,
|
||||
0x0080C000,
|
||||
0x41000000,
|
||||
0x04000002,
|
||||
0x00820000,
|
||||
0xAA0D4000,
|
||||
0x01C3A800,
|
||||
0xAA0D4000,
|
||||
0x01C3A800,
|
||||
0xAA0D4000,
|
||||
0x01C3A800,
|
||||
0x00040100,
|
||||
0x00000800,
|
||||
0x00000000,
|
||||
0x00001208,
|
||||
0x00482000,
|
||||
0x00008000,
|
||||
0x00000000,
|
||||
0x00410482,
|
||||
0x0006A000,
|
||||
0x0001B400,
|
||||
0x00020000,
|
||||
0x00000400,
|
||||
0x0002A000,
|
||||
0x0001E400,
|
||||
0x5506A000,
|
||||
0x00E1D400,
|
||||
0x00000000,
|
||||
0xC880090C,
|
||||
0x00003001,
|
||||
0x90400000,
|
||||
0x00000000,
|
||||
0x2020C243,
|
||||
0x2A835000,
|
||||
0x0070EA00,
|
||||
0x2A835000,
|
||||
0x0070EA00,
|
||||
0x2A835000,
|
||||
0x0070EA00,
|
||||
0x00010040,
|
||||
0x00000200,
|
||||
0x00000000,
|
||||
0x00000482,
|
||||
0x00120800,
|
||||
0x00002000,
|
||||
0x80000000,
|
||||
0x00104120,
|
||||
0x00000200,
|
||||
0xAC0D5F80,
|
||||
0xFFFFFFFF,
|
||||
0x14F3690D,
|
||||
0x1A041414,
|
||||
0x00D00000,
|
||||
0x0C864000,
|
||||
0x79E47A03,
|
||||
0xB2AAA3D1,
|
||||
0xF551451E,
|
||||
0x035CD348,
|
||||
0x821A0000,
|
||||
0x0000D000,
|
||||
0x00000680,
|
||||
0xD159647A,
|
||||
0x1ED32CA3,
|
||||
0x48F55145,
|
||||
0x00035CD3,
|
||||
0x00080200,
|
||||
0x00001000,
|
||||
0x00080200,
|
||||
0x00001000,
|
||||
0x000A8000,
|
||||
0x00075000,
|
||||
0x541A8000,
|
||||
0x03875001,
|
||||
0x10000000,
|
||||
0x00000000,
|
||||
0x0080C000,
|
||||
0x41000000,
|
||||
0x04000002,
|
||||
0x00820000,
|
||||
0xAA0D4000,
|
||||
0x01C3A800,
|
||||
0xAA0D4000,
|
||||
0x01C3A800,
|
||||
0xAA0D4000,
|
||||
0x01C3A800,
|
||||
0x00040100,
|
||||
0x00000800,
|
||||
0x00000000,
|
||||
0x00001208,
|
||||
0x00482000,
|
||||
0x00008000,
|
||||
0x00000000,
|
||||
0x00410482,
|
||||
0x0006A000,
|
||||
0x0001B400,
|
||||
0x00020000,
|
||||
0x00000400,
|
||||
0x00020080,
|
||||
0x00000400,
|
||||
0x5506A000,
|
||||
0x00E1D400,
|
||||
0x00000000,
|
||||
0x0000090C,
|
||||
0x00000010,
|
||||
0x90400000,
|
||||
0x00000000,
|
||||
0x2020C243,
|
||||
0x2A835000,
|
||||
0x0070EA00,
|
||||
0x2A835000,
|
||||
0x0070EA00,
|
||||
0x2A835000,
|
||||
0x0070EA00,
|
||||
0x00010040,
|
||||
0x00000200,
|
||||
0x00000000,
|
||||
0x00000482,
|
||||
0x00120800,
|
||||
0x00400000,
|
||||
0x80000000,
|
||||
0x00104120,
|
||||
0x00000200,
|
||||
0xAC0D5F80,
|
||||
0xFFFFFFFF,
|
||||
0x14F1690D,
|
||||
0x1A041414,
|
||||
0x00D00000,
|
||||
0x04864000,
|
||||
0x69A47A01,
|
||||
0x9228A3D6,
|
||||
0xF65E791E,
|
||||
0x034C9248,
|
||||
0x821A0000,
|
||||
0x0000D000,
|
||||
0x00000680,
|
||||
0xDE59647A,
|
||||
0x1ED32CA3,
|
||||
0x48F55E79,
|
||||
0x00034CD3,
|
||||
0x00080200,
|
||||
0x00001000,
|
||||
0x00080200,
|
||||
0x00001000,
|
||||
0x000A8000,
|
||||
0x00075000,
|
||||
0x541A8000,
|
||||
0x03875001,
|
||||
0x10000000,
|
||||
0x00000000,
|
||||
0x0080C000,
|
||||
0x41000000,
|
||||
0x04000002,
|
||||
0x00820000,
|
||||
0x00489800,
|
||||
0x801A1A1A,
|
||||
0x00000200,
|
||||
0x80000004,
|
||||
0x00000200,
|
||||
0x80000004,
|
||||
0x00000200,
|
||||
0x80000004,
|
||||
0x00000200,
|
||||
0x00000004,
|
||||
0x00040000,
|
||||
0x10000000,
|
||||
0x00000000,
|
||||
0x00000040,
|
||||
0x00010000,
|
||||
0x40002000,
|
||||
0x00000100,
|
||||
0x40000002,
|
||||
0x00000100,
|
||||
0x40000002,
|
||||
0x00000100,
|
||||
0x40000002,
|
||||
0x00000100,
|
||||
0x00000002,
|
||||
0x00020000,
|
||||
0x08000000,
|
||||
0x00000000,
|
||||
0x00000020,
|
||||
0x00008000,
|
||||
0x20001000,
|
||||
0x00000080,
|
||||
0x20000001,
|
||||
0x00000080,
|
||||
0x20000001,
|
||||
0x00000080,
|
||||
0x20000001,
|
||||
0x00000080,
|
||||
0x00000001,
|
||||
0x00010000,
|
||||
0x04000000,
|
||||
0x00FF0000,
|
||||
0x00000000,
|
||||
0x00004000,
|
||||
0x00000800,
|
||||
0xC0000001,
|
||||
0x00041419,
|
||||
0x40000000,
|
||||
0x04000816,
|
||||
0x000D0000,
|
||||
0x00006800,
|
||||
0x00000340,
|
||||
0xD000001A,
|
||||
0x06800000,
|
||||
0x00340000,
|
||||
0x0001A000,
|
||||
0x00000D00,
|
||||
0x40000068,
|
||||
0x1A000003,
|
||||
0x00D00000,
|
||||
0x00068000,
|
||||
0x00003400,
|
||||
0x000001A0,
|
||||
0x00000401,
|
||||
0x00000008,
|
||||
0x00000401,
|
||||
0x00000008,
|
||||
0x00000401,
|
||||
0x00000008,
|
||||
0x00000401,
|
||||
0x80000008,
|
||||
0x0000007F,
|
||||
0x20000000,
|
||||
0x00000000,
|
||||
0xE0000080,
|
||||
0x0000001F,
|
||||
0x00004000,
|
||||
};
|
||||
|
||||
|
||||
#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */
|
219
board/terasic/sockit/qts/pinmux_config.h
Normal file
219
board/terasic/sockit/qts/pinmux_config.h
Normal file
|
@ -0,0 +1,219 @@
|
|||
/*
|
||||
* Altera SoCFPGA PinMux configuration
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef __SOCFPGA_PINMUX_CONFIG_H__
|
||||
#define __SOCFPGA_PINMUX_CONFIG_H__
|
||||
|
||||
const u8 sys_mgr_init_table[] = {
|
||||
0, /* EMACIO0 */
|
||||
2, /* EMACIO1 */
|
||||
2, /* EMACIO2 */
|
||||
2, /* EMACIO3 */
|
||||
2, /* EMACIO4 */
|
||||
2, /* EMACIO5 */
|
||||
2, /* EMACIO6 */
|
||||
2, /* EMACIO7 */
|
||||
2, /* EMACIO8 */
|
||||
0, /* EMACIO9 */
|
||||
2, /* EMACIO10 */
|
||||
2, /* EMACIO11 */
|
||||
2, /* EMACIO12 */
|
||||
2, /* EMACIO13 */
|
||||
0, /* EMACIO14 */
|
||||
0, /* EMACIO15 */
|
||||
0, /* EMACIO16 */
|
||||
0, /* EMACIO17 */
|
||||
0, /* EMACIO18 */
|
||||
0, /* EMACIO19 */
|
||||
3, /* FLASHIO0 */
|
||||
0, /* FLASHIO1 */
|
||||
3, /* FLASHIO2 */
|
||||
3, /* FLASHIO3 */
|
||||
0, /* FLASHIO4 */
|
||||
0, /* FLASHIO5 */
|
||||
0, /* FLASHIO6 */
|
||||
0, /* FLASHIO7 */
|
||||
0, /* FLASHIO8 */
|
||||
3, /* FLASHIO9 */
|
||||
3, /* FLASHIO10 */
|
||||
3, /* FLASHIO11 */
|
||||
0, /* GENERALIO0 */
|
||||
1, /* GENERALIO1 */
|
||||
1, /* GENERALIO2 */
|
||||
1, /* GENERALIO3 */
|
||||
1, /* GENERALIO4 */
|
||||
0, /* GENERALIO5 */
|
||||
0, /* GENERALIO6 */
|
||||
0, /* GENERALIO7 */
|
||||
0, /* GENERALIO8 */
|
||||
3, /* GENERALIO9 */
|
||||
3, /* GENERALIO10 */
|
||||
3, /* GENERALIO11 */
|
||||
3, /* GENERALIO12 */
|
||||
0, /* GENERALIO13 */
|
||||
0, /* GENERALIO14 */
|
||||
1, /* GENERALIO15 */
|
||||
1, /* GENERALIO16 */
|
||||
1, /* GENERALIO17 */
|
||||
1, /* GENERALIO18 */
|
||||
0, /* GENERALIO19 */
|
||||
0, /* GENERALIO20 */
|
||||
0, /* GENERALIO21 */
|
||||
0, /* GENERALIO22 */
|
||||
0, /* GENERALIO23 */
|
||||
0, /* GENERALIO24 */
|
||||
0, /* GENERALIO25 */
|
||||
0, /* GENERALIO26 */
|
||||
0, /* GENERALIO27 */
|
||||
0, /* GENERALIO28 */
|
||||
0, /* GENERALIO29 */
|
||||
0, /* GENERALIO30 */
|
||||
0, /* GENERALIO31 */
|
||||
2, /* MIXED1IO0 */
|
||||
2, /* MIXED1IO1 */
|
||||
2, /* MIXED1IO2 */
|
||||
2, /* MIXED1IO3 */
|
||||
2, /* MIXED1IO4 */
|
||||
2, /* MIXED1IO5 */
|
||||
2, /* MIXED1IO6 */
|
||||
2, /* MIXED1IO7 */
|
||||
2, /* MIXED1IO8 */
|
||||
2, /* MIXED1IO9 */
|
||||
2, /* MIXED1IO10 */
|
||||
2, /* MIXED1IO11 */
|
||||
2, /* MIXED1IO12 */
|
||||
2, /* MIXED1IO13 */
|
||||
0, /* MIXED1IO14 */
|
||||
3, /* MIXED1IO15 */
|
||||
3, /* MIXED1IO16 */
|
||||
3, /* MIXED1IO17 */
|
||||
3, /* MIXED1IO18 */
|
||||
3, /* MIXED1IO19 */
|
||||
3, /* MIXED1IO20 */
|
||||
0, /* MIXED1IO21 */
|
||||
0, /* MIXED2IO0 */
|
||||
0, /* MIXED2IO1 */
|
||||
0, /* MIXED2IO2 */
|
||||
0, /* MIXED2IO3 */
|
||||
0, /* MIXED2IO4 */
|
||||
0, /* MIXED2IO5 */
|
||||
0, /* MIXED2IO6 */
|
||||
0, /* MIXED2IO7 */
|
||||
0, /* GPLINMUX48 */
|
||||
0, /* GPLINMUX49 */
|
||||
0, /* GPLINMUX50 */
|
||||
0, /* GPLINMUX51 */
|
||||
0, /* GPLINMUX52 */
|
||||
0, /* GPLINMUX53 */
|
||||
0, /* GPLINMUX54 */
|
||||
0, /* GPLINMUX55 */
|
||||
0, /* GPLINMUX56 */
|
||||
0, /* GPLINMUX57 */
|
||||
0, /* GPLINMUX58 */
|
||||
0, /* GPLINMUX59 */
|
||||
0, /* GPLINMUX60 */
|
||||
0, /* GPLINMUX61 */
|
||||
0, /* GPLINMUX62 */
|
||||
0, /* GPLINMUX63 */
|
||||
0, /* GPLINMUX64 */
|
||||
0, /* GPLINMUX65 */
|
||||
0, /* GPLINMUX66 */
|
||||
0, /* GPLINMUX67 */
|
||||
0, /* GPLINMUX68 */
|
||||
0, /* GPLINMUX69 */
|
||||
0, /* GPLINMUX70 */
|
||||
1, /* GPLMUX0 */
|
||||
1, /* GPLMUX1 */
|
||||
1, /* GPLMUX2 */
|
||||
1, /* GPLMUX3 */
|
||||
1, /* GPLMUX4 */
|
||||
1, /* GPLMUX5 */
|
||||
1, /* GPLMUX6 */
|
||||
1, /* GPLMUX7 */
|
||||
1, /* GPLMUX8 */
|
||||
1, /* GPLMUX9 */
|
||||
1, /* GPLMUX10 */
|
||||
1, /* GPLMUX11 */
|
||||
1, /* GPLMUX12 */
|
||||
1, /* GPLMUX13 */
|
||||
1, /* GPLMUX14 */
|
||||
1, /* GPLMUX15 */
|
||||
1, /* GPLMUX16 */
|
||||
1, /* GPLMUX17 */
|
||||
1, /* GPLMUX18 */
|
||||
1, /* GPLMUX19 */
|
||||
1, /* GPLMUX20 */
|
||||
1, /* GPLMUX21 */
|
||||
1, /* GPLMUX22 */
|
||||
1, /* GPLMUX23 */
|
||||
1, /* GPLMUX24 */
|
||||
1, /* GPLMUX25 */
|
||||
1, /* GPLMUX26 */
|
||||
1, /* GPLMUX27 */
|
||||
1, /* GPLMUX28 */
|
||||
1, /* GPLMUX29 */
|
||||
1, /* GPLMUX30 */
|
||||
1, /* GPLMUX31 */
|
||||
1, /* GPLMUX32 */
|
||||
1, /* GPLMUX33 */
|
||||
1, /* GPLMUX34 */
|
||||
1, /* GPLMUX35 */
|
||||
1, /* GPLMUX36 */
|
||||
1, /* GPLMUX37 */
|
||||
1, /* GPLMUX38 */
|
||||
1, /* GPLMUX39 */
|
||||
1, /* GPLMUX40 */
|
||||
1, /* GPLMUX41 */
|
||||
1, /* GPLMUX42 */
|
||||
1, /* GPLMUX43 */
|
||||
1, /* GPLMUX44 */
|
||||
1, /* GPLMUX45 */
|
||||
1, /* GPLMUX46 */
|
||||
1, /* GPLMUX47 */
|
||||
1, /* GPLMUX48 */
|
||||
1, /* GPLMUX49 */
|
||||
1, /* GPLMUX50 */
|
||||
1, /* GPLMUX51 */
|
||||
1, /* GPLMUX52 */
|
||||
1, /* GPLMUX53 */
|
||||
1, /* GPLMUX54 */
|
||||
1, /* GPLMUX55 */
|
||||
1, /* GPLMUX56 */
|
||||
1, /* GPLMUX57 */
|
||||
1, /* GPLMUX58 */
|
||||
1, /* GPLMUX59 */
|
||||
1, /* GPLMUX60 */
|
||||
1, /* GPLMUX61 */
|
||||
1, /* GPLMUX62 */
|
||||
1, /* GPLMUX63 */
|
||||
1, /* GPLMUX64 */
|
||||
1, /* GPLMUX65 */
|
||||
1, /* GPLMUX66 */
|
||||
1, /* GPLMUX67 */
|
||||
1, /* GPLMUX68 */
|
||||
1, /* GPLMUX69 */
|
||||
1, /* GPLMUX70 */
|
||||
0, /* NANDUSEFPGA */
|
||||
0, /* UART0USEFPGA */
|
||||
0, /* RGMII1USEFPGA */
|
||||
0, /* SPIS0USEFPGA */
|
||||
0, /* CAN0USEFPGA */
|
||||
0, /* I2C0USEFPGA */
|
||||
0, /* SDMMCUSEFPGA */
|
||||
0, /* QSPIUSEFPGA */
|
||||
0, /* SPIS1USEFPGA */
|
||||
0, /* RGMII0USEFPGA */
|
||||
0, /* UART1USEFPGA */
|
||||
0, /* CAN1USEFPGA */
|
||||
0, /* USB1USEFPGA */
|
||||
0, /* I2C3USEFPGA */
|
||||
0, /* I2C2USEFPGA */
|
||||
0, /* I2C1USEFPGA */
|
||||
0, /* SPIM1USEFPGA */
|
||||
0, /* USB0USEFPGA */
|
||||
0 /* SPIM0USEFPGA */
|
||||
};
|
||||
#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */
|
85
board/terasic/sockit/qts/pll_config.h
Normal file
85
board/terasic/sockit/qts/pll_config.h
Normal file
|
@ -0,0 +1,85 @@
|
|||
/*
|
||||
* Altera SoCFPGA Clock and PLL configuration
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef __SOCFPGA_PLL_CONFIG_H__
|
||||
#define __SOCFPGA_PLL_CONFIG_H__
|
||||
|
||||
#define CONFIG_HPS_DBCTRL_STAYOSC1 1
|
||||
|
||||
#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
|
||||
#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 73
|
||||
#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
|
||||
#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
|
||||
#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 14
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
|
||||
#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
|
||||
#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
|
||||
#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
|
||||
#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
|
||||
#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
|
||||
|
||||
#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
|
||||
#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
|
||||
#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
|
||||
#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
|
||||
#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
|
||||
#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
|
||||
#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
|
||||
#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
|
||||
#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
|
||||
#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
|
||||
#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
|
||||
#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4
|
||||
#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
|
||||
#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
|
||||
#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
|
||||
#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
|
||||
#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
|
||||
|
||||
#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
|
||||
#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
|
||||
#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
|
||||
#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
|
||||
#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
|
||||
#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
|
||||
#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
|
||||
#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
|
||||
#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
|
||||
#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
|
||||
#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
|
||||
|
||||
#define CONFIG_HPS_CLK_OSC1_HZ 25000000
|
||||
#define CONFIG_HPS_CLK_OSC2_HZ 25000000
|
||||
#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
|
||||
#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
|
||||
#define CONFIG_HPS_CLK_MAINVCO_HZ 1850000000
|
||||
#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
|
||||
#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
|
||||
#define CONFIG_HPS_CLK_EMAC0_HZ 1953125
|
||||
#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
|
||||
#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
|
||||
#define CONFIG_HPS_CLK_NAND_HZ 50000000
|
||||
#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
|
||||
#define CONFIG_HPS_CLK_QSPI_HZ 370000000
|
||||
#define CONFIG_HPS_CLK_SPIM_HZ 200000000
|
||||
#define CONFIG_HPS_CLK_CAN0_HZ 12500000
|
||||
#define CONFIG_HPS_CLK_CAN1_HZ 12500000
|
||||
#define CONFIG_HPS_CLK_GPIODB_HZ 32000
|
||||
#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
|
||||
#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
|
||||
|
||||
#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
|
||||
#define CONFIG_HPS_ALTERAGRP_MAINCLK 4
|
||||
#define CONFIG_HPS_ALTERAGRP_DBGATCLK 4
|
||||
|
||||
|
||||
#endif /* __SOCFPGA_PLL_CONFIG_H__ */
|
341
board/terasic/sockit/qts/sdram_config.h
Normal file
341
board/terasic/sockit/qts/sdram_config.h
Normal file
|
@ -0,0 +1,341 @@
|
|||
/*
|
||||
* Altera SoCFPGA SDRAM configuration
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef __SOCFPGA_SDRAM_CONFIG_H__
|
||||
#define __SOCFPGA_SDRAM_CONFIG_H__
|
||||
|
||||
/* SDRAM configuration */
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 12
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x1FF
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
|
||||
|
||||
/* Sequencer auto configuration */
|
||||
#define RW_MGR_ACTIVATE_0_AND_1 0x0D
|
||||
#define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E
|
||||
#define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10
|
||||
#define RW_MGR_ACTIVATE_1 0x0F
|
||||
#define RW_MGR_CLEAR_DQS_ENABLE 0x49
|
||||
#define RW_MGR_GUARANTEED_READ 0x4C
|
||||
#define RW_MGR_GUARANTEED_READ_CONT 0x54
|
||||
#define RW_MGR_GUARANTEED_WRITE 0x18
|
||||
#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1B
|
||||
#define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1F
|
||||
#define RW_MGR_GUARANTEED_WRITE_WAIT2 0x19
|
||||
#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1D
|
||||
#define RW_MGR_IDLE 0x00
|
||||
#define RW_MGR_IDLE_LOOP1 0x7B
|
||||
#define RW_MGR_IDLE_LOOP2 0x7A
|
||||
#define RW_MGR_INIT_RESET_0_CKE_0 0x6F
|
||||
#define RW_MGR_INIT_RESET_1_CKE_0 0x74
|
||||
#define RW_MGR_LFSR_WR_RD_BANK_0 0x22
|
||||
#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x25
|
||||
#define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x24
|
||||
#define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x23
|
||||
#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x32
|
||||
#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x21
|
||||
#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x36
|
||||
#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x39
|
||||
#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x38
|
||||
#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x37
|
||||
#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x46
|
||||
#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x35
|
||||
#define RW_MGR_MRS0_DLL_RESET 0x02
|
||||
#define RW_MGR_MRS0_DLL_RESET_MIRR 0x08
|
||||
#define RW_MGR_MRS0_USER 0x07
|
||||
#define RW_MGR_MRS0_USER_MIRR 0x0C
|
||||
#define RW_MGR_MRS1 0x03
|
||||
#define RW_MGR_MRS1_MIRR 0x09
|
||||
#define RW_MGR_MRS2 0x04
|
||||
#define RW_MGR_MRS2_MIRR 0x0A
|
||||
#define RW_MGR_MRS3 0x05
|
||||
#define RW_MGR_MRS3_MIRR 0x0B
|
||||
#define RW_MGR_PRECHARGE_ALL 0x12
|
||||
#define RW_MGR_READ_B2B 0x59
|
||||
#define RW_MGR_READ_B2B_WAIT1 0x61
|
||||
#define RW_MGR_READ_B2B_WAIT2 0x6B
|
||||
#define RW_MGR_REFRESH_ALL 0x14
|
||||
#define RW_MGR_RETURN 0x01
|
||||
#define RW_MGR_SGLE_READ 0x7D
|
||||
#define RW_MGR_ZQCL 0x06
|
||||
|
||||
/* Sequencer defines configuration */
|
||||
#define AFI_RATE_RATIO 1
|
||||
#define CALIB_LFIFO_OFFSET 8
|
||||
#define CALIB_VFIFO_OFFSET 6
|
||||
#define ENABLE_SUPER_QUICK_CALIBRATION 0
|
||||
#define IO_DELAY_PER_DCHAIN_TAP 25
|
||||
#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25
|
||||
#define IO_DELAY_PER_OPA_TAP 312
|
||||
#define IO_DLL_CHAIN_LENGTH 8
|
||||
#define IO_DQDQS_OUT_PHASE_MAX 0
|
||||
#define IO_DQS_EN_DELAY_MAX 31
|
||||
#define IO_DQS_EN_DELAY_OFFSET 0
|
||||
#define IO_DQS_EN_PHASE_MAX 7
|
||||
#define IO_DQS_IN_DELAY_MAX 31
|
||||
#define IO_DQS_IN_RESERVE 4
|
||||
#define IO_DQS_OUT_RESERVE 4
|
||||
#define IO_IO_IN_DELAY_MAX 31
|
||||
#define IO_IO_OUT1_DELAY_MAX 31
|
||||
#define IO_IO_OUT2_DELAY_MAX 0
|
||||
#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0
|
||||
#define MAX_LATENCY_COUNT_WIDTH 5
|
||||
#define READ_VALID_FIFO_SIZE 16
|
||||
#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048d
|
||||
#define RW_MGR_MEM_ADDRESS_MIRRORING 0
|
||||
#define RW_MGR_MEM_DATA_MASK_WIDTH 4
|
||||
#define RW_MGR_MEM_DATA_WIDTH 32
|
||||
#define RW_MGR_MEM_DQ_PER_READ_DQS 8
|
||||
#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8
|
||||
#define RW_MGR_MEM_IF_READ_DQS_WIDTH 4
|
||||
#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 4
|
||||
#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1
|
||||
#define RW_MGR_MEM_NUMBER_OF_RANKS 1
|
||||
#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1
|
||||
#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1
|
||||
#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 4
|
||||
#define TINIT_CNTR0_VAL 99
|
||||
#define TINIT_CNTR1_VAL 32
|
||||
#define TINIT_CNTR2_VAL 32
|
||||
#define TRESET_CNTR0_VAL 99
|
||||
#define TRESET_CNTR1_VAL 99
|
||||
#define TRESET_CNTR2_VAL 10
|
||||
|
||||
/* Sequencer ac_rom_init configuration */
|
||||
const u32 ac_rom_init[] = {
|
||||
0x20700000,
|
||||
0x20780000,
|
||||
0x10080431,
|
||||
0x10080530,
|
||||
0x10090044,
|
||||
0x100a0008,
|
||||
0x100b0000,
|
||||
0x10380400,
|
||||
0x10080449,
|
||||
0x100804c8,
|
||||
0x100a0024,
|
||||
0x10090010,
|
||||
0x100b0000,
|
||||
0x30780000,
|
||||
0x38780000,
|
||||
0x30780000,
|
||||
0x10680000,
|
||||
0x106b0000,
|
||||
0x10280400,
|
||||
0x10480000,
|
||||
0x1c980000,
|
||||
0x1c9b0000,
|
||||
0x1c980008,
|
||||
0x1c9b0008,
|
||||
0x38f80000,
|
||||
0x3cf80000,
|
||||
0x38780000,
|
||||
0x18180000,
|
||||
0x18980000,
|
||||
0x13580000,
|
||||
0x135b0000,
|
||||
0x13580008,
|
||||
0x135b0008,
|
||||
0x33780000,
|
||||
0x10580008,
|
||||
0x10780000
|
||||
};
|
||||
|
||||
/* Sequencer inst_rom_init configuration */
|
||||
const u32 inst_rom_init[] = {
|
||||
0x80000,
|
||||
0x80680,
|
||||
0x8180,
|
||||
0x8200,
|
||||
0x8280,
|
||||
0x8300,
|
||||
0x8380,
|
||||
0x8100,
|
||||
0x8480,
|
||||
0x8500,
|
||||
0x8580,
|
||||
0x8600,
|
||||
0x8400,
|
||||
0x800,
|
||||
0x8680,
|
||||
0x880,
|
||||
0xa680,
|
||||
0x80680,
|
||||
0x900,
|
||||
0x80680,
|
||||
0x980,
|
||||
0xa680,
|
||||
0x8680,
|
||||
0x80680,
|
||||
0xb68,
|
||||
0xcce8,
|
||||
0xae8,
|
||||
0x8ce8,
|
||||
0xb88,
|
||||
0xec88,
|
||||
0xa08,
|
||||
0xac88,
|
||||
0x80680,
|
||||
0xce00,
|
||||
0xcd80,
|
||||
0xe700,
|
||||
0xc00,
|
||||
0x20ce0,
|
||||
0x20ce0,
|
||||
0x20ce0,
|
||||
0x20ce0,
|
||||
0xd00,
|
||||
0x680,
|
||||
0x680,
|
||||
0x680,
|
||||
0x680,
|
||||
0x60e80,
|
||||
0x61080,
|
||||
0x61080,
|
||||
0x61080,
|
||||
0xa680,
|
||||
0x8680,
|
||||
0x80680,
|
||||
0xce00,
|
||||
0xcd80,
|
||||
0xe700,
|
||||
0xc00,
|
||||
0x30ce0,
|
||||
0x30ce0,
|
||||
0x30ce0,
|
||||
0x30ce0,
|
||||
0xd00,
|
||||
0x680,
|
||||
0x680,
|
||||
0x680,
|
||||
0x680,
|
||||
0x70e80,
|
||||
0x71080,
|
||||
0x71080,
|
||||
0x71080,
|
||||
0xa680,
|
||||
0x8680,
|
||||
0x80680,
|
||||
0x1158,
|
||||
0x6d8,
|
||||
0x80680,
|
||||
0x1168,
|
||||
0x7e8,
|
||||
0x7e8,
|
||||
0x87e8,
|
||||
0x40fe8,
|
||||
0x410e8,
|
||||
0x410e8,
|
||||
0x410e8,
|
||||
0x1168,
|
||||
0x7e8,
|
||||
0x7e8,
|
||||
0xa7e8,
|
||||
0x80680,
|
||||
0x40e88,
|
||||
0x41088,
|
||||
0x41088,
|
||||
0x41088,
|
||||
0x40f68,
|
||||
0x410e8,
|
||||
0x410e8,
|
||||
0x410e8,
|
||||
0xa680,
|
||||
0x40fe8,
|
||||
0x410e8,
|
||||
0x410e8,
|
||||
0x410e8,
|
||||
0x41008,
|
||||
0x41088,
|
||||
0x41088,
|
||||
0x41088,
|
||||
0x1100,
|
||||
0xc680,
|
||||
0x8680,
|
||||
0xe680,
|
||||
0x80680,
|
||||
0x0,
|
||||
0x8000,
|
||||
0xa000,
|
||||
0xc000,
|
||||
0x80000,
|
||||
0x80,
|
||||
0x8080,
|
||||
0xa080,
|
||||
0xc080,
|
||||
0x80080,
|
||||
0x9180,
|
||||
0x8680,
|
||||
0xa680,
|
||||
0x80680,
|
||||
0x40f08,
|
||||
0x80680
|
||||
};
|
||||
|
||||
#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */
|
85
board/terasic/sockit/socfpga.c
Normal file
85
board/terasic/sockit/socfpga.c
Normal file
|
@ -0,0 +1,85 @@
|
|||
/*
|
||||
* Copyright (C) 2012 Altera Corporation <www.altera.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/reset_manager.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#include <usb.h>
|
||||
#include <usb/s3c_udc.h>
|
||||
#include <usb_mass_storage.h>
|
||||
|
||||
#include <micrel.h>
|
||||
#include <netdev.h>
|
||||
#include <phy.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
void s_init(void) {}
|
||||
|
||||
/*
|
||||
* Miscellaneous platform dependent initialisations
|
||||
*/
|
||||
int board_init(void)
|
||||
{
|
||||
/* Address of boot parameters for ATAG (if ATAG is used) */
|
||||
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* PHY configuration
|
||||
*/
|
||||
#ifdef CONFIG_PHY_MICREL_KSZ9021
|
||||
int board_phy_config(struct phy_device *phydev)
|
||||
{
|
||||
int ret;
|
||||
/*
|
||||
* These skew settings for the KSZ9021 ethernet phy is required for ethernet
|
||||
* to work reliably on most flavors of cyclone5 boards.
|
||||
*/
|
||||
ret = ksz9021_phy_extended_write(phydev,
|
||||
MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
|
||||
0x0);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = ksz9021_phy_extended_write(phydev,
|
||||
MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
|
||||
0x0);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = ksz9021_phy_extended_write(phydev,
|
||||
MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
|
||||
0xf0f0);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (phydev->drv->config)
|
||||
return phydev->drv->config(phydev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USB_GADGET
|
||||
struct s3c_plat_otg_data socfpga_otg_data = {
|
||||
.regs_otg = CONFIG_USB_DWC2_REG_ADDR,
|
||||
.usb_gusbcfg = 0x1417,
|
||||
};
|
||||
|
||||
int board_usb_init(int index, enum usb_init_type init)
|
||||
{
|
||||
return s3c_udc_probe(&socfpga_otg_data);
|
||||
}
|
||||
|
||||
int g_dnl_board_usb_cable_connected(void)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
#endif
|
20
configs/socfpga_de0_nano_soc_defconfig
Normal file
20
configs/socfpga_de0_nano_soc_defconfig
Normal file
|
@ -0,0 +1,20 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_SOCFPGA=y
|
||||
CONFIG_TARGET_SOCFPGA_CYCLONE5=y
|
||||
CONFIG_TARGET_SOCFPGA_TERASIC_DE0_NANO=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de0_nano_soc"
|
||||
CONFIG_SPL=y
|
||||
# CONFIG_CMD_IMLS is not set
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_ETH_DESIGNWARE=y
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_DWAPB_GPIO=y
|
||||
CONFIG_SPL_DM=y
|
||||
CONFIG_SPL_MMC_SUPPORT=y
|
||||
CONFIG_SPL_SIMPLE_BUS=y
|
||||
CONFIG_SPL_STACK_R=y
|
||||
CONFIG_SPL_STACK_R_ADDR=0x00800000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x2000
|
21
configs/socfpga_mcvevk_defconfig
Normal file
21
configs/socfpga_mcvevk_defconfig
Normal file
|
@ -0,0 +1,21 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_SOCFPGA=y
|
||||
CONFIG_TARGET_SOCFPGA_CYCLONE5=y
|
||||
CONFIG_TARGET_SOCFPGA_DENX_MCVEVK=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_mcvevk"
|
||||
CONFIG_SPL=y
|
||||
# CONFIG_CMD_IMLS is not set
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_ETH_DESIGNWARE=y
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_DWAPB_GPIO=y
|
||||
CONFIG_SPL_DM=y
|
||||
CONFIG_SPL_MMC_SUPPORT=y
|
||||
CONFIG_DM_SEQ_ALIAS=y
|
||||
CONFIG_SPL_SIMPLE_BUS=y
|
||||
CONFIG_SPL_STACK_R=y
|
||||
CONFIG_SPL_STACK_R_ADDR=0x00800000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x2000
|
26
configs/socfpga_sockit_defconfig
Normal file
26
configs/socfpga_sockit_defconfig
Normal file
|
@ -0,0 +1,26 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_SOCFPGA=y
|
||||
CONFIG_TARGET_SOCFPGA_CYCLONE5=y
|
||||
CONFIG_TARGET_SOCFPGA_TERASIC_SOCKIT=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sockit"
|
||||
CONFIG_SPL=y
|
||||
# CONFIG_CMD_IMLS is not set
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_USE_4K_SECTORS=n
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_ETH_DESIGNWARE=y
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_DWAPB_GPIO=y
|
||||
CONFIG_SPL_DM=y
|
||||
CONFIG_SPL_MMC_SUPPORT=y
|
||||
CONFIG_DM_SEQ_ALIAS=y
|
||||
CONFIG_SPL_SIMPLE_BUS=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_SPL_SPI_SUPPORT=y
|
||||
CONFIG_SPL_STACK_R=y
|
||||
CONFIG_SPL_STACK_R_ADDR=0x00800000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x2000
|
|
@ -6,6 +6,8 @@
|
|||
|
||||
#include <common.h>
|
||||
#include <malloc.h>
|
||||
#include <fdtdec.h>
|
||||
#include <libfdt.h>
|
||||
#include <dwmmc.h>
|
||||
#include <errno.h>
|
||||
#include <asm/arch/dwmmc.h>
|
||||
|
@ -42,34 +44,87 @@ static void socfpga_dwmci_clksel(struct dwmci_host *host)
|
|||
CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
|
||||
}
|
||||
|
||||
int socfpga_dwmmc_init(u32 regbase, int bus_width, int index)
|
||||
static int socfpga_dwmci_of_probe(const void *blob, int node, const int idx)
|
||||
{
|
||||
/* FIXME: probe from DT eventually too/ */
|
||||
const unsigned long clk = cm_get_mmc_controller_clk_hz();
|
||||
|
||||
struct dwmci_host *host;
|
||||
unsigned long clk = cm_get_mmc_controller_clk_hz();
|
||||
fdt_addr_t reg_base;
|
||||
int bus_width, fifo_depth;
|
||||
|
||||
if (clk == 0) {
|
||||
printf("%s: MMC clock is zero!", __func__);
|
||||
printf("DWMMC%d: MMC clock is zero!", idx);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* calloc for zero init */
|
||||
host = calloc(1, sizeof(struct dwmci_host));
|
||||
if (!host) {
|
||||
printf("%s: calloc() failed!\n", __func__);
|
||||
return -ENOMEM;
|
||||
/* Get the register address from the device node */
|
||||
reg_base = fdtdec_get_addr(blob, node, "reg");
|
||||
if (!reg_base) {
|
||||
printf("DWMMC%d: Can't get base address\n", idx);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Get the bus width from the device node */
|
||||
bus_width = fdtdec_get_int(blob, node, "bus-width", 0);
|
||||
if (bus_width <= 0) {
|
||||
printf("DWMMC%d: Can't get bus-width\n", idx);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
fifo_depth = fdtdec_get_int(blob, node, "fifo-depth", 0);
|
||||
if (fifo_depth < 0) {
|
||||
printf("DWMMC%d: Can't get FIFO depth\n", idx);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Allocate the host */
|
||||
host = calloc(1, sizeof(*host));
|
||||
if (!host)
|
||||
return -ENOMEM;
|
||||
|
||||
host->name = "SOCFPGA DWMMC";
|
||||
host->ioaddr = (void *)regbase;
|
||||
host->ioaddr = (void *)reg_base;
|
||||
host->buswidth = bus_width;
|
||||
host->clksel = socfpga_dwmci_clksel;
|
||||
host->dev_index = index;
|
||||
/* fixed clock divide by 4 which due to the SDMMC wrapper */
|
||||
host->dev_index = idx;
|
||||
/* Fixed clock divide by 4 which due to the SDMMC wrapper */
|
||||
host->bus_hz = clk;
|
||||
host->fifoth_val = MSIZE(0x2) |
|
||||
RX_WMARK(CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH / 2 - 1) |
|
||||
TX_WMARK(CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH / 2);
|
||||
RX_WMARK(fifo_depth / 2 - 1) | TX_WMARK(fifo_depth / 2);
|
||||
|
||||
return add_dwmci(host, host->bus_hz, 400000);
|
||||
}
|
||||
|
||||
static int socfpga_dwmci_process_node(const void *blob, int nodes[],
|
||||
int count)
|
||||
{
|
||||
int i, node, ret;
|
||||
|
||||
for (i = 0; i < count; i++) {
|
||||
node = nodes[i];
|
||||
if (node <= 0)
|
||||
continue;
|
||||
|
||||
ret = socfpga_dwmci_of_probe(blob, node, i);
|
||||
if (ret) {
|
||||
printf("%s: failed to decode dev %d\n", __func__, i);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
int socfpga_dwmmc_init(const void *blob)
|
||||
{
|
||||
int nodes[2]; /* Max. two controllers. */
|
||||
int ret, count;
|
||||
|
||||
count = fdtdec_find_aliases_for_id(blob, "mmc",
|
||||
COMPAT_ALTERA_SOCFPGA_DWMMC,
|
||||
nodes, ARRAY_SIZE(nodes));
|
||||
|
||||
ret = socfpga_dwmci_process_node(blob, nodes, count);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
|
@ -182,12 +182,10 @@ static int alt_sgdma_do_sync_transfer(volatile struct alt_sgdma_registers *dev,
|
|||
static int alt_sgdma_do_async_transfer(volatile struct alt_sgdma_registers *dev,
|
||||
volatile struct alt_sgdma_descriptor *desc)
|
||||
{
|
||||
unsigned int status;
|
||||
int counter = 0;
|
||||
|
||||
/* Wait for any pending transfers to complete */
|
||||
alt_sgdma_print_desc(desc);
|
||||
status = dev->status;
|
||||
|
||||
counter = 0;
|
||||
while (dev->status & ALT_SGDMA_STATUS_BUSY_MSK) {
|
||||
|
|
|
@ -192,7 +192,6 @@ unsigned int cm_get_l4_sp_clk_hz(void);
|
|||
/*
|
||||
* QSPI support
|
||||
*/
|
||||
#ifdef CONFIG_OF_CONTROL /* QSPI is controlled via DT */
|
||||
#define CONFIG_CADENCE_QSPI
|
||||
/* Enable multiple SPI NOR flash manufacturers */
|
||||
#define CONFIG_SPI_FLASH_STMICRO /* Micron/Numonyx flash */
|
||||
|
@ -212,12 +211,12 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
|
|||
#define CONFIG_CQSPI_DECODER 0
|
||||
#define CONFIG_CMD_SF
|
||||
#define CONFIG_SPI_FLASH_BAR
|
||||
#endif
|
||||
|
||||
#if CONFIG_IS_ENABLED(OF_CONTROL) /* DW SPI is controlled via DT */
|
||||
/*
|
||||
* Designware SPI support
|
||||
*/
|
||||
#define CONFIG_DESIGNWARE_SPI
|
||||
#define CONFIG_CMD_SPI
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Serial Driver
|
||||
|
|
87
include/configs/socfpga_de0_nano_soc.h
Normal file
87
include/configs/socfpga_de0_nano_soc.h
Normal file
|
@ -0,0 +1,87 @@
|
|||
/*
|
||||
* Copyright (C) 2015 Marek Vasut <marex@denx.de>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
#ifndef __CONFIG_TERASIC_DE0_H__
|
||||
#define __CONFIG_TERASIC_DE0_H__
|
||||
|
||||
#include <asm/arch/socfpga_base_addrs.h>
|
||||
|
||||
/* U-Boot Commands */
|
||||
#define CONFIG_SYS_NO_FLASH
|
||||
#define CONFIG_DOS_PARTITION
|
||||
#define CONFIG_FAT_WRITE
|
||||
#define CONFIG_HW_WATCHDOG
|
||||
|
||||
#define CONFIG_CMD_ASKENV
|
||||
#define CONFIG_CMD_BOOTZ
|
||||
#define CONFIG_CMD_CACHE
|
||||
#define CONFIG_CMD_DFU
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_EXT4
|
||||
#define CONFIG_CMD_EXT4_WRITE
|
||||
#define CONFIG_CMD_FAT
|
||||
#define CONFIG_CMD_FS_GENERIC
|
||||
#define CONFIG_CMD_GPIO
|
||||
#define CONFIG_CMD_GREPENV
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_MMC
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_USB
|
||||
#define CONFIG_CMD_USB_MASS_STORAGE
|
||||
|
||||
/* Memory configurations */
|
||||
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB */
|
||||
|
||||
/* Booting Linux */
|
||||
#define CONFIG_BOOTDELAY 3
|
||||
#define CONFIG_BOOTFILE "fitImage"
|
||||
#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE)
|
||||
#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
|
||||
#define CONFIG_BOOTCOMMAND "run ramboot"
|
||||
#else
|
||||
#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot"
|
||||
#endif
|
||||
#define CONFIG_LOADADDR 0x01000000
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
|
||||
|
||||
/* Ethernet on SoC (EMAC) */
|
||||
#if defined(CONFIG_CMD_NET)
|
||||
|
||||
/* PHY */
|
||||
#define CONFIG_PHY_MICREL
|
||||
#define CONFIG_PHY_MICREL_KSZ9031
|
||||
|
||||
#endif
|
||||
|
||||
/* USB */
|
||||
#ifdef CONFIG_CMD_USB
|
||||
#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS
|
||||
#endif
|
||||
#define CONFIG_G_DNL_MANUFACTURER "Terasic"
|
||||
|
||||
/* Extra Environment */
|
||||
#define CONFIG_HOSTNAME socfpga_de0_nano_soc
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
|
||||
"ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
|
||||
"bootm ${loadaddr} - ${fdt_addr}\0" \
|
||||
"bootimage=zImage\0" \
|
||||
"fdt_addr=100\0" \
|
||||
"fdtimage=socfpga.dtb\0" \
|
||||
"fsloadcmd=ext2load\0" \
|
||||
"bootm ${loadaddr} - ${fdt_addr}\0" \
|
||||
"mmcroot=/dev/mmcblk0p2\0" \
|
||||
"mmcboot=setenv bootargs " CONFIG_BOOTARGS \
|
||||
" root=${mmcroot} rw rootwait;" \
|
||||
"bootz ${loadaddr} - ${fdt_addr}\0" \
|
||||
"mmcload=mmc rescan;" \
|
||||
"load mmc 0:1 ${loadaddr} ${bootimage};" \
|
||||
"load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
|
||||
|
||||
/* The rest of the configuration is shared */
|
||||
#include <configs/socfpga_common.h>
|
||||
|
||||
#endif /* __CONFIG_TERASIC_DE0_H__ */
|
132
include/configs/socfpga_mcvevk.h
Normal file
132
include/configs/socfpga_mcvevk.h
Normal file
|
@ -0,0 +1,132 @@
|
|||
/*
|
||||
* Copyright (C) 2015 Marek Vasut <marex@denx.de>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
#ifndef __CONFIG_DENX_MCVEVK_H__
|
||||
#define __CONFIG_DENX_MCVEVK_H__
|
||||
|
||||
#include <asm/arch/socfpga_base_addrs.h>
|
||||
|
||||
/* U-Boot Commands */
|
||||
#define CONFIG_SYS_NO_FLASH
|
||||
#define CONFIG_DOS_PARTITION
|
||||
#define CONFIG_FAT_WRITE
|
||||
#define CONFIG_HW_WATCHDOG
|
||||
|
||||
#define CONFIG_CMD_ASKENV
|
||||
#define CONFIG_CMD_BOOTZ
|
||||
#define CONFIG_CMD_CACHE
|
||||
#define CONFIG_CMD_DFU
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_EXT4
|
||||
#define CONFIG_CMD_EXT4_WRITE
|
||||
#define CONFIG_CMD_FAT
|
||||
#define CONFIG_CMD_FS_GENERIC
|
||||
#define CONFIG_CMD_GPIO
|
||||
#define CONFIG_CMD_GREPENV
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_MMC
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_USB
|
||||
#define CONFIG_CMD_USB_MASS_STORAGE
|
||||
|
||||
/* Memory configurations */
|
||||
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on MCV */
|
||||
|
||||
/* Booting Linux */
|
||||
#define CONFIG_BOOTDELAY 3
|
||||
#define CONFIG_BOOTFILE "fitImage"
|
||||
#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE)
|
||||
#define CONFIG_PREBOOT "run try_bootscript"
|
||||
#define CONFIG_BOOTCOMMAND "run mmc_mmc"
|
||||
#define CONFIG_LOADADDR 0x01000000
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
|
||||
|
||||
/* USB */
|
||||
#ifdef CONFIG_CMD_USB
|
||||
#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS
|
||||
#endif
|
||||
#define CONFIG_G_DNL_MANUFACTURER "DENX"
|
||||
|
||||
/* Extra Environment */
|
||||
#define CONFIG_HOSTNAME mcvevk
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"consdev=ttyS0\0" \
|
||||
"baudrate=115200\0" \
|
||||
"bootscript=boot.scr\0" \
|
||||
"bootdev=/dev/mmcblk0p2\0" \
|
||||
"rootdev=/dev/mmcblk0p3\0" \
|
||||
"netdev=eth0\0" \
|
||||
"hostname=mcvevk\0" \
|
||||
"kernel_addr_r=0x10000000\0" \
|
||||
"update_filename=u-boot-with-spl-dtb.sfp\0" \
|
||||
"update_sd_offset=0x800\0" \
|
||||
"update_sd=" /* Update the SD firmware partition */ \
|
||||
"if mmc rescan ; then " \
|
||||
"if tftp ${update_filename} ; then " \
|
||||
"setexpr fw_sz ${filesize} / 0x200 ; " /* SD block size */ \
|
||||
"setexpr fw_sz ${fw_sz} + 1 ; " \
|
||||
"mmc write ${loadaddr} ${update_sd_offset} ${fw_sz} ; " \
|
||||
"fi ; " \
|
||||
"fi\0" \
|
||||
"update_qspi_offset=0x0\0" \
|
||||
"update_qspi=" /* Update the QSPI firmware */ \
|
||||
"if sf probe ; then " \
|
||||
"if tftp ${update_filename} ; then " \
|
||||
"sf update ${loadaddr} ${update_qspi_offset} ${filesize} ; " \
|
||||
"fi ; " \
|
||||
"fi\0" \
|
||||
"fpga_filename=output_file.rbf\0" \
|
||||
"load_fpga=" /* Load FPGA bitstream */ \
|
||||
"if tftp ${fpga_filename} ; then " \
|
||||
"fpga load 0 $loadaddr $filesize ; " \
|
||||
"bridge enable ; " \
|
||||
"fi\0" \
|
||||
"addcons=" \
|
||||
"setenv bootargs ${bootargs} " \
|
||||
"console=${consdev},${baudrate}\0" \
|
||||
"addip=" \
|
||||
"setenv bootargs ${bootargs} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:" \
|
||||
"${netmask}:${hostname}:${netdev}:off\0" \
|
||||
"addmisc=" \
|
||||
"setenv bootargs ${bootargs} ${miscargs}\0" \
|
||||
"addargs=run addcons addmisc\0" \
|
||||
"mmcload=" \
|
||||
"mmc rescan ; " \
|
||||
"load mmc 0:2 ${kernel_addr_r} ${bootfile}\0" \
|
||||
"netload=" \
|
||||
"tftp ${kernel_addr_r} ${hostname}/${bootfile}\0" \
|
||||
"miscargs=nohlt panic=1\0" \
|
||||
"mmcargs=setenv bootargs root=${rootdev} rw rootwait\0" \
|
||||
"nfsargs=" \
|
||||
"setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=${serverip}:${rootpath},v3,tcp\0" \
|
||||
"mmc_mmc=" \
|
||||
"run mmcload mmcargs addargs ; " \
|
||||
"bootm ${kernel_addr_r}\0" \
|
||||
"mmc_nfs=" \
|
||||
"run mmcload nfsargs addip addargs ; " \
|
||||
"bootm ${kernel_addr_r}\0" \
|
||||
"net_mmc=" \
|
||||
"run netload mmcargs addargs ; " \
|
||||
"bootm ${kernel_addr_r}\0" \
|
||||
"net_nfs=" \
|
||||
"run netload nfsargs addip addargs ; " \
|
||||
"bootm ${kernel_addr_r}\0" \
|
||||
"try_bootscript=" \
|
||||
"mmc rescan;" \
|
||||
"if test -e mmc 0:2 ${bootscript} ; then " \
|
||||
"if load mmc 0:2 ${kernel_addr_r} ${bootscript};" \
|
||||
"then ; " \
|
||||
"echo Running bootscript... ; " \
|
||||
"source ${kernel_addr_r} ; " \
|
||||
"fi ; " \
|
||||
"fi\0"
|
||||
|
||||
/* The rest of the configuration is shared */
|
||||
#include <configs/socfpga_common.h>
|
||||
|
||||
#endif /* __CONFIG_DENX_MCVEVK_H__ */
|
92
include/configs/socfpga_sockit.h
Normal file
92
include/configs/socfpga_sockit.h
Normal file
|
@ -0,0 +1,92 @@
|
|||
/*
|
||||
* Copyright (C) 2015 Marek Vasut <marex@denx.de>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
#ifndef __CONFIG_TERASIC_SOCKIT_H__
|
||||
#define __CONFIG_TERASIC_SOCKIT_H__
|
||||
|
||||
#include <asm/arch/socfpga_base_addrs.h>
|
||||
|
||||
/* U-Boot Commands */
|
||||
#define CONFIG_SYS_NO_FLASH
|
||||
#define CONFIG_DOS_PARTITION
|
||||
#define CONFIG_FAT_WRITE
|
||||
#define CONFIG_HW_WATCHDOG
|
||||
|
||||
#define CONFIG_CMD_ASKENV
|
||||
#define CONFIG_CMD_BOOTZ
|
||||
#define CONFIG_CMD_CACHE
|
||||
#define CONFIG_CMD_DFU
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_EXT4
|
||||
#define CONFIG_CMD_EXT4_WRITE
|
||||
#define CONFIG_CMD_FAT
|
||||
#define CONFIG_CMD_FS_GENERIC
|
||||
#define CONFIG_CMD_GPIO
|
||||
#define CONFIG_CMD_GREPENV
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_MMC
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_USB
|
||||
#define CONFIG_CMD_USB_MASS_STORAGE
|
||||
|
||||
/* Memory configurations */
|
||||
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */
|
||||
|
||||
/* Booting Linux */
|
||||
#define CONFIG_BOOTDELAY 3
|
||||
#define CONFIG_BOOTFILE "fitImage"
|
||||
#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE)
|
||||
#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
|
||||
#define CONFIG_BOOTCOMMAND "run ramboot"
|
||||
#else
|
||||
#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot"
|
||||
#endif
|
||||
#define CONFIG_LOADADDR 0x01000000
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
|
||||
|
||||
/* Ethernet on SoC (EMAC) */
|
||||
#if defined(CONFIG_CMD_NET)
|
||||
|
||||
/* PHY */
|
||||
#define CONFIG_PHY_MICREL
|
||||
#define CONFIG_PHY_MICREL_KSZ9021
|
||||
#define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew"
|
||||
#define CONFIG_KSZ9021_CLK_SKEW_VAL 0xf0f0
|
||||
#define CONFIG_KSZ9021_DATA_SKEW_ENV "micrel-ksz9021-data-skew"
|
||||
#define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0
|
||||
|
||||
#endif
|
||||
|
||||
/* USB */
|
||||
#ifdef CONFIG_CMD_USB
|
||||
#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS
|
||||
#endif
|
||||
#define CONFIG_G_DNL_MANUFACTURER "Terasic"
|
||||
|
||||
/* Extra Environment */
|
||||
#define CONFIG_HOSTNAME socfpga_sockit
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"verify=n\0" \
|
||||
"loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
|
||||
"ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
|
||||
"bootm ${loadaddr} - ${fdt_addr}\0" \
|
||||
"bootimage=zImage\0" \
|
||||
"fdt_addr=100\0" \
|
||||
"fdtimage=socfpga.dtb\0" \
|
||||
"fsloadcmd=ext2load\0" \
|
||||
"bootm ${loadaddr} - ${fdt_addr}\0" \
|
||||
"mmcroot=/dev/mmcblk0p2\0" \
|
||||
"mmcboot=setenv bootargs " CONFIG_BOOTARGS \
|
||||
" root=${mmcroot} rw rootwait;" \
|
||||
"bootz ${loadaddr} - ${fdt_addr}\0" \
|
||||
"mmcload=mmc rescan;" \
|
||||
"load mmc 0:1 ${loadaddr} ${bootimage};" \
|
||||
"load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
|
||||
|
||||
/* The rest of the configuration is shared */
|
||||
#include <configs/socfpga_common.h>
|
||||
|
||||
#endif /* __CONFIG_TERASIC_SOCKIT_H__ */
|
|
@ -170,6 +170,7 @@ enum fdt_compat_id {
|
|||
COMPAT_INTEL_PCH, /* Intel PCH */
|
||||
COMPAT_INTEL_IRQ_ROUTER, /* Intel Interrupt Router */
|
||||
COMPAT_ALTERA_SOCFPGA_DWMAC, /* SoCFPGA Ethernet controller */
|
||||
COMPAT_ALTERA_SOCFPGA_DWMMC, /* SoCFPGA DWMMC controller */
|
||||
COMPAT_INTEL_BAYTRAIL_FSP, /* Intel Bay Trail FSP */
|
||||
COMPAT_INTEL_BAYTRAIL_FSP_MDP, /* Intel FSP memory-down params */
|
||||
|
||||
|
|
|
@ -74,6 +74,7 @@ static const char * const compat_names[COMPAT_COUNT] = {
|
|||
COMPAT(COMPAT_INTEL_PCH, "intel,bd82x6x"),
|
||||
COMPAT(COMPAT_INTEL_IRQ_ROUTER, "intel,irq-router"),
|
||||
COMPAT(ALTERA_SOCFPGA_DWMAC, "altr,socfpga-stmmac"),
|
||||
COMPAT(ALTERA_SOCFPGA_DWMMC, "altr,socfpga-dw-mshc"),
|
||||
COMPAT(COMPAT_INTEL_BAYTRAIL_FSP, "intel,baytrail-fsp"),
|
||||
COMPAT(COMPAT_INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"),
|
||||
};
|
||||
|
|
Loading…
Reference in a new issue