mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-11 07:34:31 +00:00
arm: dts: imx8mn, imx8mn-beacon: Sync dts files with Kernel 5.12-rc5
There have been a few updates including flexspi, so it's necessary to re-sync. Signed-off-by: Adam Ford <aford173@gmail.com>
This commit is contained in:
Adam Ford
Stefano Babic
parent
f980299004
commit
a5f8cc3301
3 changed files with 172 additions and 8 deletions
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@ -34,6 +34,15 @@
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};
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};
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reg_audio: regulator-audio {
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compatible = "regulator-fixed";
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regulator-name = "3v3_aud";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&pca6416_1 11 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_usdhc2_vmmc: regulator-usdhc2 {
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compatible = "regulator-fixed";
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regulator-name = "vsd_3v3";
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@ -53,6 +62,20 @@
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gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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sound {
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compatible = "fsl,imx-audio-wm8962";
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model = "wm8962-audio";
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audio-cpu = <&sai3>;
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audio-codec = <&wm8962>;
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audio-routing =
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"Headphone Jack", "HPOUTL",
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"Headphone Jack", "HPOUTR",
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"Ext Spk", "SPKOUTL",
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"Ext Spk", "SPKOUTR",
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"AMIC", "MICBIAS",
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"IN3R", "AMIC";
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};
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};
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&ecspi2 {
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@ -98,6 +121,44 @@
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interrupt-parent = <&gpio4>;
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interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
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};
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wm8962: audio-codec@1a {
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compatible = "wlf,wm8962";
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reg = <0x1a>;
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clocks = <&clk IMX8MN_CLK_SAI3_ROOT>;
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clock-names = "xclk";
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DCVDD-supply = <®_audio>;
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DBVDD-supply = <®_audio>;
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AVDD-supply = <®_audio>;
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CPVDD-supply = <®_audio>;
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MICVDD-supply = <®_audio>;
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PLLVDD-supply = <®_audio>;
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SPKVDD1-supply = <®_audio>;
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SPKVDD2-supply = <®_audio>;
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gpio-cfg = <
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0x0000 /* 0:Default */
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0x0000 /* 1:Default */
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0x0000 /* 2:FN_DMICCLK */
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0x0000 /* 3:Default */
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0x0000 /* 4:FN_DMICCDAT */
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0x0000 /* 5:Default */
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>;
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};
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};
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&easrc {
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fsl,asrc-rate = <48000>;
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status = "okay";
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};
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&sai3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sai3>;
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assigned-clocks = <&clk IMX8MN_CLK_SAI3>;
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assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
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assigned-clock-rates = <24576000>;
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fsl,sai-mclk-direction-output;
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status = "okay";
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};
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&snvs_pwrkey {
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@ -177,6 +238,16 @@
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>;
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};
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pinctrl_sai3: sai3grp {
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fsl,pins = <
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MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
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MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
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MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
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MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
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MX8MN_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
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>;
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};
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pinctrl_uart2: uart2grp {
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fsl,pins = <
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MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
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@ -4,6 +4,12 @@
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*/
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/ {
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aliases {
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rtc0 = &rtc;
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rtc1 = &snvs_rtc;
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spi0 = &flexspi;
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};
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usdhc1_pwrseq: usdhc1_pwrseq {
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compatible = "mmc-pwrseq-simple";
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pinctrl-names = "default";
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@ -36,11 +42,39 @@
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cpu-supply = <&buck2_reg>;
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};
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/* DDR controller is running LPDDR at 800MHz which requires 0.95V */
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&a53_opp_table {
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opp-1200000000 {
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opp-microvolt = <950000>;
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};
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};
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&ddrc {
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operating-points-v2 = <&ddrc_opp_table>;
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ddrc_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-25M {
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opp-hz = /bits/ 64 <25000000>;
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};
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opp-100M {
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opp-hz = /bits/ 64 <100000000>;
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};
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opp-800M {
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opp-hz = /bits/ 64 <800000000>;
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};
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};
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec1>;
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phy-mode = "rgmii-id";
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phy-handle = <ðphy0>;
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phy-supply = <&buck6_reg>;
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phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
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fsl,magic-packet;
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status = "okay";
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@ -56,6 +90,22 @@
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};
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};
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&flexspi {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexspi>;
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status = "okay";
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flash@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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spi-max-frequency = <80000000>;
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spi-tx-bus-width = <4>;
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spi-rx-bus-width = <4>;
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};
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};
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&i2c1 {
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clock-frequency = <400000>;
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pinctrl-names = "default";
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@ -184,7 +234,7 @@
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reg = <0x50>;
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};
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rtc@51 {
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rtc: rtc@51 {
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compatible = "nxp,pcf85263";
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reg = <0x51>;
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};
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@ -285,6 +335,17 @@
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>;
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};
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pinctrl_flexspi: flexspigrp {
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fsl,pins = <
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MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2
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MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
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MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
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MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
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MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
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MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
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>;
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};
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pinctrl_pmic: pmicirqgrp {
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fsl,pins = <
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MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141
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@ -241,10 +241,12 @@
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};
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soc@0 {
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compatible = "simple-bus";
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compatible = "fsl,imx8mn-soc", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0x0 0x3e000000>;
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nvmem-cells = <&imx8mn_uid>;
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nvmem-cell-names = "soc_unique_id";
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aips1: bus@30000000 {
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compatible = "fsl,aips-bus", "simple-bus";
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@ -253,7 +255,7 @@
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#size-cells = <1>;
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ranges;
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spba: bus@30000000 {
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spba: spba-bus@30000000 {
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compatible = "fsl,spba-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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@ -531,9 +533,17 @@
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#address-cells = <1>;
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#size-cells = <1>;
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imx8mn_uid: unique-id@410 {
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reg = <0x4 0x8>;
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};
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cpu_speed_grade: speed-grade@10 {
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reg = <0x10 4>;
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};
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fec_mac_address: mac-address@90 {
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reg = <0x90 6>;
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};
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};
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anatop: anatop@30360000 {
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@ -581,7 +591,9 @@
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<&clk IMX8MN_CLK_NOC>,
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<&clk IMX8MN_CLK_AUDIO_AHB>,
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<&clk IMX8MN_CLK_IPG_AUDIO_ROOT>,
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<&clk IMX8MN_SYS_PLL3>;
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<&clk IMX8MN_SYS_PLL3>,
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<&clk IMX8MN_AUDIO_PLL1>,
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<&clk IMX8MN_AUDIO_PLL2>;
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assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_800M>,
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<&clk IMX8MN_ARM_PLL_OUT>,
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<&clk IMX8MN_SYS_PLL3_OUT>,
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@ -589,7 +601,9 @@
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assigned-clock-rates = <0>, <0>, <0>,
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<400000000>,
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<400000000>,
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<600000000>;
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<600000000>,
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<393216000>,
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<361267200>;
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};
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src: reset-controller@30390000 {
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@ -875,6 +889,19 @@
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status = "disabled";
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};
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flexspi: spi@30bb0000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "nxp,imx8mm-fspi";
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reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
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reg-names = "fspi_base", "fspi_mmap";
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interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX8MN_CLK_QSPI_ROOT>,
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<&clk IMX8MN_CLK_QSPI_ROOT>;
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clock-names = "fspi", "fspi_en";
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status = "disabled";
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};
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sdma1: dma-controller@30bd0000 {
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compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
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reg = <0x30bd0000 0x10000>;
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@ -903,13 +930,18 @@
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assigned-clocks = <&clk IMX8MN_CLK_ENET_AXI>,
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<&clk IMX8MN_CLK_ENET_TIMER>,
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<&clk IMX8MN_CLK_ENET_REF>,
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<&clk IMX8MN_CLK_ENET_TIMER>;
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<&clk IMX8MN_CLK_ENET_PHY_REF>;
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assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>,
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<&clk IMX8MN_SYS_PLL2_100M>,
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<&clk IMX8MN_SYS_PLL2_125M>;
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assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
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<&clk IMX8MN_SYS_PLL2_125M>,
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<&clk IMX8MN_SYS_PLL2_50M>;
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assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
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fsl,num-tx-queues = <3>;
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fsl,num-rx-queues = <3>;
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nvmem-cells = <&fec_mac_address>;
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nvmem-cell-names = "mac-address";
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nvmem_macaddr_swap;
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fsl,stop-mode = <&gpr 0x10 3>;
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status = "disabled";
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};
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