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net: rtl8139: Register macro cleanup
Clean up the horrible register definitions in the RTL8139 driver. This does create a couple of checkpatch errors, but the driver is full of them anyway, and those will be cleaned up later. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
This commit is contained in:
Marek Vasut
marex
parent
24891dd8d4
commit
a5e66e515b
1 changed files with 152 additions and 111 deletions
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@ -99,77 +99,96 @@
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#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
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/* Symbolic offsets to registers. */
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enum RTL8139_registers {
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MAC0=0, /* Ethernet hardware address. */
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MAR0=8, /* Multicast filter. */
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TxStatus0=0x10, /* Transmit status (four 32bit registers). */
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TxAddr0=0x20, /* Tx descriptors (also four 32bit). */
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RxBuf=0x30, RxEarlyCnt=0x34, RxEarlyStatus=0x36,
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ChipCmd=0x37, RxBufPtr=0x38, RxBufAddr=0x3A,
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IntrMask=0x3C, IntrStatus=0x3E,
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TxConfig=0x40, RxConfig=0x44,
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Timer=0x48, /* general-purpose counter. */
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RxMissed=0x4C, /* 24 bits valid, write clears. */
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Cfg9346=0x50, Config0=0x51, Config1=0x52,
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TimerIntrReg=0x54, /* intr if gp counter reaches this value */
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MediaStatus=0x58,
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Config3=0x59,
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MultiIntr=0x5C,
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RevisionID=0x5E, /* revision of the RTL8139 chip */
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TxSummary=0x60,
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MII_BMCR=0x62, MII_BMSR=0x64, NWayAdvert=0x66, NWayLPAR=0x68,
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NWayExpansion=0x6A,
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DisconnectCnt=0x6C, FalseCarrierCnt=0x6E,
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NWayTestReg=0x70,
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RxCnt=0x72, /* packet received counter */
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CSCR=0x74, /* chip status and configuration register */
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PhyParm1=0x78,TwisterParm=0x7c,PhyParm2=0x80, /* undocumented */
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/* from 0x84 onwards are a number of power management/wakeup frame
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* definitions we will probably never need to know about. */
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};
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/* Ethernet hardware address. */
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#define RTL_REG_MAC0 0x00
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/* Multicast filter. */
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#define RTL_REG_MAR0 0x08
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/* Transmit status (four 32bit registers). */
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#define RTL_REG_TXSTATUS0 0x10
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/* Tx descriptors (also four 32bit). */
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#define RTL_REG_TXADDR0 0x20
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#define RTL_REG_RXBUF 0x30
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#define RTL_REG_RXEARLYCNT 0x34
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#define RTL_REG_RXEARLYSTATUS 0x36
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#define RTL_REG_CHIPCMD 0x37
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#define RTL_REG_CHIPCMD_CMDRESET BIT(4)
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#define RTL_REG_CHIPCMD_CMDRXENB BIT(3)
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#define RTL_REG_CHIPCMD_CMDTXENB BIT(2)
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#define RTL_REG_CHIPCMD_RXBUFEMPTY BIT(0)
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#define RTL_REG_RXBUFPTR 0x38
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#define RTL_REG_RXBUFADDR 0x3A
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#define RTL_REG_INTRMASK 0x3C
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#define RTL_REG_INTRSTATUS 0x3E
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#define RTL_REG_INTRSTATUS_PCIERR BIT(15)
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#define RTL_REG_INTRSTATUS_PCSTIMEOUT BIT(14)
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#define RTL_REG_INTRSTATUS_CABLELENCHANGE BIT(13)
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#define RTL_REG_INTRSTATUS_RXFIFOOVER BIT(6)
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#define RTL_REG_INTRSTATUS_RXUNDERRUN BIT(5)
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#define RTL_REG_INTRSTATUS_RXOVERFLOW BIT(4)
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#define RTL_REG_INTRSTATUS_TXERR BIT(3)
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#define RTL_REG_INTRSTATUS_TXOK BIT(2)
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#define RTL_REG_INTRSTATUS_RXERR BIT(1)
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#define RTL_REG_INTRSTATUS_RXOK BIT(0)
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#define RTL_REG_TXCONFIG 0x40
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#define RTL_REG_RXCONFIG 0x44
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#define RTL_REG_RXCONFIG_RXCFGWRAP BIT(7)
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#define RTL_REG_RXCONFIG_ACCEPTERR BIT(5)
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#define RTL_REG_RXCONFIG_ACCEPTRUNT BIT(4)
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#define RTL_REG_RXCONFIG_ACCEPTBROADCAST BIT(3)
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#define RTL_REG_RXCONFIG_ACCEPTMULTICAST BIT(2)
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#define RTL_REG_RXCONFIG_ACCEPTMYPHYS BIT(1)
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#define RTL_REG_RXCONFIG_ACCEPTALLPHYS BIT(0)
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/* general-purpose counter. */
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#define RTL_REG_TIMER 0x48
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/* 24 bits valid, write clears. */
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#define RTL_REG_RXMISSED 0x4C
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#define RTL_REG_CFG9346 0x50
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#define RTL_REG_CONFIG0 0x51
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#define RTL_REG_CONFIG1 0x52
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/* intr if gp counter reaches this value */
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#define RTL_REG_TIMERINTRREG 0x54
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#define RTL_REG_MEDIASTATUS 0x58
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#define RTL_REG_MEDIASTATUS_MSRTXFLOWENABLE BIT(7)
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#define RTL_REG_MEDIASTATUS_MSRRXFLOWENABLE BIT(6)
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#define RTL_REG_MEDIASTATUS_MSRSPEED10 BIT(3)
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#define RTL_REG_MEDIASTATUS_MSRLINKFAIL BIT(2)
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#define RTL_REG_MEDIASTATUS_MSRRXPAUSEFLAG BIT(1)
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#define RTL_REG_MEDIASTATUS_MSRTXPAUSEFLAG BIT(0)
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#define RTL_REG_CONFIG3 0x59
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#define RTL_REG_MULTIINTR 0x5C
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/* revision of the RTL8139 chip */
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#define RTL_REG_REVISIONID 0x5E
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#define RTL_REG_TXSUMMARY 0x60
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#define RTL_REG_MII_BMCR 0x62
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#define RTL_REG_MII_BMSR 0x64
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#define RTL_REG_NWAYADVERT 0x66
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#define RTL_REG_NWAYLPAR 0x68
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#define RTL_REG_NWAYEXPANSION 0x6A
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#define RTL_REG_DISCONNECTCNT 0x6C
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#define RTL_REG_FALSECARRIERCNT 0x6E
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#define RTL_REG_NWAYTESTREG 0x70
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/* packet received counter */
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#define RTL_REG_RXCNT 0x72
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/* chip status and configuration register */
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#define RTL_REG_CSCR 0x74
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#define RTL_REG_PHYPARM1 0x78
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#define RTL_REG_TWISTERPARM 0x7c
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/* undocumented */
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#define RTL_REG_PHYPARM2 0x80
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/*
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* from 0x84 onwards are a number of power management/wakeup frame
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* definitions we will probably never need to know about.
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*/
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enum ChipCmdBits {
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CmdReset=0x10, CmdRxEnb=0x08, CmdTxEnb=0x04, RxBufEmpty=0x01, };
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/* Interrupt register bits, using my own meaningful names. */
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enum IntrStatusBits {
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PCIErr=0x8000, PCSTimeout=0x4000, CableLenChange= 0x2000,
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RxFIFOOver=0x40, RxUnderrun=0x20, RxOverflow=0x10,
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TxErr=0x08, TxOK=0x04, RxErr=0x02, RxOK=0x01,
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};
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enum TxStatusBits {
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TxHostOwns=0x2000, TxUnderrun=0x4000, TxStatOK=0x8000,
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TxOutOfWindow=0x20000000, TxAborted=0x40000000,
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TxCarrierLost=0x80000000,
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};
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enum RxStatusBits {
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RxMulticast=0x8000, RxPhysical=0x4000, RxBroadcast=0x2000,
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RxBadSymbol=0x0020, RxRunt=0x0010, RxTooLong=0x0008, RxCRCErr=0x0004,
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RxBadAlign=0x0002, RxStatusOK=0x0001,
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};
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enum MediaStatusBits {
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MSRTxFlowEnable=0x80, MSRRxFlowEnable=0x40, MSRSpeed10=0x08,
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MSRLinkFail=0x04, MSRRxPauseFlag=0x02, MSRTxPauseFlag=0x01,
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};
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enum MIIBMCRBits {
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BMCRReset=0x8000, BMCRSpeed100=0x2000, BMCRNWayEnable=0x1000,
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BMCRRestartNWay=0x0200, BMCRDuplex=0x0100,
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};
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enum CSCRBits {
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CSCR_LinkOKBit=0x0400, CSCR_LinkChangeBit=0x0800,
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CSCR_LinkStatusBits=0x0f000, CSCR_LinkDownOffCmd=0x003c0,
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CSCR_LinkDownCmd=0x0f3c0,
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};
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/* Bits in RxConfig. */
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enum rx_mode_bits {
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RxCfgWrap=0x80,
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AcceptErr=0x20, AcceptRunt=0x10, AcceptBroadcast=0x08,
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AcceptMulticast=0x04, AcceptMyPhys=0x02, AcceptAllPhys=0x01,
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};
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#define RTL_STS_RXMULTICAST BIT(15)
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#define RTL_STS_RXPHYSICAL BIT(14)
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#define RTL_STS_RXBROADCAST BIT(13)
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#define RTL_STS_RXBADSYMBOL BIT(5)
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#define RTL_STS_RXRUNT BIT(4)
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#define RTL_STS_RXTOOLONG BIT(3)
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#define RTL_STS_RXCRCERR BIT(2)
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#define RTL_STS_RXBADALIGN BIT(1)
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#define RTL_STS_RXSTATUSOK BIT(0)
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static int ioaddr;
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static unsigned int cur_rx,cur_tx;
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@ -251,7 +270,7 @@ static int rtl8139_probe(struct eth_device *dev, bd_t *bis)
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ioaddr = dev->iobase;
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/* Bring the chip out of low-power mode. */
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outb(0x00, ioaddr + Config1);
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outb(0x00, ioaddr + RTL_REG_CONFIG1);
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addr_len = read_eeprom(0,8) == 0x8129 ? 8 : 6;
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for (i = 0; i < 3; i++)
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@ -259,7 +278,7 @@ static int rtl8139_probe(struct eth_device *dev, bd_t *bis)
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rtl_reset(dev);
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if (inb(ioaddr + MediaStatus) & MSRLinkFail) {
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if (inb(ioaddr + RTL_REG_MEDIASTATUS) & RTL_REG_MEDIASTATUS_MSRLINKFAIL) {
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printf("Cable not connected or other link failure\n");
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return -1 ;
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}
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@ -286,15 +305,15 @@ static int rtl8139_probe(struct eth_device *dev, bd_t *bis)
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#define eeprom_delay() inl(ee_addr)
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/* The EEPROM commands include the alway-set leading bit. */
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#define EE_WRITE_CMD (5)
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#define EE_READ_CMD (6)
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#define EE_ERASE_CMD (7)
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#define EE_WRITE_CMD 5
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#define EE_READ_CMD 6
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#define EE_ERASE_CMD 7
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static int read_eeprom(int location, int addr_len)
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{
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int i;
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unsigned int retval = 0;
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long ee_addr = ioaddr + Cfg9346;
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long ee_addr = ioaddr + RTL_REG_CFG9346;
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int read_cmd = location | (EE_READ_CMD << addr_len);
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outb(EE_ENB & ~EE_CS, ee_addr);
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@ -335,41 +354,46 @@ static void set_rx_mode(struct eth_device *dev) {
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unsigned int mc_filter[2];
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int rx_mode;
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/* !IFF_PROMISC */
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rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
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rx_mode = RTL_REG_RXCONFIG_ACCEPTBROADCAST |
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RTL_REG_RXCONFIG_ACCEPTMULTICAST |
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RTL_REG_RXCONFIG_ACCEPTMYPHYS;
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mc_filter[1] = mc_filter[0] = 0xffffffff;
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outl(rtl8139_rx_config | rx_mode, ioaddr + RxConfig);
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outl(rtl8139_rx_config | rx_mode, ioaddr + RTL_REG_RXCONFIG);
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outl(mc_filter[0], ioaddr + MAR0 + 0);
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outl(mc_filter[1], ioaddr + MAR0 + 4);
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outl(mc_filter[0], ioaddr + RTL_REG_MAR0 + 0);
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outl(mc_filter[1], ioaddr + RTL_REG_MAR0 + 4);
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}
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static void rtl_reset(struct eth_device *dev)
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{
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int i;
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outb(CmdReset, ioaddr + ChipCmd);
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outb(RTL_REG_CHIPCMD_CMDRESET, ioaddr + RTL_REG_CHIPCMD);
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cur_rx = 0;
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cur_tx = 0;
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/* Give the chip 10ms to finish the reset. */
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for (i=0; i<100; ++i){
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if ((inb(ioaddr + ChipCmd) & CmdReset) == 0) break;
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if ((inb(ioaddr + RTL_REG_CHIPCMD) &
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RTL_REG_CHIPCMD_CMDRESET) == 0)
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break;
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udelay (100); /* wait 100us */
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}
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for (i = 0; i < ETH_ALEN; i++)
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outb(dev->enetaddr[i], ioaddr + MAC0 + i);
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outb(dev->enetaddr[i], ioaddr + RTL_REG_MAC0 + i);
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/* Must enable Tx/Rx before setting transfer thresholds! */
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outb(CmdRxEnb | CmdTxEnb, ioaddr + ChipCmd);
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outb(RTL_REG_CHIPCMD_CMDRXENB | RTL_REG_CHIPCMD_CMDTXENB,
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ioaddr + RTL_REG_CHIPCMD);
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outl((RX_FIFO_THRESH<<13) | (RX_BUF_LEN_IDX<<11) | (RX_DMA_BURST<<8),
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ioaddr + RxConfig); /* accept no frames yet! */
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outl((TX_DMA_BURST<<8)|0x03000000, ioaddr + TxConfig);
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ioaddr + RTL_REG_RXCONFIG); /* accept no frames yet! */
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outl((TX_DMA_BURST<<8)|0x03000000, ioaddr + RTL_REG_TXCONFIG);
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/* The Linux driver changes Config1 here to use a different LED pattern
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/* The Linux driver changes RTL_REG_CONFIG1 here to use a different LED pattern
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* for half duplex or full/autodetect duplex (for full/autodetect, the
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* outputs are TX/RX, Link10/100, FULL, while for half duplex it uses
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* TX/RX, Link100, Link10). This is messy, because it doesn't match
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@ -380,24 +404,25 @@ static void rtl_reset(struct eth_device *dev)
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debug_cond(DEBUG_RX,
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"rx ring address is %lX\n",(unsigned long)rx_ring);
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flush_cache((unsigned long)rx_ring, RX_BUF_LEN);
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outl(phys_to_bus((int)rx_ring), ioaddr + RxBuf);
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outl(phys_to_bus((int)rx_ring), ioaddr + RTL_REG_RXBUF);
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/* If we add multicast support, the MAR0 register would have to be
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/* If we add multicast support, the RTL_REG_MAR0 register would have to be
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* initialized to 0xffffffffffffffff (two 32 bit accesses). Etherboot
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* only needs broadcast (for ARP/RARP/BOOTP/DHCP) and unicast. */
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outb(CmdRxEnb | CmdTxEnb, ioaddr + ChipCmd);
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outb(RTL_REG_CHIPCMD_CMDRXENB | RTL_REG_CHIPCMD_CMDTXENB,
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ioaddr + RTL_REG_CHIPCMD);
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outl(rtl8139_rx_config, ioaddr + RxConfig);
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outl(rtl8139_rx_config, ioaddr + RTL_REG_RXCONFIG);
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/* Start the chip's Tx and Rx process. */
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outl(0, ioaddr + RxMissed);
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outl(0, ioaddr + RTL_REG_RXMISSED);
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/* set_rx_mode */
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set_rx_mode(dev);
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/* Disable all known interrupts by setting the interrupt mask. */
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outw(0, ioaddr + IntrMask);
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outw(0, ioaddr + RTL_REG_INTRMASK);
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}
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static int rtl_transmit(struct eth_device *dev, void *packet, int length)
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@ -420,23 +445,32 @@ static int rtl_transmit(struct eth_device *dev, void *packet, int length)
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}
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flush_cache((unsigned long)tx_buffer, length);
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outl(phys_to_bus((int)tx_buffer), ioaddr + TxAddr0 + cur_tx*4);
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outl(phys_to_bus((int)tx_buffer), ioaddr + RTL_REG_TXADDR0 + cur_tx*4);
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outl(((TX_FIFO_THRESH<<11) & 0x003f0000) | len,
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ioaddr + TxStatus0 + cur_tx*4);
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ioaddr + RTL_REG_TXSTATUS0 + cur_tx*4);
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do {
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status = inw(ioaddr + IntrStatus);
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/* Only acknlowledge interrupt sources we can properly handle
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* here - the RxOverflow/RxFIFOOver MUST be handled in the
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* rtl_poll() function. */
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outw(status & (TxOK | TxErr | PCIErr), ioaddr + IntrStatus);
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if ((status & (TxOK | TxErr | PCIErr)) != 0) break;
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status = inw(ioaddr + RTL_REG_INTRSTATUS);
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/*
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* Only acknlowledge interrupt sources we can properly
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* handle here - the RTL_REG_INTRSTATUS_RXOVERFLOW/
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* RTL_REG_INTRSTATUS_RXFIFOOVER MUST be handled in the
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* rtl_poll() function.
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*/
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outw(status & (RTL_REG_INTRSTATUS_TXOK |
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RTL_REG_INTRSTATUS_TXERR |
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RTL_REG_INTRSTATUS_PCIERR),
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ioaddr + RTL_REG_INTRSTATUS);
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if ((status & (RTL_REG_INTRSTATUS_TXOK |
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RTL_REG_INTRSTATUS_TXERR |
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RTL_REG_INTRSTATUS_PCIERR)) != 0)
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break;
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udelay(10);
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} while (i++ < RTL_TIMEOUT);
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txstatus = inl(ioaddr + TxStatus0 + cur_tx*4);
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txstatus = inl(ioaddr + RTL_REG_TXSTATUS0 + cur_tx*4);
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if (status & TxOK) {
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if (status & RTL_REG_INTRSTATUS_TXOK) {
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cur_tx = (cur_tx + 1) % NUM_TX_DESC;
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debug_cond(DEBUG_TX,
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@ -465,13 +499,16 @@ static int rtl_poll(struct eth_device *dev)
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ioaddr = dev->iobase;
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if (inb(ioaddr + ChipCmd) & RxBufEmpty) {
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if (inb(ioaddr + RTL_REG_CHIPCMD) & RTL_REG_CHIPCMD_RXBUFEMPTY) {
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return 0;
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}
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status = inw(ioaddr + IntrStatus);
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status = inw(ioaddr + RTL_REG_INTRSTATUS);
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/* See below for the rest of the interrupt acknowledges. */
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outw(status & ~(RxFIFOOver | RxOverflow | RxOK), ioaddr + IntrStatus);
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outw(status & ~(RTL_REG_INTRSTATUS_RXFIFOOVER |
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RTL_REG_INTRSTATUS_RXOVERFLOW |
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RTL_REG_INTRSTATUS_RXOK),
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ioaddr + RTL_REG_INTRSTATUS);
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debug_cond(DEBUG_RX, "rtl_poll: int %hX ", status);
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@ -481,7 +518,9 @@ static int rtl_poll(struct eth_device *dev)
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rx_size = rx_status >> 16;
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rx_status &= 0xffff;
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||||
|
||||
if ((rx_status & (RxBadSymbol|RxRunt|RxTooLong|RxCRCErr|RxBadAlign)) ||
|
||||
if ((rx_status & (RTL_STS_RXBADSYMBOL | RTL_STS_RXRUNT |
|
||||
RTL_STS_RXTOOLONG | RTL_STS_RXCRCERR |
|
||||
RTL_STS_RXBADALIGN)) ||
|
||||
(rx_size < ETH_ZLEN) || (rx_size > ETH_FRAME_LEN + 4)) {
|
||||
printf("rx error %hX\n", rx_status);
|
||||
rtl_reset(dev); /* this clears all interrupts still pending */
|
||||
|
|
@ -507,11 +546,13 @@ static int rtl_poll(struct eth_device *dev)
|
|||
flush_cache((unsigned long)rx_ring, RX_BUF_LEN);
|
||||
|
||||
cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
|
||||
outw(cur_rx - 16, ioaddr + RxBufPtr);
|
||||
outw(cur_rx - 16, ioaddr + RTL_REG_RXBUFPTR);
|
||||
/* See RTL8139 Programming Guide V0.1 for the official handling of
|
||||
* Rx overflow situations. The document itself contains basically no
|
||||
* usable information, except for a few exception handling rules. */
|
||||
outw(status & (RxFIFOOver | RxOverflow | RxOK), ioaddr + IntrStatus);
|
||||
outw(status & (RTL_REG_INTRSTATUS_RXFIFOOVER |
|
||||
RTL_REG_INTRSTATUS_RXOVERFLOW |
|
||||
RTL_REG_INTRSTATUS_RXOK), ioaddr + RTL_REG_INTRSTATUS);
|
||||
return length;
|
||||
}
|
||||
|
||||
|
|
@ -522,11 +563,11 @@ static void rtl_disable(struct eth_device *dev)
|
|||
ioaddr = dev->iobase;
|
||||
|
||||
/* reset the chip */
|
||||
outb(CmdReset, ioaddr + ChipCmd);
|
||||
outb(RTL_REG_CHIPCMD_CMDRESET, ioaddr + RTL_REG_CHIPCMD);
|
||||
|
||||
/* Give the chip 10ms to finish the reset. */
|
||||
for (i=0; i<100; ++i){
|
||||
if ((inb(ioaddr + ChipCmd) & CmdReset) == 0) break;
|
||||
if ((inb(ioaddr + RTL_REG_CHIPCMD) & RTL_REG_CHIPCMD_CMDRESET) == 0) break;
|
||||
udelay (100); /* wait 100us */
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in a new issue