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mpc8xxx: LCRR[CLKDIV] is sometimes five bits

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On newer CPUs, 8536, 8572, and 8610, the CLKDIV field of LCRR is five bits
instead of four.

In order to avoid an ifdef, LCRR_CLKDIV is set to 0x1f on all systems.  It
should be safe as the fifth bit was defined as reserved and set to 0.

Code that was using a hard coded 0x0f is changed to use LCRR_CLKDIV.

Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Jon Loeliger <jdl@freescale.com>
This commit is contained in:
Trent Piepho 2008-12-03 15:16:34 -08:00 committed by Andrew Fleming-AFLEMING
parent 58ec4866ed
commit a5d212a263
15 changed files with 18 additions and 15 deletions
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2
board/freescale/mpc8540ads/mpc8540ads.c
View file

@ -133,7 +133,7 @@ local_bus_init(void)
*/
get_sys_info(&sysinfo);
clkdiv = lbc->lcrr & 0x0f;
clkdiv = lbc->lcrr & LCRR_CLKDIV;
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
if (lbc_hz < 66) {

2
board/freescale/mpc8541cds/mpc8541cds.c
View file

@ -308,7 +308,7 @@ local_bus_init(void)
*/
get_sys_info(&sysinfo);
clkdiv = lbc->lcrr & 0x0f;
clkdiv = lbc->lcrr & LCRR_CLKDIV;
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
if (lbc_hz < 66) {

2
board/freescale/mpc8548cds/mpc8548cds.c
View file

@ -125,7 +125,7 @@ local_bus_init(void)
sys_info_t sysinfo;
get_sys_info(&sysinfo);
clkdiv = (lbc->lcrr & 0x0f) * 2;
clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
gur->lbiuiplldcr1 = 0x00078080;

2
board/freescale/mpc8555cds/mpc8555cds.c
View file

@ -308,7 +308,7 @@ local_bus_init(void)
*/
get_sys_info(&sysinfo);
clkdiv = lbc->lcrr & 0x0f;
clkdiv = lbc->lcrr & LCRR_CLKDIV;
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
if (lbc_hz < 66) {

2
board/freescale/mpc8560ads/mpc8560ads.c
View file

@ -337,7 +337,7 @@ local_bus_init(void)
*/
get_sys_info(&sysinfo);
clkdiv = lbc->lcrr & 0x0f;
clkdiv = lbc->lcrr & LCRR_CLKDIV;
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
if (lbc_hz < 66) {

2
board/freescale/mpc8568mds/mpc8568mds.c
View file

@ -188,7 +188,7 @@ local_bus_init(void)
sys_info_t sysinfo;
get_sys_info(&sysinfo);
clkdiv = (lbc->lcrr & 0x0f) * 2;
clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
gur->lbiuiplldcr1 = 0x00078080;

2
board/mpc8540eval/mpc8540eval.c
View file

@ -101,7 +101,7 @@ phys_size_t initdram (int board_type)
#if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus is not emulating flash */
get_sys_info(&sysinfo);
/* if localbus freq is less than 66MHz,we use bypass mode,otherwise use DLL */
if(sysinfo.freqSystemBus/(CONFIG_SYS_LBC_LCRR & 0x0f) < 66000000) {
if(sysinfo.freqSystemBus/(CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV) < 66000000) {
lbc->lcrr = (CONFIG_SYS_LBC_LCRR & 0x0fffffff)| 0x80000000;
} else {
lbc->lcrr = CONFIG_SYS_LBC_LCRR & 0x7fffffff;

2
board/pm854/pm854.c
View file

@ -150,7 +150,7 @@ local_bus_init(void)
*/
get_sys_info(&sysinfo);
clkdiv = lbc->lcrr & 0x0f;
clkdiv = lbc->lcrr & LCRR_CLKDIV;
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
if (lbc_hz < 66) {

2
board/pm856/pm856.c
View file

@ -306,7 +306,7 @@ local_bus_init(void)
*/
get_sys_info(&sysinfo);
clkdiv = lbc->lcrr & 0x0f;
clkdiv = lbc->lcrr & LCRR_CLKDIV;
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
if (lbc_hz < 66) {

2
board/sbc8548/sbc8548.c
View file

@ -126,7 +126,7 @@ local_bus_init(void)
sys_info_t sysinfo;
get_sys_info(&sysinfo);
clkdiv = (lbc->lcrr & 0x0f) * 2;
clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
gur->lbiuiplldcr1 = 0x00078080;

2
board/socrates/socrates.c
View file

@ -156,7 +156,7 @@ void local_bus_init (void)
uint lcrr = CONFIG_SYS_LBC_LCRR;
get_sys_info (&sysinfo);
clkdiv = lbc->lcrr & 0x0f;
clkdiv = lbc->lcrr & LCRR_CLKDIV;
lbc_mhz = sysinfo.freqSystemBus / 1000000 / clkdiv;
/* Disable PLL bypass for Local Bus Clock >= 66 MHz */

2
board/tqc/tqm85xx/tqm85xx.c
View file

@ -361,7 +361,7 @@ uint get_lbc_clock (void)
{
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
sys_info_t sys_info;
ulong clkdiv = lbc->lcrr & 0x0f;
ulong clkdiv = lbc->lcrr & LCRR_CLKDIV;
get_sys_info (&sys_info);

2
cpu/mpc85xx/cpu.c
View file

@ -174,7 +174,7 @@ int checkcpu (void)
lcrr = lbc->lcrr;
}
#endif
clkdiv = lcrr & 0x0f;
clkdiv = lcrr & LCRR_CLKDIV;
if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
#if defined(CONFIG_MPC8548) || defined(CONFIG_MPC8544) || \
defined(CONFIG_MPC8572) || defined(CONFIG_MPC8536)

2
cpu/mpc86xx/cpu.c
View file

@ -110,7 +110,7 @@ checkcpu(void)
lcrr = lbc->lcrr;
}
#endif
clkdiv = lcrr & 0x0f;
clkdiv = lcrr & LCRR_CLKDIV;
if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
printf("LBC:%4lu MHz\n",
sysinfo.freqSystemBus / 1000000 / clkdiv);

5
include/asm-ppc/fsl_lbc.h
View file

@ -300,7 +300,10 @@
#define LCRR_EADC_2 0x00020000
#define LCRR_EADC_3 0x00030000
#define LCRR_EADC_4 0x00000000
#define LCRR_CLKDIV 0x0000000F
/* CLKDIV is five bits only on 8536, 8572, and 8610, so far, but the fifth bit
* should always be zero on older parts that have a four bit CLKDIV.
*/
#define LCRR_CLKDIV 0x0000001F
#define LCRR_CLKDIV_SHIFT 0
#define LCRR_CLKDIV_2 0x00000002
#define LCRR_CLKDIV_4 0x00000004