mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-10 23:24:38 +00:00
* Make BMS2003 use a separate config file to avoid #ifdef mess;
add I2C support; add support for DS1337 RTC * Add CompactFlash support for BMS2003 board * Add support for status LED on BMS2003 board
This commit is contained in:
wdenk
parent
180d3f74e4
commit
a522fa0e7c
10 changed files with 698 additions and 19 deletions
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@ -2,6 +2,13 @@
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Changes since U-Boot 1.0.0:
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======================================================================
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* Make BMS2003 use a separate config file to avoid #ifdef mess;
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add I2C support; add support for DS1337 RTC
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* Add CompactFlash support for BMS2003 board
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* Add support for status LED on BMS2003 board
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* Patch by Scott McNutt, 02 Jan 2004:
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Add support for the Nios Active Serial Memory Interface (ASMI)
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on Cyclone devices
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5
Makefile
5
Makefile
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@ -261,10 +261,7 @@ AMX860_config : unconfig
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@./mkconfig $(@:_config=) ppc mpc8xx amx860 westel
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bms2003_config : unconfig
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@echo "#define CONFIG_BMS2003" >include/config.h
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@echo "#define CONFIG_LCD" >>include/config.h
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@echo "#define CONFIG_NEC_NL6448BC33_54" >>include/config.h
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@./mkconfig -a TQM823L ppc mpc8xx tqm8xx
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@./mkconfig $(@:_config=) ppc mpc8xx tqm8xx
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c2mon_config: unconfig
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@./mkconfig $(@:_config=) ppc mpc8xx c2mon
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@ -39,13 +39,6 @@ long int initdram(int board_type)
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/* In cpu/mips/cpu.c */
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void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 );
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#ifdef CONFIG_DBAU1100
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#warning "FIXME Check that bcsr is the same as dbau1000 board!"
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#endif
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#ifdef CONFIG_DBAU1500
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#warning "FIXME Check that bcsr is the same as dbau1000 board!"
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#endif
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int checkboard (void)
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{
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u16 status;
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@ -835,6 +835,7 @@ output_data_short(int dev, ulong *sect_buf, int words)
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static void
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input_swap_data(int dev, ulong *sect_buf, int words)
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{
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#ifndef CONFIG_BMS2003
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volatile ushort *pbuf = (ushort *)(ATA_CURR_BASE(dev)+ATA_DATA_REG);
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ushort *dbuf = (ushort *)sect_buf;
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@ -842,6 +843,20 @@ input_swap_data(int dev, ulong *sect_buf, int words)
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*dbuf++ = ld_le16(pbuf);
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*dbuf++ = ld_le16(pbuf);
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}
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#else /* CONFIG_BMS2003 */
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uchar i;
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volatile uchar *pbuf_even = (uchar *)(ATA_CURR_BASE(dev)+ATA_DATA_EVEN);
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volatile uchar *pbuf_odd = (uchar *)(ATA_CURR_BASE(dev)+ATA_DATA_ODD);
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ushort *dbuf = (ushort *)sect_buf;
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while (words--) {
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for (i=0; i<2; i++) {
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*(((uchar *)(dbuf)) + 1) = *pbuf_even;
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*(uchar *)dbuf = *pbuf_odd;
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dbuf+=1;
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}
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}
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#endif /* CONFIG_BMS2003 */
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}
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#endif /* __LITTLE_ENDIAN || CONFIG_AU1X00 */
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@ -850,6 +865,7 @@ input_swap_data(int dev, ulong *sect_buf, int words)
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static void
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output_data(int dev, ulong *sect_buf, int words)
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{
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#ifndef CONFIG_BMS2003
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ushort *dbuf;
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volatile ushort *pbuf;
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@ -861,6 +877,25 @@ output_data(int dev, ulong *sect_buf, int words)
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__asm__ volatile ("eieio");
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*pbuf = *dbuf++;
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}
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#else /* CONFIG_BMS2003 */
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uchar *dbuf;
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volatile uchar *pbuf_even;
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volatile uchar *pbuf_odd;
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pbuf_even = (uchar *)(ATA_CURR_BASE(dev)+ATA_DATA_EVEN);
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pbuf_odd = (uchar *)(ATA_CURR_BASE(dev)+ATA_DATA_ODD);
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dbuf = (uchar *)sect_buf;
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while (words--) {
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__asm__ volatile ("eieio");
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*pbuf_even = *dbuf++;
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__asm__ volatile ("eieio");
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*pbuf_odd = *dbuf++;
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__asm__ volatile ("eieio");
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*pbuf_even = *dbuf++;
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__asm__ volatile ("eieio");
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*pbuf_odd = *dbuf++;
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}
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#endif /* CONFIG_BMS2003 */
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}
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#else /* ! __PPC__ */
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static void
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@ -874,6 +909,7 @@ output_data(int dev, ulong *sect_buf, int words)
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static void
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input_data(int dev, ulong *sect_buf, int words)
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{
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#ifndef CONFIG_BMS2003
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ushort *dbuf;
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volatile ushort *pbuf;
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@ -885,6 +921,25 @@ input_data(int dev, ulong *sect_buf, int words)
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__asm__ volatile ("eieio");
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*dbuf++ = *pbuf;
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}
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#else /* CONFIG_BMS2003 */
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uchar *dbuf;
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volatile uchar *pbuf_even;
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volatile uchar *pbuf_odd;
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pbuf_even = (uchar *)(ATA_CURR_BASE(dev)+ATA_DATA_EVEN);
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pbuf_odd = (uchar *)(ATA_CURR_BASE(dev)+ATA_DATA_ODD);
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dbuf = (uchar *)sect_buf;
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while (words--) {
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__asm__ volatile ("eieio");
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*dbuf++ = *pbuf_even;
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__asm__ volatile ("eieio");
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*dbuf++ = *pbuf_odd;
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__asm__ volatile ("eieio");
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*dbuf++ = *pbuf_even;
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__asm__ volatile ("eieio");
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*dbuf++ = *pbuf_odd;
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}
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#endif /* CONFIG_BMS2003 */
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}
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#else /* ! __PPC__ */
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static void
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@ -1409,6 +1464,7 @@ static void ide_led (uchar led, uchar status)
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static void
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output_data_shorts(int dev, ushort *sect_buf, int shorts)
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{
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#ifndef CONFIG_BMS2003
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ushort *dbuf;
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volatile ushort *pbuf;
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@ -1418,11 +1474,26 @@ output_data_shorts(int dev, ushort *sect_buf, int shorts)
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__asm__ volatile ("eieio");
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*pbuf = *dbuf++;
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}
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#else /* CONFIG_BMS2003 */
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uchar *dbuf;
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volatile uchar *pbuf_even;
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volatile uchar *pbuf_odd;
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pbuf_even = (uchar *)(ATA_CURR_BASE(dev)+ATA_DATA_EVEN);
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pbuf_odd = (uchar *)(ATA_CURR_BASE(dev)+ATA_DATA_ODD);
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while (shorts--) {
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__asm__ volatile ("eieio");
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*pbuf_even = *dbuf++;
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__asm__ volatile ("eieio");
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*pbuf_odd = *dbuf++;
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}
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#endif /* CONFIG_BMS2003 */
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}
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static void
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input_data_shorts(int dev, ushort *sect_buf, int shorts)
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{
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#ifndef CONFIG_BMS2003
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ushort *dbuf;
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volatile ushort *pbuf;
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@ -1432,6 +1503,20 @@ input_data_shorts(int dev, ushort *sect_buf, int shorts)
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__asm__ volatile ("eieio");
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*dbuf++ = *pbuf;
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}
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#else /* CONFIG_BMS2003 */
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uchar *dbuf;
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volatile uchar *pbuf_even;
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volatile uchar *pbuf_odd;
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pbuf_even = (uchar *)(ATA_CURR_BASE(dev)+ATA_DATA_EVEN);
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pbuf_odd = (uchar *)(ATA_CURR_BASE(dev)+ATA_DATA_ODD);
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while (shorts--) {
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__asm__ volatile ("eieio");
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*dbuf++ = *pbuf_even;
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__asm__ volatile ("eieio");
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*dbuf++ = *pbuf_odd;
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}
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#endif /* CONFIG_BMS2003 */
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}
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#else /* ! __PPC__ */
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@ -229,7 +229,7 @@ int pcmcia_on (void)
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#endif /* CONFIG_IDE_8xx_PCCARD */
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#ifdef CONFIG_BMS2003
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case 3: { /* map I/O window for 4xUART data/ctrl */
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win->br += 0x140000;
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win->br += 0x40000;
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win->or = ( PCMCIA_BSIZE_256K
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| PCMCIA_PPS_8
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| PCMCIA_PRS_IO
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@ -622,6 +622,7 @@ static int hardware_enable(int slot)
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PCMCIA_PGCRX(slot) = reg;
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udelay(500);
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#ifndef CONFIG_BMS2003
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#ifndef CONFIG_NSCU
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/*
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* Configure Port C pins for
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@ -633,6 +634,16 @@ static int hardware_enable(int slot)
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immap->im_ioport.iop_pcdat &= ~(0x0002 | 0x0004);
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#endif
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#else /* CONFIG_BMS2003 */
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/*
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* Configure Port B pins for
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* 5 Volts Enable and 3 Volts enable
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*/
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immap->im_cpm.cp_pbpar &= ~(0x00000300);
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/* remove all power */
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immap->im_cpm.cp_pbdat |= 0x00000300;
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#endif /* CONFIG_BMS2003 */
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/*
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* Make sure there is a card in the slot, then configure the interface.
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debug ("[%d] %s: PIPR(%p)=0x%x\n",
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__LINE__,__FUNCTION__,
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&(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
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#ifndef CONFIG_BMS2003
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if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
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#else
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if (pcmp->pcmc_pipr & (0x10000000 >> (slot << 4))) {
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#endif /* CONFIG_BMS2003 */
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printf (" No Card found\n");
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return (1);
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}
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(reg&PCMCIA_VS2(slot))?"n":"ff");
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#ifndef CONFIG_NSCU
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if ((reg & mask) == mask) {
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#ifndef CONFIG_BMS2003
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immap->im_ioport.iop_pcdat |= 0x0004;
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#else
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immap->im_cpm.cp_pbdat &= ~(0x0000100);
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#endif /* CONFIG_BMS2003 */
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puts (" 5.0V card found: ");
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} else {
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#ifndef CONFIG_BMS2003
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immap->im_ioport.iop_pcdat |= 0x0002;
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#else
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immap->im_cpm.cp_pbdat &= ~(0x0000200);
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#endif /* CONFIG_BMS2003 */
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puts (" 3.3V card found: ");
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}
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#ifndef CONFIG_BMS2003
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immap->im_ioport.iop_pcdir |= (0x0002 | 0x0004);
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#else
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immap->im_cpm.cp_pbdir |= 0x00000300;
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#endif /* CONFIG_BMS2003 */
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#else
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if ((reg & mask) == mask) {
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puts (" 5.0V card found: ");
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@ -708,10 +735,14 @@ static int hardware_disable(int slot)
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immap = (immap_t *)CFG_IMMR;
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pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
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#ifndef CONFIG_BMS2003
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#ifndef CONFIG_NSCU
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/* remove all power */
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immap->im_ioport.iop_pcdat &= ~(0x0002 | 0x0004);
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#endif
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#else /* CONFIG_BMS2003 */
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immap->im_cpm.cp_pbdat |= 0x00000300;
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#endif /* CONFIG_BMS2003 */
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debug ("Disable PCMCIA buffers and assert RESET\n");
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reg = 0;
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@ -761,6 +792,7 @@ static int voltage_set(int slot, int vcc, int vpp)
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PCMCIA_PGCRX(slot) = reg;
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udelay(500);
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#ifndef CONFIG_BMS2003
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/*
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* Configure Port C pins for
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* 5 Volts Enable and 3 Volts enable,
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@ -778,6 +810,26 @@ static int voltage_set(int slot, int vcc, int vpp)
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case 50: reg |= 0x0004; break;
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default: goto done;
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}
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#else /* CONFIG_BMS2003 */
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/*
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* Configure Port B pins for
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* 5 Volts Enable and 3 Volts enable,
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* Turn off all power
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*/
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debug ("PCMCIA power OFF\n");
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immap->im_cpm.cp_pbpar &= ~(0x00000300);
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/* remove all power */
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immap->im_cpm.cp_pbdat |= 0x00000300;
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reg = 0;
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switch(vcc) {
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case 0: break;
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case 33: reg |= 0x00000200; break;
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case 50: reg |= 0x00000100; break;
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default: goto done;
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}
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#endif /* CONFIG_BMS2003 */
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/* Checking supported voltages */
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@ -785,11 +837,21 @@ static int voltage_set(int slot, int vcc, int vpp)
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pcmp->pcmc_pipr,
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(pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V");
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#ifndef CONFIG_BMS2003
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immap->im_ioport.iop_pcdat |= reg;
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immap->im_ioport.iop_pcdir |= (0x0002 | 0x0004);
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#else
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immap->im_cpm.cp_pbdat &= !reg;
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immap->im_cpm.cp_pbdir |= 0x00000300;
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#endif /* CONFIG_BMS2003 */
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if (reg) {
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#ifndef CONFIG_BMS2003
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debug ("PCMCIA powered at %sV\n",
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(reg&0x0004) ? "5.0" : "3.3");
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#else
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debug ("PCMCIA powered at %sV\n",
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(reg&0x00000200) ? "5.0" : "3.3");
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#endif /* CONFIG_BMS2003 */
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} else {
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debug ("PCMCIA powered down\n");
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}
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@ -1774,7 +1836,11 @@ static int hardware_enable (int slot)
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debug ("[%d] %s: PIPR(%p)=0x%x\n",
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__LINE__,__FUNCTION__,
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&(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
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#ifndef CONFIG_BMS2003
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if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
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#else
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if (pcmp->pcmc_pipr & (0x10000000 >> (slot << 4))) {
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#endif /* CONFIG_BMS2003 */
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printf (" No Card found\n");
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return (1);
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}
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@ -128,6 +128,9 @@ static __inline__ int au_ffs(int x)
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#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
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#endif
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#define CP0_IWATCHLO $18,1
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#define CP0_DEBUG $23
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/* SDRAM Controller */
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#define MEM_SDMODE0 0xB4000000
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#define MEM_SDMODE1 0xB4000004
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@ -56,6 +56,8 @@
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#define ATA_CYL_HIGH ATA_IO_REG(5)
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#define ATA_DEV_HD ATA_IO_REG(6)
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#define ATA_COMMAND ATA_IO_REG(7)
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#define ATA_DATA_EVEN ATA_IO_REG(8)
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#define ATA_DATA_ODD ATA_IO_REG(9)
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#define ATA_STATUS ATA_COMMAND
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#define ATA_DEV_CTL ATA_IO_ALT(6)
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#define ATA_LBA_LOW ATA_SECT_NUM
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@ -80,17 +80,13 @@
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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#ifdef CONFIG_LCD
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#if defined(CONFIG_LCD)
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# undef CONFIG_STATUS_LED /* disturbs display */
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#else
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# define CONFIG_STATUS_LED 1 /* Status LED enabled */
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#endif /* CONFIG_LCD */
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#ifdef CONFIG_BMS2003
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# define CONFIG_CAN_DRIVER 1 /* CAN Driver support enabled */
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#else
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# undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
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#endif
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#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
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#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
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515
include/configs/bms2003.h
Normal file
515
include/configs/bms2003.h
Normal file
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@ -0,0 +1,515 @@
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/*
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* (C) Copyright 2000-2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
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*
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* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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||||
*/
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
* (easy to change)
|
||||
*/
|
||||
|
||||
#define CONFIG_BMS2003
|
||||
#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
|
||||
#define CONFIG_TQM823L 1 /* ...on a TQM8xxL module */
|
||||
|
||||
#define CONFIG_LCD
|
||||
#define CONFIG_NEC_NL6448BC33_54 /* NEC NL6448BC33_54 display */
|
||||
|
||||
#ifdef CONFIG_LCD /* with LCD controller ? */
|
||||
#define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/
|
||||
#endif
|
||||
|
||||
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
|
||||
#undef CONFIG_8xx_CONS_SMC2
|
||||
#undef CONFIG_8xx_CONS_NONE
|
||||
#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
|
||||
|
||||
#define CONFIG_BOOTCOUNT_LIMIT
|
||||
|
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
|
||||
|
||||
#define CONFIG_BOARD_TYPES 1 /* support board types */
|
||||
|
||||
#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
|
||||
|
||||
#undef CONFIG_BOOTARGS
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"netdev=eth0\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=$(serverip):$(rootpath)\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"addip=setenv bootargs $(bootargs) " \
|
||||
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
|
||||
":$(hostname):$(netdev):off panic=1\0" \
|
||||
"flash_nfs=run nfsargs addip;" \
|
||||
"bootm $(kernel_addr)\0" \
|
||||
"flash_self=run ramargs addip;" \
|
||||
"bootm $(kernel_addr) $(ramdisk_addr)\0" \
|
||||
"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
|
||||
"rootpath=/opt/eldk/ppc_8xx\0" \
|
||||
"bootfile=/tftpboot/TQM860L/uImage\0" \
|
||||
"kernel_addr=40040000\0" \
|
||||
"ramdisk_addr=40100000\0" \
|
||||
""
|
||||
#define CONFIG_BOOTCOMMAND "run flash_self"
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
|
||||
|
||||
/* enable I2C and select the hardware/software driver */
|
||||
#undef CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
|
||||
|
||||
#define CFG_I2C_SPEED 40000 /* 40 kHz is supposed to work */
|
||||
#define CFG_I2C_SLAVE 0xFE
|
||||
|
||||
/* Software (bit-bang) I2C driver configuration */
|
||||
#define PB_SCL 0x00000020 /* PB 26 */
|
||||
#define PB_SDA 0x00000010 /* PB 27 */
|
||||
|
||||
#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
|
||||
#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
|
||||
#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
|
||||
#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
|
||||
#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
|
||||
else immr->im_cpm.cp_pbdat &= ~PB_SDA
|
||||
#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
|
||||
else immr->im_cpm.cp_pbdat &= ~PB_SCL
|
||||
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
|
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||
|
||||
#define CONFIG_STATUS_LED 1 /* Status LED enabled */
|
||||
|
||||
#define CONFIG_CAN_DRIVER 1 /* CAN Driver support enabled */
|
||||
|
||||
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
|
||||
|
||||
#define CONFIG_MAC_PARTITION
|
||||
#define CONFIG_DOS_PARTITION
|
||||
|
||||
#define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */
|
||||
#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
|
||||
|
||||
#ifdef CONFIG_SPLASH_SCREEN
|
||||
# define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
|
||||
CFG_CMD_ASKENV | \
|
||||
CFG_CMD_BMP | \
|
||||
CFG_CMD_DATE | \
|
||||
CFG_CMD_DHCP | \
|
||||
CFG_CMD_I2C | \
|
||||
CFG_CMD_IDE )
|
||||
#else
|
||||
# define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
|
||||
CFG_CMD_ASKENV | \
|
||||
CFG_CMD_DATE | \
|
||||
CFG_CMD_DHCP | \
|
||||
CFG_CMD_I2C | \
|
||||
CFG_CMD_IDE )
|
||||
#endif
|
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
|
||||
#include <cmd_confdefs.h>
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CFG_LONGHELP /* undef to save memory */
|
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
|
||||
|
||||
#if 0
|
||||
#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
|
||||
#endif
|
||||
#ifdef CFG_HUSH_PARSER
|
||||
#define CFG_PROMPT_HUSH_PS2 "> "
|
||||
#endif
|
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CFG_MAXARGS 16 /* max number of command args */
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
|
||||
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
|
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */
|
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
|
||||
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
||||
|
||||
/*
|
||||
* Low Level Configuration Settings
|
||||
* (address mappings, register initial values, etc.)
|
||||
* You should know what you are doing if you make changes here.
|
||||
*/
|
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Memory Mapped Register
|
||||
*/
|
||||
#define CFG_IMMR 0xFFF00000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM)
|
||||
*/
|
||||
#define CFG_INIT_RAM_ADDR CFG_IMMR
|
||||
#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
|
||||
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
|
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
|
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration
|
||||
* (Set up by the startup code)
|
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0
|
||||
*/
|
||||
#define CFG_SDRAM_BASE 0x00000000
|
||||
#define CFG_FLASH_BASE 0x40000000
|
||||
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
|
||||
#define CFG_MONITOR_BASE CFG_FLASH_BASE
|
||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization
|
||||
*/
|
||||
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
|
||||
#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
|
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
|
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
|
||||
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
|
||||
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
|
||||
|
||||
/* Address and size of Redundant Environment Sector */
|
||||
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
|
||||
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Hardware Information Block
|
||||
*/
|
||||
#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
|
||||
#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
|
||||
#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration
|
||||
*/
|
||||
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 11-9
|
||||
* SYPCR can only be written once after reset!
|
||||
*-----------------------------------------------------------------------
|
||||
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
|
||||
*/
|
||||
#if defined(CONFIG_WATCHDOG)
|
||||
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
|
||||
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
|
||||
#else
|
||||
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 11-6
|
||||
*-----------------------------------------------------------------------
|
||||
* PCMCIA config., multi-function pin tri-state
|
||||
*/
|
||||
#ifndef CONFIG_CAN_DRIVER
|
||||
#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
|
||||
#else /* we must activate GPL5 in the SIUMCR for CAN */
|
||||
#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
|
||||
#endif /* CONFIG_CAN_DRIVER */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TBSCR - Time Base Status and Control 11-26
|
||||
*-----------------------------------------------------------------------
|
||||
* Clear Reference Interrupt Status, Timebase freezing enabled
|
||||
*/
|
||||
#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RTCSC - Real-Time Clock Status and Control Register 11-27
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 11-31
|
||||
*-----------------------------------------------------------------------
|
||||
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
|
||||
*/
|
||||
#define CFG_PISCR (PISCR_PS | PISCR_PITF)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
|
||||
*-----------------------------------------------------------------------
|
||||
* Reset PLL lock status sticky bit, timer expired status bit and timer
|
||||
* interrupt status bit
|
||||
*
|
||||
* If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
|
||||
*/
|
||||
#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
|
||||
#define CFG_PLPRCR \
|
||||
( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
|
||||
#else /* up to 66 MHz we use a 1:1 clock */
|
||||
#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
|
||||
#endif /* CONFIG_80MHz */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27
|
||||
*-----------------------------------------------------------------------
|
||||
* Set clock output, timebase and RTC source and divider,
|
||||
* power management and some other internal clocks
|
||||
*/
|
||||
#define SCCR_MASK SCCR_EBDF11
|
||||
#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
|
||||
#define CFG_SCCR (/* SCCR_TBS | */ \
|
||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00)
|
||||
#else /* up to 66 MHz we use a 1:1 clock */
|
||||
#define CFG_SCCR (SCCR_TBS | \
|
||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00)
|
||||
#endif /* CONFIG_80MHz */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCMCIA stuff
|
||||
*-----------------------------------------------------------------------
|
||||
*
|
||||
*/
|
||||
#ifndef CONFIG_BMS2003
|
||||
#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
|
||||
#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
|
||||
#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
|
||||
#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
|
||||
#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
|
||||
#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
|
||||
#define CFG_PCMCIA_IO_ADDR (0xEC000000)
|
||||
#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
|
||||
#else /* CONFIG_BMS2003 */
|
||||
#define CFG_PCMCIA_MEM_ADDR (0xE0100000)
|
||||
#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
|
||||
#define CFG_PCMCIA_DMA_ADDR (0xE4100000)
|
||||
#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
|
||||
#define CFG_PCMCIA_ATTRB_ADDR (0xE8100000)
|
||||
#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
|
||||
#define CFG_PCMCIA_IO_ADDR (0xEC100000)
|
||||
#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
|
||||
#define NSCU_OE_INV 1 /* PCMCIA_GCRX_CXOE is inverted */
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
|
||||
|
||||
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
|
||||
#undef CONFIG_IDE_LED /* LED for ide not supported */
|
||||
#undef CONFIG_IDE_RESET /* reset for ide not supported */
|
||||
|
||||
#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
|
||||
#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
|
||||
|
||||
#define CFG_ATA_IDE0_OFFSET 0x0000
|
||||
|
||||
#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
|
||||
|
||||
/* Offset for data I/O */
|
||||
#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
|
||||
|
||||
/* Offset for normal register accesses */
|
||||
#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
|
||||
|
||||
/* Offset for alternate registers */
|
||||
#define CFG_ATA_ALT_OFFSET 0x0100
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*
|
||||
*-----------------------------------------------------------------------
|
||||
*
|
||||
*/
|
||||
#define CFG_DER 0
|
||||
|
||||
/*
|
||||
* Init Memory Controller:
|
||||
*
|
||||
* BR0/1 and OR0/1 (FLASH)
|
||||
*/
|
||||
|
||||
#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
|
||||
#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
|
||||
|
||||
/* used to re-map FLASH both when starting from SRAM or FLASH:
|
||||
* restrict access enough to keep SRAM working (if any)
|
||||
* but not too much to meddle with FLASH accesses
|
||||
*/
|
||||
#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
|
||||
#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
|
||||
|
||||
/*
|
||||
* FLASH timing:
|
||||
*/
|
||||
#if defined(CONFIG_80MHz)
|
||||
/* 80 MHz CPU - 40 MHz bus: ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | 0 | OR_CSNT_SAM | \
|
||||
OR_SCY_3_CLK | OR_EHTR | OR_BI)
|
||||
#elif defined(CONFIG_66MHz)
|
||||
/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
|
||||
OR_SCY_3_CLK | OR_EHTR | OR_BI)
|
||||
#else /* 50 MHz */
|
||||
/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
|
||||
OR_SCY_2_CLK | OR_EHTR | OR_BI)
|
||||
#endif /*CONFIG_??MHz */
|
||||
|
||||
#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
|
||||
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
|
||||
#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
|
||||
|
||||
#define CFG_OR1_REMAP CFG_OR0_REMAP
|
||||
#define CFG_OR1_PRELIM CFG_OR0_PRELIM
|
||||
#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
|
||||
|
||||
/*
|
||||
* BR2/3 and OR2/3 (SDRAM)
|
||||
*
|
||||
*/
|
||||
#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
|
||||
#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
|
||||
#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
|
||||
|
||||
/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
|
||||
#define CFG_OR_TIMING_SDRAM 0x00000A00
|
||||
|
||||
#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
|
||||
#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
|
||||
|
||||
#ifndef CONFIG_CAN_DRIVER
|
||||
#define CFG_OR3_PRELIM CFG_OR2_PRELIM
|
||||
#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
|
||||
#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
|
||||
#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
|
||||
#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
|
||||
#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI)
|
||||
#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \
|
||||
BR_PS_8 | BR_MS_UPMB | BR_V )
|
||||
#endif /* CONFIG_CAN_DRIVER */
|
||||
|
||||
/*
|
||||
* Memory Periodic Timer Prescaler
|
||||
*
|
||||
* The Divider for PTA (refresh timer) configuration is based on an
|
||||
* example SDRAM configuration (64 MBit, one bank). The adjustment to
|
||||
* the number of chip selects (NCS) and the actually needed refresh
|
||||
* rate is done by setting MPTPR.
|
||||
*
|
||||
* PTA is calculated from
|
||||
* PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
|
||||
*
|
||||
* gclk CPU clock (not bus clock!)
|
||||
* Trefresh Refresh cycle * 4 (four word bursts used)
|
||||
*
|
||||
* 4096 Rows from SDRAM example configuration
|
||||
* 1000 factor s -> ms
|
||||
* 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
|
||||
* 4 Number of refresh cycles per period
|
||||
* 64 Refresh cycle in ms per number of rows
|
||||
* --------------------------------------------
|
||||
* Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
|
||||
*
|
||||
* 50 MHz => 50.000.000 / Divider = 98
|
||||
* 66 Mhz => 66.000.000 / Divider = 129
|
||||
* 80 Mhz => 80.000.000 / Divider = 156
|
||||
*/
|
||||
#if defined(CONFIG_80MHz)
|
||||
#define CFG_MAMR_PTA 156
|
||||
#elif defined(CONFIG_66MHz)
|
||||
#define CFG_MAMR_PTA 129
|
||||
#else /* 50 MHz */
|
||||
#define CFG_MAMR_PTA 98
|
||||
#endif /*CONFIG_??MHz */
|
||||
|
||||
/*
|
||||
* For 16 MBit, refresh rates could be 31.3 us
|
||||
* (= 64 ms / 2K = 125 / quad bursts).
|
||||
* For a simpler initialization, 15.6 us is used instead.
|
||||
*
|
||||
* #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
|
||||
* #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
|
||||
*/
|
||||
#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
|
||||
#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
|
||||
|
||||
/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
|
||||
#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
|
||||
#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
|
||||
|
||||
/*
|
||||
* MAMR settings for SDRAM
|
||||
*/
|
||||
|
||||
/* 8 column SDRAM */
|
||||
#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
|
||||
MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
|
||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
|
||||
/* 9 column SDRAM */
|
||||
#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
|
||||
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
|
||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
|
||||
|
||||
|
||||
/*
|
||||
* Internal Definitions
|
||||
*
|
||||
* Boot Flags
|
||||
*/
|
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
|
@ -43,7 +43,7 @@ void status_led_tick (unsigned long timestamp);
|
|||
void status_led_set (int led, int state);
|
||||
|
||||
/***** TQM8xxL ********************************************************/
|
||||
#if defined(CONFIG_TQM8xxL)
|
||||
#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_BMS2003)
|
||||
# define STATUS_LED_PAR im_cpm.cp_pbpar
|
||||
# define STATUS_LED_DIR im_cpm.cp_pbdir
|
||||
# define STATUS_LED_ODR im_cpm.cp_pbodr
|
||||
|
|
@ -318,6 +318,21 @@ void status_led_set (int led, int state);
|
|||
|
||||
# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
|
||||
|
||||
/***** BMS2003 ********************************************************/
|
||||
#elif defined(CONFIG_BMS2003)
|
||||
# define STATUS_LED_PAR im_ioport.iop_papar
|
||||
# define STATUS_LED_DIR im_ioport.iop_padir
|
||||
# define STATUS_LED_ODR im_ioport.iop_paodr
|
||||
# define STATUS_LED_DAT im_ioport.iop_padat
|
||||
|
||||
# define STATUS_LED_BIT 0x00000001 /* LED is on PA15 */
|
||||
# define STATUS_LED_PERIOD (CFG_HZ / 2)
|
||||
# define STATUS_LED_STATE STATUS_LED_BLINKING
|
||||
|
||||
# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
|
||||
|
||||
# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
|
||||
|
||||
/************************************************************************/
|
||||
#else
|
||||
# error Status LED configuration missing
|
||||
|
|
|
|||
Loading…
Reference in a new issue