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mmc: omap_hsmmc: Reduce the max timeout for reset controller fsm

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>From OMAP3 SoCs (OMAP3, OMAP4, OMAP5, AM572x, AM571x), the DAT/CMD lines
reset procedure section in TRM suggests to first poll the SRD/SRC bit
until it is set to 0x1. But looks like that bit is never set to 1 and there
is an observable delay of 1sec everytime the driver tries to reset DAT/CMD.
(The same is observed in linux kernel).

Reduce the time the driver waits for the controller to set the SRC/SRD bits
to 1 so that there is no observable delay.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
This commit is contained in:
Jean-Jacques Hiblot 2018-01-30 16:01:37 +01:00 committed by Jaehoon Chung
parent 2faa1a302b
commit a4efd73773
1 changed files with 2 additions and 1 deletions
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3
drivers/mmc/omap_hsmmc.c
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@ -108,6 +108,7 @@ struct omap_hsmmc_adma_desc {
/* If we fail after 1 second wait, something is really bad */
#define MAX_RETRY_MS 1000
#define MMC_TIMEOUT_MS 20
/* DMA transfers can take a long time if a lot a data is transferred.
* The timeout must take in account the amount of data. Let's assume
@ -598,7 +599,7 @@ static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
if (!(readl(&mmc_base->sysctl) & bit)) {
start = get_timer(0);
while (!(readl(&mmc_base->sysctl) & bit)) {
if (get_timer(0) - start > MAX_RETRY_MS)
if (get_timer(0) - start > MMC_TIMEOUT_MS)
return;
}
}