Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2024-09-20 14:41:58 +00:00
Code Issues Projects Releases Packages Wiki Activity

arm: Remove PXA architecture support

Browse source 
With the last platform for this architecture removed, remove the rest of
the architecture support as well.

Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Tom Rini 2022-06-25 11:02:42 -04:00
parent fcf4fa71ab
commit a457ebd786
42 changed files with 3 additions and 6417 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

7
MAINTAINERS
View file

@ -348,13 +348,6 @@ S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-marvell.git
F: drivers/serial/serial_mvebu_a3700.c
ARM MARVELL PXA
M: Marek Vasut <marex@denx.de>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-pxa.git
F: arch/arm/cpu/pxa/
F: arch/arm/include/asm/arch-pxa/
ARM MEDIATEK
M: Ryder Lee <ryder.lee@mediatek.com>
M: Weijie Gao <weijie.gao@mediatek.com>

7
README
View file

@ -850,13 +850,6 @@ The following options need to be configured:
the appropriate value in Hz.
- MMC Support:
The MMC controller on the Intel PXA is supported. To
enable this define CONFIG_MMC. The MMC can be
accessed from the boot prompt by mapping the device
to physical memory similar to flash. Command line is
enabled with CONFIG_CMD_MMC. The MMC driver also works with
the FAT fs. This is enabled with CONFIG_CMD_FAT.
CONFIG_SH_MMCIF
Support for Renesas on-chip MMCIF controller

14
arch/arm/Kconfig
View file

@ -330,15 +330,6 @@ config CPU_V7R
select SYS_ARM_MPU
select SYS_CACHE_SHIFT_6
config CPU_PXA
bool
select SYS_CACHE_SHIFT_5
imply SYS_ARM_MMU
config CPU_PXA27X
bool
select CPU_PXA
config CPU_SA1100
bool
select SYS_CACHE_SHIFT_5
@ -354,7 +345,6 @@ config SYS_CPU
default "armv7" if CPU_V7A
default "armv7" if CPU_V7R
default "armv7m" if CPU_V7M
default "pxa" if CPU_PXA
default "sa1100" if CPU_SA1100
default "armv8" if ARM64
@ -369,14 +359,12 @@ config SYS_ARM_ARCH
default 7 if CPU_V7A
default 7 if CPU_V7M
default 7 if CPU_V7R
default 5 if CPU_PXA
default 4 if CPU_SA1100
default 8 if ARM64
choice
prompt "Select the ARM data write cache policy"
default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || \
CPU_PXA || RZA1
default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || RZA1
default SYS_ARM_CACHE_WRITEBACK
config SYS_ARM_CACHE_WRITEBACK

2
arch/arm/Makefile
View file

@ -11,7 +11,6 @@ arch-$(CONFIG_CPU_ARM920T) =-march=armv4t
arch-$(CONFIG_CPU_ARM926EJS) =-march=armv5te
arch-$(CONFIG_CPU_ARM946ES) =-march=armv5te
arch-$(CONFIG_CPU_SA1100) =-march=armv4
arch-$(CONFIG_CPU_PXA) =
arch-$(CONFIG_CPU_ARM1136) =-march=armv5t
arch-$(CONFIG_CPU_ARM1176) =-march=armv5t
arch-$(CONFIG_CPU_V7A) =$(call cc-option, -march=armv7-a, \
@ -41,7 +40,6 @@ tune-$(CONFIG_CPU_ARM920T) =
tune-$(CONFIG_CPU_ARM926EJS) =
tune-$(CONFIG_CPU_ARM946ES) =
tune-$(CONFIG_CPU_SA1100) =-mtune=strongarm1100
tune-$(CONFIG_CPU_PXA) =-mcpu=xscale
tune-$(CONFIG_CPU_ARM1136) =
tune-$(CONFIG_CPU_ARM1176) =
tune-$(CONFIG_CPU_V7A) =-mtune=generic-armv7-a

14
arch/arm/cpu/pxa/Makefile
View file

@ -1,14 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
extra-y = start.o
obj-$(CONFIG_CPU_PXA27X) += pxa2xx.o
obj-y += cpuinfo.o
obj-y += timer.o
obj-y += usb.o
obj-y += relocate.o
obj-y += cache.o

58
arch/arm/cpu/pxa/cache.c
View file

@ -1,58 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2016 Vasily Khoruzhick <anarsoul@gmail.com>
*/
#include <cpu_func.h>
#include <asm/cache.h>
#include <linux/types.h>
#include <common.h>
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void invalidate_dcache_all(void)
{
/* Flush/Invalidate I cache */
asm volatile("mcr p15, 0, %0, c7, c5, 0\n" : : "r"(0));
/* Flush/Invalidate D cache */
asm volatile("mcr p15, 0, %0, c7, c6, 0\n" : : "r"(0));
}
void flush_dcache_all(void)
{
return invalidate_dcache_all();
}
void invalidate_dcache_range(unsigned long start, unsigned long stop)
{
start &= ~(CONFIG_SYS_CACHELINE_SIZE - 1);
stop &= ~(CONFIG_SYS_CACHELINE_SIZE - 1);
while (start <= stop) {
asm volatile("mcr p15, 0, %0, c7, c6, 1\n" : : "r"(start));
start += CONFIG_SYS_CACHELINE_SIZE;
}
}
void flush_dcache_range(unsigned long start, unsigned long stop)
{
return invalidate_dcache_range(start, stop);
}
#else /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
void invalidate_dcache_all(void)
{
}
void flush_dcache_all(void)
{
}
#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
/*
* Stub implementations for l2 cache operations
*/
__weak void l2_cache_disable(void) {}
#if CONFIG_IS_ENABLED(SYS_THUMB_BUILD)
__weak void invalidate_l2_cache(void) {}
#endif

18
arch/arm/cpu/pxa/config.mk
View file

@ -1,18 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2002
# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
# Marius Groeger <mgroeger@sysgo.de>
#
# !WARNING!
# The PXA's OneNAND SPL uses .text.0 and .text.1 segments to allow booting from
# really small OneNAND memories where the mmap'd window is only 1KiB big. The
# .text.0 contains only the bare minimum needed to load the real SPL into SRAM.
# Add .text.0 and .text.1 into OBJFLAGS, so when the SPL is being objcopy'd,
# they are not discarded.
#
#ifdef CONFIG_SPL_BUILD
OBJCOPYFLAGS += -j .text.0 -j .text.1
#endif

139
arch/arm/cpu/pxa/cpuinfo.c
View file

@ -1,139 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* PXA CPU information display
*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
*/
#include <common.h>
#include <init.h>
#include <asm/io.h>
#include <errno.h>
#include <linux/compiler.h>
#define CPU_MASK_PXA_PRODID 0x000003f0
#define CPU_MASK_PXA_REVID 0x0000000f
#define CPU_MASK_PRODREV (CPU_MASK_PXA_PRODID | CPU_MASK_PXA_REVID)
#define CPU_VALUE_PXA25X 0x100
#define CPU_VALUE_PXA27X 0x110
static uint32_t pxa_get_cpuid(void)
{
uint32_t cpuid;
asm volatile("mrc p15, 0, %0, c0, c0, 0" : "=r"(cpuid));
return cpuid;
}
int cpu_is_pxa25x(void)
{
uint32_t id = pxa_get_cpuid();
id &= CPU_MASK_PXA_PRODID;
return id == CPU_VALUE_PXA25X;
}
int cpu_is_pxa27x(void)
{
uint32_t id = pxa_get_cpuid();
id &= CPU_MASK_PXA_PRODID;
return id == CPU_VALUE_PXA27X;
}
int cpu_is_pxa27xm(void)
{
uint32_t id = pxa_get_cpuid();
return ((id & CPU_MASK_PXA_PRODID) == CPU_VALUE_PXA27X) &&
((id & CPU_MASK_PXA_REVID) == 8);
}
uint32_t pxa_get_cpu_revision(void)
{
return pxa_get_cpuid() & CPU_MASK_PRODREV;
}
#ifdef CONFIG_DISPLAY_CPUINFO
static const char *pxa25x_get_revision(void)
{
static __maybe_unused const char * const revs_25x[] = { "A0" };
static __maybe_unused const char * const revs_26x[] = {
"A0", "B0", "B1"
};
static const char *unknown = "Unknown";
uint32_t id;
if (!cpu_is_pxa25x())
return unknown;
id = pxa_get_cpuid() & CPU_MASK_PXA_REVID;
/* PXA26x is a sick special case as it can't be told apart from PXA25x :-( */
#ifdef CONFIG_CPU_PXA26X
switch (id) {
case 3: return revs_26x[0];
case 5: return revs_26x[1];
case 6: return revs_26x[2];
}
#else
if (id == 6)
return revs_25x[0];
#endif
return unknown;
}
static const char *pxa27x_get_revision(void)
{
static const char *const rev[] = { "A0", "A1", "B0", "B1", "C0", "C5" };
static const char *unknown = "Unknown";
uint32_t id;
if (!cpu_is_pxa27x())
return unknown;
id = pxa_get_cpuid() & CPU_MASK_PXA_REVID;
if ((id == 5) || (id == 6) || (id > 8))
return unknown;
/* Cap the special PXA270 C5 case. */
if (id == 7)
id = 5;
/* Cap the special PXA270M A1 case. */
if (id == 8)
id = 1;
return rev[id];
}
static int print_cpuinfo_pxa2xx(void)
{
if (cpu_is_pxa25x()) {
puts("Marvell PXA25x rev. ");
puts(pxa25x_get_revision());
} else if (cpu_is_pxa27x()) {
puts("Marvell PXA27x");
if (cpu_is_pxa27xm()) puts("M");
puts(" rev. ");
puts(pxa27x_get_revision());
} else
return -EINVAL;
puts("\n");
return 0;
}
int print_cpuinfo(void)
{
int ret;
puts("CPU: ");
ret = print_cpuinfo_pxa2xx();
if (!ret)
return ret;
return ret;
}
#endif

295
arch/arm/cpu/pxa/pxa2xx.c
View file

@ -1,295 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Alex Zuepke <azu@sysgo.de>
*/
#include <common.h>
#include <cpu_func.h>
#include <init.h>
#include <irq_func.h>
#include <asm/arch/pxa-regs.h>
#include <asm/cache.h>
#include <asm/io.h>
#include <asm/system.h>
#include <command.h>
/* Flush I/D-cache */
static void cache_flush(void)
{
unsigned long i = 0;
asm ("mcr p15, 0, %0, c7, c5, 0" : : "r" (i));
}
int cleanup_before_linux(void)
{
/*
* This function is called just before we call Linux. It prepares
* the processor for Linux by just disabling everything that can
* disturb booting Linux.
*/
disable_interrupts();
icache_disable();
dcache_disable();
cache_flush();
return 0;
}
inline void writelrb(uint32_t val, uint32_t addr)
{
writel(val, addr);
asm volatile("" : : : "memory");
readl(addr);
asm volatile("" : : : "memory");
}
void pxa2xx_dram_init(void)
{
uint32_t tmp;
int i;
/*
* 1) Initialize Asynchronous static memory controller
*/
writelrb(CONFIG_SYS_MSC0_VAL, MSC0);
writelrb(CONFIG_SYS_MSC1_VAL, MSC1);
writelrb(CONFIG_SYS_MSC2_VAL, MSC2);
/*
* 2) Initialize Card Interface
*/
/* MECR: Memory Expansion Card Register */
writelrb(CONFIG_SYS_MECR_VAL, MECR);
/* MCMEM0: Card Interface slot 0 timing */
writelrb(CONFIG_SYS_MCMEM0_VAL, MCMEM0);
/* MCMEM1: Card Interface slot 1 timing */
writelrb(CONFIG_SYS_MCMEM1_VAL, MCMEM1);
/* MCATT0: Card Interface Attribute Space Timing, slot 0 */
writelrb(CONFIG_SYS_MCATT0_VAL, MCATT0);
/* MCATT1: Card Interface Attribute Space Timing, slot 1 */
writelrb(CONFIG_SYS_MCATT1_VAL, MCATT1);
/* MCIO0: Card Interface I/O Space Timing, slot 0 */
writelrb(CONFIG_SYS_MCIO0_VAL, MCIO0);
/* MCIO1: Card Interface I/O Space Timing, slot 1 */
writelrb(CONFIG_SYS_MCIO1_VAL, MCIO1);
/*
* 3) Configure Fly-By DMA register
*/
writelrb(CONFIG_SYS_FLYCNFG_VAL, FLYCNFG);
/*
* 4) Initialize Timing for Sync Memory (SDCLK0)
*/
/*
* Before accessing MDREFR we need a valid DRI field, so we set
* this to power on defaults + DRI field.
*/
/* Read current MDREFR config and zero out DRI */
tmp = readl(MDREFR) & ~0xfff;
/* Add user-specified DRI */
tmp |= CONFIG_SYS_MDREFR_VAL & 0xfff;
/* Configure important bits */
tmp |= MDREFR_K0RUN | MDREFR_SLFRSH;
tmp &= ~(MDREFR_APD | MDREFR_E1PIN);
/* Write MDREFR back */
writelrb(tmp, MDREFR);
/*
* 5) Initialize Synchronous Static Memory (Flash/Peripherals)
*/
/* Initialize SXCNFG register. Assert the enable bits.
*
* Write SXMRS to cause an MRS command to all enabled banks of
* synchronous static memory. Note that SXLCR need not be written
* at this time.
*/
writelrb(CONFIG_SYS_SXCNFG_VAL, SXCNFG);
/*
* 6) Initialize SDRAM
*/
writelrb(CONFIG_SYS_MDREFR_VAL & ~MDREFR_SLFRSH, MDREFR);
writelrb(CONFIG_SYS_MDREFR_VAL | MDREFR_E1PIN, MDREFR);
/*
* 7) Write MDCNFG with MDCNFG:DEx deasserted (set to 0), to configure
* but not enable each SDRAM partition pair.
*/
writelrb(CONFIG_SYS_MDCNFG_VAL &
~(MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3), MDCNFG);
/* Wait for the clock to the SDRAMs to stabilize, 100..200 usec. */
writel(0, OSCR);
while (readl(OSCR) < 0x300)
asm volatile("" : : : "memory");
/*
* 8) Trigger a number (usually 8) refresh cycles by attempting
* non-burst read or write accesses to disabled SDRAM, as commonly
* specified in the power up sequence documented in SDRAM data
* sheets. The address(es) used for this purpose must not be
* cacheable.
*/
for (i = 9; i >= 0; i--) {
writel(i, 0xa0000000);
asm volatile("" : : : "memory");
}
/*
* 9) Write MDCNFG with enable bits asserted (MDCNFG:DEx set to 1).
*/
tmp = CONFIG_SYS_MDCNFG_VAL &
(MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3);
tmp |= readl(MDCNFG);
writelrb(tmp, MDCNFG);
/*
* 10) Write MDMRS.
*/
writelrb(CONFIG_SYS_MDMRS_VAL, MDMRS);
/*
* 11) Enable APD
*/
if (CONFIG_SYS_MDREFR_VAL & MDREFR_APD) {
tmp = readl(MDREFR);
tmp |= MDREFR_APD;
writelrb(tmp, MDREFR);
}
}
void pxa_gpio_setup(void)
{
writel(CONFIG_SYS_GPSR0_VAL, GPSR0);
writel(CONFIG_SYS_GPSR1_VAL, GPSR1);
writel(CONFIG_SYS_GPSR2_VAL, GPSR2);
#if defined(CONFIG_CPU_PXA27X)
writel(CONFIG_SYS_GPSR3_VAL, GPSR3);
#endif
writel(CONFIG_SYS_GPCR0_VAL, GPCR0);
writel(CONFIG_SYS_GPCR1_VAL, GPCR1);
writel(CONFIG_SYS_GPCR2_VAL, GPCR2);
#if defined(CONFIG_CPU_PXA27X)
writel(CONFIG_SYS_GPCR3_VAL, GPCR3);
#endif
writel(CONFIG_SYS_GPDR0_VAL, GPDR0);
writel(CONFIG_SYS_GPDR1_VAL, GPDR1);
writel(CONFIG_SYS_GPDR2_VAL, GPDR2);
#if defined(CONFIG_CPU_PXA27X)
writel(CONFIG_SYS_GPDR3_VAL, GPDR3);
#endif
writel(CONFIG_SYS_GAFR0_L_VAL, GAFR0_L);
writel(CONFIG_SYS_GAFR0_U_VAL, GAFR0_U);
writel(CONFIG_SYS_GAFR1_L_VAL, GAFR1_L);
writel(CONFIG_SYS_GAFR1_U_VAL, GAFR1_U);
writel(CONFIG_SYS_GAFR2_L_VAL, GAFR2_L);
writel(CONFIG_SYS_GAFR2_U_VAL, GAFR2_U);
#if defined(CONFIG_CPU_PXA27X)
writel(CONFIG_SYS_GAFR3_L_VAL, GAFR3_L);
writel(CONFIG_SYS_GAFR3_U_VAL, GAFR3_U);
#endif
writel(CONFIG_SYS_PSSR_VAL, PSSR);
}
void pxa_interrupt_setup(void)
{
writel(0, ICLR);
writel(0, ICMR);
#if defined(CONFIG_CPU_PXA27X)
writel(0, ICLR2);
writel(0, ICMR2);
#endif
}
void pxa_clock_setup(void)
{
writel(CONFIG_SYS_CKEN, CKEN);
writel(CONFIG_SYS_CCCR, CCCR);
asm volatile("mcr p14, 0, %0, c6, c0, 0" : : "r"(0x0b));
/* enable the 32Khz oscillator for RTC and PowerManager */
writel(OSCC_OON, OSCC);
while (!(readl(OSCC) & OSCC_OOK))
asm volatile("" : : : "memory");
}
void pxa_wakeup(void)
{
uint32_t rcsr;
rcsr = readl(RCSR);
writel(rcsr & (RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR), RCSR);
/* Wakeup */
if (rcsr & RCSR_SMR) {
writel(PSSR_PH, PSSR);
pxa2xx_dram_init();
icache_disable();
dcache_disable();
asm volatile("mov pc, %0" : : "r"(readl(PSPR)));
}
}
int arch_cpu_init(void)
{
pxa_gpio_setup();
pxa_wakeup();
pxa_interrupt_setup();
pxa_clock_setup();
return 0;
}
void i2c_clk_enable(void)
{
/* Set the global I2C clock on */
writel(readl(CKEN) | CKEN14_I2C, CKEN);
}
void __attribute__((weak)) reset_cpu(void) __attribute__((noreturn));
void reset_cpu(void)
{
uint32_t tmp;
setbits_le32(OWER, OWER_WME);
tmp = readl(OSCR);
tmp += 0x1000;
writel(tmp, OSMR3);
writel(MDREFR_SLFRSH, MDREFR);
for (;;)
;
}
void enable_caches(void)
{
#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
icache_enable();
#endif
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
dcache_enable();
#endif
}

22
arch/arm/cpu/pxa/relocate.S
View file

@ -1,22 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* relocate - PXA270 vector relocation
*
* Copyright (c) 2013 Albert ARIBAUD <albert.u.boot@aribaud.net>
*/
#include <linux/linkage.h>
/*
* The PXA SoC is very specific with respect to exceptions: it
* does not provide RAM at the high vectors address (0xFFFF0000),
* thus only the low address (0x00000000) is useable; but that is
* in ROM, so let's avoid relocating the vectors.
*/
.section .text.relocate_vectors,"ax",%progbits
ENTRY(relocate_vectors)
bx lr
ENDPROC(relocate_vectors)

98
arch/arm/cpu/pxa/start.S
View file

@ -1,98 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* armboot - Startup Code for XScale CPU-core
*
* Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
* Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
* Copyright (C) 2000 Wolfgang Denk <wd@denx.de>
* Copyright (C) 2001 Alex Zuepke <azu@sysgo.de>
* Copyright (C) 2001 Marius Groger <mag@sysgo.de>
* Copyright (C) 2002 Alex Zupke <azu@sysgo.de>
* Copyright (C) 2002 Gary Jennejohn <garyj@denx.de>
* Copyright (C) 2002 Kyle Harris <kharris@nexus-tech.net>
* Copyright (C) 2003 Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de>
* Copyright (C) 2003 Kshitij <kshitij@ti.com>
* Copyright (C) 2003 Richard Woodruff <r-woodruff2@ti.com>
* Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
* Copyright (C) 2004 Texas Instruments <r-woodruff2@ti.com>
* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
*/
#include <asm-offsets.h>
#include <config.h>
/*
*************************************************************************
*
* Startup Code (reset vector)
*
* do important init only if we don't start from memory!
* setup Memory and board specific bits prior to relocation.
* relocate armboot to ram
* setup stack
*
*************************************************************************
*/
.globl reset
reset:
/*
* set the cpu to SVC32 mode
*/
mrs r0,cpsr
bic r0,r0,#0x1f
orr r0,r0,#0xd3
msr cpsr,r0
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
bl cpu_init_crit
#endif
#ifdef CONFIG_CPU_PXA27X
/*
* enable clock for SRAM
*/
ldr r0,=CKEN
ldr r1,[r0]
orr r1,r1,#(1 << 20)
str r1,[r0]
#endif
bl _main
/*------------------------------------------------------------------------------*/
.globl c_runtime_cpu_setup
c_runtime_cpu_setup:
bx lr
/*
*************************************************************************
*
* CPU_init_critical registers
*
* setup important registers
* setup memory timing
*
*************************************************************************
*/
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
cpu_init_crit:
/*
* flush v4 I/D caches
*/
mov r0, #0
mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */
mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */
/*
* disable MMU stuff and caches
*/
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x00003300 @ clear bits 13:12, 9:8 (--VI --RS)
bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
orr r0, r0, #0x00000002 @ set bit 1 (A) Align
mcr p15, 0, r0, c1, c0, 0
mov pc, lr /* back to my caller */
#endif /* !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */

16
arch/arm/cpu/pxa/timer.c
View file

@ -1,16 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Marvell PXA2xx/3xx timer driver
*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
*/
#include <common.h>
#include <init.h>
#include <asm/io.h>
int timer_init(void)
{
writel(0, CONFIG_SYS_TIMER_COUNTER);
return 0;
}

89
arch/arm/cpu/pxa/usb.c
View file

@ -1,89 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2006
* Markus Klotzbuecher, DENX Software Engineering <mk@denx.de>
*/
#include <common.h>
#include <linux/delay.h>
#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
# if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_CPU_PXA27X)
#include <asm/arch/pxa-regs.h>
#include <asm/io.h>
#include <usb.h>
int usb_cpu_init(void)
{
#if defined(CONFIG_CPU_MONAHANS)
/* Enable USB host clock. */
writel(readl(CKENA) | CKENA_2_USBHOST | CKENA_20_UDC, CKENA);
udelay(100);
#endif
#if defined(CONFIG_CPU_PXA27X)
/* Enable USB host clock. */
writel(readl(CKEN) | CKEN10_USBHOST, CKEN);
#endif
#if defined(CONFIG_CPU_MONAHANS)
/* Configure Port 2 for Host (USB Client Registers) */
writel(0x3000c, UP2OCR);
#endif
writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
mdelay(11);
writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
while (readl(UHCHR) & UHCHR_FSBIR)
udelay(1);
#if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X)
writel(readl(UHCHR) & ~UHCHR_SSEP0, UHCHR);
#endif
#if defined(CONFIG_CPU_PXA27X)
writel(readl(UHCHR) & ~UHCHR_SSEP2, UHCHR);
#endif
writel(readl(UHCHR) & ~(UHCHR_SSEP1 | UHCHR_SSE), UHCHR);
return 0;
}
int usb_cpu_stop(void)
{
writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
udelay(11);
writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
writel(readl(UHCCOMS) | UHCCOMS_HCR, UHCCOMS);
udelay(10);
#if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X)
writel(readl(UHCHR) | UHCHR_SSEP0, UHCHR);
#endif
#if defined(CONFIG_CPU_PXA27X)
writel(readl(UHCHR) | UHCHR_SSEP2, UHCHR);
#endif
writel(readl(UHCHR) | UHCHR_SSEP1 | UHCHR_SSE, UHCHR);
#if defined(CONFIG_CPU_MONAHANS)
/* Disable USB host clock. */
writel(readl(CKENA) & ~(CKENA_2_USBHOST | CKENA_20_UDC), CKENA);
udelay(100);
#endif
#if defined(CONFIG_CPU_PXA27X)
/* Disable USB host clock. */
writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
#endif
return 0;
}
int usb_cpu_init_fail(void)
{
return usb_cpu_stop();
}
# endif /* defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_CPU_PXA27X) */
#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */

112
arch/arm/include/asm/arch-pxa/bitfield.h
View file

@ -1,112 +0,0 @@
/*
* FILE bitfield.h
*
* Version 1.1
* Author Copyright (c) Marc A. Viredaz, 1998
* DEC Western Research Laboratory, Palo Alto, CA
* Date April 1998 (April 1997)
* System Advanced RISC Machine (ARM)
* Language C or ARM Assembly
* Purpose Definition of macros to operate on bit fields.
*/
#ifndef __BITFIELD_H
#define __BITFIELD_H
#ifndef __ASSEMBLY__
#define UData(Data) ((unsigned long) (Data))
#else
#define UData(Data) (Data)
#endif
/*
* MACRO: Fld
*
* Purpose
* The macro "Fld" encodes a bit field, given its size and its shift value
* with respect to bit 0.
*
* Note
* A more intuitive way to encode bit fields would have been to use their
* mask. However, extracting size and shift value information from a bit
* field's mask is cumbersome and might break the assembler (255-character
* line-size limit).
*
* Input
* Size Size of the bit field, in number of bits.
* Shft Shift value of the bit field with respect to bit 0.
*
* Output
* Fld Encoded bit field.
*/
#define Fld(Size, Shft) (((Size) << 16) + (Shft))
/*
* MACROS: FSize, FShft, FMsk, FAlnMsk, F1stBit
*
* Purpose
* The macros "FSize", "FShft", "FMsk", "FAlnMsk", and "F1stBit" return
* the size, shift value, mask, aligned mask, and first bit of a
* bit field.
*
* Input
* Field Encoded bit field (using the macro "Fld").
*
* Output
* FSize Size of the bit field, in number of bits.
* FShft Shift value of the bit field with respect to bit 0.
* FMsk Mask for the bit field.
* FAlnMsk Mask for the bit field, aligned on bit 0.
* F1stBit First bit of the bit field.
*/
#define FSize(Field) ((Field) >> 16)
#define FShft(Field) ((Field) & 0x0000FFFF)
#define FMsk(Field) (((UData (1) << FSize (Field)) - 1) << FShft (Field))
#define FAlnMsk(Field) ((UData (1) << FSize (Field)) - 1)
#define F1stBit(Field) (UData (1) << FShft (Field))
/*
* MACRO: FInsrt
*
* Purpose
* The macro "FInsrt" inserts a value into a bit field by shifting the
* former appropriately.
*
* Input
* Value Bit-field value.
* Field Encoded bit field (using the macro "Fld").
*
* Output
* FInsrt Bit-field value positioned appropriately.
*/
#define FInsrt(Value, Field) \
(UData (Value) << FShft (Field))
/*
* MACRO: FExtr
*
* Purpose
* The macro "FExtr" extracts the value of a bit field by masking and
* shifting it appropriately.
*
* Input
* Data Data containing the bit-field to be extracted.
* Field Encoded bit field (using the macro "Fld").
*
* Output
* FExtr Bit-field value.
*/
#define FExtr(Data, Field) \
((UData (Data) >> FShft (Field)) & FAlnMsk (Field))
#endif /* __BITFIELD_H */

22
arch/arm/include/asm/arch-pxa/config.h
View file

@ -1,22 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2014 Andrew Ruder <andrew.ruder@elecsyscorp.com>
*/
#ifndef _ASM_ARM_PXA_CONFIG_
#define _ASM_ARM_PXA_CONFIG_
#include <asm/arch/pxa-regs.h>
/*
* Generic timer support
*/
#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
#define CONFIG_SYS_TIMER_RATE 3250000
#else
#error "Timer frequency unknown - please config PXA CPU type"
#endif
#define CONFIG_SYS_TIMER_COUNTER OSCR
#endif /* _ASM_ARM_PXA_CONFIG_ */

82
arch/arm/include/asm/arch-pxa/hardware.h
View file

@ -1,82 +0,0 @@
/*
* linux/include/asm-arm/arch-pxa/hardware.h
*
* Author: Nicolas Pitre
* Created: Jun 15, 2001
* Copyright: MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Note: This file was taken from linux-2.4.19-rmk4-pxa1
*
* - 2003/01/20 implementation specifics activated
* Robert Schwebel <r.schwebel@pengutronix.de>
*/
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H
#include <asm/mach-types.h>
/*
* Define CONFIG_CPU_MONAHANS in case some CPU of the PXA3xx family is selected.
* PXA300/310/320 all have distinct register mappings in some cases, that's why
* the exact CPU has to be selected. CONFIG_CPU_MONAHANS is a helper for common
* drivers and compatibility glue with old source then.
*/
#ifndef CONFIG_CPU_MONAHANS
#if defined(CONFIG_CPU_PXA300) || \
defined(CONFIG_CPU_PXA310) || \
defined(CONFIG_CPU_PXA320)
#define CONFIG_CPU_MONAHANS
#endif
#endif
/*
* These are statically mapped PCMCIA IO space for designs using it as a
* generic IO bus, typically with ISA parts, hardwired IDE interfaces, etc.
* The actual PCMCIA code is mapping required IO region at run time.
*/
#define PCMCIA_IO_0_BASE 0xf6000000
#define PCMCIA_IO_1_BASE 0xf7000000
/*
* We requires absolute addresses.
*/
#define PCIO_BASE 0
/*
* Workarounds for at least 2 errata so far require this.
* The mapping is set in mach-pxa/generic.c.
*/
#define UNCACHED_PHYS_0 0xff000000
#define UNCACHED_ADDR UNCACHED_PHYS_0
/*
* Intel PXA internal I/O mappings:
*
* 0x40000000 - 0x41ffffff <--> 0xf8000000 - 0xf9ffffff
* 0x44000000 - 0x45ffffff <--> 0xfa000000 - 0xfbffffff
* 0x48000000 - 0x49ffffff <--> 0xfc000000 - 0xfdffffff
*/
#include "pxa-regs.h"
#ifndef __ASSEMBLY__
/*
* GPIO edge detection for IRQs:
* IRQs are generated on Falling-Edge, Rising-Edge, or both.
* This must be called *before* the corresponding IRQ is registered.
* Use this instead of directly setting GRER/GFER.
*/
#define GPIO_FALLING_EDGE 1
#define GPIO_RISING_EDGE 2
#define GPIO_BOTH_EDGES 3
#endif
#endif /* _ASM_ARCH_HARDWARE_H */

2635
arch/arm/include/asm/arch-pxa/pxa-regs.h
View file

File diff suppressed because it is too large Load diff

28
arch/arm/include/asm/arch-pxa/pxa.h
View file

@ -1,28 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* PXA common functions
*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
*/
#ifndef __PXA_H__
#define __PXA_H__
#define PXA255_A0 0x00000106
#define PXA250_C0 0x00000105
#define PXA250_B2 0x00000104
#define PXA250_B1 0x00000103
#define PXA250_B0 0x00000102
#define PXA250_A1 0x00000101
#define PXA250_A0 0x00000100
#define PXA210_C0 0x00000125
#define PXA210_B2 0x00000124
#define PXA210_B1 0x00000123
#define PXA210_B0 0x00000122
int cpu_is_pxa25x(void);
int cpu_is_pxa27x(void);
uint32_t pxa_get_cpu_revision(void);
void pxa2xx_dram_init(void);
#endif /* __PXA_H__ */

140
arch/arm/include/asm/arch-pxa/regs-mmc.h
View file

@ -1,140 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
*/
#ifndef __REGS_MMC_H__
#define __REGS_MMC_H__
#define MMC0_BASE 0x41100000
#define MMC1_BASE 0x42000000
int pxa_mmc_register(int card_index);
struct pxa_mmc_regs {
uint32_t strpcl;
uint32_t stat;
uint32_t clkrt;
uint32_t spi;
uint32_t cmdat;
uint32_t resto;
uint32_t rdto;
uint32_t blklen;
uint32_t nob;
uint32_t prtbuf;
uint32_t i_mask;
uint32_t i_reg;
uint32_t cmd;
uint32_t argh;
uint32_t argl;
uint32_t res;
uint32_t rxfifo;
uint32_t txfifo;
};
/* MMC_STRPCL */
#define MMC_STRPCL_STOP_CLK (1 << 0)
#define MMC_STRPCL_START_CLK (1 << 1)
/* MMC_STAT */
#define MMC_STAT_END_CMD_RES (1 << 13)
#define MMC_STAT_PRG_DONE (1 << 12)
#define MMC_STAT_DATA_TRAN_DONE (1 << 11)
#define MMC_STAT_CLK_EN (1 << 8)
#define MMC_STAT_RECV_FIFO_FULL (1 << 7)
#define MMC_STAT_XMIT_FIFO_EMPTY (1 << 6)
#define MMC_STAT_RES_CRC_ERROR (1 << 5)
#define MMC_STAT_SPI_READ_ERROR_TOKEN (1 << 4)
#define MMC_STAT_CRC_READ_ERROR (1 << 3)
#define MMC_STAT_CRC_WRITE_ERROR (1 << 2)
#define MMC_STAT_TIME_OUT_RESPONSE (1 << 1)
#define MMC_STAT_READ_TIME_OUT (1 << 0)
/* MMC_CLKRT */
#define MMC_CLKRT_20MHZ 0
#define MMC_CLKRT_10MHZ 1
#define MMC_CLKRT_5MHZ 2
#define MMC_CLKRT_2_5MHZ 3
#define MMC_CLKRT_1_25MHZ 4
#define MMC_CLKRT_0_625MHZ 5
#define MMC_CLKRT_0_3125MHZ 6
/* MMC_SPI */
#define MMC_SPI_EN (1 << 0)
#define MMC_SPI_CS_EN (1 << 2)
#define MMC_SPI_CS_ADDRESS (1 << 3)
#define MMC_SPI_CRC_ON (1 << 1)
/* MMC_CMDAT */
#define MMC_CMDAT_SD_4DAT (1 << 8)
#define MMC_CMDAT_MMC_DMA_EN (1 << 7)
#define MMC_CMDAT_INIT (1 << 6)
#define MMC_CMDAT_BUSY (1 << 5)
#define MMC_CMDAT_BCR (MMC_CMDAT_BUSY | MMC_CMDAT_INIT)
#define MMC_CMDAT_STREAM (1 << 4)
#define MMC_CMDAT_WRITE (1 << 3)
#define MMC_CMDAT_DATA_EN (1 << 2)
#define MMC_CMDAT_R0 0
#define MMC_CMDAT_R1 1
#define MMC_CMDAT_R2 2
#define MMC_CMDAT_R3 3
/* MMC_RESTO */
#define MMC_RES_TO_MAX_MASK 0x7f
/* MMC_RDTO */
#define MMC_READ_TO_MAX_MASK 0xffff
/* MMC_BLKLEN */
#define MMC_BLK_LEN_MAX_MASK 0x3ff
/* MMC_PRTBUF */
#define MMC_PRTBUF_BUF_PART_FULL (1 << 0)
/* MMC_I_MASK */
#define MMC_I_MASK_TXFIFO_WR_REQ (1 << 6)
#define MMC_I_MASK_RXFIFO_RD_REQ (1 << 5)
#define MMC_I_MASK_CLK_IS_OFF (1 << 4)
#define MMC_I_MASK_STOP_CMD (1 << 3)
#define MMC_I_MASK_END_CMD_RES (1 << 2)
#define MMC_I_MASK_PRG_DONE (1 << 1)
#define MMC_I_MASK_DATA_TRAN_DONE (1 << 0)
#define MMC_I_MASK_ALL 0x7f
/* MMC_I_REG */
#define MMC_I_REG_TXFIFO_WR_REQ (1 << 6)
#define MMC_I_REG_RXFIFO_RD_REQ (1 << 5)
#define MMC_I_REG_CLK_IS_OFF (1 << 4)
#define MMC_I_REG_STOP_CMD (1 << 3)
#define MMC_I_REG_END_CMD_RES (1 << 2)
#define MMC_I_REG_PRG_DONE (1 << 1)
#define MMC_I_REG_DATA_TRAN_DONE (1 << 0)
/* MMC_CMD */
#define MMC_CMD_INDEX_MAX 0x6f
#define MMC_R1_IDLE_STATE 0x01
#define MMC_R1_ERASE_STATE 0x02
#define MMC_R1_ILLEGAL_CMD 0x04
#define MMC_R1_COM_CRC_ERR 0x08
#define MMC_R1_ERASE_SEQ_ERR 0x01
#define MMC_R1_ADDR_ERR 0x02
#define MMC_R1_PARAM_ERR 0x04
#define MMC_R1B_WP_ERASE_SKIP 0x0002
#define MMC_R1B_ERR 0x0004
#define MMC_R1B_CC_ERR 0x0008
#define MMC_R1B_CARD_ECC_ERR 0x0010
#define MMC_R1B_WP_VIOLATION 0x0020
#define MMC_R1B_ERASE_PARAM 0x0040
#define MMC_R1B_OOR 0x0080
#define MMC_R1B_IDLE_STATE 0x0100
#define MMC_R1B_ERASE_RESET 0x0200
#define MMC_R1B_ILLEGAL_CMD 0x0400
#define MMC_R1B_COM_CRC_ERR 0x0800
#define MMC_R1B_ERASE_SEQ_ERR 0x1000
#define MMC_R1B_ADDR_ERR 0x2000
#define MMC_R1B_PARAM_ERR 0x4000
#endif /* __REGS_MMC_H__ */

95
arch/arm/include/asm/arch-pxa/regs-uart.h
View file

@ -1,95 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
*/
#ifndef __REGS_UART_H__
#define __REGS_UART_H__
#define FFUART_BASE 0x40100000
#define BTUART_BASE 0x40200000
#define STUART_BASE 0x40700000
#define HWUART_BASE 0x41600000
struct pxa_uart_regs {
union {
uint32_t thr;
uint32_t rbr;
uint32_t dll;
};
union {
uint32_t ier;
uint32_t dlh;
};
union {
uint32_t fcr;
uint32_t iir;
};
uint32_t lcr;
uint32_t mcr;
uint32_t lsr;
uint32_t msr;
uint32_t spr;
uint32_t isr;
};
#define IER_DMAE (1 << 7)
#define IER_UUE (1 << 6)
#define IER_NRZE (1 << 5)
#define IER_RTIOE (1 << 4)
#define IER_MIE (1 << 3)
#define IER_RLSE (1 << 2)
#define IER_TIE (1 << 1)
#define IER_RAVIE (1 << 0)
#define IIR_FIFOES1 (1 << 7)
#define IIR_FIFOES0 (1 << 6)
#define IIR_TOD (1 << 3)
#define IIR_IID2 (1 << 2)
#define IIR_IID1 (1 << 1)
#define IIR_IP (1 << 0)
#define FCR_ITL2 (1 << 7)
#define FCR_ITL1 (1 << 6)
#define FCR_RESETTF (1 << 2)
#define FCR_RESETRF (1 << 1)
#define FCR_TRFIFOE (1 << 0)
#define FCR_ITL_1 0
#define FCR_ITL_8 (FCR_ITL1)
#define FCR_ITL_16 (FCR_ITL2)
#define FCR_ITL_32 (FCR_ITL2|FCR_ITL1)
#define LCR_DLAB (1 << 7)
#define LCR_SB (1 << 6)
#define LCR_STKYP (1 << 5)
#define LCR_EPS (1 << 4)
#define LCR_PEN (1 << 3)
#define LCR_STB (1 << 2)
#define LCR_WLS1 (1 << 1)
#define LCR_WLS0 (1 << 0)
#define LSR_FIFOE (1 << 7)
#define LSR_TEMT (1 << 6)
#define LSR_TDRQ (1 << 5)
#define LSR_BI (1 << 4)
#define LSR_FE (1 << 3)
#define LSR_PE (1 << 2)
#define LSR_OE (1 << 1)
#define LSR_DR (1 << 0)
#define MCR_LOOP (1 << 4)
#define MCR_OUT2 (1 << 3)
#define MCR_OUT1 (1 << 2)
#define MCR_RTS (1 << 1)
#define MCR_DTR (1 << 0)
#define MSR_DCD (1 << 7)
#define MSR_RI (1 << 6)
#define MSR_DSR (1 << 5)
#define MSR_CTS (1 << 4)
#define MSR_DDCD (1 << 3)
#define MSR_TERI (1 << 2)
#define MSR_DDSR (1 << 1)
#define MSR_DCTS (1 << 0)
#endif /* __REGS_UART_H__ */

146
arch/arm/include/asm/arch-pxa/regs-usb.h
View file

@ -1,146 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* PXA25x UDC definitions
*
* Copyright (C) 2012 Łukasz Dałek <luk0104@gmail.com>
*/
#ifndef __REGS_USB_H__
#define __REGS_USB_H__
struct pxa25x_udc_regs {
/* UDC Control Register */
uint32_t udccr; /* 0x000 */
uint32_t reserved1;
/* UDC Control Function Register */
uint32_t udccfr; /* 0x008 */
uint32_t reserved2;
/* UDC Endpoint Control/Status Registers */
uint32_t udccs[16]; /* 0x010 - 0x04c */
/* UDC Interrupt Control/Status Registers */
uint32_t uicr0; /* 0x050 */
uint32_t uicr1; /* 0x054 */
uint32_t usir0; /* 0x058 */
uint32_t usir1; /* 0x05c */
/* UDC Frame Number/Byte Count Registers */
uint32_t ufnrh; /* 0x060 */
uint32_t ufnrl; /* 0x064 */
uint32_t ubcr2; /* 0x068 */
uint32_t ubcr4; /* 0x06c */
uint32_t ubcr7; /* 0x070 */
uint32_t ubcr9; /* 0x074 */
uint32_t ubcr12; /* 0x078 */
uint32_t ubcr14; /* 0x07c */
/* UDC Endpoint Data Registers */
uint32_t uddr0; /* 0x080 */
uint32_t reserved3[7];
uint32_t uddr5; /* 0x0a0 */
uint32_t reserved4[7];
uint32_t uddr10; /* 0x0c0 */
uint32_t reserved5[7];
uint32_t uddr15; /* 0x0e0 */
uint32_t reserved6[7];
uint32_t uddr1; /* 0x100 */
uint32_t reserved7[31];
uint32_t uddr2; /* 0x180 */
uint32_t reserved8[31];
uint32_t uddr3; /* 0x200 */
uint32_t reserved9[127];
uint32_t uddr4; /* 0x400 */
uint32_t reserved10[127];
uint32_t uddr6; /* 0x600 */
uint32_t reserved11[31];
uint32_t uddr7; /* 0x680 */
uint32_t reserved12[31];
uint32_t uddr8; /* 0x700 */
uint32_t reserved13[127];
uint32_t uddr9; /* 0x900 */
uint32_t reserved14[127];
uint32_t uddr11; /* 0xb00 */
uint32_t reserved15[31];
uint32_t uddr12; /* 0xb80 */
uint32_t reserved16[31];
uint32_t uddr13; /* 0xc00 */
uint32_t reserved17[127];
uint32_t uddr14; /* 0xe00 */
};
#define PXA25X_UDC_BASE 0x40600000
#define UDCCR_UDE (1 << 0)
#define UDCCR_UDA (1 << 1)
#define UDCCR_RSM (1 << 2)
#define UDCCR_RESIR (1 << 3)
#define UDCCR_SUSIR (1 << 4)
#define UDCCR_SRM (1 << 5)
#define UDCCR_RSTIR (1 << 6)
#define UDCCR_REM (1 << 7)
/* Bulk IN endpoint 1/6/11 */
#define UDCCS_BI_TSP (1 << 7)
#define UDCCS_BI_FST (1 << 5)
#define UDCCS_BI_SST (1 << 4)
#define UDCCS_BI_TUR (1 << 3)
#define UDCCS_BI_FTF (1 << 2)
#define UDCCS_BI_TPC (1 << 1)
#define UDCCS_BI_TFS (1 << 0)
/* Bulk OUT endpoint 2/7/12 */
#define UDCCS_BO_RSP (1 << 7)
#define UDCCS_BO_RNE (1 << 6)
#define UDCCS_BO_FST (1 << 5)
#define UDCCS_BO_SST (1 << 4)
#define UDCCS_BO_DME (1 << 3)
#define UDCCS_BO_RPC (1 << 1)
#define UDCCS_BO_RFS (1 << 0)
/* Isochronous OUT endpoint 4/9/14 */
#define UDCCS_IO_RSP (1 << 7)
#define UDCCS_IO_RNE (1 << 6)
#define UDCCS_IO_DME (1 << 3)
#define UDCCS_IO_ROF (1 << 2)
#define UDCCS_IO_RPC (1 << 1)
#define UDCCS_IO_RFS (1 << 0)
/* Control endpoint 0 */
#define UDCCS0_OPR (1 << 0)
#define UDCCS0_IPR (1 << 1)
#define UDCCS0_FTF (1 << 2)
#define UDCCS0_DRWF (1 << 3)
#define UDCCS0_SST (1 << 4)
#define UDCCS0_FST (1 << 5)
#define UDCCS0_RNE (1 << 6)
#define UDCCS0_SA (1 << 7)
#define UICR0_IM0 (1 << 0)
#define USIR0_IR0 (1 << 0)
#define USIR0_IR1 (1 << 1)
#define USIR0_IR2 (1 << 2)
#define USIR0_IR3 (1 << 3)
#define USIR0_IR4 (1 << 4)
#define USIR0_IR5 (1 << 5)
#define USIR0_IR6 (1 << 6)
#define USIR0_IR7 (1 << 7)
#define UDCCFR_AREN (1 << 7) /* ACK response enable (now) */
#define UDCCFR_ACM (1 << 2) /* ACK control mode (wait for AREN) */
/*
* Intel(R) PXA255 Processor Specification, September 2003 (page 31)
* define new "must be one" bits in UDCCFR (see Table 12-13.)
*/
#define UDCCFR_MB1 (0xff & ~(UDCCFR_AREN | UDCCFR_ACM))
#define UFNRH_SIR (1 << 7) /* SOF interrupt request */
#define UFNRH_SIM (1 << 6) /* SOF interrupt mask */
#define UFNRH_IPE14 (1 << 5) /* ISO packet error, ep14 */
#define UFNRH_IPE9 (1 << 4) /* ISO packet error, ep9 */
#define UFNRH_IPE4 (1 << 3) /* ISO packet error, ep4 */
#endif /* __REGS_USB_H__ */

2
arch/arm/include/asm/config.h
View file

@ -9,8 +9,6 @@
#define CONFIG_SYS_BOOT_RAMDISK_HIGH
#if defined(CONFIG_ARCH_LS1021A) || \
defined(CONFIG_CPU_PXA27X) || \
defined(CONFIG_CPU_MONAHANS) || \
defined(CONFIG_FSL_LAYERSCAPE)
#include <asm/arch/config.h>
#endif

9
doc/develop/driver-model/serial-howto.rst
View file

@ -3,15 +3,6 @@
How to port a serial driver to driver model
===========================================
Almost all of the serial drivers have been converted as at January 2016. These
ones remain:
* serial_bfin.c
* serial_pxa.c
The deadline for this work was the end of January 2016. If no one steps
forward to convert these, at some point there may come a patch to remove them!
Here is a suggested approach for converting your serial driver over to driver
model. Please feel free to update this file with your ideas and suggestions.

8
drivers/mmc/Kconfig
View file

@ -346,14 +346,6 @@ config MVEBU_MMC
If unsure, say N.
config PXA_MMC_GENERIC
bool "Support for MMC controllers on PXA"
help
This selects MMC controllers on PXA.
If you are on a PXA architecture, say Y here.
If unsure, say N.
config MMC_OMAP_HS
bool "TI OMAP High Speed Multimedia Card Interface support"
select DM_REGULATOR_PBIAS if DM_MMC && DM_REGULATOR

1
drivers/mmc/Makefile
View file

@ -46,7 +46,6 @@ obj-$(CONFIG_MMC_MXS) += mxsmmc.o
obj-$(CONFIG_MMC_OCTEONTX) += octeontx_hsmmc.o
obj-$(CONFIG_MMC_OWL) += owl_mmc.o
obj-$(CONFIG_MMC_PCI) += pci_mmc.o
obj-$(CONFIG_PXA_MMC_GENERIC) += pxa_mmc_gen.o
obj-$(CONFIG_$(SPL_TPL_)SUPPORT_EMMC_RPMB) += rpmb.o
obj-$(CONFIG_MMC_SANDBOX) += sandbox_mmc.o
obj-$(CONFIG_SH_MMCIF) += sh_mmcif.o

531
drivers/mmc/pxa_mmc_gen.c
View file

@ -1,531 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
*
* Modified to add driver model (DM) support
* Copyright (C) 2019 Marcel Ziswiler <marcel@ziswiler.com>
*
* Loosely based on the old code and Linux's PXA MMC driver
*/
#include <common.h>
#include <asm/arch/hardware.h>
#include <asm/arch/regs-mmc.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <asm/io.h>
#include <dm.h>
#include <dm/platform_data/pxa_mmc_gen.h>
#include <malloc.h>
#include <mmc.h>
/* PXAMMC Generic default config for various CPUs */
#if defined(CONFIG_CPU_PXA27X)
#define PXAMMC_CRC_SKIP
#define PXAMMC_FIFO_SIZE 32
#define PXAMMC_MIN_SPEED 304000
#define PXAMMC_MAX_SPEED 19500000
#define PXAMMC_HOST_CAPS (MMC_MODE_4BIT)
#elif defined(CONFIG_CPU_MONAHANS)
#define PXAMMC_FIFO_SIZE 32
#define PXAMMC_MIN_SPEED 304000
#define PXAMMC_MAX_SPEED 26000000
#define PXAMMC_HOST_CAPS (MMC_MODE_4BIT | MMC_MODE_HS)
#else
#error "This CPU isn't supported by PXA MMC!"
#endif
#define MMC_STAT_ERRORS \
(MMC_STAT_RES_CRC_ERROR | MMC_STAT_SPI_READ_ERROR_TOKEN | \
MMC_STAT_CRC_READ_ERROR | MMC_STAT_TIME_OUT_RESPONSE | \
MMC_STAT_READ_TIME_OUT | MMC_STAT_CRC_WRITE_ERROR)
/* 1 millisecond (in wait cycles below it's 100 x 10uS waits) */
#define PXA_MMC_TIMEOUT 100
struct pxa_mmc_priv {
struct pxa_mmc_regs *regs;
};
/* Wait for bit to be set */
static int pxa_mmc_wait(struct mmc *mmc, uint32_t mask)
{
struct pxa_mmc_priv *priv = mmc->priv;
struct pxa_mmc_regs *regs = priv->regs;
unsigned int timeout = PXA_MMC_TIMEOUT;
/* Wait for bit to be set */
while (--timeout) {
if (readl(&regs->stat) & mask)
break;
udelay(10);
}
if (!timeout)
return -ETIMEDOUT;
return 0;
}
static int pxa_mmc_stop_clock(struct mmc *mmc)
{
struct pxa_mmc_priv *priv = mmc->priv;
struct pxa_mmc_regs *regs = priv->regs;
unsigned int timeout = PXA_MMC_TIMEOUT;
/* If the clock aren't running, exit */
if (!(readl(&regs->stat) & MMC_STAT_CLK_EN))
return 0;
/* Tell the controller to turn off the clock */
writel(MMC_STRPCL_STOP_CLK, &regs->strpcl);
/* Wait until the clock are off */
while (--timeout) {
if (!(readl(&regs->stat) & MMC_STAT_CLK_EN))
break;
udelay(10);
}
/* The clock refused to stop, scream and die a painful death */
if (!timeout)
return -ETIMEDOUT;
/* The clock stopped correctly */
return 0;
}
static int pxa_mmc_start_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
uint32_t cmdat)
{
struct pxa_mmc_priv *priv = mmc->priv;
struct pxa_mmc_regs *regs = priv->regs;
int ret;
/* The card can send a "busy" response */
if (cmd->resp_type & MMC_RSP_BUSY)
cmdat |= MMC_CMDAT_BUSY;
/* Inform the controller about response type */
switch (cmd->resp_type) {
case MMC_RSP_R1:
case MMC_RSP_R1b:
cmdat |= MMC_CMDAT_R1;
break;
case MMC_RSP_R2:
cmdat |= MMC_CMDAT_R2;
break;
case MMC_RSP_R3:
cmdat |= MMC_CMDAT_R3;
break;
default:
break;
}
/* Load command and it's arguments into the controller */
writel(cmd->cmdidx, &regs->cmd);
writel(cmd->cmdarg >> 16, &regs->argh);
writel(cmd->cmdarg & 0xffff, &regs->argl);
writel(cmdat, &regs->cmdat);
/* Start the controller clock and wait until they are started */
writel(MMC_STRPCL_START_CLK, &regs->strpcl);
ret = pxa_mmc_wait(mmc, MMC_STAT_CLK_EN);
if (ret)
return ret;
/* Correct and happy end */
return 0;
}
static int pxa_mmc_cmd_done(struct mmc *mmc, struct mmc_cmd *cmd)
{
struct pxa_mmc_priv *priv = mmc->priv;
struct pxa_mmc_regs *regs = priv->regs;
u32 a, b, c;
int i;
int stat;
/* Read the controller status */
stat = readl(&regs->stat);
/*
* Linux says:
* Did I mention this is Sick. We always need to
* discard the upper 8 bits of the first 16-bit word.
*/
a = readl(&regs->res) & 0xffff;
for (i = 0; i < 4; i++) {
b = readl(&regs->res) & 0xffff;
c = readl(&regs->res) & 0xffff;
cmd->response[i] = (a << 24) | (b << 8) | (c >> 8);
a = c;
}
/* The command response didn't arrive */
if (stat & MMC_STAT_TIME_OUT_RESPONSE) {
return -ETIMEDOUT;
} else if (stat & MMC_STAT_RES_CRC_ERROR &&
cmd->resp_type & MMC_RSP_CRC) {
#ifdef PXAMMC_CRC_SKIP
if (cmd->resp_type & MMC_RSP_136 &&
cmd->response[0] & (1 << 31))
printf("Ignoring CRC, this may be dangerous!\n");
else
#endif
return -EILSEQ;
}
/* The command response was successfully read */
return 0;
}
static int pxa_mmc_do_read_xfer(struct mmc *mmc, struct mmc_data *data)
{
struct pxa_mmc_priv *priv = mmc->priv;
struct pxa_mmc_regs *regs = priv->regs;
u32 len;
u32 *buf = (uint32_t *)data->dest;
int size;
int ret;
len = data->blocks * data->blocksize;
while (len) {
/* The controller has data ready */
if (readl(&regs->i_reg) & MMC_I_REG_RXFIFO_RD_REQ) {
size = min(len, (uint32_t)PXAMMC_FIFO_SIZE);
len -= size;
size /= 4;
/* Read data into the buffer */
while (size--)
*buf++ = readl(&regs->rxfifo);
}
if (readl(&regs->stat) & MMC_STAT_ERRORS)
return -EIO;
}
/* Wait for the transmission-done interrupt */
ret = pxa_mmc_wait(mmc, MMC_STAT_DATA_TRAN_DONE);
if (ret)
return ret;
return 0;
}
static int pxa_mmc_do_write_xfer(struct mmc *mmc, struct mmc_data *data)
{
struct pxa_mmc_priv *priv = mmc->priv;
struct pxa_mmc_regs *regs = priv->regs;
u32 len;
u32 *buf = (uint32_t *)data->src;
int size;
int ret;
len = data->blocks * data->blocksize;
while (len) {
/* The controller is ready to receive data */
if (readl(&regs->i_reg) & MMC_I_REG_TXFIFO_WR_REQ) {
size = min(len, (uint32_t)PXAMMC_FIFO_SIZE);
len -= size;
size /= 4;
while (size--)
writel(*buf++, &regs->txfifo);
if (min(len, (uint32_t)PXAMMC_FIFO_SIZE) < 32)
writel(MMC_PRTBUF_BUF_PART_FULL, &regs->prtbuf);
}
if (readl(&regs->stat) & MMC_STAT_ERRORS)
return -EIO;
}
/* Wait for the transmission-done interrupt */
ret = pxa_mmc_wait(mmc, MMC_STAT_DATA_TRAN_DONE);
if (ret)
return ret;
/* Wait until the data are really written to the card */
ret = pxa_mmc_wait(mmc, MMC_STAT_PRG_DONE);
if (ret)
return ret;
return 0;
}
static int pxa_mmc_send_cmd_common(struct pxa_mmc_priv *priv, struct mmc *mmc,
struct mmc_cmd *cmd, struct mmc_data *data)
{
struct pxa_mmc_regs *regs = priv->regs;
u32 cmdat = 0;
int ret;
/* Stop the controller */
ret = pxa_mmc_stop_clock(mmc);
if (ret)
return ret;
/* If we're doing data transfer, configure the controller accordingly */
if (data) {
writel(data->blocks, &regs->nob);
writel(data->blocksize, &regs->blklen);
/* This delay can be optimized, but stick with max value */
writel(0xffff, &regs->rdto);
cmdat |= MMC_CMDAT_DATA_EN;
if (data->flags & MMC_DATA_WRITE)
cmdat |= MMC_CMDAT_WRITE;
}
/* Run in 4bit mode if the card can do it */
if (mmc->bus_width == 4)
cmdat |= MMC_CMDAT_SD_4DAT;
/* Execute the command */
ret = pxa_mmc_start_cmd(mmc, cmd, cmdat);
if (ret)
return ret;
/* Wait until the command completes */
ret = pxa_mmc_wait(mmc, MMC_STAT_END_CMD_RES);
if (ret)
return ret;
/* Read back the result */
ret = pxa_mmc_cmd_done(mmc, cmd);
if (ret)
return ret;
/* In case there was a data transfer scheduled, do it */
if (data) {
if (data->flags & MMC_DATA_WRITE)
pxa_mmc_do_write_xfer(mmc, data);
else
pxa_mmc_do_read_xfer(mmc, data);
}
return 0;
}
static int pxa_mmc_set_ios_common(struct pxa_mmc_priv *priv, struct mmc *mmc)
{
struct pxa_mmc_regs *regs = priv->regs;
u32 tmp;
u32 pxa_mmc_clock;
if (!mmc->clock) {
pxa_mmc_stop_clock(mmc);
return 0;
}
/* PXA3xx can do 26MHz with special settings. */
if (mmc->clock == 26000000) {
writel(0x7, &regs->clkrt);
return 0;
}
/* Set clock to the card the usual way. */
pxa_mmc_clock = 0;
tmp = mmc->cfg->f_max / mmc->clock;
tmp += tmp % 2;
while (tmp > 1) {
pxa_mmc_clock++;
tmp >>= 1;
}
writel(pxa_mmc_clock, &regs->clkrt);
return 0;
}
static int pxa_mmc_init_common(struct pxa_mmc_priv *priv, struct mmc *mmc)
{
struct pxa_mmc_regs *regs = priv->regs;
/* Make sure the clock are stopped */
pxa_mmc_stop_clock(mmc);
/* Turn off SPI mode */
writel(0, &regs->spi);
/* Set up maximum timeout to wait for command response */
writel(MMC_RES_TO_MAX_MASK, &regs->resto);
/* Mask all interrupts */
writel(~(MMC_I_MASK_TXFIFO_WR_REQ | MMC_I_MASK_RXFIFO_RD_REQ),
&regs->i_mask);
return 0;
}
#if !CONFIG_IS_ENABLED(DM_MMC)
static int pxa_mmc_init(struct mmc *mmc)
{
struct pxa_mmc_priv *priv = mmc->priv;
return pxa_mmc_init_common(priv, mmc);
}
static int pxa_mmc_request(struct mmc *mmc, struct mmc_cmd *cmd,
struct mmc_data *data)
{
struct pxa_mmc_priv *priv = mmc->priv;
return pxa_mmc_send_cmd_common(priv, mmc, cmd, data);
}
static int pxa_mmc_set_ios(struct mmc *mmc)
{
struct pxa_mmc_priv *priv = mmc->priv;
return pxa_mmc_set_ios_common(priv, mmc);
}
static const struct mmc_ops pxa_mmc_ops = {
.send_cmd = pxa_mmc_request,
.set_ios = pxa_mmc_set_ios,
.init = pxa_mmc_init,
};
static struct mmc_config pxa_mmc_cfg = {
.name = "PXA MMC",
.ops = &pxa_mmc_ops,
.voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
.f_max = PXAMMC_MAX_SPEED,
.f_min = PXAMMC_MIN_SPEED,
.host_caps = PXAMMC_HOST_CAPS,
.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
};
int pxa_mmc_register(int card_index)
{
struct mmc *mmc;
struct pxa_mmc_priv *priv;
u32 reg;
int ret = -ENOMEM;
priv = malloc(sizeof(struct pxa_mmc_priv));
if (!priv)
goto err0;
memset(priv, 0, sizeof(*priv));
switch (card_index) {
case 0:
priv->regs = (struct pxa_mmc_regs *)MMC0_BASE;
break;
case 1:
priv->regs = (struct pxa_mmc_regs *)MMC1_BASE;
break;
default:
ret = -EINVAL;
printf("PXA MMC: Invalid MMC controller ID (card_index = %d)\n",
card_index);
goto err1;
}
#ifndef CONFIG_CPU_MONAHANS /* PXA2xx */
reg = readl(CKEN);
reg |= CKEN12_MMC;
writel(reg, CKEN);
#else /* PXA3xx */
reg = readl(CKENA);
reg |= CKENA_12_MMC0 | CKENA_13_MMC1;
writel(reg, CKENA);
#endif
mmc = mmc_create(&pxa_mmc_cfg, priv);
if (!mmc)
goto err1;
return 0;
err1:
free(priv);
err0:
return ret;
}
#else /* !CONFIG_IS_ENABLED(DM_MMC) */
static int pxa_mmc_probe(struct udevice *dev)
{
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct pxa_mmc_plat *plat = dev_get_plat(dev);
struct mmc_config *cfg = &plat->cfg;
struct mmc *mmc = &plat->mmc;
struct pxa_mmc_priv *priv = dev_get_priv(dev);
u32 reg;
upriv->mmc = mmc;
cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
cfg->f_max = PXAMMC_MAX_SPEED;
cfg->f_min = PXAMMC_MIN_SPEED;
cfg->host_caps = PXAMMC_HOST_CAPS;
cfg->name = dev->name;
cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
mmc->priv = priv;
priv->regs = plat->base;
#ifndef CONFIG_CPU_MONAHANS /* PXA2xx */
reg = readl(CKEN);
reg |= CKEN12_MMC;
writel(reg, CKEN);
#else /* PXA3xx */
reg = readl(CKENA);
reg |= CKENA_12_MMC0 | CKENA_13_MMC1;
writel(reg, CKENA);
#endif
return pxa_mmc_init_common(priv, mmc);
}
static int pxa_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
struct mmc_data *data)
{
struct pxa_mmc_plat *plat = dev_get_plat(dev);
struct pxa_mmc_priv *priv = dev_get_priv(dev);
return pxa_mmc_send_cmd_common(priv, &plat->mmc, cmd, data);
}
static int pxa_mmc_set_ios(struct udevice *dev)
{
struct pxa_mmc_plat *plat = dev_get_plat(dev);
struct pxa_mmc_priv *priv = dev_get_priv(dev);
return pxa_mmc_set_ios_common(priv, &plat->mmc);
}
static const struct dm_mmc_ops pxa_mmc_ops = {
.get_cd = NULL,
.send_cmd = pxa_mmc_send_cmd,
.set_ios = pxa_mmc_set_ios,
};
#if CONFIG_IS_ENABLED(BLK)
static int pxa_mmc_bind(struct udevice *dev)
{
struct pxa_mmc_plat *plat = dev_get_plat(dev);
return mmc_bind(dev, &plat->mmc, &plat->cfg);
}
#endif
U_BOOT_DRIVER(pxa_mmc) = {
#if CONFIG_IS_ENABLED(BLK)
.bind = pxa_mmc_bind,
#endif
.id = UCLASS_MMC,
.name = "pxa_mmc",
.ops = &pxa_mmc_ops,
.priv_auto = sizeof(struct pxa_mmc_priv),
.probe = pxa_mmc_probe,
};
#endif /* !CONFIG_IS_ENABLED(DM_MMC) */

6
drivers/serial/Kconfig
View file

@ -940,12 +940,6 @@ config OWL_SERIAL
serial port, say Y to this option. If unsure, say N.
Single baudrate is supported in current implementation (115200).
config PXA_SERIAL
bool "PXA serial port support"
help
If you have a machine based on a Marvell XScale PXA2xx CPU you
can enable its onboard serial ports by enabling this option.
config HTIF_CONSOLE
bool "RISC-V HTIF console support"
depends on DM_SERIAL && 64BIT

1
drivers/serial/Makefile
View file

@ -43,7 +43,6 @@ obj-$(CONFIG_MCFUART) += serial_mcf.o
obj-$(CONFIG_SYS_NS16550) += ns16550.o
obj-$(CONFIG_S5P_SERIAL) += serial_s5p.o
obj-$(CONFIG_MXC_UART) += serial_mxc.o
obj-$(CONFIG_PXA_SERIAL) += serial_pxa.o
obj-$(CONFIG_MESON_SERIAL) += serial_meson.o
obj-$(CONFIG_INTEL_MID_SERIAL) += serial_intel_mid.o
obj-$(CONFIG_ROCKCHIP_SERIAL) += serial_rockchip.o

342
drivers/serial/serial_pxa.c
View file

@ -1,342 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
*
* (C) Copyright 2002
* Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Alex Zuepke <azu@sysgo.de>
*
* Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl)
*
* Modified to add driver model (DM) support
* (C) Copyright 2016 Marcel Ziswiler <marcel.ziswiler@toradex.com>
*/
#include <common.h>
#include <hang.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/regs-uart.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <dm.h>
#include <dm/platform_data/serial_pxa.h>
#include <linux/compiler.h>
#include <serial.h>
#include <watchdog.h>
DECLARE_GLOBAL_DATA_PTR;
static uint32_t pxa_uart_get_baud_divider(int baudrate)
{
return 921600 / baudrate;
}
static void pxa_uart_toggle_clock(uint32_t uart_index, int enable)
{
uint32_t clk_reg, clk_offset, reg;
clk_reg = UART_CLK_REG;
clk_offset = UART_CLK_BASE << uart_index;
reg = readl(clk_reg);
if (enable)
reg |= clk_offset;
else
reg &= ~clk_offset;
writel(reg, clk_reg);
}
/*
* Enable clock and set baud rate, parity etc.
*/
void pxa_setbrg_common(struct pxa_uart_regs *uart_regs, int port, int baudrate)
{
uint32_t divider = pxa_uart_get_baud_divider(baudrate);
if (!divider)
hang();
pxa_uart_toggle_clock(port, 1);
/* Disable interrupts and FIFOs */
writel(0, &uart_regs->ier);
writel(0, &uart_regs->fcr);
/* Set baud rate */
writel(LCR_WLS0 | LCR_WLS1 | LCR_DLAB, &uart_regs->lcr);
writel(divider & 0xff, &uart_regs->dll);
writel(divider >> 8, &uart_regs->dlh);
writel(LCR_WLS0 | LCR_WLS1, &uart_regs->lcr);
/* Enable UART */
writel(IER_UUE, &uart_regs->ier);
}
#ifndef CONFIG_DM_SERIAL
static struct pxa_uart_regs *pxa_uart_index_to_regs(uint32_t uart_index)
{
switch (uart_index) {
case FFUART_INDEX: return (struct pxa_uart_regs *)FFUART_BASE;
case BTUART_INDEX: return (struct pxa_uart_regs *)BTUART_BASE;
case STUART_INDEX: return (struct pxa_uart_regs *)STUART_BASE;
default:
return NULL;
}
}
/*
* Enable clock and set baud rate, parity etc.
*/
void pxa_setbrg_dev(uint32_t uart_index)
{
struct pxa_uart_regs *uart_regs = pxa_uart_index_to_regs(uart_index);
if (!uart_regs)
panic("Failed getting UART registers\n");
pxa_setbrg_common(uart_regs, uart_index, gd->baudrate);
}
/*
* Initialise the serial port with the given baudrate. The settings
* are always 8 data bits, no parity, 1 stop bit, no start bits.
*/
int pxa_init_dev(unsigned int uart_index)
{
pxa_setbrg_dev(uart_index);
return 0;
}
/*
* Output a single byte to the serial port.
*/
void pxa_putc_dev(unsigned int uart_index, const char c)
{
struct pxa_uart_regs *uart_regs;
/* If \n, also do \r */
if (c == '\n')
pxa_putc_dev(uart_index, '\r');
uart_regs = pxa_uart_index_to_regs(uart_index);
if (!uart_regs)
hang();
while (!(readl(&uart_regs->lsr) & LSR_TEMT))
WATCHDOG_RESET();
writel(c, &uart_regs->thr);
}
/*
* Read a single byte from the serial port. Returns 1 on success, 0
* otherwise. When the function is succesfull, the character read is
* written into its argument c.
*/
int pxa_tstc_dev(unsigned int uart_index)
{
struct pxa_uart_regs *uart_regs;
uart_regs = pxa_uart_index_to_regs(uart_index);
if (!uart_regs)
return -1;
return readl(&uart_regs->lsr) & LSR_DR;
}
/*
* Read a single byte from the serial port. Returns 1 on success, 0
* otherwise. When the function is succesfull, the character read is
* written into its argument c.
*/
int pxa_getc_dev(unsigned int uart_index)
{
struct pxa_uart_regs *uart_regs;
uart_regs = pxa_uart_index_to_regs(uart_index);
if (!uart_regs)
return -1;
while (!(readl(&uart_regs->lsr) & LSR_DR))
WATCHDOG_RESET();
return readl(&uart_regs->rbr) & 0xff;
}
void pxa_puts_dev(unsigned int uart_index, const char *s)
{
while (*s)
pxa_putc_dev(uart_index, *s++);
}
#define pxa_uart(uart, UART) \
int uart##_init(void) \
{ \
return pxa_init_dev(UART##_INDEX); \
} \
\
void uart##_setbrg(void) \
{ \
return pxa_setbrg_dev(UART##_INDEX); \
} \
\
void uart##_putc(const char c) \
{ \
return pxa_putc_dev(UART##_INDEX, c); \
} \
\
void uart##_puts(const char *s) \
{ \
return pxa_puts_dev(UART##_INDEX, s); \
} \
\
int uart##_getc(void) \
{ \
return pxa_getc_dev(UART##_INDEX); \
} \
\
int uart##_tstc(void) \
{ \
return pxa_tstc_dev(UART##_INDEX); \
} \
#define pxa_uart_desc(uart) \
struct serial_device serial_##uart##_device = \
{ \
.name = "serial_"#uart, \
.start = uart##_init, \
.stop = NULL, \
.setbrg = uart##_setbrg, \
.getc = uart##_getc, \
.tstc = uart##_tstc, \
.putc = uart##_putc, \
.puts = uart##_puts, \
};
#define pxa_uart_multi(uart, UART) \
pxa_uart(uart, UART) \
pxa_uart_desc(uart)
#if defined(CONFIG_HWUART)
pxa_uart_multi(hwuart, HWUART)
#endif
#if defined(CONFIG_STUART)
pxa_uart_multi(stuart, STUART)
#endif
#if defined(CONFIG_FFUART)
pxa_uart_multi(ffuart, FFUART)
#endif
#if defined(CONFIG_BTUART)
pxa_uart_multi(btuart, BTUART)
#endif
__weak struct serial_device *default_serial_console(void)
{
#if CONFIG_CONS_INDEX == 1
return &serial_hwuart_device;
#elif CONFIG_CONS_INDEX == 2
return &serial_stuart_device;
#elif CONFIG_CONS_INDEX == 3
return &serial_ffuart_device;
#elif CONFIG_CONS_INDEX == 4
return &serial_btuart_device;
#else
#error "Bad CONFIG_CONS_INDEX."
#endif
}
void pxa_serial_initialize(void)
{
#if defined(CONFIG_FFUART)
serial_register(&serial_ffuart_device);
#endif
#if defined(CONFIG_BTUART)
serial_register(&serial_btuart_device);
#endif
#if defined(CONFIG_STUART)
serial_register(&serial_stuart_device);
#endif
}
#endif /* CONFIG_DM_SERIAL */
#ifdef CONFIG_DM_SERIAL
static int pxa_serial_probe(struct udevice *dev)
{
struct pxa_serial_plat *plat = dev_get_plat(dev);
pxa_setbrg_common((struct pxa_uart_regs *)plat->base, plat->port,
plat->baudrate);
return 0;
}
static int pxa_serial_putc(struct udevice *dev, const char ch)
{
struct pxa_serial_plat *plat = dev_get_plat(dev);
struct pxa_uart_regs *uart_regs = (struct pxa_uart_regs *)plat->base;
/* Wait for last character to go. */
if (!(readl(&uart_regs->lsr) & LSR_TEMT))
return -EAGAIN;
writel(ch, &uart_regs->thr);
return 0;
}
static int pxa_serial_getc(struct udevice *dev)
{
struct pxa_serial_plat *plat = dev_get_plat(dev);
struct pxa_uart_regs *uart_regs = (struct pxa_uart_regs *)plat->base;
/* Wait for a character to arrive. */
if (!(readl(&uart_regs->lsr) & LSR_DR))
return -EAGAIN;
return readl(&uart_regs->rbr) & 0xff;
}
int pxa_serial_setbrg(struct udevice *dev, int baudrate)
{
struct pxa_serial_plat *plat = dev_get_plat(dev);
struct pxa_uart_regs *uart_regs = (struct pxa_uart_regs *)plat->base;
int port = plat->port;
pxa_setbrg_common(uart_regs, port, baudrate);
return 0;
}
static int pxa_serial_pending(struct udevice *dev, bool input)
{
struct pxa_serial_plat *plat = dev_get_plat(dev);
struct pxa_uart_regs *uart_regs = (struct pxa_uart_regs *)plat->base;
if (input)
return readl(&uart_regs->lsr) & LSR_DR ? 1 : 0;
else
return readl(&uart_regs->lsr) & LSR_TEMT ? 0 : 1;
return 0;
}
static const struct dm_serial_ops pxa_serial_ops = {
.putc = pxa_serial_putc,
.pending = pxa_serial_pending,
.getc = pxa_serial_getc,
.setbrg = pxa_serial_setbrg,
};
U_BOOT_DRIVER(serial_pxa) = {
.name = "serial_pxa",
.id = UCLASS_SERIAL,
.probe = pxa_serial_probe,
.ops = &pxa_serial_ops,
.flags = DM_FLAG_PRE_RELOC,
};
#endif /* CONFIG_DM_SERIAL */

2
drivers/serial/usbtty.h
View file

@ -13,8 +13,6 @@
#include <usbdevice.h>
#if defined(CONFIG_PPC)
#include <usb/mpc8xx_udc.h>
#elif defined(CONFIG_CPU_PXA27X)
#include <usb/pxa27x_udc.h>
#elif defined(CONFIG_DW_UDC)
#include <usb/designware_udc.h>
#elif defined(CONFIG_CI_UDC)

1
drivers/usb/gadget/Makefile
View file

@ -43,6 +43,5 @@ ifdef CONFIG_USB_DEVICE
obj-y += core.o
obj-y += ep0.o
obj-$(CONFIG_DW_UDC) += designware_udc.o
obj-$(CONFIG_CPU_PXA27X) += pxa27x_udc.o
endif
endif

6
drivers/usb/gadget/epautoconf.c
View file

@ -79,12 +79,6 @@ static int ep_matches(
*/
if ('s' == tmp[2]) /* == "-iso" */
return 0;
/* for now, avoid PXA "interrupt-in";
* it's documented as never using DATA1.
*/
if (gadget_is_pxa(gadget)
&& 'i' == tmp[1])
return 0;
break;
case USB_ENDPOINT_XFER_BULK:
if ('b' != tmp[1]) /* != "-bulk" */

25
drivers/usb/gadget/ether.c
View file

@ -1325,24 +1325,6 @@ eth_setup(struct usb_gadget *gadget, const struct usb_ctrlrequest *ctrl)
if (!cdc_active(dev) && wIndex != 0)
break;
/*
* PXA hardware partially handles SET_INTERFACE;
* we need to kluge around that interference.
*/
if (gadget_is_pxa(gadget)) {
value = eth_set_config(dev, DEV_CONFIG_VALUE,
GFP_ATOMIC);
/*
* PXA25x driver use non-CDC ethernet gadget.
* But only _CDC and _RNDIS code can signalize
* that network is working. So we signalize it
* here.
*/
dev->network_started = 1;
debug("USB network up!\n");
goto done_set_intf;
}
#ifdef CONFIG_USB_ETH_CDC
switch (wIndex) {
case 0: /* control/master intf */
@ -1386,8 +1368,6 @@ eth_setup(struct usb_gadget *gadget, const struct usb_ctrlrequest *ctrl)
*/
debug("set_interface ignored!\n");
#endif /* CONFIG_USB_ETH_CDC */
done_set_intf:
break;
case USB_REQ_GET_INTERFACE:
if (ctrl->bRequestType != (USB_DIR_IN|USB_RECIP_INTERFACE)
@ -2032,10 +2012,7 @@ static int eth_bind(struct usb_gadget *gadget)
* standard protocol is _strongly_ preferred for interop purposes.
* (By everyone except Microsoft.)
*/
if (gadget_is_pxa(gadget)) {
/* pxa doesn't support altsettings */
cdc = 0;
} else if (gadget_is_musbhdrc(gadget)) {
if (gadget_is_musbhdrc(gadget)) {
/* reduce tx dma overhead by avoiding special cases */
zlp = 0;
} else if (gadget_is_sh(gadget)) {

17
drivers/usb/gadget/gadget_chips.h
View file

@ -32,12 +32,6 @@
#define gadget_is_dummy(g) 0
#endif
#ifdef CONFIG_USB_GADGET_PXA2XX
#define gadget_is_pxa(g) (!strcmp("pxa2xx_udc", (g)->name))
#else
#define gadget_is_pxa(g) 0
#endif
#ifdef CONFIG_USB_GADGET_GOKU
#define gadget_is_goku(g) (!strcmp("goku_udc", (g)->name))
#else
@ -78,13 +72,6 @@
#define gadget_is_n9604(g) 0
#endif
/* various unstable versions available */
#ifdef CONFIG_USB_GADGET_PXA27X
#define gadget_is_pxa27x(g) (!strcmp("pxa27x_udc", (g)->name))
#else
#define gadget_is_pxa27x(g) 0
#endif
#ifdef CONFIG_USB_GADGET_ATMEL_USBA
#define gadget_is_atmel_usba(g) (!strcmp("atmel_usba_udc", (g)->name))
#else
@ -194,8 +181,6 @@ static inline int usb_gadget_controller_number(struct usb_gadget *gadget)
return 0x01;
else if (gadget_is_dummy(gadget))
return 0x02;
else if (gadget_is_pxa(gadget))
return 0x03;
else if (gadget_is_sh(gadget))
return 0x04;
else if (gadget_is_sa1100(gadget))
@ -208,8 +193,6 @@ static inline int usb_gadget_controller_number(struct usb_gadget *gadget)
return 0x08;
else if (gadget_is_n9604(gadget))
return 0x09;
else if (gadget_is_pxa27x(gadget))
return 0x10;
else if (gadget_is_at91(gadget))
return 0x12;
else if (gadget_is_imx(gadget))

703
drivers/usb/gadget/pxa27x_udc.c
View file

@ -1,703 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* PXA27x USB device driver for u-boot.
*
* Copyright (C) 2007 Rodolfo Giometti <giometti@linux.it>
* Copyright (C) 2007 Eurotech S.p.A. <info@eurotech.it>
* Copyright (C) 2008 Vivek Kutal <vivek.kutal@azingo.com>
*/
#include <common.h>
#include <asm/arch/hardware.h>
#include <asm/byteorder.h>
#include <asm/io.h>
#include <usbdevice.h>
#include <linux/delay.h>
#include <usb/pxa27x_udc.h>
#include <usb/udc.h>
#include "ep0.h"
/* number of endpoints on this UDC */
#define UDC_MAX_ENDPOINTS 24
static struct urb *ep0_urb;
static struct usb_device_instance *udc_device;
static int ep0state = EP0_IDLE;
#ifdef USBDDBG
static void udc_dump_buffer(char *name, u8 *buf, int len)
{
usbdbg("%s - buf %p, len %d", name, buf, len);
print_buffer(0, buf, 1, len, 0);
}
#else
#define udc_dump_buffer(name, buf, len) /* void */
#endif
static inline void udc_ack_int_UDCCR(int mask)
{
writel(readl(USIR1) | mask, USIR1);
}
/*
* If the endpoint has an active tx_urb, then the next packet of data from the
* URB is written to the tx FIFO.
* The total amount of data in the urb is given by urb->actual_length.
* The maximum amount of data that can be sent in any one packet is given by
* endpoint->tx_packetSize.
* The number of data bytes from this URB that have already been transmitted
* is given by endpoint->sent.
* endpoint->last is updated by this routine with the number of data bytes
* transmitted in this packet.
*/
static int udc_write_urb(struct usb_endpoint_instance *endpoint)
{
struct urb *urb = endpoint->tx_urb;
int ep_num = endpoint->endpoint_address & USB_ENDPOINT_NUMBER_MASK;
u32 *data32 = (u32 *) urb->buffer;
u8 *data8 = (u8 *) urb->buffer;
unsigned int i, n, w, b, is_short;
int timeout = 2000; /* 2ms */
if (!urb || !urb->actual_length)
return -1;
n = min_t(unsigned int, urb->actual_length - endpoint->sent,
endpoint->tx_packetSize);
if (n <= 0)
return -1;
usbdbg("write urb on ep %d", ep_num);
#if defined(USBDDBG) && defined(USBDPARANOIA)
usbdbg("urb: buf %p, buf_len %d, actual_len %d",
urb->buffer, urb->buffer_length, urb->actual_length);
usbdbg("endpoint: sent %d, tx_packetSize %d, last %d",
endpoint->sent, endpoint->tx_packetSize, endpoint->last);
#endif
is_short = n != endpoint->tx_packetSize;
w = n / 4;
b = n % 4;
usbdbg("n %d%s w %d b %d", n, is_short ? "-s" : "", w, b);
udc_dump_buffer("urb write", data8 + endpoint->sent, n);
/* Prepare for data send */
if (ep_num)
writel(UDCCSR_PC ,UDCCSN(ep_num));
for (i = 0; i < w; i++)
writel(data32[endpoint->sent / 4 + i], UDCDN(ep_num));
for (i = 0; i < b; i++)
writeb(data8[endpoint->sent + w * 4 + i], UDCDN(ep_num));
/* Set "Packet Complete" if less data then tx_packetSize */
if (is_short)
writel(ep_num ? UDCCSR_SP : UDCCSR0_IPR, UDCCSN(ep_num));
/* Wait for data sent */
if (ep_num) {
while (!(readl(UDCCSN(ep_num)) & UDCCSR_PC)) {
if (timeout-- == 0)
return -1;
else
udelay(1);
}
}
endpoint->last = n;
if (ep_num) {
usbd_tx_complete(endpoint);
} else {
endpoint->sent += n;
endpoint->last -= n;
}
if (endpoint->sent >= urb->actual_length) {
urb->actual_length = 0;
endpoint->sent = 0;
endpoint->last = 0;
}
if ((endpoint->sent >= urb->actual_length) && (!ep_num)) {
usbdbg("ep0 IN stage done");
if (is_short)
ep0state = EP0_IDLE;
else
ep0state = EP0_XFER_COMPLETE;
}
return 0;
}
static int udc_read_urb(struct usb_endpoint_instance *endpoint)
{
struct urb *urb = endpoint->rcv_urb;
int ep_num = endpoint->endpoint_address & USB_ENDPOINT_NUMBER_MASK;
u32 *data32 = (u32 *) urb->buffer;
unsigned int i, n;
usbdbg("read urb on ep %d", ep_num);
#if defined(USBDDBG) && defined(USBDPARANOIA)
usbdbg("urb: buf %p, buf_len %d, actual_len %d",
urb->buffer, urb->buffer_length, urb->actual_length);
usbdbg("endpoint: rcv_packetSize %d",
endpoint->rcv_packetSize);
#endif
if (readl(UDCCSN(ep_num)) & UDCCSR_BNE)
n = readl(UDCBCN(ep_num)) & 0x3ff;
else /* zlp */
n = 0;
usbdbg("n %d%s", n, n != endpoint->rcv_packetSize ? "-s" : "");
for (i = 0; i < n; i += 4)
data32[urb->actual_length / 4 + i / 4] = readl(UDCDN(ep_num));
udc_dump_buffer("urb read", (u8 *) data32, urb->actual_length + n);
usbd_rcv_complete(endpoint, n, 0);
return 0;
}
static int udc_read_urb_ep0(void)
{
u32 *data32 = (u32 *) ep0_urb->buffer;
u8 *data8 = (u8 *) ep0_urb->buffer;
unsigned int i, n, w, b;
usbdbg("read urb on ep 0");
#if defined(USBDDBG) && defined(USBDPARANOIA)
usbdbg("urb: buf %p, buf_len %d, actual_len %d",
ep0_urb->buffer, ep0_urb->buffer_length, ep0_urb->actual_length);
#endif
n = readl(UDCBCR0);
w = n / 4;
b = n % 4;
for (i = 0; i < w; i++) {
data32[ep0_urb->actual_length / 4 + i] = readl(UDCDN(0));
/* ep0_urb->actual_length += 4; */
}
for (i = 0; i < b; i++) {
data8[ep0_urb->actual_length + w * 4 + i] = readb(UDCDN(0));
/* ep0_urb->actual_length++; */
}
ep0_urb->actual_length += n;
udc_dump_buffer("urb read", (u8 *) data32, ep0_urb->actual_length);
writel(UDCCSR0_OPC | UDCCSR0_IPR, UDCCSR0);
if (ep0_urb->actual_length == ep0_urb->device_request.wLength)
return 1;
return 0;
}
static void udc_handle_ep0(struct usb_endpoint_instance *endpoint)
{
u32 udccsr0 = readl(UDCCSR0);
u32 *data = (u32 *) &ep0_urb->device_request;
int i;
usbdbg("udccsr0 %x", udccsr0);
/* Clear stall status */
if (udccsr0 & UDCCSR0_SST) {
usberr("clear stall status");
writel(UDCCSR0_SST, UDCCSR0);
ep0state = EP0_IDLE;
}
/* previous request unfinished? non-error iff back-to-back ... */
if ((udccsr0 & UDCCSR0_SA) != 0 && ep0state != EP0_IDLE)
ep0state = EP0_IDLE;
switch (ep0state) {
case EP0_IDLE:
udccsr0 = readl(UDCCSR0);
/* Start control request? */
if ((udccsr0 & (UDCCSR0_OPC | UDCCSR0_SA | UDCCSR0_RNE))
== (UDCCSR0_OPC | UDCCSR0_SA | UDCCSR0_RNE)) {
/* Read SETUP packet.
* SETUP packet size is 8 bytes (aka 2 words)
*/
usbdbg("try reading SETUP packet");
for (i = 0; i < 2; i++) {
if ((readl(UDCCSR0) & UDCCSR0_RNE) == 0) {
usberr("setup packet too short:%d", i);
goto stall;
}
data[i] = readl(UDCDR0);
}
writel(readl(UDCCSR0) | UDCCSR0_OPC | UDCCSR0_SA, UDCCSR0);
if ((readl(UDCCSR0) & UDCCSR0_RNE) != 0) {
usberr("setup packet too long");
goto stall;
}
udc_dump_buffer("ep0 setup read", (u8 *) data, 8);
if (ep0_urb->device_request.wLength == 0) {
usbdbg("Zero Data control Packet\n");
if (ep0_recv_setup(ep0_urb)) {
usberr("Invalid Setup Packet\n");
udc_dump_buffer("ep0 setup read",
(u8 *)data, 8);
goto stall;
}
writel(UDCCSR0_IPR, UDCCSR0);
ep0state = EP0_IDLE;
} else {
/* Check direction */
if ((ep0_urb->device_request.bmRequestType &
USB_REQ_DIRECTION_MASK)
== USB_REQ_HOST2DEVICE) {
ep0state = EP0_OUT_DATA;
ep0_urb->buffer =
(u8 *)ep0_urb->buffer_data;
ep0_urb->buffer_length =
sizeof(ep0_urb->buffer_data);
ep0_urb->actual_length = 0;
writel(UDCCSR0_IPR, UDCCSR0);
} else {
/* The ep0_recv_setup function has
* already placed our response packet
* data in ep0_urb->buffer and the
* packet length in
* ep0_urb->actual_length.
*/
if (ep0_recv_setup(ep0_urb)) {
stall:
usberr("Invalid setup packet");
udc_dump_buffer("ep0 setup read"
, (u8 *) data, 8);
ep0state = EP0_IDLE;
writel(UDCCSR0_SA |
UDCCSR0_OPC | UDCCSR0_FST |
UDCCS0_FTF, UDCCSR0);
return;
}
endpoint->tx_urb = ep0_urb;
endpoint->sent = 0;
usbdbg("EP0_IN_DATA");
ep0state = EP0_IN_DATA;
if (udc_write_urb(endpoint) < 0)
goto stall;
}
}
return;
} else if ((udccsr0 & (UDCCSR0_OPC | UDCCSR0_SA))
== (UDCCSR0_OPC|UDCCSR0_SA)) {
usberr("Setup Active but no data. Stalling ....\n");
goto stall;
} else {
usbdbg("random early IRQs");
/* Some random early IRQs:
* - we acked FST
* - IPR cleared
* - OPC got set, without SA (likely status stage)
*/
writel(udccsr0 & (UDCCSR0_SA | UDCCSR0_OPC), UDCCSR0);
}
break;
case EP0_OUT_DATA:
if ((udccsr0 & UDCCSR0_OPC) && !(udccsr0 & UDCCSR0_SA)) {
if (udc_read_urb_ep0()) {
read_complete:
ep0state = EP0_IDLE;
if (ep0_recv_setup(ep0_urb)) {
/* Not a setup packet, stall next
* EP0 transaction
*/
udc_dump_buffer("ep0 setup read",
(u8 *) data, 8);
usberr("can't parse setup packet\n");
goto stall;
}
}
} else if (!(udccsr0 & UDCCSR0_OPC) &&
!(udccsr0 & UDCCSR0_IPR)) {
if (ep0_urb->device_request.wLength ==
ep0_urb->actual_length)
goto read_complete;
usberr("Premature Status\n");
ep0state = EP0_IDLE;
}
break;
case EP0_IN_DATA:
/* GET_DESCRIPTOR etc */
if (udccsr0 & UDCCSR0_OPC) {
writel(UDCCSR0_OPC | UDCCSR0_FTF, UDCCSR0);
usberr("ep0in premature status");
ep0state = EP0_IDLE;
} else {
/* irq was IPR clearing */
if (udc_write_urb(endpoint) < 0) {
usberr("ep0_write_error\n");
goto stall;
}
}
break;
case EP0_XFER_COMPLETE:
writel(UDCCSR0_IPR, UDCCSR0);
ep0state = EP0_IDLE;
break;
default:
usbdbg("Default\n");
}
writel(USIR0_IR0, USIR0);
}
static void udc_handle_ep(struct usb_endpoint_instance *endpoint)
{
int ep_addr = endpoint->endpoint_address;
int ep_num = ep_addr & USB_ENDPOINT_NUMBER_MASK;
int ep_isout = (ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_OUT;
u32 flags = readl(UDCCSN(ep_num)) & (UDCCSR_SST | UDCCSR_TRN);
if (flags)
writel(flags, UDCCSN(ep_num));
if (ep_isout)
udc_read_urb(endpoint);
else
udc_write_urb(endpoint);
writel(UDCCSR_PC, UDCCSN(ep_num));
}
static void udc_state_changed(void)
{
writel(readl(UDCCR) | UDCCR_SMAC, UDCCR);
usbdbg("New UDC settings are: conf %d - inter %d - alter %d",
(readl(UDCCR) & UDCCR_ACN) >> UDCCR_ACN_S,
(readl(UDCCR) & UDCCR_AIN) >> UDCCR_AIN_S,
(readl(UDCCR) & UDCCR_AAISN) >> UDCCR_AAISN_S);
usbd_device_event_irq(udc_device, DEVICE_CONFIGURED, 0);
writel(UDCISR1_IRCC, UDCISR1);
}
void udc_irq(void)
{
int handled;
struct usb_endpoint_instance *endpoint;
int ep_num, i;
u32 udcisr0;
do {
handled = 0;
/* Suspend Interrupt Request */
if (readl(USIR1) & UDCCR_SUSIR) {
usbdbg("Suspend\n");
udc_ack_int_UDCCR(UDCCR_SUSIR);
handled = 1;
ep0state = EP0_IDLE;
}
/* Resume Interrupt Request */
if (readl(USIR1) & UDCCR_RESIR) {
udc_ack_int_UDCCR(UDCCR_RESIR);
handled = 1;
usbdbg("USB resume\n");
}
if (readl(USIR1) & (1<<31)) {
handled = 1;
udc_state_changed();
}
/* Reset Interrupt Request */
if (readl(USIR1) & UDCCR_RSTIR) {
udc_ack_int_UDCCR(UDCCR_RSTIR);
handled = 1;
usbdbg("Reset\n");
usbd_device_event_irq(udc_device, DEVICE_RESET, 0);
} else {
if (readl(USIR0))
usbdbg("UISR0: %x \n", readl(USIR0));
if (readl(USIR0) & 0x2)
writel(0x2, USIR0);
/* Control traffic */
if (readl(USIR0) & USIR0_IR0) {
handled = 1;
writel(USIR0_IR0, USIR0);
udc_handle_ep0(udc_device->bus->endpoint_array);
}
endpoint = udc_device->bus->endpoint_array;
for (i = 0; i < udc_device->bus->max_endpoints; i++) {
ep_num = (endpoint[i].endpoint_address) &
USB_ENDPOINT_NUMBER_MASK;
if (!ep_num)
continue;
udcisr0 = readl(UDCISR0);
if (udcisr0 &
UDCISR_INT(ep_num, UDC_INT_PACKETCMP)) {
writel(UDCISR_INT(ep_num, UDC_INT_PACKETCMP),
UDCISR0);
udc_handle_ep(&endpoint[i]);
}
}
}
} while (handled);
}
/* The UDCCR reg contains mask and interrupt status bits,
* so using '|=' isn't safe as it may ack an interrupt.
*/
#define UDCCR_OEN (1 << 31) /* On-the-Go Enable */
#define UDCCR_MASK_BITS (UDCCR_OEN | UDCCR_UDE)
static inline void udc_set_mask_UDCCR(int mask)
{
writel((readl(UDCCR) & UDCCR_MASK_BITS) | (mask & UDCCR_MASK_BITS), UDCCR);
}
static inline void udc_clear_mask_UDCCR(int mask)
{
writel((readl(UDCCR) & UDCCR_MASK_BITS) & ~(mask & UDCCR_MASK_BITS), UDCCR);
}
static void pio_irq_enable(int ep_num)
{
if (ep_num < 16)
writel(readl(UDCICR0) | 3 << (ep_num * 2), UDCICR0);
else {
ep_num -= 16;
writel(readl(UDCICR1) | 3 << (ep_num * 2), UDCICR1);
}
}
/*
* udc_set_nak
*
* Allow upper layers to signal lower layers should not accept more RX data
*/
void udc_set_nak(int ep_num)
{
/* TODO */
}
/*
* udc_unset_nak
*
* Suspend sending of NAK tokens for DATA OUT tokens on a given endpoint.
* Switch off NAKing on this endpoint to accept more data output from host.
*/
void udc_unset_nak(int ep_num)
{
/* TODO */
}
int udc_endpoint_write(struct usb_endpoint_instance *endpoint)
{
return udc_write_urb(endpoint);
}
/* Associate a physical endpoint with endpoint instance */
void udc_setup_ep(struct usb_device_instance *device, unsigned int id,
struct usb_endpoint_instance *endpoint)
{
int ep_num, ep_addr, ep_isout, ep_type, ep_size;
int config, interface, alternate;
u32 tmp;
usbdbg("setting up endpoint id %d", id);
if (!endpoint) {
usberr("endpoint void!");
return;
}
ep_num = endpoint->endpoint_address & USB_ENDPOINT_NUMBER_MASK;
if (ep_num >= UDC_MAX_ENDPOINTS) {
usberr("unable to setup ep %d!", ep_num);
return;
}
pio_irq_enable(ep_num);
if (ep_num == 0) {
/* Done for ep0 */
return;
}
config = 1;
interface = 0;
alternate = 0;
usbdbg("config %d - interface %d - alternate %d",
config, interface, alternate);
ep_addr = endpoint->endpoint_address;
ep_num = ep_addr & USB_ENDPOINT_NUMBER_MASK;
ep_isout = (ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_OUT;
ep_type = ep_isout ? endpoint->rcv_attributes : endpoint->tx_attributes;
ep_size = ep_isout ? endpoint->rcv_packetSize : endpoint->tx_packetSize;
usbdbg("addr %x, num %d, dir %s, type %s, packet size %d",
ep_addr, ep_num,
ep_isout ? "out" : "in",
ep_type == USB_ENDPOINT_XFER_ISOC ? "isoc" :
ep_type == USB_ENDPOINT_XFER_BULK ? "bulk" :
ep_type == USB_ENDPOINT_XFER_INT ? "int" : "???",
ep_size
);
/* Configure UDCCRx */
tmp = 0;
tmp |= (config << UDCCONR_CN_S) & UDCCONR_CN;
tmp |= (interface << UDCCONR_IN_S) & UDCCONR_IN;
tmp |= (alternate << UDCCONR_AISN_S) & UDCCONR_AISN;
tmp |= (ep_num << UDCCONR_EN_S) & UDCCONR_EN;
tmp |= (ep_type << UDCCONR_ET_S) & UDCCONR_ET;
tmp |= ep_isout ? 0 : UDCCONR_ED;
tmp |= (ep_size << UDCCONR_MPS_S) & UDCCONR_MPS;
tmp |= UDCCONR_EE;
writel(tmp, UDCCN(ep_num));
usbdbg("UDCCR%c = %x", 'A' + ep_num-1, readl(UDCCN(ep_num)));
usbdbg("UDCCSR%c = %x", 'A' + ep_num-1, readl(UDCCSN(ep_num)));
}
/* Connect the USB device to the bus */
void udc_connect(void)
{
usbdbg("UDC connect");
#ifdef CONFIG_USB_DEV_PULLUP_GPIO
/* Turn on the USB connection by enabling the pullup resistor */
writel(readl(GPDR(CONFIG_USB_DEV_PULLUP_GPIO))
| GPIO_bit(CONFIG_USB_DEV_PULLUP_GPIO),
GPDR(CONFIG_USB_DEV_PULLUP_GPIO));
writel(GPIO_bit(CONFIG_USB_DEV_PULLUP_GPIO), GPSR(CONFIG_USB_DEV_PULLUP_GPIO));
#else
/* Host port 2 transceiver D+ pull up enable */
writel(readl(UP2OCR) | UP2OCR_DPPUE, UP2OCR);
#endif
}
/* Disconnect the USB device to the bus */
void udc_disconnect(void)
{
usbdbg("UDC disconnect");
#ifdef CONFIG_USB_DEV_PULLUP_GPIO
/* Turn off the USB connection by disabling the pullup resistor */
writel(GPIO_bit(CONFIG_USB_DEV_PULLUP_GPIO), GPCR(CONFIG_USB_DEV_PULLUP_GPIO));
#else
/* Host port 2 transceiver D+ pull up disable */
writel(readl(UP2OCR) & ~UP2OCR_DPPUE, UP2OCR);
#endif
}
/* Switch on the UDC */
void udc_enable(struct usb_device_instance *device)
{
ep0state = EP0_IDLE;
/* enable endpoint 0, A, B's Packet Complete Interrupt. */
writel(0xffffffff, UDCICR0);
writel(0xa8000000, UDCICR1);
/* clear the interrupt status/control registers */
writel(0xffffffff, UDCISR0);
writel(0xffffffff, UDCISR1);
/* set UDC-enable */
udc_set_mask_UDCCR(UDCCR_UDE);
udc_device = device;
if (!ep0_urb)
ep0_urb = usbd_alloc_urb(udc_device,
udc_device->bus->endpoint_array);
else
usbinfo("ep0_urb %p already allocated", ep0_urb);
usbdbg("UDC Enabled\n");
}
/* Need to check this again */
void udc_disable(void)
{
usbdbg("disable UDC");
udc_clear_mask_UDCCR(UDCCR_UDE);
/* Disable clock for USB device */
writel(readl(CKEN) & ~CKEN11_USB, CKEN);
/* Free ep0 URB */
if (ep0_urb) {
usbd_dealloc_urb(ep0_urb);
ep0_urb = NULL;
}
/* Reset device pointer */
udc_device = NULL;
}
/* Allow udc code to do any additional startup */
void udc_startup_events(struct usb_device_instance *device)
{
/* The DEVICE_INIT event puts the USB device in the state STATE_INIT */
usbd_device_event_irq(device, DEVICE_INIT, 0);
/* The DEVICE_CREATE event puts the USB device in the state
* STATE_ATTACHED */
usbd_device_event_irq(device, DEVICE_CREATE, 0);
/* Some USB controller driver implementations signal
* DEVICE_HUB_CONFIGURED and DEVICE_RESET events here.
* DEVICE_HUB_CONFIGURED causes a transition to the state
* STATE_POWERED, and DEVICE_RESET causes a transition to
* the state STATE_DEFAULT.
*/
udc_enable(device);
}
/* Initialize h/w stuff */
int udc_init(void)
{
udc_device = NULL;
usbdbg("PXA27x usbd start");
/* Enable clock for USB device */
writel(readl(CKEN) | CKEN11_USB, CKEN);
/* Disable the UDC */
udc_clear_mask_UDCCR(UDCCR_UDE);
/* Disable IRQs: we don't use them */
writel(0, UDCICR0);
writel(0, UDCICR1);
return 0;
}

1
drivers/video/Makefile
View file

@ -36,7 +36,6 @@ obj-$(CONFIG_LG4573) += lg4573.o
obj-$(CONFIG_LOGICORE_DP_TX) += logicore_dp_tx.o
obj-$(CONFIG_NXP_TDA19988) += tda19988.o
obj-$(CONFIG_OSD) += video_osd-uclass.o
obj-$(CONFIG_PXA_LCD) += pxa_lcd.o
obj-$(CONFIG_SANDBOX_OSD) += sandbox_osd.o
obj-$(CONFIG_SCF0403_LCD) += scf0403_lcd.o
obj-$(CONFIG_VIDEO_ARM_MALIDP) += mali_dp.o

549
drivers/video/pxa_lcd.c
View file

@ -1,549 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* PXA LCD Controller
*
* (C) Copyright 2001-2002
* Wolfgang Denk, DENX Software Engineering -- wd@denx.de
*/
/************************************************************************/
/* ** HEADER FILES */
/************************************************************************/
#include <common.h>
#include <log.h>
#include <asm/arch/pxa-regs.h>
#include <asm/io.h>
#include <lcd.h>
#include <linux/types.h>
#include <stdarg.h>
#include <stdio_dev.h>
/* #define DEBUG */
#ifdef CONFIG_LCD
/*----------------------------------------------------------------------*/
/*
* Define panel bpp, LCCR0, LCCR3 and panel_info video struct for
* your display.
*/
#ifdef CONFIG_PXA_VGA
/* LCD outputs connected to a video DAC */
# define LCD_BPP LCD_COLOR8
/* you have to set lccr0 and lccr3 (including pcd) */
# define REG_LCCR0 0x003008f8
# define REG_LCCR3 0x0300FF01
/* 640x480x16 @ 61 Hz */
vidinfo_t panel_info = {
.vl_col = 640,
.vl_row = 480,
.vl_width = 640,
.vl_height = 480,
.vl_clkp = CONFIG_SYS_HIGH,
.vl_oep = CONFIG_SYS_HIGH,
.vl_hsp = CONFIG_SYS_HIGH,
.vl_vsp = CONFIG_SYS_HIGH,
.vl_dp = CONFIG_SYS_HIGH,
.vl_bpix = LCD_BPP,
.vl_lbw = 0,
.vl_splt = 0,
.vl_clor = 0,
.vl_tft = 1,
.vl_hpw = 40,
.vl_blw = 56,
.vl_elw = 56,
.vl_vpw = 20,
.vl_bfw = 8,
.vl_efw = 8,
};
#endif /* CONFIG_PXA_VIDEO */
/*----------------------------------------------------------------------*/
#ifdef CONFIG_SHARP_LM8V31
# define LCD_BPP LCD_COLOR8
# define LCD_INVERT_COLORS /* Needed for colors to be correct, but why? */
/* you have to set lccr0 and lccr3 (including pcd) */
# define REG_LCCR0 0x0030087C
# define REG_LCCR3 0x0340FF08
vidinfo_t panel_info = {
.vl_col = 640,
.vl_row = 480,
.vl_width = 157,
.vl_height = 118,
.vl_clkp = CONFIG_SYS_HIGH,
.vl_oep = CONFIG_SYS_HIGH,
.vl_hsp = CONFIG_SYS_HIGH,
.vl_vsp = CONFIG_SYS_HIGH,
.vl_dp = CONFIG_SYS_HIGH,
.vl_bpix = LCD_BPP,
.vl_lbw = 0,
.vl_splt = 1,
.vl_clor = 1,
.vl_tft = 0,
.vl_hpw = 1,
.vl_blw = 3,
.vl_elw = 3,
.vl_vpw = 1,
.vl_bfw = 0,
.vl_efw = 0,
};
#endif /* CONFIG_SHARP_LM8V31 */
/*----------------------------------------------------------------------*/
#ifdef CONFIG_VOIPAC_LCD
# define LCD_BPP LCD_COLOR8
# define LCD_INVERT_COLORS
/* you have to set lccr0 and lccr3 (including pcd) */
# define REG_LCCR0 0x043008f8
# define REG_LCCR3 0x0340FF08
vidinfo_t panel_info = {
.vl_col = 640,
.vl_row = 480,
.vl_width = 157,
.vl_height = 118,
.vl_clkp = CONFIG_SYS_HIGH,
.vl_oep = CONFIG_SYS_HIGH,
.vl_hsp = CONFIG_SYS_HIGH,
.vl_vsp = CONFIG_SYS_HIGH,
.vl_dp = CONFIG_SYS_HIGH,
.vl_bpix = LCD_BPP,
.vl_lbw = 0,
.vl_splt = 1,
.vl_clor = 1,
.vl_tft = 1,
.vl_hpw = 32,
.vl_blw = 144,
.vl_elw = 32,
.vl_vpw = 2,
.vl_bfw = 13,
.vl_efw = 30,
};
#endif /* CONFIG_VOIPAC_LCD */
/*----------------------------------------------------------------------*/
#ifdef CONFIG_HITACHI_SX14
/* Hitachi SX14Q004-ZZA color STN LCD */
#define LCD_BPP LCD_COLOR8
/* you have to set lccr0 and lccr3 (including pcd) */
#define REG_LCCR0 0x00301079
#define REG_LCCR3 0x0340FF20
vidinfo_t panel_info = {
.vl_col = 320,
.vl_row = 240,
.vl_width = 167,
.vl_height = 109,
.vl_clkp = CONFIG_SYS_HIGH,
.vl_oep = CONFIG_SYS_HIGH,
.vl_hsp = CONFIG_SYS_HIGH,
.vl_vsp = CONFIG_SYS_HIGH,
.vl_dp = CONFIG_SYS_HIGH,
.vl_bpix = LCD_BPP,
.vl_lbw = 1,
.vl_splt = 0,
.vl_clor = 1,
.vl_tft = 0,
.vl_hpw = 1,
.vl_blw = 1,
.vl_elw = 1,
.vl_vpw = 7,
.vl_bfw = 0,
.vl_efw = 0,
};
#endif /* CONFIG_HITACHI_SX14 */
/*----------------------------------------------------------------------*/
#ifdef CONFIG_LMS283GF05
# define LCD_BPP LCD_COLOR8
/*# define LCD_INVERT_COLORS*/
/* you have to set lccr0 and lccr3 (including pcd) */
# define REG_LCCR0 0x043008f8
# define REG_LCCR3 0x03b00009
vidinfo_t panel_info = {
.vl_col = 240,
.vl_row = 320,
.vl_rot = 3,
.vl_width = 240,
.vl_height = 320,
.vl_clkp = CONFIG_SYS_HIGH,
.vl_oep = CONFIG_SYS_LOW,
.vl_hsp = CONFIG_SYS_LOW,
.vl_vsp = CONFIG_SYS_LOW,
.vl_dp = CONFIG_SYS_HIGH,
.vl_bpix = LCD_BPP,
.vl_lbw = 0,
.vl_splt = 1,
.vl_clor = 1,
.vl_tft = 1,
.vl_hpw = 4,
.vl_blw = 4,
.vl_elw = 8,
.vl_vpw = 4,
.vl_bfw = 4,
.vl_efw = 8,
};
#endif /* CONFIG_LMS283GF05 */
/*----------------------------------------------------------------------*/
#ifdef CONFIG_LQ038J7DH53
# define LCD_BPP LCD_COLOR8
/* you have to set lccr0 and lccr3 (including pcd) */
# define REG_LCCR0 0x003008f9
# define REG_LCCR3 0x03700004
vidinfo_t panel_info = {
.vl_col = 320,
.vl_row = 480,
.vl_width = 320,
.vl_height = 480,
.vl_clkp = CONFIG_SYS_HIGH,
.vl_oep = CONFIG_SYS_LOW,
.vl_hsp = CONFIG_SYS_LOW,
.vl_vsp = CONFIG_SYS_LOW,
.vl_dp = CONFIG_SYS_HIGH,
.vl_bpix = LCD_BPP,
.vl_lbw = 0,
.vl_splt = 1,
.vl_clor = 1,
.vl_tft = 1,
.vl_hpw = 0x04,
.vl_blw = 0x20,
.vl_elw = 0x01,
.vl_vpw = 0x01,
.vl_bfw = 0x04,
.vl_efw = 0x01,
};
#endif /* CONFIG_LQ038J7DH53 */
/*----------------------------------------------------------------------*/
#ifdef CONFIG_LITTLETON_LCD
# define LCD_BPP LCD_COLOR8
/* you have to set lccr0 and lccr3 (including pcd) */
# define REG_LCCR0 0x003008f8
# define REG_LCCR3 0x0300FF04
vidinfo_t panel_info = {
.vl_col = 480,
.vl_row = 640,
.vl_width = 480,
.vl_height = 640,
.vl_clkp = CONFIG_SYS_HIGH,
.vl_oep = CONFIG_SYS_HIGH,
.vl_hsp = CONFIG_SYS_HIGH,
.vl_vsp = CONFIG_SYS_HIGH,
.vl_dp = CONFIG_SYS_HIGH,
.vl_bpix = LCD_BPP,
.vl_lbw = 0,
.vl_splt = 0,
.vl_clor = 0,
.vl_tft = 1,
.vl_hpw = 9,
.vl_blw = 8,
.vl_elw = 24,
.vl_vpw = 2,
.vl_bfw = 2,
.vl_efw = 4,
};
#endif /* CONFIG_LITTLETON_LCD */
/*----------------------------------------------------------------------*/
static int pxafb_init_mem (void *lcdbase, vidinfo_t *vid);
static void pxafb_setup_gpio (vidinfo_t *vid);
static void pxafb_enable_controller (vidinfo_t *vid);
static int pxafb_init (vidinfo_t *vid);
/************************************************************************/
/* --------------- PXA chipset specific functions ------------------- */
/************************************************************************/
ushort *configuration_get_cmap(void)
{
struct pxafb_info *fbi = &panel_info.pxa;
return (ushort *)fbi->palette;
}
void lcd_ctrl_init (void *lcdbase)
{
pxafb_init_mem(lcdbase, &panel_info);
pxafb_init(&panel_info);
pxafb_setup_gpio(&panel_info);
pxafb_enable_controller(&panel_info);
}
/*----------------------------------------------------------------------*/
#if LCD_BPP == LCD_COLOR8
void
lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue)
{
struct pxafb_info *fbi = &panel_info.pxa;
unsigned short *palette = (unsigned short *)fbi->palette;
u_int val;
if (regno < fbi->palette_size) {
val = ((red << 8) & 0xf800);
val |= ((green << 4) & 0x07e0);
val |= (blue & 0x001f);
#ifdef LCD_INVERT_COLORS
palette[regno] = ~val;
#else
palette[regno] = val;
#endif
}
debug ("setcolreg: reg %2d @ %p: R=%02X G=%02X B=%02X => %04X\n",
regno, &palette[regno],
red, green, blue,
palette[regno]);
}
#endif /* LCD_COLOR8 */
/*----------------------------------------------------------------------*/
__weak void lcd_enable(void)
{
}
/************************************************************************/
/* ** PXA255 specific routines */
/************************************************************************/
/*
* Calculate fb size for VIDEOLFB_ATAG. Size returned contains fb,
* descriptors and palette areas.
*/
ulong calc_fbsize (void)
{
ulong size;
int line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8;
size = line_length * panel_info.vl_row;
size += PAGE_SIZE;
return size;
}
static int pxafb_init_mem (void *lcdbase, vidinfo_t *vid)
{
u_long palette_mem_size;
struct pxafb_info *fbi = &vid->pxa;
int fb_size = vid->vl_row * (vid->vl_col * NBITS (vid->vl_bpix)) / 8;
fbi->screen = (u_long)lcdbase;
fbi->palette_size = NBITS(vid->vl_bpix) == 8 ? 256 : 16;
palette_mem_size = fbi->palette_size * sizeof(u16);
debug("palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size);
/* locate palette and descs at end of page following fb */
fbi->palette = (u_long)lcdbase + fb_size + PAGE_SIZE - palette_mem_size;
return 0;
}
#ifdef CONFIG_CPU_MONAHANS
static inline void pxafb_setup_gpio (vidinfo_t *vid) {}
#else
static void pxafb_setup_gpio (vidinfo_t *vid)
{
u_long lccr0;
/*
* setup is based on type of panel supported
*/
lccr0 = vid->pxa.reg_lccr0;
/* 4 bit interface */
if ((lccr0 & LCCR0_CMS) && (lccr0 & LCCR0_SDS) && !(lccr0 & LCCR0_DPD))
{
debug("Setting GPIO for 4 bit data\n");
/* bits 58-61 */
writel(readl(GPDR1) | (0xf << 26), GPDR1);
writel((readl(GAFR1_U) & ~(0xff << 20)) | (0xaa << 20),
GAFR1_U);
/* bits 74-77 */
writel(readl(GPDR2) | (0xf << 10), GPDR2);
writel((readl(GAFR2_L) & ~(0xff << 20)) | (0xaa << 20),
GAFR2_L);
}
/* 8 bit interface */
else if (((lccr0 & LCCR0_CMS) && ((lccr0 & LCCR0_SDS) || (lccr0 & LCCR0_DPD))) ||
(!(lccr0 & LCCR0_CMS) && !(lccr0 & LCCR0_PAS) && !(lccr0 & LCCR0_SDS)))
{
debug("Setting GPIO for 8 bit data\n");
/* bits 58-65 */
writel(readl(GPDR1) | (0x3f << 26), GPDR1);
writel(readl(GPDR2) | (0x3), GPDR2);
writel((readl(GAFR1_U) & ~(0xfff << 20)) | (0xaaa << 20),
GAFR1_U);
writel((readl(GAFR2_L) & ~0xf) | (0xa), GAFR2_L);
/* bits 74-77 */
writel(readl(GPDR2) | (0xf << 10), GPDR2);
writel((readl(GAFR2_L) & ~(0xff << 20)) | (0xaa << 20),
GAFR2_L);
}
/* 16 bit interface */
else if (!(lccr0 & LCCR0_CMS) && ((lccr0 & LCCR0_SDS) || (lccr0 & LCCR0_PAS)))
{
debug("Setting GPIO for 16 bit data\n");
/* bits 58-77 */
writel(readl(GPDR1) | (0x3f << 26), GPDR1);
writel(readl(GPDR2) | 0x00003fff, GPDR2);
writel((readl(GAFR1_U) & ~(0xfff << 20)) | (0xaaa << 20),
GAFR1_U);
writel((readl(GAFR2_L) & 0xf0000000) | 0x0aaaaaaa, GAFR2_L);
}
else
{
printf("pxafb_setup_gpio: unable to determine bits per pixel\n");
}
}
#endif
static void pxafb_enable_controller (vidinfo_t *vid)
{
debug("Enabling LCD controller\n");
/* Sequence from 11.7.10 */
writel(vid->pxa.reg_lccr3, LCCR3);
writel(vid->pxa.reg_lccr2, LCCR2);
writel(vid->pxa.reg_lccr1, LCCR1);
writel(vid->pxa.reg_lccr0 & ~LCCR0_ENB, LCCR0);
writel(vid->pxa.fdadr0, FDADR0);
writel(vid->pxa.fdadr1, FDADR1);
writel(readl(LCCR0) | LCCR0_ENB, LCCR0);
#ifdef CONFIG_CPU_MONAHANS
writel(readl(CKENA) | CKENA_1_LCD, CKENA);
#else
writel(readl(CKEN) | CKEN16_LCD, CKEN);
#endif
debug("FDADR0 = 0x%08x\n", readl(FDADR0));
debug("FDADR1 = 0x%08x\n", readl(FDADR1));
debug("LCCR0 = 0x%08x\n", readl(LCCR0));
debug("LCCR1 = 0x%08x\n", readl(LCCR1));
debug("LCCR2 = 0x%08x\n", readl(LCCR2));
debug("LCCR3 = 0x%08x\n", readl(LCCR3));
}
static int pxafb_init (vidinfo_t *vid)
{
struct pxafb_info *fbi = &vid->pxa;
debug("Configuring PXA LCD\n");
fbi->reg_lccr0 = REG_LCCR0;
fbi->reg_lccr3 = REG_LCCR3;
debug("vid: vl_col=%d hslen=%d lm=%d rm=%d\n",
vid->vl_col, vid->vl_hpw,
vid->vl_blw, vid->vl_elw);
debug("vid: vl_row=%d vslen=%d um=%d bm=%d\n",
vid->vl_row, vid->vl_vpw,
vid->vl_bfw, vid->vl_efw);
fbi->reg_lccr1 =
LCCR1_DisWdth(vid->vl_col) +
LCCR1_HorSnchWdth(vid->vl_hpw) +
LCCR1_BegLnDel(vid->vl_blw) +
LCCR1_EndLnDel(vid->vl_elw);
fbi->reg_lccr2 =
LCCR2_DisHght(vid->vl_row) +
LCCR2_VrtSnchWdth(vid->vl_vpw) +
LCCR2_BegFrmDel(vid->vl_bfw) +
LCCR2_EndFrmDel(vid->vl_efw);
fbi->reg_lccr3 = REG_LCCR3 & ~(LCCR3_HSP | LCCR3_VSP);
fbi->reg_lccr3 |= (vid->vl_hsp ? LCCR3_HorSnchL : LCCR3_HorSnchH)
| (vid->vl_vsp ? LCCR3_VrtSnchL : LCCR3_VrtSnchH);
/* setup dma descriptors */
fbi->dmadesc_fblow = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 3*16);
fbi->dmadesc_fbhigh = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 2*16);
fbi->dmadesc_palette = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 1*16);
#define BYTES_PER_PANEL ((fbi->reg_lccr0 & LCCR0_SDS) ? \
(vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8 / 2) : \
(vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8))
/* populate descriptors */
fbi->dmadesc_fblow->fdadr = (u_long)fbi->dmadesc_fblow;
fbi->dmadesc_fblow->fsadr = fbi->screen + BYTES_PER_PANEL;
fbi->dmadesc_fblow->fidr = 0;
fbi->dmadesc_fblow->ldcmd = BYTES_PER_PANEL;
fbi->fdadr1 = (u_long)fbi->dmadesc_fblow; /* only used in dual-panel mode */
fbi->dmadesc_fbhigh->fsadr = fbi->screen;
fbi->dmadesc_fbhigh->fidr = 0;
fbi->dmadesc_fbhigh->ldcmd = BYTES_PER_PANEL;
fbi->dmadesc_palette->fsadr = fbi->palette;
fbi->dmadesc_palette->fidr = 0;
fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2) | LDCMD_PAL;
if( NBITS(vid->vl_bpix) < 12)
{
/* assume any mode with <12 bpp is palette driven */
fbi->dmadesc_palette->fdadr = (u_long)fbi->dmadesc_fbhigh;
fbi->dmadesc_fbhigh->fdadr = (u_long)fbi->dmadesc_palette;
/* flips back and forth between pal and fbhigh */
fbi->fdadr0 = (u_long)fbi->dmadesc_palette;
}
else
{
/* palette shouldn't be loaded in true-color mode */
fbi->dmadesc_fbhigh->fdadr = (u_long)fbi->dmadesc_fbhigh;
fbi->fdadr0 = (u_long)fbi->dmadesc_fbhigh; /* no pal just fbhigh */
}
debug("fbi->dmadesc_fblow = 0x%lx\n", (u_long)fbi->dmadesc_fblow);
debug("fbi->dmadesc_fbhigh = 0x%lx\n", (u_long)fbi->dmadesc_fbhigh);
debug("fbi->dmadesc_palette = 0x%lx\n", (u_long)fbi->dmadesc_palette);
debug("fbi->dmadesc_fblow->fdadr = 0x%lx\n", fbi->dmadesc_fblow->fdadr);
debug("fbi->dmadesc_fbhigh->fdadr = 0x%lx\n", fbi->dmadesc_fbhigh->fdadr);
debug("fbi->dmadesc_palette->fdadr = 0x%lx\n", fbi->dmadesc_palette->fdadr);
debug("fbi->dmadesc_fblow->fsadr = 0x%lx\n", fbi->dmadesc_fblow->fsadr);
debug("fbi->dmadesc_fbhigh->fsadr = 0x%lx\n", fbi->dmadesc_fbhigh->fsadr);
debug("fbi->dmadesc_palette->fsadr = 0x%lx\n", fbi->dmadesc_palette->fsadr);
debug("fbi->dmadesc_fblow->ldcmd = 0x%lx\n", fbi->dmadesc_fblow->ldcmd);
debug("fbi->dmadesc_fbhigh->ldcmd = 0x%lx\n", fbi->dmadesc_fbhigh->ldcmd);
debug("fbi->dmadesc_palette->ldcmd = 0x%lx\n", fbi->dmadesc_palette->ldcmd);
return 0;
}
/************************************************************************/
/************************************************************************/
#endif /* CONFIG_LCD */

22
include/dm/platform_data/pxa_mmc_gen.h
View file

@ -1,22 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (c) 2019 Marcel Ziswiler <marcel.ziswiler@toradex.com>
*/
#ifndef __PXA_MMC_GEN_H
#define __PXA_MMC_GEN_H
#include <mmc.h>
/*
* struct pxa_mmc_plat - information about a PXA MMC controller
*
* @base: MMC controller base register address
*/
struct pxa_mmc_plat {
struct mmc_config cfg;
struct mmc mmc;
struct pxa_mmc_regs *base;
};
#endif /* __PXA_MMC_GEN_H */

40
include/dm/platform_data/serial_pxa.h
View file

@ -1,40 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (c) 2016 Marcel Ziswiler <marcel.ziswiler@toradex.com>
*/
#ifndef __SERIAL_PXA_H
#define __SERIAL_PXA_H
/*
* The numbering scheme differs here for PXA25x, PXA27x and PXA3xx so we can
* easily handle enabling of clock.
*/
#ifdef CONFIG_CPU_MONAHANS
#define UART_CLK_BASE CKENA_21_BTUART
#define UART_CLK_REG CKENA
#define BTUART_INDEX 0
#define FFUART_INDEX 1
#define STUART_INDEX 2
#else /* PXA27x */
#define UART_CLK_BASE CKEN5_STUART
#define UART_CLK_REG CKEN
#define STUART_INDEX 0
#define FFUART_INDEX 1
#define BTUART_INDEX 2
#endif
/*
* struct pxa_serial_plat - information about a PXA port
*
* @base: Uart port base register address
* @port: Uart port index, for cpu with pinmux for uart / gpio
* baudrtatre: Uart port baudrate
*/
struct pxa_serial_plat {
struct pxa_uart_regs *base;
int port;
int baudrate;
};
#endif /* __SERIAL_PXA_H */

4
include/lcd.h
View file

@ -40,9 +40,7 @@ ulong lcd_setmem(ulong addr);
*/
void lcd_set_flush_dcache(int flush);
#if defined(CONFIG_CPU_PXA27X) || defined CONFIG_CPU_MONAHANS
#include <pxa_lcd.h>
#elif defined(CONFIG_ATMEL_LCD) || defined(CONFIG_ATMEL_HLCD)
#if defined(CONFIG_ATMEL_LCD) || defined(CONFIG_ATMEL_HLCD)
#include <atmel_lcd.h>
#elif defined(CONFIG_EXYNOS_FB)
#include <exynos_lcd.h>

80
include/pxa_lcd.h
View file

@ -1,80 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* pxa_lcd.h - PXA LCD Controller structures
*
* (C) Copyright 2001
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*/
#ifndef _PXA_LCD_H_
#define _PXA_LCD_H_
/*
* PXA LCD DMA descriptor
*/
struct pxafb_dma_descriptor {
u_long fdadr; /* Frame descriptor address register */
u_long fsadr; /* Frame source address register */
u_long fidr; /* Frame ID register */
u_long ldcmd; /* Command register */
};
/*
* PXA LCD info
*/
struct pxafb_info {
/* Misc registers */
u_long reg_lccr3;
u_long reg_lccr2;
u_long reg_lccr1;
u_long reg_lccr0;
u_long fdadr0;
u_long fdadr1;
/* DMA descriptors */
struct pxafb_dma_descriptor *dmadesc_fblow;
struct pxafb_dma_descriptor *dmadesc_fbhigh;
struct pxafb_dma_descriptor *dmadesc_palette;
u_long screen; /* physical address of frame buffer */
u_long palette; /* physical address of palette memory */
u_int palette_size;
};
/*
* LCD controller stucture for PXA CPU
*/
typedef struct vidinfo {
ushort vl_col; /* Number of columns (i.e. 640) */
ushort vl_row; /* Number of rows (i.e. 480) */
ushort vl_rot; /* Rotation of Display (0, 1, 2, 3) */
ushort vl_width; /* Width of display area in millimeters */
ushort vl_height; /* Height of display area in millimeters */
/* LCD configuration register */
u_char vl_clkp; /* Clock polarity */
u_char vl_oep; /* Output Enable polarity */
u_char vl_hsp; /* Horizontal Sync polarity */
u_char vl_vsp; /* Vertical Sync polarity */
u_char vl_dp; /* Data polarity */
u_char vl_bpix;/* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */
u_char vl_lbw; /* LCD Bus width, 0 = 4, 1 = 8 */
u_char vl_splt;/* Split display, 0 = single-scan, 1 = dual-scan */
u_char vl_clor; /* Color, 0 = mono, 1 = color */
u_char vl_tft; /* 0 = passive, 1 = TFT */
/* Horizontal control register. Timing from data sheet */
ushort vl_hpw; /* Horz sync pulse width */
u_char vl_blw; /* Wait before of line */
u_char vl_elw; /* Wait end of line */
/* Vertical control register. */
u_char vl_vpw; /* Vertical sync pulse width */
u_char vl_bfw; /* Wait before of frame */
u_char vl_efw; /* Wait end of frame */
/* PXA LCD controller params */
struct pxafb_info pxa;
} vidinfo_t;
#endif

31
include/usb/pxa27x_udc.h
View file

@ -1,31 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* PXA27x register declarations and HCD data structures
*
* Copyright (C) 2007 Rodolfo Giometti <giometti@linux.it>
* Copyright (C) 2007 Eurotech S.p.A. <info@eurotech.it>
*/
#ifndef __PXA270X_UDC_H__
#define __PXA270X_UDC_H__
#include <asm/byteorder.h>
/* Endpoint 0 states */
#define EP0_IDLE 0
#define EP0_IN_DATA 1
#define EP0_OUT_DATA 2
#define EP0_XFER_COMPLETE 3
/* Endpoint parameters */
#define MAX_ENDPOINTS 4
#define EP0_MAX_PACKET_SIZE 16
#define UDC_OUT_ENDPOINT 0x02
#define UDC_IN_ENDPOINT 0x01
#define UDC_INT_ENDPOINT 0x05
#endif