mirror of
https://github.com/AsahiLinux/u-boot
synced 2025-02-18 06:58:54 +00:00
Merge branch 'master' into hpc2
This commit is contained in:
roy zang
Zang Tiefei
commit
a41969e09b
39 changed files with 3775 additions and 40 deletions
24
CHANGELOG
24
CHANGELOG
|
|
@ -1,3 +1,27 @@
|
|||
commit c84bad0ef60e7055ab0bd49b93069509cecc382a
|
||||
Author: Bartlomiej Sieka <tur@semihalf.com>
|
||||
Date: Wed Dec 20 00:29:43 2006 +0100
|
||||
|
||||
Fix to make the baudrate changes immediate for the MCF52x2 family.
|
||||
|
||||
commit daa6e418bcc0c717752e8de939c213c790286096
|
||||
Author: Bartlomiej Sieka <tur@semihalf.com>
|
||||
Date: Wed Dec 20 00:27:32 2006 +0100
|
||||
|
||||
Preliminary support for the iDMR board (ColdFire).
|
||||
|
||||
commit cdb97a6678826f85e7c69eae6a1c113d034c9b10
|
||||
Author: Andrei Safronov <safronov@pollux.denx.de>
|
||||
Date: Fri Dec 8 16:23:08 2006 +0100
|
||||
|
||||
automatic update mechanism
|
||||
|
||||
commit dd520bf314c7add4183c5191692180f576f96b60
|
||||
Author: Wolfgang Denk <wd@pollux.denx.de>
|
||||
Date: Thu Nov 30 18:02:20 2006 +0100
|
||||
|
||||
Code cleanup.
|
||||
|
||||
commit 8d9a8610b8256331132227e9e6585c6bd5742787
|
||||
Author: Wolfgang Denk <wd@pollux.denx.de>
|
||||
Date: Thu Nov 30 01:54:07 2006 +0100
|
||||
|
|
|
|||
4
MAKEALL
4
MAKEALL
|
|
@ -300,8 +300,8 @@ LIST_microblaze=" \
|
|||
|
||||
LIST_coldfire=" \
|
||||
cobra5272 EB+MCF-EV123 EB+MCF-EV123_internal \
|
||||
M5271EVB M5272C3 M5282EVB TASREG \
|
||||
r5200 M5271EVB \
|
||||
idmr M5271EVB M5272C3 M5282EVB \
|
||||
TASREG r5200 M5271EVB \
|
||||
"
|
||||
|
||||
#########################################################################
|
||||
|
|
|
|||
6
Makefile
6
Makefile
|
|
@ -1539,6 +1539,9 @@ TQM8265_AA_config: unconfig
|
|||
fi
|
||||
@$(MKCONFIG) -a TQM8260 ppc mpc8260 tqm8260
|
||||
|
||||
TQM8272_config: unconfig
|
||||
@$(MKCONFIG) -a TQM8272 ppc mpc8260 tqm8272
|
||||
|
||||
VoVPN-GW_66MHz_config \
|
||||
VoVPN-GW_100MHz_config: unconfig
|
||||
@mkdir -p $(obj)include
|
||||
|
|
@ -1569,6 +1572,9 @@ EB+MCF-EV123_internal_config : unconfig
|
|||
@echo "TEXT_BASE = 0xF0000000"|tee $(obj)board/BuS/EB+MCF-EV123/textbase.mk
|
||||
@$(MKCONFIG) EB+MCF-EV123 m68k mcf52x2 EB+MCF-EV123 BuS
|
||||
|
||||
idmr_config : unconfig
|
||||
@$(MKCONFIG) $(@:_config=) m68k mcf52x2 idmr
|
||||
|
||||
M5271EVB_config : unconfig
|
||||
@$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5271evb
|
||||
|
||||
|
|
|
|||
|
|
@ -31,6 +31,8 @@ DECLARE_GLOBAL_DATA_PTR;
|
|||
|
||||
extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
|
||||
|
||||
ulong flash_get_size (ulong base, int banknum);
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
unsigned long sdr0_cust0;
|
||||
|
|
@ -152,6 +154,11 @@ int misc_init_r(void)
|
|||
*/
|
||||
|
||||
/* Re-do sizing to get full correct info */
|
||||
|
||||
/* adjust flash start and offset */
|
||||
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
|
||||
gd->bd->bi_flashoffset = 0;
|
||||
|
||||
#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
|
||||
mtdcr(ebccfga, pb3cr);
|
||||
#else
|
||||
|
|
@ -192,9 +199,10 @@ int misc_init_r(void)
|
|||
#endif
|
||||
mtdcr(ebccfgd, pbcr);
|
||||
|
||||
/* adjust flash start and offset */
|
||||
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
|
||||
gd->bd->bi_flashoffset = 0;
|
||||
/*
|
||||
* Re-check to get correct base address
|
||||
*/
|
||||
flash_get_size(gd->bd->bi_flashstart, 0);
|
||||
|
||||
#ifdef CFG_ENV_IS_IN_FLASH
|
||||
/* Monitor protection ON by default */
|
||||
|
|
|
|||
|
|
@ -105,7 +105,7 @@ static int ppchameleonevb_device_ready(struct mtd_info *mtdinfo)
|
|||
* Members with a "?" were not set in the merged testing-NAND branch,
|
||||
* so they are not set here either.
|
||||
*/
|
||||
void board_nand_init(struct nand_chip *nand)
|
||||
int board_nand_init(struct nand_chip *nand)
|
||||
{
|
||||
|
||||
nand->hwcontrol = ppchameleonevb_hwcontrol;
|
||||
|
|
@ -113,5 +113,6 @@ void board_nand_init(struct nand_chip *nand)
|
|||
nand->eccmode = NAND_ECC_SOFT;
|
||||
nand->chip_delay = NAND_BIG_DELAY_US;
|
||||
nand->options = NAND_SAMSUNG_LP_OPTIONS;
|
||||
return 0;
|
||||
}
|
||||
#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */
|
||||
|
|
|
|||
|
|
@ -448,7 +448,7 @@ static void dfc_gpio_init(void)
|
|||
* Members with a "?" were not set in the merged testing-NAND branch,
|
||||
* so they are not set here either.
|
||||
*/
|
||||
void board_nand_init(struct nand_chip *nand)
|
||||
int board_nand_init(struct nand_chip *nand)
|
||||
{
|
||||
unsigned long tCH, tCS, tWH, tWP, tRH, tRP, tRP_high, tR, tWHR, tAR;
|
||||
|
||||
|
|
@ -576,6 +576,7 @@ void board_nand_init(struct nand_chip *nand)
|
|||
nand->cmdfunc = dfc_cmdfunc;
|
||||
nand->autooob = &delta_oob;
|
||||
nand->badblock_pattern = &delta_bbt_descr;
|
||||
return 0;
|
||||
}
|
||||
|
||||
#else
|
||||
|
|
|
|||
44
board/idmr/Makefile
Normal file
44
board/idmr/Makefile
Normal file
|
|
@ -0,0 +1,44 @@
|
|||
#
|
||||
# (C) Copyright 2000-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS = $(BOARD).o flash.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS)
|
||||
$(AR) $(ARFLAGS) $@ $(OBJS)
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
25
board/idmr/config.mk
Normal file
25
board/idmr/config.mk
Normal file
|
|
@ -0,0 +1,25 @@
|
|||
#
|
||||
# (C) Copyright 2000-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
TEXT_BASE = 0xff800000
|
||||
356
board/idmr/flash.c
Normal file
356
board/idmr/flash.c
Normal file
|
|
@ -0,0 +1,356 @@
|
|||
/*
|
||||
* (C) Copyright 2000-2006
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
|
||||
#define PHYS_FLASH_1 CFG_FLASH_BASE
|
||||
#define FLASH_BANK_SIZE 0x800000
|
||||
#define EN29LV640 0x227e227e
|
||||
|
||||
flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
|
||||
|
||||
void flash_print_info (flash_info_t * info)
|
||||
{
|
||||
int i;
|
||||
|
||||
switch (info->flash_id & FLASH_VENDMASK) {
|
||||
case (AMD_MANUFACT & FLASH_VENDMASK):
|
||||
printf ("AMD: ");
|
||||
break;
|
||||
default:
|
||||
printf ("Unknown Vendor ");
|
||||
break;
|
||||
}
|
||||
|
||||
switch (info->flash_id & FLASH_TYPEMASK) {
|
||||
case (EN29LV640 & FLASH_TYPEMASK):
|
||||
printf ("EN29LV640 (16Mbit)\n");
|
||||
break;
|
||||
default:
|
||||
printf ("Unknown Chip Type\n");
|
||||
goto Done;
|
||||
break;
|
||||
}
|
||||
|
||||
printf (" Size: %ld MB in %d Sectors\n",
|
||||
info->size >> 20, info->sector_count);
|
||||
|
||||
printf (" Sector Start Addresses:");
|
||||
for (i = 0; i < info->sector_count; i++) {
|
||||
if ((i % 5) == 0) {
|
||||
printf ("\n ");
|
||||
}
|
||||
printf (" %08lX%s", info->start[i],
|
||||
info->protect[i] ? " (RO)" : " ");
|
||||
}
|
||||
printf ("\n");
|
||||
|
||||
Done:
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
unsigned long flash_init (void)
|
||||
{
|
||||
int i, j;
|
||||
ulong size = 0;
|
||||
|
||||
for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
|
||||
ulong flashbase = 0;
|
||||
|
||||
flash_info[i].flash_id =
|
||||
(AMD_MANUFACT & FLASH_VENDMASK) |
|
||||
(EN29LV640 & FLASH_TYPEMASK);
|
||||
flash_info[i].size = FLASH_BANK_SIZE;
|
||||
flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
|
||||
memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
|
||||
if (i == 0)
|
||||
flashbase = PHYS_FLASH_1;
|
||||
else
|
||||
panic ("configured to many flash banks!\n");
|
||||
|
||||
for (j = 0; j < flash_info[i].sector_count; j++) {
|
||||
flash_info[i].start[j] = flashbase + 0x10000 * j;
|
||||
}
|
||||
size += flash_info[i].size;
|
||||
}
|
||||
|
||||
flash_protect (FLAG_PROTECT_SET,
|
||||
CFG_FLASH_BASE,
|
||||
CFG_FLASH_BASE + 0x30000, &flash_info[0]);
|
||||
|
||||
return size;
|
||||
}
|
||||
|
||||
|
||||
#define CMD_READ_ARRAY 0x00F0
|
||||
#define CMD_UNLOCK1 0x00AA
|
||||
#define CMD_UNLOCK2 0x0055
|
||||
#define CMD_ERASE_SETUP 0x0080
|
||||
#define CMD_ERASE_CONFIRM 0x0030
|
||||
#define CMD_PROGRAM 0x00A0
|
||||
#define CMD_UNLOCK_BYPASS 0x0020
|
||||
|
||||
#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CFG_FLASH_BASE + (0x00000555<<1)))
|
||||
#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CFG_FLASH_BASE + (0x000002AA<<1)))
|
||||
|
||||
#define BIT_ERASE_DONE 0x0080
|
||||
#define BIT_RDY_MASK 0x0080
|
||||
#define BIT_PROGRAM_ERROR 0x0020
|
||||
#define BIT_TIMEOUT 0x80000000 /* our flag */
|
||||
|
||||
#define READY 1
|
||||
#define ERR 2
|
||||
#define TMO 4
|
||||
|
||||
|
||||
int flash_erase (flash_info_t * info, int s_first, int s_last)
|
||||
{
|
||||
ulong result;
|
||||
int iflag, prot, sect;
|
||||
int rc = ERR_OK;
|
||||
int chip1;
|
||||
|
||||
/* first look for protection bits */
|
||||
|
||||
if (info->flash_id == FLASH_UNKNOWN)
|
||||
return ERR_UNKNOWN_FLASH_TYPE;
|
||||
|
||||
if ((s_first < 0) || (s_first > s_last)) {
|
||||
return ERR_INVAL;
|
||||
}
|
||||
|
||||
if ((info->flash_id & FLASH_VENDMASK) !=
|
||||
(AMD_MANUFACT & FLASH_VENDMASK)) {
|
||||
return ERR_UNKNOWN_FLASH_VENDOR;
|
||||
}
|
||||
|
||||
prot = 0;
|
||||
for (sect = s_first; sect <= s_last; ++sect) {
|
||||
if (info->protect[sect]) {
|
||||
prot++;
|
||||
}
|
||||
}
|
||||
if (prot)
|
||||
return ERR_PROTECTED;
|
||||
|
||||
/*
|
||||
* Disable interrupts which might cause a timeout
|
||||
* here. Remember that our exception vectors are
|
||||
* at address 0 in the flash, and we don't want a
|
||||
* (ticker) exception to happen while the flash
|
||||
* chip is in programming mode.
|
||||
*/
|
||||
iflag = disable_interrupts ();
|
||||
|
||||
printf ("\n");
|
||||
|
||||
/* Start erase on unprotected sectors */
|
||||
for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
|
||||
printf ("Erasing sector %2d ... ", sect);
|
||||
|
||||
/* arm simple, non interrupt dependent timer */
|
||||
set_timer (0);
|
||||
|
||||
if (info->protect[sect] == 0) { /* not protected */
|
||||
volatile u16 *addr =
|
||||
(volatile u16 *) (info->start[sect]);
|
||||
|
||||
MEM_FLASH_ADDR1 = CMD_UNLOCK1;
|
||||
MEM_FLASH_ADDR2 = CMD_UNLOCK2;
|
||||
MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
|
||||
|
||||
MEM_FLASH_ADDR1 = CMD_UNLOCK1;
|
||||
MEM_FLASH_ADDR2 = CMD_UNLOCK2;
|
||||
*addr = CMD_ERASE_CONFIRM;
|
||||
|
||||
/* wait until flash is ready */
|
||||
chip1 = 0;
|
||||
|
||||
do {
|
||||
result = *addr;
|
||||
|
||||
/* check timeout */
|
||||
if (get_timer (0) > CFG_FLASH_ERASE_TOUT * CFG_HZ / 1000) {
|
||||
MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
|
||||
chip1 = TMO;
|
||||
break;
|
||||
}
|
||||
|
||||
if (!chip1
|
||||
&& (result & 0xFFFF) & BIT_ERASE_DONE)
|
||||
chip1 = READY;
|
||||
|
||||
} while (!chip1);
|
||||
|
||||
MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
|
||||
|
||||
if (chip1 == ERR) {
|
||||
rc = ERR_PROG_ERROR;
|
||||
goto outahere;
|
||||
}
|
||||
if (chip1 == TMO) {
|
||||
rc = ERR_TIMOUT;
|
||||
goto outahere;
|
||||
}
|
||||
|
||||
printf ("ok.\n");
|
||||
} else { /* it was protected */
|
||||
|
||||
printf ("protected!\n");
|
||||
}
|
||||
}
|
||||
|
||||
if (ctrlc ())
|
||||
printf ("User Interrupt!\n");
|
||||
|
||||
outahere:
|
||||
/* allow flash to settle - wait 10 ms */
|
||||
printf("Waiting 10 ms...");
|
||||
udelay (10000);
|
||||
|
||||
/* for (i = 0; i < 10 * 1000 * 1000; ++i)
|
||||
asm(" nop");
|
||||
*/
|
||||
|
||||
printf("done\n");
|
||||
if (iflag)
|
||||
enable_interrupts ();
|
||||
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
static int write_word (flash_info_t * info, ulong dest, ulong data)
|
||||
{
|
||||
volatile u16 *addr = (volatile u16 *) dest;
|
||||
ulong result;
|
||||
int rc = ERR_OK;
|
||||
int iflag;
|
||||
int chip1;
|
||||
|
||||
/*
|
||||
* Check if Flash is (sufficiently) erased
|
||||
*/
|
||||
result = *addr;
|
||||
if ((result & data) != data)
|
||||
return ERR_NOT_ERASED;
|
||||
|
||||
|
||||
/*
|
||||
* Disable interrupts which might cause a timeout
|
||||
* here. Remember that our exception vectors are
|
||||
* at address 0 in the flash, and we don't want a
|
||||
* (ticker) exception to happen while the flash
|
||||
* chip is in programming mode.
|
||||
*/
|
||||
iflag = disable_interrupts ();
|
||||
|
||||
MEM_FLASH_ADDR1 = CMD_UNLOCK1;
|
||||
MEM_FLASH_ADDR2 = CMD_UNLOCK2;
|
||||
MEM_FLASH_ADDR1 = CMD_PROGRAM;
|
||||
*addr = data;
|
||||
|
||||
/* arm simple, non interrupt dependent timer */
|
||||
set_timer (0);
|
||||
|
||||
/* wait until flash is ready */
|
||||
chip1 = 0;
|
||||
do {
|
||||
result = *addr;
|
||||
|
||||
/* check timeout */
|
||||
if (get_timer (0) > CFG_FLASH_ERASE_TOUT * CFG_HZ / 1000) {
|
||||
chip1 = ERR | TMO;
|
||||
break;
|
||||
}
|
||||
if (!chip1 && ((result & 0x80) == (data & 0x80)))
|
||||
chip1 = READY;
|
||||
|
||||
} while (!chip1);
|
||||
|
||||
*addr = CMD_READ_ARRAY;
|
||||
|
||||
if (chip1 == ERR || *addr != data)
|
||||
rc = ERR_PROG_ERROR;
|
||||
|
||||
if (iflag)
|
||||
enable_interrupts ();
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
|
||||
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
|
||||
{
|
||||
ulong wp, data;
|
||||
int rc;
|
||||
|
||||
if (addr & 1) {
|
||||
printf ("unaligned destination not supported\n");
|
||||
return ERR_ALIGN;
|
||||
}
|
||||
|
||||
#if 0
|
||||
if (cnt & 1) {
|
||||
printf ("odd transfer sizes not supported\n");
|
||||
return ERR_ALIGN;
|
||||
}
|
||||
#endif
|
||||
|
||||
wp = addr;
|
||||
|
||||
if (addr & 1) {
|
||||
data = (*((volatile u8 *) addr) << 8) | *((volatile u8 *)
|
||||
src);
|
||||
if ((rc = write_word (info, wp - 1, data)) != 0) {
|
||||
return (rc);
|
||||
}
|
||||
src += 1;
|
||||
wp += 1;
|
||||
cnt -= 1;
|
||||
}
|
||||
|
||||
while (cnt >= 2) {
|
||||
data = *((volatile u16 *) src);
|
||||
if ((rc = write_word (info, wp, data)) != 0) {
|
||||
return (rc);
|
||||
}
|
||||
src += 2;
|
||||
wp += 2;
|
||||
cnt -= 2;
|
||||
}
|
||||
|
||||
if (cnt == 1) {
|
||||
data = (*((volatile u8 *) src) << 8) |
|
||||
*((volatile u8 *) (wp + 1));
|
||||
if ((rc = write_word (info, wp, data)) != 0) {
|
||||
return (rc);
|
||||
}
|
||||
src += 1;
|
||||
wp += 1;
|
||||
cnt -= 1;
|
||||
}
|
||||
|
||||
return ERR_OK;
|
||||
}
|
||||
169
board/idmr/idmr.c
Normal file
169
board/idmr/idmr.c
Normal file
|
|
@ -0,0 +1,169 @@
|
|||
/*
|
||||
* (C) Copyright 2000-2006
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/m5271.h>
|
||||
#include <asm/immap_5271.h>
|
||||
|
||||
int checkboard (void) {
|
||||
puts ("Board: iDMR\n");
|
||||
return 0;
|
||||
};
|
||||
|
||||
long int initdram (int board_type) {
|
||||
int i;
|
||||
|
||||
/*
|
||||
* After reset, CS0 is configured to cover entire address space. We
|
||||
* need to configure it to its proper values, so that writes to
|
||||
* CFG_SDRAM_BASE and vicinity during SDRAM controller setup below do
|
||||
* now fall under CS0 (see 16.3.1 of the MCF5271 Reference Manual).
|
||||
*/
|
||||
|
||||
/* Flash chipselect, CS0 */
|
||||
/* ;CSAR0: Flash at 0xFF800000 */
|
||||
mbar_writeShort(0x0080, 0xFF80);
|
||||
|
||||
/* CSCR0: Flash 6 waits, 16bit */
|
||||
mbar_writeShort(0x008A, 0x1980);
|
||||
|
||||
/* CSMR0: Flash 8MB, R/W, valid */
|
||||
mbar_writeLong(0x0084, 0x007F0001);
|
||||
|
||||
|
||||
/*
|
||||
* SDRAM configuration proper
|
||||
*/
|
||||
|
||||
/*
|
||||
* Address/Data Pin Assignment Reg.: enable address lines 23-21; do
|
||||
* not enable data pins D[15:0], as we have 16 bit port to SDRAM
|
||||
*/
|
||||
mbar_writeByte(MCF_GPIO_PAR_AD,
|
||||
MCF_GPIO_AD_ADDR23 |
|
||||
MCF_GPIO_AD_ADDR22 |
|
||||
MCF_GPIO_AD_ADDR21);
|
||||
|
||||
/* No need to configure BS pins - reset values are OK */
|
||||
|
||||
/* Chip Select Pin Assignment Reg.: set CS[1-7] to GPIO */
|
||||
mbar_writeByte(MCF_GPIO_PAR_CS, 0x00);
|
||||
|
||||
/* SDRAM Control Pin Assignment Reg. */
|
||||
mbar_writeByte(MCF_GPIO_PAR_SDRAM,
|
||||
MCF_GPIO_SDRAM_CSSDCS_00 | /* no matter: PAR_CS=0 */
|
||||
MCF_GPIO_SDRAM_SDWE |
|
||||
MCF_GPIO_SDRAM_SCAS |
|
||||
MCF_GPIO_SDRAM_SRAS |
|
||||
MCF_GPIO_SDRAM_SCKE |
|
||||
MCF_GPIO_SDRAM_SDCS_01);
|
||||
|
||||
/*
|
||||
* Wait 100us. We run the bus at 50Mhz, one cycle is 20ns. So 5
|
||||
* iterations will do, but we do 10 just to be safe.
|
||||
*/
|
||||
for (i = 0; i < 10; ++i)
|
||||
asm(" nop");
|
||||
|
||||
|
||||
/* 1. Initialize DRAM Control Register: DCR */
|
||||
mbar_writeShort(MCF_SDRAMC_DCR,
|
||||
MCF_SDRAMC_DCR_RTIM(0x10) | /* 65ns */
|
||||
MCF_SDRAMC_DCR_RC(0x60)); /* 1562 cycles */
|
||||
|
||||
|
||||
/*
|
||||
* 2. Initialize DACR0
|
||||
*
|
||||
* CL: 11 (CL=3: 0x03, 0x02; CL=2: 0x1)
|
||||
* CBM: cmd at A20, bank select bits 21 and up
|
||||
* PS: 16 bit
|
||||
*/
|
||||
mbar_writeLong(MCF_SDRAMC_DACR0,
|
||||
MCF_SDRAMC_DACRn_BA(CFG_SDRAM_BASE>>18) |
|
||||
MCF_SDRAMC_DACRn_BA(0x00) |
|
||||
MCF_SDRAMC_DACRn_CASL(0x03) |
|
||||
MCF_SDRAMC_DACRn_CBM(0x03) |
|
||||
MCF_SDRAMC_DACRn_PS(0x03));
|
||||
|
||||
/* Initialize DMR0 */
|
||||
mbar_writeLong(MCF_SDRAMC_DMR0,
|
||||
MCF_SDRAMC_DMRn_BAM_16M |
|
||||
MCF_SDRAMC_DMRn_V);
|
||||
|
||||
|
||||
/* 3. Set IP bit in DACR to initiate PALL command */
|
||||
mbar_writeLong(MCF_SDRAMC_DACR0,
|
||||
mbar_readLong(MCF_SDRAMC_DACR0) |
|
||||
MCF_SDRAMC_DACRn_IP);
|
||||
|
||||
/* Write to this block to initiate precharge */
|
||||
*(volatile u16 *)(CFG_SDRAM_BASE) = 0xa5a5;
|
||||
|
||||
/*
|
||||
* Wait at least 20ns to allow banks to precharge (t_RP = 20ns). We
|
||||
* wait a wee longer, just to be safe.
|
||||
*/
|
||||
for (i = 0; i < 5; ++i)
|
||||
asm(" nop");
|
||||
|
||||
|
||||
/* 4. Set RE bit in DACR */
|
||||
mbar_writeLong(MCF_SDRAMC_DACR0,
|
||||
mbar_readLong(MCF_SDRAMC_DACR0) |
|
||||
MCF_SDRAMC_DACRn_RE);
|
||||
|
||||
/*
|
||||
* Wait for at least 8 auto refresh cycles to occur, i.e. at least
|
||||
* 781 bus cycles.
|
||||
*/
|
||||
for (i = 0; i < 1000; ++i)
|
||||
asm(" nop");
|
||||
|
||||
/* Finish the configuration by issuing the MRS */
|
||||
mbar_writeLong(MCF_SDRAMC_DACR0,
|
||||
mbar_readLong(MCF_SDRAMC_DACR0) |
|
||||
MCF_SDRAMC_DACRn_MRS);
|
||||
|
||||
/*
|
||||
* Write to the SDRAM Mode Register A0-A11 = 0x400
|
||||
*
|
||||
* Write Burst Mode = Programmed Burst Length
|
||||
* Op Mode = Standard Op
|
||||
* CAS Latency = 3
|
||||
* Burst Type = Sequential
|
||||
* Burst Length = 1
|
||||
*/
|
||||
*(volatile u32 *)(CFG_SDRAM_BASE + 0x1800) = 0xa5a5a5a5;
|
||||
|
||||
return CFG_SDRAM_SIZE * 1024 * 1024;
|
||||
};
|
||||
|
||||
|
||||
int testdram (void) {
|
||||
|
||||
/* TODO: XXX XXX XXX */
|
||||
printf ("DRAM test not implemented!\n");
|
||||
|
||||
return (0);
|
||||
}
|
||||
145
board/idmr/u-boot.lds
Normal file
145
board/idmr/u-boot.lds
Normal file
|
|
@ -0,0 +1,145 @@
|
|||
/*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(m68k)
|
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
|
||||
/* Do we need any of these for elf?
|
||||
__DYNAMIC = 0; */
|
||||
GROUP(libgcc.a)
|
||||
SECTIONS
|
||||
{
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.interp : { *(.interp) }
|
||||
.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.rel.text : { *(.rel.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rel.data : { *(.rel.data) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rel.got : { *(.rel.got) }
|
||||
.rela.got : { *(.rela.got) }
|
||||
.rel.ctors : { *(.rel.ctors) }
|
||||
.rela.ctors : { *(.rela.ctors) }
|
||||
.rel.dtors : { *(.rel.dtors) }
|
||||
.rela.dtors : { *(.rela.dtors) }
|
||||
.rel.bss : { *(.rel.bss) }
|
||||
.rela.bss : { *(.rela.bss) }
|
||||
.rel.plt : { *(.rel.plt) }
|
||||
.rela.plt : { *(.rela.plt) }
|
||||
.init : { *(.init) }
|
||||
.plt : { *(.plt) }
|
||||
.text :
|
||||
{
|
||||
/* WARNING - the following is hand-optimized to fit within */
|
||||
/* the sector layout of our flash chips! XXX FIXME XXX */
|
||||
|
||||
cpu/mcf52x2/start.o (.text)
|
||||
lib_m68k/traps.o (.text)
|
||||
cpu/mcf52x2/interrupts.o (.text)
|
||||
common/dlmalloc.o (.text)
|
||||
lib_generic/zlib.o (.text)
|
||||
|
||||
. = DEFINED(env_offset) ? env_offset : .;
|
||||
common/environment.o (.ppcenv)
|
||||
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
*(.got1)
|
||||
}
|
||||
_etext = .;
|
||||
PROVIDE (etext = .);
|
||||
.rodata :
|
||||
{
|
||||
*(.rodata)
|
||||
*(.rodata1)
|
||||
}
|
||||
.fini : { *(.fini) } =0
|
||||
.ctors : { *(.ctors) }
|
||||
.dtors : { *(.dtors) }
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x00FF) & 0xFFFFFF00;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
|
||||
.reloc :
|
||||
{
|
||||
__got_start = .;
|
||||
*(.got)
|
||||
__got_end = .;
|
||||
_GOT2_TABLE_ = .;
|
||||
*(.got2)
|
||||
_FIXUP_TABLE_ = .;
|
||||
*(.fixup)
|
||||
}
|
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.dynamic)
|
||||
CONSTRUCTORS
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
. = .;
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
|
||||
. = .;
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(256);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(256);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
_sbss = .;
|
||||
*(.sbss) *(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_ebss = .;
|
||||
}
|
||||
_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
||||
|
|
@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
|
|||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS := $(BOARD).o lcd.o
|
||||
COBJS := $(BOARD).o lcd.o auto_update.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
|
|
|||
457
board/mcc200/auto_update.c
Normal file
457
board/mcc200/auto_update.c
Normal file
|
|
@ -0,0 +1,457 @@
|
|||
/*
|
||||
* (C) Copyright 2006
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <malloc.h>
|
||||
#include <image.h>
|
||||
#include <asm/byteorder.h>
|
||||
#include <usb.h>
|
||||
|
||||
#ifdef CFG_HUSH_PARSER
|
||||
#include <hush.h>
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef CONFIG_AUTO_UPDATE
|
||||
|
||||
#ifndef CONFIG_USB_OHCI
|
||||
#error "must define CONFIG_USB_OHCI"
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_USB_STORAGE
|
||||
#error "must define CONFIG_USB_STORAGE"
|
||||
#endif
|
||||
|
||||
#ifndef CFG_HUSH_PARSER
|
||||
#error "must define CFG_HUSH_PARSER"
|
||||
#endif
|
||||
|
||||
#if !(CONFIG_COMMANDS & CFG_CMD_FAT)
|
||||
#error "must define CFG_CMD_FAT"
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Check whether a USB memory stick is plugged in.
|
||||
* If one is found:
|
||||
* 1) if prepare.img ist found load it into memory. If it is
|
||||
* valid then run it.
|
||||
* 2) if preinst.img is found load it into memory. If it is
|
||||
* valid then run it. Update the EEPROM.
|
||||
* 3) if firmw_01.img is found load it into memory. If it is valid,
|
||||
* burn it into FLASH and update the EEPROM.
|
||||
* 4) if kernl_01.img is found load it into memory. If it is valid,
|
||||
* burn it into FLASH and update the EEPROM.
|
||||
* 5) if app.img is found load it into memory. If it is valid,
|
||||
* burn it into FLASH and update the EEPROM.
|
||||
* 6) if disk.img is found load it into memory. If it is valid,
|
||||
* burn it into FLASH and update the EEPROM.
|
||||
* 7) if postinst.img is found load it into memory. If it is
|
||||
* valid then run it. Update the EEPROM.
|
||||
*/
|
||||
|
||||
#undef AU_DEBUG
|
||||
|
||||
#undef debug
|
||||
#ifdef AU_DEBUG
|
||||
#define debug(fmt,args...) printf (fmt ,##args)
|
||||
#else
|
||||
#define debug(fmt,args...)
|
||||
#endif /* AU_DEBUG */
|
||||
|
||||
/* possible names of files on the USB stick. */
|
||||
#define AU_FIRMWARE "u-boot.img"
|
||||
#define AU_KERNEL "kernel.img"
|
||||
|
||||
struct flash_layout {
|
||||
long start;
|
||||
long end;
|
||||
};
|
||||
|
||||
/* layout of the FLASH. ST = start address, ND = end address. */
|
||||
#define AU_FL_FIRMWARE_ST 0xfC000000
|
||||
#define AU_FL_FIRMWARE_ND 0xfC03FFFF
|
||||
#define AU_FL_KERNEL_ST 0xfC0C0000
|
||||
#define AU_FL_KERNEL_ND 0xfC1BFFFF
|
||||
|
||||
static int au_usb_stor_curr_dev; /* current device */
|
||||
|
||||
/* index of each file in the following arrays */
|
||||
#define IDX_FIRMWARE 0
|
||||
#define IDX_KERNEL 1
|
||||
|
||||
/* max. number of files which could interest us */
|
||||
#define AU_MAXFILES 2
|
||||
|
||||
/* pointers to file names */
|
||||
char *aufile[AU_MAXFILES];
|
||||
|
||||
/* sizes of flash areas for each file */
|
||||
long ausize[AU_MAXFILES];
|
||||
|
||||
/* array of flash areas start and end addresses */
|
||||
struct flash_layout aufl_layout[AU_MAXFILES] = { \
|
||||
{AU_FL_FIRMWARE_ST, AU_FL_FIRMWARE_ND,}, \
|
||||
{AU_FL_KERNEL_ST, AU_FL_KERNEL_ND,}, \
|
||||
};
|
||||
|
||||
/* where to load files into memory */
|
||||
#define LOAD_ADDR ((unsigned char *)0x00200000)
|
||||
|
||||
/* the app is the largest image */
|
||||
#define MAX_LOADSZ ausize[IDX_KERNEL]
|
||||
|
||||
/*i2c address of the keypad status*/
|
||||
#define I2C_PSOC_KEYPAD_ADDR 0x53
|
||||
|
||||
/* keypad mask */
|
||||
#define KEYPAD_ROW 3
|
||||
#define KEYPAD_COL 3
|
||||
#define KEYPAD_MASK_LO ((1<<(KEYPAD_COL-1+(KEYPAD_ROW*4-4)))&0xFF)
|
||||
#define KEYPAD_MASK_HI ((1<<(KEYPAD_COL-1+(KEYPAD_ROW*4-4)))>>8)
|
||||
|
||||
/* externals */
|
||||
extern int fat_register_device(block_dev_desc_t *, int);
|
||||
extern int file_fat_detectfs(void);
|
||||
extern long file_fat_read(const char *, void *, unsigned long);
|
||||
extern int i2c_read (unsigned char, unsigned int, int , unsigned char* , int);
|
||||
extern int flash_sect_erase(ulong, ulong);
|
||||
extern int flash_sect_protect (int, ulong, ulong);
|
||||
extern int flash_write (char *, ulong, ulong);
|
||||
/* change char* to void* to shutup the compiler */
|
||||
extern block_dev_desc_t *get_dev (char*, int);
|
||||
extern int u_boot_hush_start(void);
|
||||
|
||||
int au_check_cksum_valid(int idx, long nbytes)
|
||||
{
|
||||
image_header_t *hdr;
|
||||
unsigned long checksum;
|
||||
|
||||
hdr = (image_header_t *)LOAD_ADDR;
|
||||
|
||||
if (nbytes != (sizeof(*hdr) + ntohl(hdr->ih_size))) {
|
||||
printf ("Image %s bad total SIZE\n", aufile[idx]);
|
||||
return -1;
|
||||
}
|
||||
/* check the data CRC */
|
||||
checksum = ntohl(hdr->ih_dcrc);
|
||||
|
||||
if (crc32 (0, (uchar *)(LOAD_ADDR + sizeof(*hdr)), ntohl(hdr->ih_size)) != checksum) {
|
||||
printf ("Image %s bad data checksum\n", aufile[idx]);
|
||||
return -1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
int au_check_header_valid(int idx, long nbytes)
|
||||
{
|
||||
image_header_t *hdr;
|
||||
unsigned long checksum;
|
||||
unsigned char buf[4];
|
||||
|
||||
hdr = (image_header_t *)LOAD_ADDR;
|
||||
/* check the easy ones first */
|
||||
#undef CHECK_VALID_DEBUG
|
||||
#ifdef CHECK_VALID_DEBUG
|
||||
printf("magic %#x %#x ", ntohl(hdr->ih_magic), IH_MAGIC);
|
||||
printf("arch %#x %#x ", hdr->ih_arch, IH_CPU_ARM);
|
||||
printf("size %#x %#lx ", ntohl(hdr->ih_size), nbytes);
|
||||
printf("type %#x %#x ", hdr->ih_type, IH_TYPE_KERNEL);
|
||||
#endif
|
||||
if (nbytes < sizeof(*hdr)) {
|
||||
printf ("Image %s bad header SIZE\n", aufile[idx]);
|
||||
return -1;
|
||||
}
|
||||
if (ntohl(hdr->ih_magic) != IH_MAGIC || hdr->ih_arch != IH_CPU_PPC) {
|
||||
printf ("Image %s bad MAGIC or ARCH\n", aufile[idx]);
|
||||
return -1;
|
||||
}
|
||||
/* check the hdr CRC */
|
||||
checksum = ntohl(hdr->ih_hcrc);
|
||||
hdr->ih_hcrc = 0;
|
||||
|
||||
if (crc32 (0, (uchar *)hdr, sizeof(*hdr)) != checksum) {
|
||||
printf ("Image %s bad header checksum\n", aufile[idx]);
|
||||
return -1;
|
||||
}
|
||||
hdr->ih_hcrc = htonl(checksum);
|
||||
/* check the type - could do this all in one gigantic if() */
|
||||
if ((idx == IDX_FIRMWARE) && (hdr->ih_type != IH_TYPE_FIRMWARE)) {
|
||||
printf ("Image %s wrong type\n", aufile[idx]);
|
||||
return -1;
|
||||
}
|
||||
if ((idx == IDX_KERNEL) && (hdr->ih_type != IH_TYPE_KERNEL)) {
|
||||
printf ("Image %s wrong type\n", aufile[idx]);
|
||||
return -1;
|
||||
}
|
||||
/* recycle checksum */
|
||||
checksum = ntohl(hdr->ih_size);
|
||||
/* for kernel and app the image header must also fit into flash */
|
||||
if (idx != IDX_FIRMWARE)
|
||||
checksum += sizeof(*hdr);
|
||||
/* check the size does not exceed space in flash. HUSH scripts */
|
||||
/* all have ausize[] set to 0 */
|
||||
if ((ausize[idx] != 0) && (ausize[idx] < checksum)) {
|
||||
printf ("Image %s is bigger than FLASH\n", aufile[idx]);
|
||||
return -1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
int au_do_update(int idx, long sz)
|
||||
{
|
||||
image_header_t *hdr;
|
||||
char *addr;
|
||||
long start, end;
|
||||
int off, rc;
|
||||
uint nbytes;
|
||||
|
||||
hdr = (image_header_t *)LOAD_ADDR;
|
||||
|
||||
/* execute a script */
|
||||
if (hdr->ih_type == IH_TYPE_SCRIPT) {
|
||||
addr = (char *)((char *)hdr + sizeof(*hdr));
|
||||
/* stick a NULL at the end of the script, otherwise */
|
||||
/* parse_string_outer() runs off the end. */
|
||||
addr[ntohl(hdr->ih_size)] = 0;
|
||||
addr += 8;
|
||||
parse_string_outer(addr, FLAG_PARSE_SEMICOLON);
|
||||
return 0;
|
||||
}
|
||||
|
||||
start = aufl_layout[idx].start;
|
||||
end = aufl_layout[idx].end;
|
||||
|
||||
/* unprotect the address range */
|
||||
/* this assumes that ONLY the firmware is protected! */
|
||||
if (idx == IDX_FIRMWARE) {
|
||||
#undef AU_UPDATE_TEST
|
||||
#ifdef AU_UPDATE_TEST
|
||||
/* erase it where Linux goes */
|
||||
start = aufl_layout[1].start;
|
||||
end = aufl_layout[1].end;
|
||||
#endif
|
||||
flash_sect_protect(0, start, end);
|
||||
}
|
||||
|
||||
/*
|
||||
* erase the address range.
|
||||
*/
|
||||
debug ("flash_sect_erase(%lx, %lx);\n", start, end);
|
||||
flash_sect_erase(start, end);
|
||||
wait_ms(100);
|
||||
/* strip the header - except for the kernel and ramdisk */
|
||||
if (hdr->ih_type == IH_TYPE_KERNEL) {
|
||||
addr = (char *)hdr;
|
||||
off = sizeof(*hdr);
|
||||
nbytes = sizeof(*hdr) + ntohl(hdr->ih_size);
|
||||
} else {
|
||||
addr = (char *)((char *)hdr + sizeof(*hdr));
|
||||
#ifdef AU_UPDATE_TEST
|
||||
/* copy it to where Linux goes */
|
||||
if (idx == IDX_FIRMWARE)
|
||||
start = aufl_layout[1].start;
|
||||
#endif
|
||||
off = 0;
|
||||
nbytes = ntohl(hdr->ih_size);
|
||||
}
|
||||
|
||||
/* copy the data from RAM to FLASH */
|
||||
debug ("flash_write(%p, %lx %x)\n", addr, start, nbytes);
|
||||
rc = flash_write(addr, start, nbytes);
|
||||
if (rc != 0) {
|
||||
printf("Flashing failed due to error %d\n", rc);
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* check the dcrc of the copy */
|
||||
if (crc32 (0, (uchar *)(start + off), ntohl(hdr->ih_size)) != ntohl(hdr->ih_dcrc)) {
|
||||
printf ("Image %s Bad Data Checksum After COPY\n", aufile[idx]);
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* protect the address range */
|
||||
/* this assumes that ONLY the firmware is protected! */
|
||||
if (idx == IDX_FIRMWARE)
|
||||
flash_sect_protect(1, start, end);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* this is called from board_init() after the hardware has been set up
|
||||
* and is usable. That seems like a good time to do this.
|
||||
* Right now the return value is ignored.
|
||||
*/
|
||||
int do_auto_update(void)
|
||||
{
|
||||
block_dev_desc_t *stor_dev;
|
||||
long sz;
|
||||
int i, res, bitmap_first, cnt, old_ctrlc, got_ctrlc;
|
||||
char *env;
|
||||
long start, end;
|
||||
char keypad_status1[2] = {0,0}, keypad_status2[2] = {0,0};
|
||||
|
||||
/*
|
||||
* Read keypad status
|
||||
*/
|
||||
i2c_read(I2C_PSOC_KEYPAD_ADDR, 0, 0, keypad_status1, 2);
|
||||
wait_ms(500);
|
||||
i2c_read(I2C_PSOC_KEYPAD_ADDR, 0, 0, keypad_status2, 2);
|
||||
|
||||
/*
|
||||
* Check keypad
|
||||
*/
|
||||
if ( !(keypad_status1[0] & KEYPAD_MASK_HI) ||
|
||||
(keypad_status1[0] != keypad_status2[0])) {
|
||||
return 0;
|
||||
}
|
||||
if ( !(keypad_status1[1] & KEYPAD_MASK_LO) ||
|
||||
(keypad_status1[1] != keypad_status2[1])) {
|
||||
return 0;
|
||||
}
|
||||
au_usb_stor_curr_dev = -1;
|
||||
/* start USB */
|
||||
if (usb_stop() < 0) {
|
||||
debug ("usb_stop failed\n");
|
||||
return -1;
|
||||
}
|
||||
if (usb_init() < 0) {
|
||||
debug ("usb_init failed\n");
|
||||
return -1;
|
||||
}
|
||||
/*
|
||||
* check whether a storage device is attached (assume that it's
|
||||
* a USB memory stick, since nothing else should be attached).
|
||||
*/
|
||||
au_usb_stor_curr_dev = usb_stor_scan(0);
|
||||
if (au_usb_stor_curr_dev == -1) {
|
||||
debug ("No device found. Not initialized?\n");
|
||||
return -1;
|
||||
}
|
||||
/* check whether it has a partition table */
|
||||
stor_dev = get_dev("usb", 0);
|
||||
if (stor_dev == NULL) {
|
||||
debug ("uknown device type\n");
|
||||
return -1;
|
||||
}
|
||||
if (fat_register_device(stor_dev, 1) != 0) {
|
||||
debug ("Unable to use USB %d:%d for fatls\n",
|
||||
au_usb_stor_curr_dev, 1);
|
||||
return -1;
|
||||
}
|
||||
if (file_fat_detectfs() != 0) {
|
||||
debug ("file_fat_detectfs failed\n");
|
||||
}
|
||||
|
||||
/* initialize the array of file names */
|
||||
memset(aufile, 0, sizeof(aufile));
|
||||
aufile[IDX_FIRMWARE] = AU_FIRMWARE;
|
||||
aufile[IDX_KERNEL] = AU_KERNEL;
|
||||
/* initialize the array of flash sizes */
|
||||
memset(ausize, 0, sizeof(ausize));
|
||||
ausize[IDX_FIRMWARE] = (AU_FL_FIRMWARE_ND + 1) - AU_FL_FIRMWARE_ST;
|
||||
ausize[IDX_KERNEL] = (AU_FL_KERNEL_ND + 1) - AU_FL_KERNEL_ST;
|
||||
/*
|
||||
* now check whether start and end are defined using environment
|
||||
* variables.
|
||||
*/
|
||||
start = -1;
|
||||
end = 0;
|
||||
env = getenv("firmware_st");
|
||||
if (env != NULL)
|
||||
start = simple_strtoul(env, NULL, 16);
|
||||
env = getenv("firmware_nd");
|
||||
if (env != NULL)
|
||||
end = simple_strtoul(env, NULL, 16);
|
||||
if (start >= 0 && end && end > start) {
|
||||
ausize[IDX_FIRMWARE] = (end + 1) - start;
|
||||
aufl_layout[0].start = start;
|
||||
aufl_layout[0].end = end;
|
||||
}
|
||||
start = -1;
|
||||
end = 0;
|
||||
env = getenv("kernel_st");
|
||||
if (env != NULL)
|
||||
start = simple_strtoul(env, NULL, 16);
|
||||
env = getenv("kernel_nd");
|
||||
if (env != NULL)
|
||||
end = simple_strtoul(env, NULL, 16);
|
||||
if (start >= 0 && end && end > start) {
|
||||
ausize[IDX_KERNEL] = (end + 1) - start;
|
||||
aufl_layout[1].start = start;
|
||||
aufl_layout[1].end = end;
|
||||
}
|
||||
/* make certain that HUSH is runnable */
|
||||
u_boot_hush_start();
|
||||
/* make sure that we see CTRL-C and save the old state */
|
||||
old_ctrlc = disable_ctrlc(0);
|
||||
|
||||
bitmap_first = 0;
|
||||
/* just loop thru all the possible files */
|
||||
for (i = 0; i < AU_MAXFILES; i++) {
|
||||
/* just read the header */
|
||||
sz = file_fat_read(aufile[i], LOAD_ADDR, sizeof(image_header_t));
|
||||
debug ("read %s sz %ld hdr %d\n",
|
||||
aufile[i], sz, sizeof(image_header_t));
|
||||
if (sz <= 0 || sz < sizeof(image_header_t)) {
|
||||
debug ("%s not found\n", aufile[i]);
|
||||
continue;
|
||||
}
|
||||
if (au_check_header_valid(i, sz) < 0) {
|
||||
debug ("%s header not valid\n", aufile[i]);
|
||||
continue;
|
||||
}
|
||||
sz = file_fat_read(aufile[i], LOAD_ADDR, MAX_LOADSZ);
|
||||
debug ("read %s sz %ld hdr %d\n",
|
||||
aufile[i], sz, sizeof(image_header_t));
|
||||
if (sz <= 0 || sz <= sizeof(image_header_t)) {
|
||||
debug ("%s not found\n", aufile[i]);
|
||||
continue;
|
||||
}
|
||||
if (au_check_cksum_valid(i, sz) < 0) {
|
||||
debug ("%s checksum not valid\n", aufile[i]);
|
||||
continue;
|
||||
}
|
||||
/* this is really not a good idea, but it's what the */
|
||||
/* customer wants. */
|
||||
cnt = 0;
|
||||
got_ctrlc = 0;
|
||||
do {
|
||||
res = au_do_update(i, sz);
|
||||
/* let the user break out of the loop */
|
||||
if (ctrlc() || had_ctrlc()) {
|
||||
clear_ctrlc();
|
||||
if (res < 0)
|
||||
got_ctrlc = 1;
|
||||
break;
|
||||
}
|
||||
cnt++;
|
||||
#ifdef AU_TEST_ONLY
|
||||
} while (res < 0 && cnt < 3);
|
||||
if (cnt < 3)
|
||||
#else
|
||||
} while (res < 0);
|
||||
#endif
|
||||
}
|
||||
usb_stop();
|
||||
/* restore the old state */
|
||||
disable_ctrlc(old_ctrlc);
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_AUTO_UPDATE */
|
||||
|
|
@ -44,6 +44,7 @@ DECLARE_GLOBAL_DATA_PTR;
|
|||
|
||||
extern flash_info_t flash_info[]; /* FLASH chips info */
|
||||
|
||||
extern int do_auto_update(void);
|
||||
ulong flash_get_size (ulong base, int banknum);
|
||||
|
||||
#ifndef CFG_RAMBOOT
|
||||
|
|
@ -227,6 +228,10 @@ int misc_init_r (void)
|
|||
{
|
||||
ulong flash_sup_end, snum;
|
||||
|
||||
#ifdef CONFIG_AUTO_UPDATE
|
||||
/* this has priority over all else */
|
||||
do_auto_update();
|
||||
#endif
|
||||
/*
|
||||
* Adjust flash start and offset to detected values
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -106,12 +106,13 @@ static void nc650_hwcontrol(struct mtd_info *mtd, int cmd)
|
|||
* Members with a "?" were not set in the merged testing-NAND branch,
|
||||
* so they are not set here either.
|
||||
*/
|
||||
void board_nand_init(struct nand_chip *nand)
|
||||
int board_nand_init(struct nand_chip *nand)
|
||||
{
|
||||
|
||||
nand->hwcontrol = nc650_hwcontrol;
|
||||
nand->eccmode = NAND_ECC_SOFT;
|
||||
nand->chip_delay = 12;
|
||||
/* nand->options = NAND_SAMSUNG_LP_OPTIONS;*/
|
||||
return 0;
|
||||
}
|
||||
#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */
|
||||
|
|
|
|||
|
|
@ -55,12 +55,13 @@ static int netstar_nand_ready(struct mtd_info *mtd)
|
|||
}
|
||||
***/
|
||||
|
||||
void board_nand_init(struct nand_chip *nand)
|
||||
int board_nand_init(struct nand_chip *nand)
|
||||
{
|
||||
nand->options = NAND_SAMSUNG_LP_OPTIONS;
|
||||
nand->eccmode = NAND_ECC_SOFT;
|
||||
nand->hwcontrol = netstar_nand_hwcontrol;
|
||||
/* nand->dev_ready = netstar_nand_ready; */
|
||||
nand->chip_delay = 18;
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -148,7 +148,7 @@ static int pdnb3_nand_dev_ready(struct mtd_info *mtd)
|
|||
return 1;
|
||||
}
|
||||
|
||||
void board_nand_init(struct nand_chip *nand)
|
||||
int board_nand_init(struct nand_chip *nand)
|
||||
{
|
||||
pdnb3_ndfc = (struct pdnb3_ndfc_regs *)CFG_NAND_BASE;
|
||||
|
||||
|
|
@ -167,5 +167,6 @@ void board_nand_init(struct nand_chip *nand)
|
|||
nand->read_buf = pdnb3_nand_read_buf;
|
||||
nand->verify_buf = pdnb3_nand_verify_buf;
|
||||
nand->dev_ready = pdnb3_nand_dev_ready;
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
40
board/tqm8272/Makefile
Normal file
40
board/tqm8272/Makefile
Normal file
|
|
@ -0,0 +1,40 @@
|
|||
#
|
||||
# (C) Copyright 2001
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = lib$(BOARD).a
|
||||
|
||||
OBJS = $(BOARD).o ../tqm8xx/load_sernum_ethaddr.o
|
||||
|
||||
$(LIB): .depend $(OBJS)
|
||||
$(AR) crv $@ $(OBJS)
|
||||
|
||||
#########################################################################
|
||||
|
||||
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
|
||||
$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
|
||||
|
||||
sinclude .depend
|
||||
|
||||
#########################################################################
|
||||
34
board/tqm8272/config.mk
Normal file
34
board/tqm8272/config.mk
Normal file
|
|
@ -0,0 +1,34 @@
|
|||
#
|
||||
# (C) Copyright 2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
#
|
||||
# TQM8272 boards
|
||||
#
|
||||
|
||||
# This should be equal to the CFG_FLASH_BASE define in config_TQM8260.h
|
||||
# for the "final" configuration, with U-Boot in flash, or the address
|
||||
# in RAM where U-Boot is loaded at for debugging.
|
||||
#
|
||||
TEXT_BASE = 0x40000000
|
||||
|
||||
PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)
|
||||
1234
board/tqm8272/tqm8272.c
Normal file
1234
board/tqm8272/tqm8272.c
Normal file
File diff suppressed because it is too large
Load diff
126
board/tqm8272/u-boot.lds
Normal file
126
board/tqm8272/u-boot.lds
Normal file
|
|
@ -0,0 +1,126 @@
|
|||
/*
|
||||
* (C) Copyright 2001
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(powerpc)
|
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
|
||||
/* Do we need any of these for elf?
|
||||
__DYNAMIC = 0; */
|
||||
SECTIONS
|
||||
{
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.interp : { *(.interp) }
|
||||
.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.rel.text : { *(.rel.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rel.data : { *(.rel.data) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rel.got : { *(.rel.got) }
|
||||
.rela.got : { *(.rela.got) }
|
||||
.rel.ctors : { *(.rel.ctors) }
|
||||
.rela.ctors : { *(.rela.ctors) }
|
||||
.rel.dtors : { *(.rel.dtors) }
|
||||
.rela.dtors : { *(.rela.dtors) }
|
||||
.rel.bss : { *(.rel.bss) }
|
||||
.rela.bss : { *(.rela.bss) }
|
||||
.rel.plt : { *(.rel.plt) }
|
||||
.rela.plt : { *(.rela.plt) }
|
||||
.init : { *(.init) }
|
||||
.plt : { *(.plt) }
|
||||
.text :
|
||||
{
|
||||
cpu/mpc8260/start.o (.text)
|
||||
*(.text)
|
||||
common/environment.o(.text)
|
||||
*(.fixup)
|
||||
*(.got1)
|
||||
. = ALIGN(16);
|
||||
*(.rodata)
|
||||
*(.rodata1)
|
||||
*(.rodata.str1.4)
|
||||
*(.eh_frame)
|
||||
}
|
||||
.fini : { *(.fini) } =0
|
||||
.ctors : { *(.ctors) }
|
||||
.dtors : { *(.dtors) }
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x0FFF) & 0xFFFFF000;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
.reloc :
|
||||
{
|
||||
*(.got)
|
||||
_GOT2_TABLE_ = .;
|
||||
*(.got2)
|
||||
_FIXUP_TABLE_ = .;
|
||||
*(.fixup)
|
||||
}
|
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.dynamic)
|
||||
CONSTRUCTORS
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
. = .;
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
|
||||
. = .;
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(4096);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(4096);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
*(.sbss) *(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
}
|
||||
_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
||||
|
|
@ -448,7 +448,7 @@ static void dfc_gpio_init(void)
|
|||
* Members with a "?" were not set in the merged testing-NAND branch,
|
||||
* so they are not set here either.
|
||||
*/
|
||||
void board_nand_init(struct nand_chip *nand)
|
||||
int board_nand_init(struct nand_chip *nand)
|
||||
{
|
||||
unsigned long tCH, tCS, tWH, tWP, tRH, tRP, tRP_high, tR, tWHR, tAR;
|
||||
|
||||
|
|
@ -576,6 +576,7 @@ void board_nand_init(struct nand_chip *nand)
|
|||
nand->cmdfunc = dfc_cmdfunc;
|
||||
nand->autooob = &delta_oob;
|
||||
nand->badblock_pattern = &delta_bbt_descr;
|
||||
return 0;
|
||||
}
|
||||
|
||||
#else
|
||||
|
|
|
|||
|
|
@ -248,7 +248,7 @@ int _do_setenv (int flag, int argc, char *argv[])
|
|||
baudrate);
|
||||
udelay(50000);
|
||||
gd->baudrate = baudrate;
|
||||
#ifdef CONFIG_PPC
|
||||
#if defined(CONFIG_PPC) || defined(CONFIG_MCF52x2)
|
||||
gd->bd->bi_baudrate = baudrate;
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -61,6 +61,7 @@
|
|||
defined(CONFIG_TRAB) || \
|
||||
defined(CONFIG_PPCHAMELEONEVB) || \
|
||||
defined(CONFIG_M5271EVB) || \
|
||||
defined(CONFIG_IDMR) || \
|
||||
defined(CONFIG_NAND_U_BOOT)) && \
|
||||
defined(ENV_CRC) /* Environment embedded in U-Boot .ppcenv section */
|
||||
/* XXX - This only works with GNU C */
|
||||
|
|
|
|||
|
|
@ -140,11 +140,11 @@ _start:
|
|||
move.l #(CFG_MBAR + 1), %d0 /* set IPSBAR address + valid flag */
|
||||
move.l %d0, 0x40000000
|
||||
|
||||
#if defined(CONFIG_M5282)
|
||||
/* Initialize RAMBAR1: locate SRAM and validate it */
|
||||
move.l #(CFG_INIT_RAM_ADDR + 0x21), %d0
|
||||
movec %d0, %RAMBAR1
|
||||
|
||||
#if defined(CONFIG_M5282)
|
||||
#if (TEXT_BASE == CFG_INT_FLASH_BASE)
|
||||
/* Setup code in SRAM to initialize FLASHBAR, if start from internal Flash */
|
||||
|
||||
|
|
|
|||
|
|
@ -49,6 +49,10 @@
|
|||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#if defined(CONFIG_GET_CPU_STR_F)
|
||||
extern int get_cpu_str_f (char *buf);
|
||||
#endif
|
||||
|
||||
int checkcpu (void)
|
||||
{
|
||||
volatile immap_t *immap = (immap_t *) CFG_IMMR;
|
||||
|
|
@ -81,7 +85,12 @@ int checkcpu (void)
|
|||
if ((immr & IMMR_ISB_MSK) != CFG_IMMR)
|
||||
return -1; /* whoops! someone moved the IMMR */
|
||||
|
||||
#if defined(CONFIG_GET_CPU_STR_F)
|
||||
get_cpu_str_f (buf);
|
||||
printf ("%s (HiP%d Rev %02x, Mask ", buf, k, rev);
|
||||
#else
|
||||
printf (CPU_ID_STR " (HiP%d Rev %02x, Mask ", k, rev);
|
||||
#endif
|
||||
|
||||
/*
|
||||
* the bottom 16 bits of the immr are the Part Number and Mask Number
|
||||
|
|
|
|||
|
|
@ -28,6 +28,10 @@
|
|||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
|
||||
extern unsigned long board_get_cpu_clk_f (void);
|
||||
#endif
|
||||
|
||||
static void config_8260_ioports (volatile immap_t * immr)
|
||||
{
|
||||
int portnum;
|
||||
|
|
@ -90,6 +94,7 @@ static void config_8260_ioports (volatile immap_t * immr)
|
|||
}
|
||||
}
|
||||
|
||||
#define SET_VAL_MASK(a, b, mask) ((a & mask) | (b & ~mask))
|
||||
/*
|
||||
* Breath some life into the CPU...
|
||||
*
|
||||
|
|
@ -101,6 +106,9 @@ void cpu_init_f (volatile immap_t * immr)
|
|||
{
|
||||
#if !defined(CONFIG_COGENT) /* done in start.S for the cogent */
|
||||
uint sccr;
|
||||
#endif
|
||||
#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
|
||||
unsigned long cpu_clk;
|
||||
#endif
|
||||
volatile memctl8260_t *memctl = &immr->im_memctl;
|
||||
extern void m8260_cpm_reset (void);
|
||||
|
|
@ -119,10 +127,27 @@ void cpu_init_f (volatile immap_t * immr)
|
|||
immr->im_clkrst.car_rmr = CFG_RMR;
|
||||
|
||||
/* BCR - Bus Configuration Register (4-25) */
|
||||
#if defined(CFG_BCR_60x) && (CFG_BCR_SINGLE)
|
||||
if (immr->im_siu_conf.sc_bcr & BCR_EBM) {
|
||||
immr->im_siu_conf.sc_bcr = CFG_BCR_60x;
|
||||
} else {
|
||||
immr->im_siu_conf.sc_bcr = CFG_BCR_SINGLE;
|
||||
}
|
||||
#else
|
||||
immr->im_siu_conf.sc_bcr = CFG_BCR;
|
||||
#endif
|
||||
|
||||
/* SIUMCR - contains debug pin configuration (4-31) */
|
||||
#if defined(CFG_SIUMCR_LOW) && (CFG_SIUMCR_HIGH)
|
||||
cpu_clk = board_get_cpu_clk_f ();
|
||||
if (cpu_clk >= 100000000) {
|
||||
immr->im_siu_conf.sc_siumcr = CFG_SIUMCR_HIGH;
|
||||
} else {
|
||||
immr->im_siu_conf.sc_siumcr = CFG_SIUMCR_LOW;
|
||||
}
|
||||
#else
|
||||
immr->im_siu_conf.sc_siumcr = CFG_SIUMCR;
|
||||
#endif
|
||||
|
||||
config_8260_ioports (immr);
|
||||
|
||||
|
|
@ -157,7 +182,8 @@ void cpu_init_f (volatile immap_t * immr)
|
|||
#endif
|
||||
|
||||
/* now restrict to preliminary range */
|
||||
memctl->memc_br0 = CFG_BR0_PRELIM;
|
||||
/* the PS came from the HRCW, don´t change it */
|
||||
memctl->memc_br0 = SET_VAL_MASK(memctl->memc_br0 , CFG_BR0_PRELIM, BRx_PS_MSK);
|
||||
memctl->memc_or0 = CFG_OR0_PRELIM;
|
||||
|
||||
#if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM)
|
||||
|
|
|
|||
|
|
@ -274,7 +274,23 @@ void pci_mpc8250_init (struct pci_controller *hose)
|
|||
| SIUMCR_CS10PC00
|
||||
| SIUMCR_BCTLC00
|
||||
| SIUMCR_MMR11;
|
||||
|
||||
#elif defined(CONFIG_TQM8272)
|
||||
#if 0
|
||||
immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
|
||||
~SIUMCR_LBPC11 &
|
||||
~SIUMCR_CS10PC11 &
|
||||
~SIUMCR_LBPC11) |
|
||||
SIUMCR_LBPC01 |
|
||||
SIUMCR_CS10PC01 |
|
||||
SIUMCR_APPC10;
|
||||
#else
|
||||
#if 0
|
||||
immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr |
|
||||
SIUMCR_APPC10);
|
||||
#else
|
||||
immap->im_siu_conf.sc_siumcr = 0x88000000;
|
||||
#endif
|
||||
#endif
|
||||
#else
|
||||
/*
|
||||
* Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]),
|
||||
|
|
@ -288,6 +304,7 @@ void pci_mpc8250_init (struct pci_controller *hose)
|
|||
SIUMCR_CS10PC01 |
|
||||
SIUMCR_APPC10;
|
||||
#endif
|
||||
printf("%s siumcr: %x\n", __FUNCTION__, immap->im_siu_conf.sc_siumcr);
|
||||
|
||||
/* Make PCI lowest priority */
|
||||
/* Each 4 bits is a device bus request and the MS 4bits
|
||||
|
|
|
|||
|
|
@ -25,6 +25,10 @@
|
|||
#include <mpc8260.h>
|
||||
#include <asm/processor.h>
|
||||
|
||||
#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
|
||||
extern unsigned long board_get_cpu_clk_f (void);
|
||||
#endif
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
|
@ -111,8 +115,12 @@ int get_clocks (void)
|
|||
|
||||
#if !defined(CONFIG_8260_CLKIN)
|
||||
#error clock measuring not implemented yet - define CONFIG_8260_CLKIN
|
||||
#else
|
||||
#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
|
||||
clkin = board_get_cpu_clk_f ();
|
||||
#else
|
||||
clkin = CONFIG_8260_CLKIN;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
sccr = immap->im_clkrst.car_sccr;
|
||||
|
|
|
|||
|
|
@ -156,7 +156,7 @@ void board_nand_select_device(struct nand_chip *nand, int chip)
|
|||
out32(base + NDFC_CCR, 0x00000000 | (cs << 24));
|
||||
}
|
||||
|
||||
void board_nand_init(struct nand_chip *nand)
|
||||
int board_nand_init(struct nand_chip *nand)
|
||||
{
|
||||
int cs = (ulong)nand->IO_ADDR_W & 0x00000003;
|
||||
ulong base = (ulong)nand->IO_ADDR_W & 0xfffffffc;
|
||||
|
|
@ -188,6 +188,7 @@ void board_nand_init(struct nand_chip *nand)
|
|||
*/
|
||||
board_nand_select_device(nand, cs);
|
||||
out32(base + NDFC_BCFG0 + (cs << 2), 0x80002222);
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -111,6 +111,7 @@
|
|||
#define FLASH_OFFSET_DEVICE_ID2 0x0E
|
||||
#define FLASH_OFFSET_DEVICE_ID3 0x0F
|
||||
#define FLASH_OFFSET_CFI 0x55
|
||||
#define FLASH_OFFSET_CFI_ALT 0x555
|
||||
#define FLASH_OFFSET_CFI_RESP 0x10
|
||||
#define FLASH_OFFSET_PRIMARY_VENDOR 0x13
|
||||
#define FLASH_OFFSET_EXT_QUERY_T_P_ADDR 0x15 /* extended query table primary addr */
|
||||
|
|
@ -161,6 +162,8 @@ typedef union {
|
|||
|
||||
#define NUM_ERASE_REGIONS 4 /* max. number of erase regions */
|
||||
|
||||
static uint flash_offset_cfi[2]={FLASH_OFFSET_CFI,FLASH_OFFSET_CFI_ALT};
|
||||
|
||||
/* use CFG_MAX_FLASH_BANKS_DETECT if defined */
|
||||
#ifdef CFG_MAX_FLASH_BANKS_DETECT
|
||||
static ulong bank_base[CFG_MAX_FLASH_BANKS_DETECT] = CFG_FLASH_BANKS_LIST;
|
||||
|
|
@ -350,7 +353,7 @@ unsigned long flash_init (void)
|
|||
if (flash_info[i].flash_id == FLASH_UNKNOWN) {
|
||||
#ifndef CFG_FLASH_QUIET_TEST
|
||||
printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
|
||||
i, flash_info[i].size, flash_info[i].size << 20);
|
||||
i+1, flash_info[i].size, flash_info[i].size << 20);
|
||||
#endif /* CFG_FLASH_QUIET_TEST */
|
||||
}
|
||||
#ifdef CFG_FLASH_PROTECTION
|
||||
|
|
@ -1153,6 +1156,7 @@ static void flash_read_jedec_ids (flash_info_t * info)
|
|||
*/
|
||||
static int flash_detect_cfi (flash_info_t * info)
|
||||
{
|
||||
int cfi_offset;
|
||||
debug ("flash detect cfi\n");
|
||||
|
||||
for (info->portwidth = CFG_FLASH_CFI_WIDTH;
|
||||
|
|
@ -1161,19 +1165,22 @@ static int flash_detect_cfi (flash_info_t * info)
|
|||
info->chipwidth <= info->portwidth;
|
||||
info->chipwidth <<= 1) {
|
||||
flash_write_cmd (info, 0, 0, info->cmd_reset);
|
||||
flash_write_cmd (info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI);
|
||||
if (flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP, 'Q')
|
||||
&& flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R')
|
||||
&& flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) {
|
||||
info->interface = flash_read_ushort (info, 0, FLASH_OFFSET_INTERFACE);
|
||||
debug ("device interface is %d\n",
|
||||
info->interface);
|
||||
debug ("found port %d chip %d ",
|
||||
info->portwidth, info->chipwidth);
|
||||
debug ("port %d bits chip %d bits\n",
|
||||
info->portwidth << CFI_FLASH_SHIFT_WIDTH,
|
||||
info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
|
||||
return 1;
|
||||
for (cfi_offset=0; cfi_offset < sizeof(flash_offset_cfi)/sizeof(uint); cfi_offset++) {
|
||||
flash_write_cmd (info, 0, flash_offset_cfi[cfi_offset], FLASH_CMD_CFI);
|
||||
if (flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP, 'Q')
|
||||
&& flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R')
|
||||
&& flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) {
|
||||
info->interface = flash_read_ushort (info, 0, FLASH_OFFSET_INTERFACE);
|
||||
info->cfi_offset=flash_offset_cfi[cfi_offset];
|
||||
debug ("device interface is %d\n",
|
||||
info->interface);
|
||||
debug ("found port %d chip %d ",
|
||||
info->portwidth, info->chipwidth);
|
||||
debug ("port %d bits chip %d bits\n",
|
||||
info->portwidth << CFI_FLASH_SHIFT_WIDTH,
|
||||
info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1210,7 +1217,7 @@ ulong flash_get_size (ulong base, int banknum)
|
|||
info->vendor = flash_read_ushort (info, 0,
|
||||
FLASH_OFFSET_PRIMARY_VENDOR);
|
||||
flash_read_jedec_ids (info);
|
||||
flash_write_cmd (info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI);
|
||||
flash_write_cmd (info, 0, info->cfi_offset, FLASH_CMD_CFI);
|
||||
num_erase_regions = flash_read_uchar (info,
|
||||
FLASH_OFFSET_NUM_ERASE_REGIONS);
|
||||
info->ext_addr = flash_read_ushort (info, 0,
|
||||
|
|
|
|||
|
|
@ -39,7 +39,7 @@ static ulong base_address[CFG_MAX_NAND_DEVICE] = CFG_NAND_BASE_LIST;
|
|||
|
||||
static const char default_nand_name[] = "nand";
|
||||
|
||||
extern void board_nand_init(struct nand_chip *nand);
|
||||
extern int board_nand_init(struct nand_chip *nand);
|
||||
|
||||
static void nand_init_chip(struct mtd_info *mtd, struct nand_chip *nand,
|
||||
ulong base_addr)
|
||||
|
|
@ -47,13 +47,16 @@ static void nand_init_chip(struct mtd_info *mtd, struct nand_chip *nand,
|
|||
mtd->priv = nand;
|
||||
|
||||
nand->IO_ADDR_R = nand->IO_ADDR_W = (void __iomem *)base_addr;
|
||||
board_nand_init(nand);
|
||||
|
||||
if (nand_scan(mtd, 1) == 0) {
|
||||
if (!mtd->name)
|
||||
mtd->name = (char *)default_nand_name;
|
||||
} else
|
||||
if (board_nand_init(nand) == 0) {
|
||||
if (nand_scan(mtd, 1) == 0) {
|
||||
if (!mtd->name)
|
||||
mtd->name = (char *)default_nand_name;
|
||||
} else
|
||||
mtd->name = NULL;
|
||||
} else {
|
||||
mtd->name = NULL;
|
||||
mtd->size = 0;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
|
|
|||
754
include/configs/TQM8272.h
Normal file
754
include/configs/TQM8272.h
Normal file
|
|
@ -0,0 +1,754 @@
|
|||
/*
|
||||
* (C) Copyright 2006
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
* (easy to change)
|
||||
*/
|
||||
|
||||
#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */
|
||||
#define CONFIG_MPC8272_FAMILY 1
|
||||
#define CONFIG_TQM8272 1
|
||||
|
||||
#define CONFIG_GET_CPU_STR_F 1 /* Get the CPU ID STR */
|
||||
#define CONFIG_BOARD_GET_CPU_CLK_F 1 /* Get the CLKIN from board fct */
|
||||
|
||||
#define STK82xx_150 1 /* on a STK82xx.150 */
|
||||
|
||||
#define CONFIG_CPM2 1 /* Has a CPM2 */
|
||||
|
||||
#define CONFIG_82xx_CONS_SMC1 1 /* console on SMC1 */
|
||||
|
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_R 1
|
||||
|
||||
#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
|
||||
#define CONFIG_BAUDRATE 230400
|
||||
#else
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#endif
|
||||
|
||||
#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
|
||||
|
||||
#undef CONFIG_BOOTARGS
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"netdev=eth0\0" \
|
||||
"consdev=ttyCPM0\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=${serverip}:${rootpath}\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"hostname=tqm8272\0" \
|
||||
"addip=setenv bootargs ${bootargs} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
||||
":${hostname}:${netdev}:off panic=1\0" \
|
||||
"addcons=setenv bootargs ${bootargs} " \
|
||||
"console=$(consdev),$(baudrate)\0" \
|
||||
"flash_nfs=run nfsargs addip addcons;" \
|
||||
"bootm ${kernel_addr}\0" \
|
||||
"flash_self=run ramargs addip addcons;" \
|
||||
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
|
||||
"net_nfs=tftp 300000 ${bootfile};" \
|
||||
"run nfsargs addip addcons;bootm\0" \
|
||||
"rootpath=/opt/eldk/ppc_82xx\0" \
|
||||
"bootfile=/tftpboot/tqm8272/uImage\0" \
|
||||
"kernel_addr=40080000\0" \
|
||||
"ramdisk_addr=40100000\0" \
|
||||
"load=tftp 300000 /tftpboot/tqm8272/u-boot.bin\0" \
|
||||
"update=protect off 40000000 4003ffff;era 40000000 4003ffff;" \
|
||||
"cp.b 300000 40000000 40000;" \
|
||||
"setenv filesize;saveenv\0" \
|
||||
"cphwib=cp.b 4003fc00 33fc00 400\0" \
|
||||
"upd=run load;run cphwib;run update\0" \
|
||||
""
|
||||
#define CONFIG_BOOTCOMMAND "run flash_self"
|
||||
|
||||
#define CONFIG_I2C 1
|
||||
|
||||
#if CONFIG_I2C
|
||||
/* enable I2C and select the hardware/software driver */
|
||||
#undef CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
|
||||
#define ADD_CMD_I2C CFG_CMD_I2C | \
|
||||
CFG_CMD_DATE |\
|
||||
CFG_CMD_DTT |\
|
||||
CFG_CMD_EEPROM
|
||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CFG_I2C_SLAVE 0x7F
|
||||
|
||||
/*
|
||||
* Software (bit-bang) I2C driver configuration
|
||||
*/
|
||||
#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
|
||||
#define I2C_ACTIVE (iop->pdir |= 0x00010000)
|
||||
#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
|
||||
#define I2C_READ ((iop->pdat & 0x00010000) != 0)
|
||||
#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
|
||||
else iop->pdat &= ~0x00010000
|
||||
#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
|
||||
else iop->pdat &= ~0x00020000
|
||||
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
|
||||
|
||||
#define CONFIG_I2C_X
|
||||
|
||||
/* EEPROM */
|
||||
#define CFG_I2C_EEPROM_ADDR_LEN 2
|
||||
#define CFG_EEPROM_PAGE_WRITE_BITS 4
|
||||
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
|
||||
#define CFG_EEPROM_PAGE_WRITE_ENABLE /* necessary for the LM75 chip */
|
||||
#define CFG_I2C_MULTI_EEPROMS 1 /* more than one eeprom */
|
||||
|
||||
/* I2C RTC */
|
||||
#define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */
|
||||
#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
|
||||
|
||||
/* I2C SYSMON (LM75) */
|
||||
#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
|
||||
#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
|
||||
#define CFG_DTT_MAX_TEMP 70
|
||||
#define CFG_DTT_LOW_TEMP -30
|
||||
#define CFG_DTT_HYSTERESIS 3
|
||||
|
||||
#else
|
||||
#undef CONFIG_HARD_I2C
|
||||
#undef CONFIG_SOFT_I2C
|
||||
#define ADD_CMD_I2C 0
|
||||
#endif
|
||||
|
||||
/*
|
||||
* select serial console configuration
|
||||
*
|
||||
* if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
|
||||
* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
|
||||
* for SCC).
|
||||
*
|
||||
* if CONFIG_CONS_NONE is defined, then the serial console routines must
|
||||
* defined elsewhere (for example, on the cogent platform, there are serial
|
||||
* ports on the motherboard which are used for the serial console - see
|
||||
* cogent/cma101/serial.[ch]).
|
||||
*/
|
||||
#define CONFIG_CONS_ON_SMC /* define if console on SMC */
|
||||
#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
|
||||
#undef CONFIG_CONS_NONE /* define if console on something else*/
|
||||
#ifdef CONFIG_82xx_CONS_SMC1
|
||||
#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
|
||||
#endif
|
||||
#ifdef CONFIG_82xx_CONS_SMC2
|
||||
#define CONFIG_CONS_INDEX 2 /* which serial channel for console */
|
||||
#endif
|
||||
|
||||
#undef CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */
|
||||
#define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */
|
||||
#define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9 */
|
||||
|
||||
/*
|
||||
* select ethernet configuration
|
||||
*
|
||||
* if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
|
||||
* CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
|
||||
* for FCC)
|
||||
*
|
||||
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
|
||||
* defined elsewhere (as for the console), or CFG_CMD_NET must be removed
|
||||
* from CONFIG_COMMANDS to remove support for networking.
|
||||
*
|
||||
* (On TQM8272 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the
|
||||
* X.29 connector, and FCC2 is hardwired to the X.1 connector)
|
||||
*/
|
||||
#define CFG_FCC_ETHERNET
|
||||
|
||||
#if defined(CFG_FCC_ETHERNET)
|
||||
#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
|
||||
#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
|
||||
#undef CONFIG_ETHER_NONE /* define if ether on something else */
|
||||
#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
|
||||
#else
|
||||
#define CONFIG_ETHER_ON_SCC /* define if ether on SCC */
|
||||
#undef CONFIG_ETHER_ON_FCC /* define if ether on FCC */
|
||||
#undef CONFIG_ETHER_NONE /* define if ether on something else */
|
||||
#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
|
||||
|
||||
/*
|
||||
* - RX clk is CLK11
|
||||
* - TX clk is CLK12
|
||||
*/
|
||||
# define CFG_CMXSCR_VALUE (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12)
|
||||
|
||||
#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
|
||||
|
||||
/*
|
||||
* - Rx-CLK is CLK13
|
||||
* - Tx-CLK is CLK14
|
||||
* - RAM for BD/Buffers is on the 60x Bus (see 28-13)
|
||||
* - Enable Full Duplex in FSMR
|
||||
*/
|
||||
# define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
|
||||
# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
|
||||
# define CFG_CPMFCR_RAMTYPE 0
|
||||
# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
|
||||
|
||||
#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
|
||||
|
||||
#define CONFIG_MII /* MII PHY management */
|
||||
#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
|
||||
/*
|
||||
* GPIO pins used for bit-banged MII communications
|
||||
*/
|
||||
#define MDIO_PORT 2 /* Port C */
|
||||
|
||||
#if STK82xx_150
|
||||
#define CFG_MDIO_PIN 0x00008000 /* PC16 */
|
||||
#define CFG_MDC_PIN 0x00004000 /* PC17 */
|
||||
#endif
|
||||
|
||||
#if STK82xx_100
|
||||
#define CFG_MDIO_PIN 0x00000002 /* PC30 */
|
||||
#define CFG_MDC_PIN 0x00000001 /* PC31 */
|
||||
#endif
|
||||
|
||||
#if 1
|
||||
#define MDIO_ACTIVE (iop->pdir |= CFG_MDIO_PIN)
|
||||
#define MDIO_TRISTATE (iop->pdir &= ~CFG_MDIO_PIN)
|
||||
#define MDIO_READ ((iop->pdat & CFG_MDIO_PIN) != 0)
|
||||
|
||||
#define MDIO(bit) if(bit) iop->pdat |= CFG_MDIO_PIN; \
|
||||
else iop->pdat &= ~CFG_MDIO_PIN
|
||||
|
||||
#define MDC(bit) if(bit) iop->pdat |= CFG_MDC_PIN; \
|
||||
else iop->pdat &= ~CFG_MDC_PIN
|
||||
#else
|
||||
#define MDIO_ACTIVE ({unsigned long tmp; tmp = iop->pdir; tmp |= CFG_MDIO_PIN; iop->pdir = tmp;})
|
||||
#define MDIO_TRISTATE ({unsigned long tmp; tmp = iop->pdir; tmp &= ~CFG_MDIO_PIN; iop->pdir = tmp;})
|
||||
#define MDIO_READ ((iop->pdat & CFG_MDIO_PIN) != 0)
|
||||
|
||||
#define MDIO(bit) if(bit) {unsigned long tmp; tmp = iop->pdat; tmp |= CFG_MDIO_PIN; iop->pdat = tmp;}\
|
||||
else {unsigned long tmp; tmp = iop->pdat; tmp &= ~CFG_MDIO_PIN; iop->pdat = tmp;}
|
||||
|
||||
#define MDC(bit) if(bit) {unsigned long tmp; tmp = iop->pdat; tmp |= CFG_MDC_PIN; iop->pdat = tmp;}\
|
||||
else {unsigned long tmp; tmp = iop->pdat; tmp &= ~CFG_MDC_PIN; iop->pdat = tmp;}
|
||||
#endif
|
||||
|
||||
#define MIIDELAY udelay(1)
|
||||
|
||||
|
||||
/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
|
||||
#define CONFIG_8260_CLKIN 66666666 /* in Hz */
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
|
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||
|
||||
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
|
||||
|
||||
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
|
||||
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
|
||||
CFG_CMD_NAND | \
|
||||
CFG_CMD_DHCP | \
|
||||
CFG_CMD_PING | \
|
||||
ADD_CMD_I2C | \
|
||||
CFG_CMD_NFS | \
|
||||
CFG_CMD_MII | \
|
||||
CFG_CMD_PCI | \
|
||||
CFG_CMD_SNTP )
|
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
|
||||
#include <cmd_confdefs.h>
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CFG_LONGHELP /* undef to save memory */
|
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
|
||||
|
||||
#if 0
|
||||
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
|
||||
#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
|
||||
#ifdef CFG_HUSH_PARSER
|
||||
#define CFG_PROMPT_HUSH_PS2 "> "
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CFG_MAXARGS 16 /* max number of command args */
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
|
||||
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
|
||||
|
||||
#define CFG_LOAD_ADDR 0x300000 /* default load address */
|
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
|
||||
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
||||
|
||||
#define CFG_RESET_ADDRESS 0x40000104 /* "bad" address */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* CAN stuff
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CFG_CAN_BASE 0x51000000
|
||||
#define CFG_CAN_SIZE 1
|
||||
#define CFG_CAN_BR ((CFG_CAN_BASE & BRx_BA_MSK) |\
|
||||
BRx_PS_8 |\
|
||||
BRx_MS_UPMC |\
|
||||
BRx_V)
|
||||
|
||||
#define CFG_CAN_OR (MEG_TO_AM(CFG_CAN_SIZE) |\
|
||||
ORxU_BI)
|
||||
|
||||
|
||||
/* What should the base address of the main FLASH be and how big is
|
||||
* it (in MBytes)? This must contain TEXT_BASE from board/tqm8272/config.mk
|
||||
* The main FLASH is whichever is connected to *CS0.
|
||||
*/
|
||||
#define CFG_FLASH0_BASE 0x40000000
|
||||
#define CFG_FLASH0_SIZE 32 /* 32 MB */
|
||||
|
||||
/* Flash bank size (for preliminary settings)
|
||||
*/
|
||||
#define CFG_FLASH_SIZE CFG_FLASH0_SIZE
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization
|
||||
*/
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
|
||||
#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
|
||||
|
||||
#define CFG_FLASH_CFI /* flash is CFI compat. */
|
||||
#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver*/
|
||||
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector */
|
||||
#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash*/
|
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
|
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
|
||||
|
||||
#define CFG_UPDATE_FLASH_SIZE
|
||||
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x40000)
|
||||
#define CFG_ENV_SIZE 0x20000
|
||||
#define CFG_ENV_SECT_SIZE 0x20000
|
||||
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SIZE)
|
||||
#define CFG_ENV_SIZE_REDUND 0x20000
|
||||
|
||||
/* Where is the Hardwareinformation Block (from Monitor Sources) */
|
||||
#define MON_RES_LENGTH (0x0003FC00)
|
||||
#define HWIB_INFO_START_ADDR (CFG_FLASH_BASE + MON_RES_LENGTH)
|
||||
#define HWIB_INFO_LEN 512
|
||||
#define CIB_INFO_START_ADDR (CFG_FLASH_BASE + MON_RES_LENGTH + HWIB_INFO_LEN)
|
||||
#define CIB_INFO_LEN 512
|
||||
|
||||
#define CFG_HWINFO_OFFSET 0x3fc00 /* offset of HW Info block */
|
||||
#define CFG_HWINFO_SIZE 0x00000060 /* size of HW Info block */
|
||||
#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* NAND-FLASH stuff
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
|
||||
|
||||
#define CFG_NAND_CS_DIST 0x80
|
||||
#define CFG_NAND_UPM_WRITE_CMD_OFS 0x20
|
||||
#define CFG_NAND_UPM_WRITE_ADDR_OFS 0x40
|
||||
|
||||
#define CFG_NAND_BR ((CFG_NAND0_BASE & BRx_BA_MSK) |\
|
||||
BRx_PS_8 |\
|
||||
BRx_MS_UPMB |\
|
||||
BRx_V)
|
||||
|
||||
#define CFG_NAND_OR (MEG_TO_AM(CFG_NAND_SIZE) |\
|
||||
ORxU_BI |\
|
||||
ORxU_EHTR_8IDLE)
|
||||
|
||||
#define CFG_NAND_SIZE 1
|
||||
#define CFG_NAND0_BASE 0x50000000
|
||||
#define CFG_NAND1_BASE (CFG_NAND0_BASE + CFG_NAND_CS_DIST)
|
||||
#define CFG_NAND2_BASE (CFG_NAND1_BASE + CFG_NAND_CS_DIST)
|
||||
#define CFG_NAND3_BASE (CFG_NAND2_BASE + CFG_NAND_CS_DIST)
|
||||
|
||||
#define CFG_MAX_NAND_DEVICE 4 /* Max number of NAND devices */
|
||||
#define NAND_MAX_CHIPS 1
|
||||
|
||||
#define CFG_NAND_BASE_LIST { CFG_NAND0_BASE, \
|
||||
CFG_NAND1_BASE, \
|
||||
CFG_NAND2_BASE, \
|
||||
CFG_NAND3_BASE, \
|
||||
}
|
||||
|
||||
#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr)) = (__u8)d; } while(0)
|
||||
#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)(adr)))
|
||||
#define WRITE_NAND_UPM(d, adr, off) do \
|
||||
{ \
|
||||
volatile unsigned char *addr = (unsigned char *) (adr + off); \
|
||||
WRITE_NAND(d, addr); \
|
||||
} while(0)
|
||||
|
||||
#endif /* CFG_CMD_NAND */
|
||||
|
||||
#define CONFIG_PCI
|
||||
#ifdef CONFIG_PCI
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
|
||||
#define CONFIG_PCI_PNP
|
||||
#define CONFIG_EEPRO100
|
||||
#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
|
||||
#define CONFIG_PCI_SCAN_SHOW
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Hard Reset Configuration Words
|
||||
*
|
||||
* if you change bits in the HRCW, you must also change the CFG_*
|
||||
* defines for the various registers affected by the HRCW e.g. changing
|
||||
* HRCW_DPPCxx requires you to also change CFG_SIUMCR.
|
||||
*/
|
||||
#if 0
|
||||
#define __HRCW__ALL__ (HRCW_CIP | HRCW_ISB111 | HRCW_BMS)
|
||||
|
||||
# define CFG_HRCW_MASTER (__HRCW__ALL__ | HRCW_MODCK_H0111)
|
||||
#else
|
||||
#define CFG_HRCW_MASTER (HRCW_BPS11 | HRCW_ISB111 | HRCW_BMS | HRCW_MODCK_H0111)
|
||||
#endif
|
||||
|
||||
/* no slaves so just fill with zeros */
|
||||
#define CFG_HRCW_SLAVE1 0
|
||||
#define CFG_HRCW_SLAVE2 0
|
||||
#define CFG_HRCW_SLAVE3 0
|
||||
#define CFG_HRCW_SLAVE4 0
|
||||
#define CFG_HRCW_SLAVE5 0
|
||||
#define CFG_HRCW_SLAVE6 0
|
||||
#define CFG_HRCW_SLAVE7 0
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Memory Mapped Register
|
||||
*/
|
||||
#define CFG_IMMR 0xFFF00000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM)
|
||||
*/
|
||||
#define CFG_INIT_RAM_ADDR CFG_IMMR
|
||||
#define CFG_INIT_RAM_END 0x2000 /* End of used area in DPRAM */
|
||||
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/
|
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
|
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration
|
||||
* (Set up by the startup code)
|
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0
|
||||
*/
|
||||
#define CFG_SDRAM_BASE 0x00000000
|
||||
#define CFG_FLASH_BASE CFG_FLASH0_BASE
|
||||
#define CFG_MONITOR_BASE TEXT_BASE
|
||||
#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
|
||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
|
||||
|
||||
/*
|
||||
* Internal Definitions
|
||||
*
|
||||
* Boot Flags
|
||||
*/
|
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/
|
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration
|
||||
*/
|
||||
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* HIDx - Hardware Implementation-dependent Registers 2-11
|
||||
*-----------------------------------------------------------------------
|
||||
* HID0 also contains cache control - initially enable both caches and
|
||||
* invalidate contents, then the final state leaves only the instruction
|
||||
* cache enabled. Note that Power-On and Hard reset invalidate the caches,
|
||||
* but Soft reset does not.
|
||||
*
|
||||
* HID1 has only read-only information - nothing to set.
|
||||
*/
|
||||
#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
|
||||
HID0_IFEM|HID0_ABE)
|
||||
#define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE)
|
||||
#define CFG_HID2 0
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RMR - Reset Mode Register 5-5
|
||||
*-----------------------------------------------------------------------
|
||||
* turn on Checkstop Reset Enable
|
||||
*/
|
||||
#define CFG_RMR RMR_CSRE
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* BCR - Bus Configuration 4-25
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CFG_BCR_60x (BCR_EBM|BCR_NPQM0|BCR_NPQM2) /* 60x mode */
|
||||
#define BCR_APD01 0x10000000
|
||||
#define CFG_BCR_SINGLE (BCR_APD01|BCR_ETM) /* 8260 mode */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 4-31
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
|
||||
#define CFG_SIUMCR_LOW (SIUMCR_DPPC00)
|
||||
#define CFG_SIUMCR_HIGH (SIUMCR_DPPC00 | SIUMCR_ABE)
|
||||
#else
|
||||
#define CFG_SIUMCR (SIUMCR_DPPC00)
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 4-35
|
||||
* SYPCR can only be written once after reset!
|
||||
*-----------------------------------------------------------------------
|
||||
* Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
|
||||
*/
|
||||
#if defined(CONFIG_WATCHDOG)
|
||||
#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
|
||||
SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
|
||||
#else
|
||||
#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
|
||||
SYPCR_SWRI|SYPCR_SWP)
|
||||
#endif /* CONFIG_WATCHDOG */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TMCNTSC - Time Counter Status and Control 4-40
|
||||
*-----------------------------------------------------------------------
|
||||
* Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
|
||||
* and enable Time Counter
|
||||
*/
|
||||
#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 4-42
|
||||
*-----------------------------------------------------------------------
|
||||
* Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
|
||||
* Periodic timer
|
||||
*/
|
||||
#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock Control 9-8
|
||||
*-----------------------------------------------------------------------
|
||||
* Ensure DFBRG is Divide by 16
|
||||
*/
|
||||
#define CFG_SCCR SCCR_DFBRG01
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RCCR - RISC Controller Configuration 13-7
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CFG_RCCR 0
|
||||
|
||||
/*
|
||||
* Init Memory Controller:
|
||||
*
|
||||
* Bank Bus Machine PortSz Device
|
||||
* ---- --- ------- ------ ------
|
||||
* 0 60x GPCM 32 bit FLASH
|
||||
* 1 60x SDRAM 64 bit SDRAM
|
||||
* 2 60x UPMB 8 bit NAND
|
||||
* 3 60x UPMC 8 bit CAN
|
||||
*
|
||||
*/
|
||||
|
||||
/* Initialize SDRAM
|
||||
*/
|
||||
#undef CFG_INIT_LOCAL_SDRAM /* No SDRAM on Local Bus */
|
||||
|
||||
#define SDRAM_MAX_SIZE 0x20000000 /* max. 512 MB */
|
||||
|
||||
/* Minimum mask to separate preliminary
|
||||
* address ranges for CS[0:2]
|
||||
*/
|
||||
#define CFG_GLOBAL_SDRAM_LIMIT (512<<20) /* less than 512 MB */
|
||||
|
||||
#define CFG_MPTPR 0x4000
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Address for Mode Register Set (MRS) command
|
||||
*-----------------------------------------------------------------------------
|
||||
* In fact, the address is rather configuration data presented to the SDRAM on
|
||||
* its address lines. Because the address lines may be mux'ed externally either
|
||||
* for 8 column or 9 column devices, some bits appear twice in the 8260's
|
||||
* address:
|
||||
*
|
||||
* | (RFU) | (RFU) | WBL | TM | CL | BT | Burst Length |
|
||||
* | BA1 BA0 | A12 : A10 | A9 | A8 A7 | A6 : A4 | A3 | A2 : A0 |
|
||||
* 8 columns mux'ing: | A9 | A10 A21 | A22 : A24 | A25 | A26 : A28 |
|
||||
* 9 columns mux'ing: | A8 | A20 A21 | A22 : A24 | A25 | A26 : A28 |
|
||||
* Settings: | 0 | 0 0 | 0 1 0 | 0 | 0 1 0 |
|
||||
*-----------------------------------------------------------------------------
|
||||
*/
|
||||
#define CFG_MRS_OFFS 0x00000110
|
||||
|
||||
/* Bank 0 - FLASH
|
||||
*/
|
||||
#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\
|
||||
BRx_PS_32 |\
|
||||
BRx_MS_GPCM_P |\
|
||||
BRx_V)
|
||||
|
||||
#define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH_SIZE) |\
|
||||
ORxG_CSNT |\
|
||||
ORxG_ACS_DIV4 |\
|
||||
ORxG_SCY_8_CLK |\
|
||||
ORxG_TRLX)
|
||||
|
||||
/* SDRAM on TQM8272 can have either 8 or 9 columns.
|
||||
* The number affects configuration values.
|
||||
*/
|
||||
|
||||
/* Bank 1 - 60x bus SDRAM
|
||||
*/
|
||||
#define CFG_PSRT 0x20 /* Low Value */
|
||||
/* #define CFG_PSRT 0x10 Fast Value */
|
||||
#define CFG_LSRT 0x20 /* Local Bus */
|
||||
#ifndef CFG_RAMBOOT
|
||||
#define CFG_BR1_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\
|
||||
BRx_PS_64 |\
|
||||
BRx_MS_SDRAM_P |\
|
||||
BRx_V)
|
||||
|
||||
#define CFG_OR1_PRELIM CFG_OR1_8COL
|
||||
|
||||
/* SDRAM initialization values for 8-column chips
|
||||
*/
|
||||
#define CFG_OR1_8COL ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
|
||||
ORxS_BPD_4 |\
|
||||
ORxS_ROWST_PBI1_A7 |\
|
||||
ORxS_NUMR_12)
|
||||
|
||||
#define CFG_PSDMR_8COL (PSDMR_PBI |\
|
||||
PSDMR_SDAM_A15_IS_A5 |\
|
||||
PSDMR_BSMA_A12_A14 |\
|
||||
PSDMR_SDA10_PBI1_A8 |\
|
||||
PSDMR_RFRC_7_CLK |\
|
||||
PSDMR_PRETOACT_2W |\
|
||||
PSDMR_ACTTORW_2W |\
|
||||
PSDMR_LDOTOPRE_1C |\
|
||||
PSDMR_WRC_2C |\
|
||||
PSDMR_EAMUX |\
|
||||
PSDMR_BUFCMD |\
|
||||
PSDMR_CL_2)
|
||||
|
||||
|
||||
/* SDRAM initialization values for 9-column chips
|
||||
*/
|
||||
#define CFG_OR1_9COL ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
|
||||
ORxS_BPD_4 |\
|
||||
ORxS_ROWST_PBI1_A5 |\
|
||||
ORxS_NUMR_13)
|
||||
|
||||
#define CFG_PSDMR_9COL (PSDMR_PBI |\
|
||||
PSDMR_SDAM_A16_IS_A5 |\
|
||||
PSDMR_BSMA_A12_A14 |\
|
||||
PSDMR_SDA10_PBI1_A7 |\
|
||||
PSDMR_RFRC_7_CLK |\
|
||||
PSDMR_PRETOACT_2W |\
|
||||
PSDMR_ACTTORW_2W |\
|
||||
PSDMR_LDOTOPRE_1C |\
|
||||
PSDMR_WRC_2C |\
|
||||
PSDMR_EAMUX |\
|
||||
PSDMR_BUFCMD |\
|
||||
PSDMR_CL_2)
|
||||
|
||||
#define CFG_OR1_10COL ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
|
||||
ORxS_BPD_4 |\
|
||||
ORxS_ROWST_PBI1_A4 |\
|
||||
ORxS_NUMR_13)
|
||||
|
||||
#define CFG_PSDMR_10COL (PSDMR_PBI |\
|
||||
PSDMR_SDAM_A17_IS_A5 |\
|
||||
PSDMR_BSMA_A12_A14 |\
|
||||
PSDMR_SDA10_PBI1_A4 |\
|
||||
PSDMR_RFRC_6_CLK |\
|
||||
PSDMR_PRETOACT_2W |\
|
||||
PSDMR_ACTTORW_2W |\
|
||||
PSDMR_LDOTOPRE_1C |\
|
||||
PSDMR_WRC_2C |\
|
||||
PSDMR_EAMUX |\
|
||||
PSDMR_BUFCMD |\
|
||||
PSDMR_CL_2)
|
||||
|
||||
#define PSDMR_RFRC_66MHZ_SINGLE 0x00028000 /* PSDMR[RFRC] at 66 MHz single mode */
|
||||
#define PSDMR_RFRC_100MHZ_SINGLE 0x00030000 /* PSDMR[RFRC] at 100 MHz single mode */
|
||||
#define PSDMR_RFRC_133MHZ_SINGLE 0x00030000 /* PSDMR[RFRC] at 133 MHz single mode */
|
||||
#define PSDMR_RFRC_66MHZ_60X 0x00030000 /* PSDMR[RFRC] at 66 MHz 60x mode */
|
||||
#define PSDMR_RFRC_100MHZ_60X 0x00028000 /* PSDMR[RFRC] at 100 MHz 60x mode */
|
||||
#define PSDMR_RFRC_DEFAULT PSDMR_RFRC_133MHZ_SINGLE /* PSDMR[RFRC] default value */
|
||||
|
||||
#define PSDMR_PRETOACT_66MHZ_SINGLE 0x00002000 /* PSDMR[PRETOACT] at 66 MHz single mode */
|
||||
#define PSDMR_PRETOACT_100MHZ_SINGLE 0x00002000 /* PSDMR[PRETOACT] at 100 MHz single mode */
|
||||
#define PSDMR_PRETOACT_133MHZ_SINGLE 0x00002000 /* PSDMR[PRETOACT] at 133 MHz single mode */
|
||||
#define PSDMR_PRETOACT_66MHZ_60X 0x00001000 /* PSDMR[PRETOACT] at 66 MHz 60x mode */
|
||||
#define PSDMR_PRETOACT_100MHZ_60X 0x00001000 /* PSDMR[PRETOACT] at 100 MHz 60x mode */
|
||||
#define PSDMR_PRETOACT_DEFAULT PSDMR_PRETOACT_133MHZ_SINGLE /* PSDMR[PRETOACT] default value */
|
||||
|
||||
#define PSDMR_WRC_66MHZ_SINGLE 0x00000020 /* PSDMR[WRC] at 66 MHz single mode */
|
||||
#define PSDMR_WRC_100MHZ_SINGLE 0x00000020 /* PSDMR[WRC] at 100 MHz single mode */
|
||||
#define PSDMR_WRC_133MHZ_SINGLE 0x00000010 /* PSDMR[WRC] at 133 MHz single mode */
|
||||
#define PSDMR_WRC_66MHZ_60X 0x00000010 /* PSDMR[WRC] at 66 MHz 60x mode */
|
||||
#define PSDMR_WRC_100MHZ_60X 0x00000010 /* PSDMR[WRC] at 100 MHz 60x mode */
|
||||
#define PSDMR_WRC_DEFAULT PSDMR_WRC_133MHZ_SINGLE /* PSDMR[WRC] default value */
|
||||
|
||||
#define PSDMR_BUFCMD_66MHZ_SINGLE 0x00000000 /* PSDMR[BUFCMD] at 66 MHz single mode */
|
||||
#define PSDMR_BUFCMD_100MHZ_SINGLE 0x00000000 /* PSDMR[BUFCMD] at 100 MHz single mode */
|
||||
#define PSDMR_BUFCMD_133MHZ_SINGLE 0x00000004 /* PSDMR[BUFCMD] at 133 MHz single mode */
|
||||
#define PSDMR_BUFCMD_66MHZ_60X 0x00000000 /* PSDMR[BUFCMD] at 66 MHz 60x mode */
|
||||
#define PSDMR_BUFCMD_100MHZ_60X 0x00000000 /* PSDMR[BUFCMD] at 100 MHz 60x mode */
|
||||
#define PSDMR_BUFCMD_DEFAULT PSDMR_BUFCMD_133MHZ_SINGLE /* PSDMR[BUFCMD] default value */
|
||||
|
||||
#endif /* CFG_RAMBOOT */
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
197
include/configs/idmr.h
Normal file
197
include/configs/idmr.h
Normal file
|
|
@ -0,0 +1,197 @@
|
|||
/*
|
||||
* Configuration settings for the iDMR board
|
||||
*
|
||||
* Based on MC5272C3, r5200 and M5271EVB board configs
|
||||
* (C) Copyright 2006 Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
* (C) Copyright 2006 Lab X Technologies <zachary.landau@labxtechnologies.com>
|
||||
* (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef _IDMR_H
|
||||
#define _IDMR_H
|
||||
|
||||
|
||||
/*
|
||||
* High Level Configuration Options (easy to change)
|
||||
*/
|
||||
|
||||
#define CONFIG_MCF52x2 /* define processor family */
|
||||
#define CONFIG_M5271 /* define processor type */
|
||||
#define CONFIG_IDMR /* define board type */
|
||||
|
||||
#undef CONFIG_WATCHDOG /* disable watchdog */
|
||||
|
||||
/*
|
||||
* Default environment settings
|
||||
*/
|
||||
#define CONFIG_BOOTCOMMAND "run net_nfs"
|
||||
#define CONFIG_BOOTDELAY 5
|
||||
#define CONFIG_BAUDRATE 19200
|
||||
#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
|
||||
#define CONFIG_ETHADDR 00:06:3b:01:41:55
|
||||
#define CONFIG_ETHPRIME
|
||||
#define CONFIG_IPADDR 192.168.30.1
|
||||
#define CONFIG_SERVERIP 192.168.1.1
|
||||
#define CONFIG_ROOTPATH
|
||||
#define CONFIG_GATEWAYIP 192.168.1.1
|
||||
#define CONFIG_NETMASK 255.255.0.0
|
||||
#define CONFIG_HOSTNAME idmr
|
||||
#define CONFIG_BOOTFILE /tftpboot/idmr/uImage
|
||||
#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root " \
|
||||
"filesystem over NFS; echo"
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"netdev=eth0\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"addip=setenv bootargs $(bootargs) " \
|
||||
"ip=$(ipaddr):$(serverip):$(gatewayip):" \
|
||||
"$(netmask):$(hostname):$(netdev):off panic=1\0" \
|
||||
"flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0" \
|
||||
"flash_self=run ramargs addip;bootm $(kernel_addr) " \
|
||||
"$(ramdisk_addr)\0" \
|
||||
"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=$(serverip):$(rootpath)\0" \
|
||||
"ethact=FEC ETHERNET\0" \
|
||||
"update=prot off ff800000 ff81ffff; era ff800000 ff81ffff; " \
|
||||
"cp.b 200000 ff800000 $(filesize);" \
|
||||
"prot on ff800000 ff81ffff\0" \
|
||||
"load=tftp 200000 $(u-boot)\0" \
|
||||
"u-boot=/tftpboot/idmr/u-boot.bin\0" \
|
||||
""
|
||||
|
||||
/*
|
||||
* Commands' definition
|
||||
*/
|
||||
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \
|
||||
CFG_CMD_PING | \
|
||||
CFG_CMD_NET | \
|
||||
CFG_CMD_MII) & \
|
||||
~(CFG_CMD_LOADS | \
|
||||
CFG_CMD_LOADB))
|
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
|
||||
#include <cmd_confdefs.h>
|
||||
|
||||
|
||||
/*
|
||||
* Low Level Configuration Settings
|
||||
* (address mappings, register initial values, etc.)
|
||||
* You should know what you are doing if you make changes here.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Configuration for environment, which occupies third sector in flash.
|
||||
*/
|
||||
#ifndef CONFIG_MONITOR_IS_IN_RAM
|
||||
#define CFG_ENV_ADDR 0xff820000
|
||||
#define CFG_ENV_SECT_SIZE 0x10000
|
||||
#define CFG_ENV_SIZE 0x2000
|
||||
#define CFG_ENV_IS_IN_FLASH
|
||||
#else /* CONFIG_MONITOR_IS_IN_RAM */
|
||||
#define CFG_ENV_OFFSET 0x4000
|
||||
#define CFG_ENV_SECT_SIZE 0x2000
|
||||
#define CFG_ENV_IS_IN_FLASH
|
||||
#endif /* !CONFIG_MONITOR_IS_IN_RAM */
|
||||
|
||||
#define CFG_PROMPT "=> "
|
||||
#define CFG_LONGHELP /* undef to save memory */
|
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else /* !(CONFIG_COMMANDS & CFG_CMD_KGDB) */
|
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif /* (CONFIG_COMMANDS & CFG_CMD_KGDB) */
|
||||
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CFG_MAXARGS 16 /* max number of command args */
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CFG_LOAD_ADDR 0x00100000
|
||||
|
||||
#define CFG_MEMTEST_START 0x400
|
||||
#define CFG_MEMTEST_END 0x380000
|
||||
|
||||
#define CFG_HZ (50000000 / 64)
|
||||
#define CFG_CLK 100000000
|
||||
|
||||
#define CFG_MBAR 0x40000000 /* Register Base Addrs */
|
||||
|
||||
/*
|
||||
* Ethernet
|
||||
*/
|
||||
#define FEC_ENET
|
||||
#define CONFIG_NET_RETRY_COUNT 5
|
||||
#define CFG_ENET_BD_BASE 0x480000
|
||||
#define CFG_DISCOVER_PHY 1
|
||||
#define CONFIG_MII 1
|
||||
|
||||
/*
|
||||
* Definitions for initial stack pointer and data area (in DPRAM)
|
||||
*/
|
||||
#define CFG_INIT_RAM_ADDR 0x20000000
|
||||
#define CFG_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */
|
||||
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
|
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
|
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
|
||||
|
||||
/*
|
||||
* Start addresses for the final memory configuration
|
||||
* (Set up by the startup code)
|
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0
|
||||
*/
|
||||
#define CFG_SDRAM_BASE 0x00000000
|
||||
#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */
|
||||
#define CFG_FLASH_BASE 0xff800000
|
||||
|
||||
#ifdef CONFIG_MONITOR_IS_IN_RAM
|
||||
#define CFG_MONITOR_BASE 0x20000
|
||||
#else /* !CONFIG_MONITOR_IS_IN_RAM */
|
||||
#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400)
|
||||
#endif /* CONFIG_MONITOR_IS_IN_RAM */
|
||||
|
||||
#define CFG_MONITOR_LEN 0x20000
|
||||
#define CFG_MALLOC_LEN (256 << 10)
|
||||
#define CFG_BOOTPARAMS_LEN (64*1024)
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization ??
|
||||
*/
|
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
|
||||
/* FLASH organization */
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
|
||||
#define CFG_FLASH_ERASE_TOUT 1000
|
||||
|
||||
#define CFG_FLASH_SIZE 0x800000
|
||||
/*
|
||||
* #define CFG_FLASH_USE_BUFFER_WRITE 1
|
||||
*/
|
||||
|
||||
/* Cache Configuration */
|
||||
#define CFG_CACHELINE_SIZE 16
|
||||
|
||||
/* Port configuration */
|
||||
#define CFG_FECI2C 0xF0
|
||||
#endif /* _IDMR_H */
|
||||
|
|
@ -94,6 +94,8 @@
|
|||
#define CONFIG_USB_OHCI
|
||||
#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
|
||||
#define CONFIG_USB_STORAGE
|
||||
/* automatic software updates (see board/mcc200/auto_update.c) */
|
||||
#define CONFIG_AUTO_UPDATE 1
|
||||
|
||||
/*
|
||||
* Supported commands
|
||||
|
|
@ -173,7 +175,7 @@
|
|||
* I2C configuration
|
||||
*/
|
||||
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
|
||||
#define CFG_I2C_MODULE 1 /* Select I2C module #1 or #2 */
|
||||
#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */
|
||||
|
||||
#define CFG_I2C_SPEED 100000 /* 100 kHz */
|
||||
#define CFG_I2C_SLAVE 0x7F
|
||||
|
|
|
|||
|
|
@ -51,6 +51,7 @@ typedef struct {
|
|||
ushort device_id2; /* extended device id */
|
||||
ushort ext_addr; /* extended query table address */
|
||||
ushort cfi_version; /* cfi version */
|
||||
ushort cfi_offset; /* offset for cfi query */
|
||||
#endif
|
||||
} flash_info_t;
|
||||
|
||||
|
|
|
|||
|
|
@ -35,7 +35,15 @@
|
|||
#endif
|
||||
#ifndef CPU_ID_STR
|
||||
#if defined(CONFIG_MPC8272_FAMILY)
|
||||
#ifdef CONFIG_MPC8247
|
||||
#define CPU_ID_STR "MPC8247"
|
||||
#elif defined CONFIG_MPC8248
|
||||
#define CPU_ID_STR "MPC8248"
|
||||
#elif defined CONFIG_MPC8271
|
||||
#define CPU_ID_STR "MPC8271"
|
||||
#else
|
||||
#define CPU_ID_STR "MPC8272"
|
||||
#endif
|
||||
#else
|
||||
#define CPU_ID_STR "MPC8260"
|
||||
#endif
|
||||
|
|
@ -66,6 +74,7 @@
|
|||
#define BCR_EXDD 0x00000400 /* External Master Delay Disable*/
|
||||
#define BCR_ISPS 0x00000010 /* Internal Space Port Size */
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PPC_ACR - 60x Bus Arbiter Configuration Register 4-28
|
||||
*/
|
||||
|
|
@ -168,6 +177,7 @@
|
|||
#define SIUMCR_MMR10 0x00008000 /* - " - */
|
||||
#define SIUMCR_MMR11 0x0000c000 /* - " - */
|
||||
#define SIUMCR_LPBSE 0x00002000 /* LocalBus Parity Byte Select Enable*/
|
||||
#define SIUMCR_ABE 0x00000400 /* Address output buffer impedance*/
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* IMMR - Internal Memory Map Register 4-34
|
||||
|
|
|
|||
|
|
@ -153,7 +153,11 @@ void udelay(unsigned long usec)
|
|||
timerp[MCFTIMER_PMR] = 0;
|
||||
/* set period to 1 us */
|
||||
timerp[MCFTIMER_PCSR] =
|
||||
#ifdef CONFIG_M5271
|
||||
(6 << 8) | MCFTIMER_PCSR_EN | MCFTIMER_PCSR_OVW;
|
||||
#else /* !CONFIG_M5271 */
|
||||
(5 << 8) | MCFTIMER_PCSR_EN | MCFTIMER_PCSR_OVW;
|
||||
#endif /* CONFIG_M5271 */
|
||||
|
||||
timerp[MCFTIMER_PMR] = tmp;
|
||||
while (timerp[MCFTIMER_PCNTR] > 0);
|
||||
|
|
@ -171,7 +175,11 @@ void timer_init (void)
|
|||
timerp[MCFTIMER_PCSR] = MCFTIMER_PCSR_OVW;
|
||||
timerp[MCFTIMER_PMR] = lastinc = 0;
|
||||
timerp[MCFTIMER_PCSR] =
|
||||
#ifdef CONFIG_M5271
|
||||
(6 << 8) | MCFTIMER_PCSR_EN | MCFTIMER_PCSR_OVW;
|
||||
#else /* !CONFIG_M5271 */
|
||||
(5 << 8) | MCFTIMER_PCSR_EN | MCFTIMER_PCSR_OVW;
|
||||
#endif /* CONFIG_M5271 */
|
||||
}
|
||||
|
||||
void set_timer (ulong t)
|
||||
|
|
|
|||
|
|
@ -72,6 +72,10 @@
|
|||
#include <keyboard.h>
|
||||
#endif
|
||||
|
||||
#ifdef CFG_UPDATE_FLASH_SIZE
|
||||
extern int update_flash_size (int flash_size);
|
||||
#endif
|
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_DOC)
|
||||
void doc_init (void);
|
||||
#endif
|
||||
|
|
@ -730,6 +734,13 @@ void board_init_r (gd_t *id, ulong dest_addr)
|
|||
|
||||
bd->bi_flashstart = CFG_FLASH_BASE; /* update start of FLASH memory */
|
||||
bd->bi_flashsize = flash_size; /* size of FLASH memory (final value) */
|
||||
|
||||
#if defined(CFG_UPDATE_FLASH_SIZE)
|
||||
/* Make a update of the Memctrl. */
|
||||
update_flash_size (flash_size);
|
||||
#endif
|
||||
|
||||
|
||||
# if defined(CONFIG_PCU_E) || defined(CONFIG_OXC) || defined(CONFIG_RMU)
|
||||
/* flash mapped at end of memory map */
|
||||
bd->bi_flashoffset = TEXT_BASE + flash_size;
|
||||
|
|
@ -876,6 +887,7 @@ void board_init_r (gd_t *id, ulong dest_addr)
|
|||
#endif
|
||||
|
||||
#if defined(CONFIG_TQM8xxL) || defined(CONFIG_TQM8260) || \
|
||||
defined(CONFIG_TQM8272) || \
|
||||
defined(CONFIG_CCM) || defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X)
|
||||
load_sernum_ethaddr ();
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue