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https://github.com/AsahiLinux/u-boot
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ARM: dts: rmobile: Import R8A7792 DTS from Linux 4.15-rc8
Import the Renesas R8A7792 DTS and headers from upstream Linux kernel v4.15-rc8, commit bebc6082da0a9f5d47a1ea2edc099bf671058bd4 . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This commit is contained in:
Marek Vasut
Marek Vasut
parent
edd15fcffb
commit
a3fb9ff3b3
5 changed files with 1355 additions and 0 deletions
327
arch/arm/dts/r8a7792-blanche.dts
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327
arch/arm/dts/r8a7792-blanche.dts
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@ -0,0 +1,327 @@
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/*
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* Device Tree Source for the Blanche board
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*
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* Copyright (C) 2014 Renesas Electronics Corporation
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* Copyright (C) 2016 Cogent Embedded, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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/dts-v1/;
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#include "r8a7792.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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/ {
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model = "Blanche";
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compatible = "renesas,blanche", "renesas,r8a7792";
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aliases {
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serial0 = &scif0;
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serial1 = &scif3;
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};
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chosen {
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bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
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stdout-path = "serial0:115200n8";
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};
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memory@40000000 {
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device_type = "memory";
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reg = <0 0x40000000 0 0x40000000>;
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};
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d3_3v: regulator-3v3 {
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compatible = "regulator-fixed";
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regulator-name = "D3.3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ethernet@18000000 {
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compatible = "smsc,lan89218", "smsc,lan9115";
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reg = <0 0x18000000 0 0x100>;
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phy-mode = "mii";
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interrupt-parent = <&irqc>;
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interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
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smsc,irq-push-pull;
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reg-io-width = <4>;
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vddvario-supply = <&d3_3v>;
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vdd33a-supply = <&d3_3v>;
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pinctrl-0 = <&lan89218_pins>;
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pinctrl-names = "default";
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};
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vga-encoder {
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compatible = "adi,adv7123";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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adv7123_in: endpoint {
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remote-endpoint = <&du_out_rgb1>;
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};
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};
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port@1 {
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reg = <1>;
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adv7123_out: endpoint {
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remote-endpoint = <&vga_in>;
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};
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};
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};
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};
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hdmi-out {
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compatible = "hdmi-connector";
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type = "a";
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port {
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hdmi_con: endpoint {
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remote-endpoint = <&adv7511_out>;
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};
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};
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};
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vga {
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compatible = "vga-connector";
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port {
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vga_in: endpoint {
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remote-endpoint = <&adv7123_out>;
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};
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};
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};
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x1_clk: x1 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <74250000>;
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};
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x2_clk: x2 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <65000000>;
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};
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keyboard {
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compatible = "gpio-keys";
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key-1 {
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linux,code = <KEY_1>;
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label = "SW2-1";
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wakeup-source;
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debounce-interval = <20>;
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gpios = <&gpio3 10 GPIO_ACTIVE_LOW>;
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};
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key-2 {
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linux,code = <KEY_2>;
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label = "SW2-2";
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wakeup-source;
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debounce-interval = <20>;
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gpios = <&gpio3 11 GPIO_ACTIVE_LOW>;
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};
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key-3 {
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linux,code = <KEY_3>;
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label = "SW2-3";
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wakeup-source;
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debounce-interval = <20>;
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gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
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};
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key-4 {
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linux,code = <KEY_4>;
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label = "SW2-4";
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wakeup-source;
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debounce-interval = <20>;
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gpios = <&gpio3 15 GPIO_ACTIVE_LOW>;
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};
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key-a {
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linux,code = <KEY_A>;
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label = "SW24";
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wakeup-source;
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debounce-interval = <20>;
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gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
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};
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key-b {
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linux,code = <KEY_B>;
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label = "SW25";
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wakeup-source;
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debounce-interval = <20>;
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gpios = <&gpio11 2 GPIO_ACTIVE_LOW>;
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};
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};
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leds {
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compatible = "gpio-leds";
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led17 {
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gpios = <&gpio10 10 GPIO_ACTIVE_HIGH>;
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};
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led18 {
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gpios = <&gpio10 11 GPIO_ACTIVE_HIGH>;
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};
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led19 {
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gpios = <&gpio10 12 GPIO_ACTIVE_HIGH>;
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};
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led20 {
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gpios = <&gpio10 23 GPIO_ACTIVE_HIGH>;
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};
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};
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vcc_sdhi0: regulator-vcc-sdhi0 {
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compatible = "regulator-fixed";
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regulator-name = "SDHI0 Vcc";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio11 12 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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};
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&extal_clk {
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clock-frequency = <20000000>;
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};
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&can_clk {
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clock-frequency = <48000000>;
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};
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&pfc {
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scif0_pins: scif0 {
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groups = "scif0_data";
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function = "scif0";
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};
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scif3_pins: scif3 {
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groups = "scif3_data";
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function = "scif3";
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};
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lan89218_pins: lan89218 {
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intc {
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groups = "intc_irq0";
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function = "intc";
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};
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lbsc {
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groups = "lbsc_ex_cs0";
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function = "lbsc";
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};
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};
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can0_pins: can0 {
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groups = "can0_data", "can_clk";
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function = "can0";
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};
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sdhi0_pins: sdhi0 {
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groups = "sdhi0_data4", "sdhi0_ctrl";
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function = "sdhi0";
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};
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du0_pins: du0 {
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groups = "du0_rgb888", "du0_sync", "du0_disp";
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function = "du0";
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};
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du1_pins: du1 {
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groups = "du1_rgb666", "du1_sync", "du1_disp";
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function = "du1";
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};
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};
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&scif0 {
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pinctrl-0 = <&scif0_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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&scif3 {
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pinctrl-0 = <&scif3_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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&can0 {
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pinctrl-0 = <&can0_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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&sdhi0 {
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pinctrl-0 = <&sdhi0_pins>;
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pinctrl-names = "default";
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vmmc-supply = <&vcc_sdhi0>;
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cd-gpios = <&gpio11 11 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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&i2c1 {
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status = "okay";
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clock-frequency = <400000>;
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hdmi@39 {
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compatible = "adi,adv7511w";
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reg = <0x39>;
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interrupt-parent = <&irqc>;
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interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
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adi,input-depth = <8>;
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adi,input-colorspace = "rgb";
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adi,input-clock = "1x";
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adi,input-style = <1>;
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adi,input-justification = "evenly";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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adv7511_in: endpoint {
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remote-endpoint = <&du_out_rgb0>;
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};
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};
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port@1 {
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reg = <1>;
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adv7511_out: endpoint {
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remote-endpoint = <&hdmi_con>;
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};
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};
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};
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};
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};
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&du {
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pinctrl-0 = <&du0_pins &du1_pins>;
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pinctrl-names = "default";
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clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&x1_clk>, <&x2_clk>;
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clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";
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status = "okay";
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ports {
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port@0 {
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endpoint {
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remote-endpoint = <&adv7511_in>;
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};
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};
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port@1 {
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endpoint {
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remote-endpoint = <&adv7123_in>;
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};
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};
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};
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};
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857
arch/arm/dts/r8a7792.dtsi
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857
arch/arm/dts/r8a7792.dtsi
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@ -0,0 +1,857 @@
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/*
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* Device Tree Source for the r8a7792 SoC
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*
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* Copyright (C) 2016 Cogent Embedded Inc.
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <dt-bindings/clock/r8a7792-cpg-mssr.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/r8a7792-sysc.h>
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/ {
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compatible = "renesas,r8a7792";
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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i2c2 = &i2c2;
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i2c3 = &i2c3;
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i2c4 = &i2c4;
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i2c5 = &i2c5;
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spi0 = &qspi;
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spi1 = &msiof0;
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spi2 = &msiof1;
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vin0 = &vin0;
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vin1 = &vin1;
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vin2 = &vin2;
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vin3 = &vin3;
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vin4 = &vin4;
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vin5 = &vin5;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "renesas,apmu";
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0>;
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clock-frequency = <1000000000>;
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clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
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power-domains = <&sysc R8A7792_PD_CA15_CPU0>;
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next-level-cache = <&L2_CA15>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <1>;
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clock-frequency = <1000000000>;
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clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
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power-domains = <&sysc R8A7792_PD_CA15_CPU1>;
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next-level-cache = <&L2_CA15>;
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};
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L2_CA15: cache-controller-0 {
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compatible = "cache";
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cache-unified;
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cache-level = <2>;
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power-domains = <&sysc R8A7792_PD_CA15_SCU>;
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};
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};
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soc {
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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apmu@e6152000 {
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compatible = "renesas,r8a7792-apmu", "renesas,apmu";
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reg = <0 0xe6152000 0 0x188>;
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cpus = <&cpu0 &cpu1>;
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};
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gic: interrupt-controller@f1001000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0 0xf1001000 0 0x1000>,
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<0 0xf1002000 0 0x2000>,
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<0 0xf1004000 0 0x2000>,
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<0 0xf1006000 0 0x2000>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_LEVEL_HIGH)>;
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clocks = <&cpg CPG_MOD 408>;
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clock-names = "clk";
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power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
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resets = <&cpg 408>;
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};
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irqc: interrupt-controller@e61c0000 {
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compatible = "renesas,irqc-r8a7792", "renesas,irqc";
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#interrupt-cells = <2>;
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interrupt-controller;
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reg = <0 0xe61c0000 0 0x200>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 407>;
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power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
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resets = <&cpg 407>;
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};
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timer {
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compatible = "arm,armv7-timer";
|
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
|
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IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
|
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IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_LEVEL_LOW)>;
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};
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rst: reset-controller@e6160000 {
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compatible = "renesas,r8a7792-rst";
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reg = <0 0xe6160000 0 0x0100>;
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};
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prr: chipid@ff000044 {
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compatible = "renesas,prr";
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reg = <0 0xff000044 0 4>;
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};
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sysc: system-controller@e6180000 {
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compatible = "renesas,r8a7792-sysc";
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reg = <0 0xe6180000 0 0x0200>;
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#power-domain-cells = <1>;
|
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};
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pfc: pin-controller@e6060000 {
|
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compatible = "renesas,pfc-r8a7792";
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reg = <0 0xe6060000 0 0x144>;
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};
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||||
|
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gpio0: gpio@e6050000 {
|
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compatible = "renesas,gpio-r8a7792",
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"renesas,rcar-gen2-gpio";
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reg = <0 0xe6050000 0 0x50>;
|
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interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
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#gpio-cells = <2>;
|
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gpio-controller;
|
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gpio-ranges = <&pfc 0 0 29>;
|
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#interrupt-cells = <2>;
|
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interrupt-controller;
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clocks = <&cpg CPG_MOD 912>;
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power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
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resets = <&cpg 912>;
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};
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||||
|
||||
gpio1: gpio@e6051000 {
|
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compatible = "renesas,gpio-r8a7792",
|
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"renesas,rcar-gen2-gpio";
|
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reg = <0 0xe6051000 0 0x50>;
|
||||
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
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#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 32 23>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 911>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 911>;
|
||||
};
|
||||
|
||||
gpio2: gpio@e6052000 {
|
||||
compatible = "renesas,gpio-r8a7792",
|
||||
"renesas,rcar-gen2-gpio";
|
||||
reg = <0 0xe6052000 0 0x50>;
|
||||
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 64 32>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 910>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 910>;
|
||||
};
|
||||
|
||||
gpio3: gpio@e6053000 {
|
||||
compatible = "renesas,gpio-r8a7792",
|
||||
"renesas,rcar-gen2-gpio";
|
||||
reg = <0 0xe6053000 0 0x50>;
|
||||
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 96 28>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 909>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 909>;
|
||||
};
|
||||
|
||||
gpio4: gpio@e6054000 {
|
||||
compatible = "renesas,gpio-r8a7792",
|
||||
"renesas,rcar-gen2-gpio";
|
||||
reg = <0 0xe6054000 0 0x50>;
|
||||
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 128 17>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 908>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 908>;
|
||||
};
|
||||
|
||||
gpio5: gpio@e6055000 {
|
||||
compatible = "renesas,gpio-r8a7792",
|
||||
"renesas,rcar-gen2-gpio";
|
||||
reg = <0 0xe6055000 0 0x50>;
|
||||
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 160 17>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 907>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 907>;
|
||||
};
|
||||
|
||||
gpio6: gpio@e6055100 {
|
||||
compatible = "renesas,gpio-r8a7792",
|
||||
"renesas,rcar-gen2-gpio";
|
||||
reg = <0 0xe6055100 0 0x50>;
|
||||
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 192 17>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 905>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 905>;
|
||||
};
|
||||
|
||||
gpio7: gpio@e6055200 {
|
||||
compatible = "renesas,gpio-r8a7792",
|
||||
"renesas,rcar-gen2-gpio";
|
||||
reg = <0 0xe6055200 0 0x50>;
|
||||
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 224 17>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 904>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 904>;
|
||||
};
|
||||
|
||||
gpio8: gpio@e6055300 {
|
||||
compatible = "renesas,gpio-r8a7792",
|
||||
"renesas,rcar-gen2-gpio";
|
||||
reg = <0 0xe6055300 0 0x50>;
|
||||
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 256 17>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 921>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 921>;
|
||||
};
|
||||
|
||||
gpio9: gpio@e6055400 {
|
||||
compatible = "renesas,gpio-r8a7792",
|
||||
"renesas,rcar-gen2-gpio";
|
||||
reg = <0 0xe6055400 0 0x50>;
|
||||
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 288 17>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 919>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 919>;
|
||||
};
|
||||
|
||||
gpio10: gpio@e6055500 {
|
||||
compatible = "renesas,gpio-r8a7792",
|
||||
"renesas,rcar-gen2-gpio";
|
||||
reg = <0 0xe6055500 0 0x50>;
|
||||
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 320 32>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 914>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 914>;
|
||||
};
|
||||
|
||||
gpio11: gpio@e6055600 {
|
||||
compatible = "renesas,gpio-r8a7792",
|
||||
"renesas,rcar-gen2-gpio";
|
||||
reg = <0 0xe6055600 0 0x50>;
|
||||
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 352 30>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 913>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 913>;
|
||||
};
|
||||
|
||||
dmac0: dma-controller@e6700000 {
|
||||
compatible = "renesas,dmac-r8a7792",
|
||||
"renesas,rcar-dmac";
|
||||
reg = <0 0xe6700000 0 0x20000>;
|
||||
interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "error",
|
||||
"ch0", "ch1", "ch2", "ch3",
|
||||
"ch4", "ch5", "ch6", "ch7",
|
||||
"ch8", "ch9", "ch10", "ch11",
|
||||
"ch12", "ch13", "ch14";
|
||||
clocks = <&cpg CPG_MOD 219>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 219>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <15>;
|
||||
};
|
||||
|
||||
dmac1: dma-controller@e6720000 {
|
||||
compatible = "renesas,dmac-r8a7792",
|
||||
"renesas,rcar-dmac";
|
||||
reg = <0 0xe6720000 0 0x20000>;
|
||||
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "error",
|
||||
"ch0", "ch1", "ch2", "ch3",
|
||||
"ch4", "ch5", "ch6", "ch7",
|
||||
"ch8", "ch9", "ch10", "ch11",
|
||||
"ch12", "ch13", "ch14";
|
||||
clocks = <&cpg CPG_MOD 218>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 218>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <15>;
|
||||
};
|
||||
|
||||
scif0: serial@e6e60000 {
|
||||
compatible = "renesas,scif-r8a7792",
|
||||
"renesas,rcar-gen2-scif", "renesas,scif";
|
||||
reg = <0 0xe6e60000 0 64>;
|
||||
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 721>,
|
||||
<&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
|
||||
<&dmac1 0x29>, <&dmac1 0x2a>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 721>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
scif1: serial@e6e68000 {
|
||||
compatible = "renesas,scif-r8a7792",
|
||||
"renesas,rcar-gen2-scif", "renesas,scif";
|
||||
reg = <0 0xe6e68000 0 64>;
|
||||
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 720>,
|
||||
<&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
|
||||
<&dmac1 0x2d>, <&dmac1 0x2e>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 720>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
scif2: serial@e6e58000 {
|
||||
compatible = "renesas,scif-r8a7792",
|
||||
"renesas,rcar-gen2-scif", "renesas,scif";
|
||||
reg = <0 0xe6e58000 0 64>;
|
||||
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 719>,
|
||||
<&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
|
||||
<&dmac1 0x2b>, <&dmac1 0x2c>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 719>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
scif3: serial@e6ea8000 {
|
||||
compatible = "renesas,scif-r8a7792",
|
||||
"renesas,rcar-gen2-scif", "renesas,scif";
|
||||
reg = <0 0xe6ea8000 0 64>;
|
||||
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 718>,
|
||||
<&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
|
||||
<&dmac1 0x2f>, <&dmac1 0x30>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 718>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
hscif0: serial@e62c0000 {
|
||||
compatible = "renesas,hscif-r8a7792",
|
||||
"renesas,rcar-gen2-hscif", "renesas,hscif";
|
||||
reg = <0 0xe62c0000 0 96>;
|
||||
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 717>,
|
||||
<&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
|
||||
<&dmac1 0x39>, <&dmac1 0x3a>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 717>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
hscif1: serial@e62c8000 {
|
||||
compatible = "renesas,hscif-r8a7792",
|
||||
"renesas,rcar-gen2-hscif", "renesas,hscif";
|
||||
reg = <0 0xe62c8000 0 96>;
|
||||
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 716>,
|
||||
<&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
|
||||
<&dmac1 0x4d>, <&dmac1 0x4e>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 716>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
icram0: sram@e63a0000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0 0xe63a0000 0 0x12000>;
|
||||
};
|
||||
|
||||
icram1: sram@e63c0000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0 0xe63c0000 0 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0xe63c0000 0x1000>;
|
||||
|
||||
smp-sram@0 {
|
||||
compatible = "renesas,smp-sram";
|
||||
reg = <0 0x10>;
|
||||
};
|
||||
};
|
||||
|
||||
sdhi0: sd@ee100000 {
|
||||
compatible = "renesas,sdhi-r8a7792";
|
||||
reg = <0 0xee100000 0 0x328>;
|
||||
interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
|
||||
<&dmac1 0xcd>, <&dmac1 0xce>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
clocks = <&cpg CPG_MOD 314>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 314>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
jpu: jpeg-codec@fe980000 {
|
||||
compatible = "renesas,jpu-r8a7792",
|
||||
"renesas,rcar-gen2-jpu";
|
||||
reg = <0 0xfe980000 0 0x10300>;
|
||||
interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 106>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 106>;
|
||||
};
|
||||
|
||||
avb: ethernet@e6800000 {
|
||||
compatible = "renesas,etheravb-r8a7792",
|
||||
"renesas,etheravb-rcar-gen2";
|
||||
reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
|
||||
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 812>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 812>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* I2C doesn't need pinmux */
|
||||
i2c0: i2c@e6508000 {
|
||||
compatible = "renesas,i2c-r8a7792",
|
||||
"renesas,rcar-gen2-i2c";
|
||||
reg = <0 0xe6508000 0 0x40>;
|
||||
interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 931>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 931>;
|
||||
i2c-scl-internal-delay-ns = <6>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@e6518000 {
|
||||
compatible = "renesas,i2c-r8a7792",
|
||||
"renesas,rcar-gen2-i2c";
|
||||
reg = <0 0xe6518000 0 0x40>;
|
||||
interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 930>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 930>;
|
||||
i2c-scl-internal-delay-ns = <6>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@e6530000 {
|
||||
compatible = "renesas,i2c-r8a7792",
|
||||
"renesas,rcar-gen2-i2c";
|
||||
reg = <0 0xe6530000 0 0x40>;
|
||||
interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 929>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 929>;
|
||||
i2c-scl-internal-delay-ns = <6>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c3: i2c@e6540000 {
|
||||
compatible = "renesas,i2c-r8a7792",
|
||||
"renesas,rcar-gen2-i2c";
|
||||
reg = <0 0xe6540000 0 0x40>;
|
||||
interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 928>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 928>;
|
||||
i2c-scl-internal-delay-ns = <6>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c4: i2c@e6520000 {
|
||||
compatible = "renesas,i2c-r8a7792",
|
||||
"renesas,rcar-gen2-i2c";
|
||||
reg = <0 0xe6520000 0 0x40>;
|
||||
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 927>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 927>;
|
||||
i2c-scl-internal-delay-ns = <6>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c5: i2c@e6528000 {
|
||||
compatible = "renesas,i2c-r8a7792",
|
||||
"renesas,rcar-gen2-i2c";
|
||||
reg = <0 0xe6528000 0 0x40>;
|
||||
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 925>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 925>;
|
||||
i2c-scl-internal-delay-ns = <110>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qspi: spi@e6b10000 {
|
||||
compatible = "renesas,qspi-r8a7792", "renesas,qspi";
|
||||
reg = <0 0xe6b10000 0 0x2c>;
|
||||
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 917>;
|
||||
dmas = <&dmac0 0x17>, <&dmac0 0x18>,
|
||||
<&dmac1 0x17>, <&dmac1 0x18>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 917>;
|
||||
num-cs = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
msiof0: spi@e6e20000 {
|
||||
compatible = "renesas,msiof-r8a7792",
|
||||
"renesas,rcar-gen2-msiof";
|
||||
reg = <0 0xe6e20000 0 0x0064>;
|
||||
interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 000>;
|
||||
dmas = <&dmac0 0x51>, <&dmac0 0x52>,
|
||||
<&dmac1 0x51>, <&dmac1 0x52>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
msiof1: spi@e6e10000 {
|
||||
compatible = "renesas,msiof-r8a7792",
|
||||
"renesas,rcar-gen2-msiof";
|
||||
reg = <0 0xe6e10000 0 0x0064>;
|
||||
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 208>;
|
||||
dmas = <&dmac0 0x55>, <&dmac0 0x56>,
|
||||
<&dmac1 0x55>, <&dmac1 0x56>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 208>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
du: display@feb00000 {
|
||||
compatible = "renesas,du-r8a7792";
|
||||
reg = <0 0xfeb00000 0 0x40000>;
|
||||
reg-names = "du";
|
||||
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 724>,
|
||||
<&cpg CPG_MOD 723>;
|
||||
clock-names = "du.0", "du.1";
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
du_out_rgb0: endpoint {
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
du_out_rgb1: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
can0: can@e6e80000 {
|
||||
compatible = "renesas,can-r8a7792",
|
||||
"renesas,rcar-gen2-can";
|
||||
reg = <0 0xe6e80000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 916>,
|
||||
<&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>;
|
||||
clock-names = "clkp1", "clkp2", "can_clk";
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 916>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
can1: can@e6e88000 {
|
||||
compatible = "renesas,can-r8a7792",
|
||||
"renesas,rcar-gen2-can";
|
||||
reg = <0 0xe6e88000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 915>,
|
||||
<&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>;
|
||||
clock-names = "clkp1", "clkp2", "can_clk";
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 915>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
vin0: video@e6ef0000 {
|
||||
compatible = "renesas,vin-r8a7792",
|
||||
"renesas,rcar-gen2-vin";
|
||||
reg = <0 0xe6ef0000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 811>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 811>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
vin1: video@e6ef1000 {
|
||||
compatible = "renesas,vin-r8a7792",
|
||||
"renesas,rcar-gen2-vin";
|
||||
reg = <0 0xe6ef1000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 810>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 810>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
vin2: video@e6ef2000 {
|
||||
compatible = "renesas,vin-r8a7792",
|
||||
"renesas,rcar-gen2-vin";
|
||||
reg = <0 0xe6ef2000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 809>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 809>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
vin3: video@e6ef3000 {
|
||||
compatible = "renesas,vin-r8a7792",
|
||||
"renesas,rcar-gen2-vin";
|
||||
reg = <0 0xe6ef3000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 808>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 808>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
vin4: video@e6ef4000 {
|
||||
compatible = "renesas,vin-r8a7792",
|
||||
"renesas,rcar-gen2-vin";
|
||||
reg = <0 0xe6ef4000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 805>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 805>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
vin5: video@e6ef5000 {
|
||||
compatible = "renesas,vin-r8a7792",
|
||||
"renesas,rcar-gen2-vin";
|
||||
reg = <0 0xe6ef5000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 804>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 804>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
vsp@fe928000 {
|
||||
compatible = "renesas,vsp1";
|
||||
reg = <0 0xfe928000 0 0x8000>;
|
||||
interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 131>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 131>;
|
||||
};
|
||||
|
||||
vsp@fe930000 {
|
||||
compatible = "renesas,vsp1";
|
||||
reg = <0 0xfe930000 0 0x8000>;
|
||||
interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 128>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 128>;
|
||||
};
|
||||
|
||||
vsp@fe938000 {
|
||||
compatible = "renesas,vsp1";
|
||||
reg = <0 0xfe938000 0 0x8000>;
|
||||
interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 127>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 127>;
|
||||
};
|
||||
|
||||
cpg: clock-controller@e6150000 {
|
||||
compatible = "renesas,r8a7792-cpg-mssr";
|
||||
reg = <0 0xe6150000 0 0x1000>;
|
||||
clocks = <&extal_clk>;
|
||||
clock-names = "extal";
|
||||
#clock-cells = <2>;
|
||||
#power-domain-cells = <0>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
/* External root clock */
|
||||
extal_clk: extal {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
/* This value must be overridden by the board. */
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
/* External SCIF clock */
|
||||
scif_clk: scif {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
/* This value must be overridden by the board. */
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
/* External CAN clock */
|
||||
can_clk: can {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
/* This value must be overridden by the board. */
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
};
|
||||
102
include/dt-bindings/clock/r8a7792-clock.h
Normal file
102
include/dt-bindings/clock/r8a7792-clock.h
Normal file
|
|
@ -0,0 +1,102 @@
|
|||
/*
|
||||
* Copyright (C) 2016 Cogent Embedded, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_R8A7792_H__
|
||||
#define __DT_BINDINGS_CLOCK_R8A7792_H__
|
||||
|
||||
/* CPG */
|
||||
#define R8A7792_CLK_MAIN 0
|
||||
#define R8A7792_CLK_PLL0 1
|
||||
#define R8A7792_CLK_PLL1 2
|
||||
#define R8A7792_CLK_PLL3 3
|
||||
#define R8A7792_CLK_LB 4
|
||||
#define R8A7792_CLK_QSPI 5
|
||||
|
||||
/* MSTP0 */
|
||||
#define R8A7792_CLK_MSIOF0 0
|
||||
|
||||
/* MSTP1 */
|
||||
#define R8A7792_CLK_JPU 6
|
||||
#define R8A7792_CLK_TMU1 11
|
||||
#define R8A7792_CLK_TMU3 21
|
||||
#define R8A7792_CLK_TMU2 22
|
||||
#define R8A7792_CLK_CMT0 24
|
||||
#define R8A7792_CLK_TMU0 25
|
||||
#define R8A7792_CLK_VSP1DU1 27
|
||||
#define R8A7792_CLK_VSP1DU0 28
|
||||
#define R8A7792_CLK_VSP1_SY 31
|
||||
|
||||
/* MSTP2 */
|
||||
#define R8A7792_CLK_MSIOF1 8
|
||||
#define R8A7792_CLK_SYS_DMAC1 18
|
||||
#define R8A7792_CLK_SYS_DMAC0 19
|
||||
|
||||
/* MSTP3 */
|
||||
#define R8A7792_CLK_TPU0 4
|
||||
#define R8A7792_CLK_SDHI0 14
|
||||
#define R8A7792_CLK_CMT1 29
|
||||
|
||||
/* MSTP4 */
|
||||
#define R8A7792_CLK_IRQC 7
|
||||
#define R8A7792_CLK_INTC_SYS 8
|
||||
|
||||
/* MSTP5 */
|
||||
#define R8A7792_CLK_AUDIO_DMAC0 2
|
||||
#define R8A7792_CLK_THERMAL 22
|
||||
#define R8A7792_CLK_PWM 23
|
||||
|
||||
/* MSTP7 */
|
||||
#define R8A7792_CLK_HSCIF1 16
|
||||
#define R8A7792_CLK_HSCIF0 17
|
||||
#define R8A7792_CLK_SCIF3 18
|
||||
#define R8A7792_CLK_SCIF2 19
|
||||
#define R8A7792_CLK_SCIF1 20
|
||||
#define R8A7792_CLK_SCIF0 21
|
||||
#define R8A7792_CLK_DU1 23
|
||||
#define R8A7792_CLK_DU0 24
|
||||
|
||||
/* MSTP8 */
|
||||
#define R8A7792_CLK_VIN5 4
|
||||
#define R8A7792_CLK_VIN4 5
|
||||
#define R8A7792_CLK_VIN3 8
|
||||
#define R8A7792_CLK_VIN2 9
|
||||
#define R8A7792_CLK_VIN1 10
|
||||
#define R8A7792_CLK_VIN0 11
|
||||
#define R8A7792_CLK_ETHERAVB 12
|
||||
|
||||
/* MSTP9 */
|
||||
#define R8A7792_CLK_GPIO7 4
|
||||
#define R8A7792_CLK_GPIO6 5
|
||||
#define R8A7792_CLK_GPIO5 7
|
||||
#define R8A7792_CLK_GPIO4 8
|
||||
#define R8A7792_CLK_GPIO3 9
|
||||
#define R8A7792_CLK_GPIO2 10
|
||||
#define R8A7792_CLK_GPIO1 11
|
||||
#define R8A7792_CLK_GPIO0 12
|
||||
#define R8A7792_CLK_GPIO11 13
|
||||
#define R8A7792_CLK_GPIO10 14
|
||||
#define R8A7792_CLK_CAN1 15
|
||||
#define R8A7792_CLK_CAN0 16
|
||||
#define R8A7792_CLK_QSPI_MOD 17
|
||||
#define R8A7792_CLK_GPIO9 19
|
||||
#define R8A7792_CLK_GPIO8 21
|
||||
#define R8A7792_CLK_I2C5 25
|
||||
#define R8A7792_CLK_IICDVFS 26
|
||||
#define R8A7792_CLK_I2C4 27
|
||||
#define R8A7792_CLK_I2C3 28
|
||||
#define R8A7792_CLK_I2C2 29
|
||||
#define R8A7792_CLK_I2C1 30
|
||||
#define R8A7792_CLK_I2C0 31
|
||||
|
||||
/* MSTP10 */
|
||||
#define R8A7792_CLK_SSI_ALL 5
|
||||
#define R8A7792_CLK_SSI4 11
|
||||
#define R8A7792_CLK_SSI3 12
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_R8A7792_H__ */
|
||||
43
include/dt-bindings/clock/r8a7792-cpg-mssr.h
Normal file
43
include/dt-bindings/clock/r8a7792-cpg-mssr.h
Normal file
|
|
@ -0,0 +1,43 @@
|
|||
/*
|
||||
* Copyright (C) 2015 Renesas Electronics Corp.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__
|
||||
#define __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__
|
||||
|
||||
#include <dt-bindings/clock/renesas-cpg-mssr.h>
|
||||
|
||||
/* r8a7792 CPG Core Clocks */
|
||||
#define R8A7792_CLK_Z 0
|
||||
#define R8A7792_CLK_ZG 1
|
||||
#define R8A7792_CLK_ZTR 2
|
||||
#define R8A7792_CLK_ZTRD2 3
|
||||
#define R8A7792_CLK_ZT 4
|
||||
#define R8A7792_CLK_ZX 5
|
||||
#define R8A7792_CLK_ZS 6
|
||||
#define R8A7792_CLK_HP 7
|
||||
#define R8A7792_CLK_I 8
|
||||
#define R8A7792_CLK_B 9
|
||||
#define R8A7792_CLK_LB 10
|
||||
#define R8A7792_CLK_P 11
|
||||
#define R8A7792_CLK_CL 12
|
||||
#define R8A7792_CLK_M2 13
|
||||
#define R8A7792_CLK_IMP 14
|
||||
#define R8A7792_CLK_ZB3 15
|
||||
#define R8A7792_CLK_ZB3D2 16
|
||||
#define R8A7792_CLK_DDR 17
|
||||
#define R8A7792_CLK_SD 18
|
||||
#define R8A7792_CLK_MP 19
|
||||
#define R8A7792_CLK_QSPI 20
|
||||
#define R8A7792_CLK_CP 21
|
||||
#define R8A7792_CLK_CPEX 22
|
||||
#define R8A7792_CLK_RCAN 23
|
||||
#define R8A7792_CLK_R 24
|
||||
#define R8A7792_CLK_OSC 25
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__ */
|
||||
26
include/dt-bindings/power/r8a7792-sysc.h
Normal file
26
include/dt-bindings/power/r8a7792-sysc.h
Normal file
|
|
@ -0,0 +1,26 @@
|
|||
/*
|
||||
* Copyright (C) 2016 Cogent Embedded Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_POWER_R8A7792_SYSC_H__
|
||||
#define __DT_BINDINGS_POWER_R8A7792_SYSC_H__
|
||||
|
||||
/*
|
||||
* These power domain indices match the numbers of the interrupt bits
|
||||
* representing the power areas in the various Interrupt Registers
|
||||
* (e.g. SYSCISR, Interrupt Status Register)
|
||||
*/
|
||||
|
||||
#define R8A7792_PD_CA15_CPU0 0
|
||||
#define R8A7792_PD_CA15_CPU1 1
|
||||
#define R8A7792_PD_CA15_SCU 12
|
||||
#define R8A7792_PD_SGX 20
|
||||
#define R8A7792_PD_IMP 24
|
||||
|
||||
/* Always-on power area */
|
||||
#define R8A7792_PD_ALWAYS_ON 32
|
||||
|
||||
#endif /* __DT_BINDINGS_POWER_R8A7792_SYSC_H__ */
|
||||
Loading…
Reference in a new issue