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arm64: zynqmp: Use assigned-clock-rates for setting up clock in SOM

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With limited low level configuration done via psu-init only IPs connected
on SOM are initialized and configured. All IPs connected to carrier card
are not initialized. There is a need to do proper reset, pin configuration
and also clock setting.
The patch targets the last part which is setting up proper clock for USBs
and SDs.
Also setup proper bus width for SD cards.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
Link: https://lore.kernel.org/r/d9f80b2551bd246c3d7ecb09b516806c8dc83ed9.1645629459.git.michal.simek@xilinx.com
This commit is contained in:
Michal Simek 2022-02-23 16:17:39 +01:00
parent 59e1bdd48d
commit a3efa53c01
4 changed files with 10 additions and 0 deletions
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4
arch/arm/dts/zynqmp-clk-ccf.dtsi
View file

@ -215,10 +215,12 @@
&sdhci0 {
clocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>;
assigned-clocks = <&zynqmp_clk SDIO0_REF>;
};
&sdhci1 {
clocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>;
assigned-clocks = <&zynqmp_clk SDIO1_REF>;
};
&spi0 {
@ -255,10 +257,12 @@
&usb0 {
clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
assigned-clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
};
&usb1 {
clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
assigned-clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
};
&watchdog0 {

2
arch/arm/dts/zynqmp-sck-kv-g-revA.dts
View file

@ -154,6 +154,8 @@
no-1-8-v;
disable-wp;
xlnx,mio-bank = <1>;
assigned-clock-rates = <187498123>;
bus-width = <8>;
};
&gem3 { /* required by spec */

3
arch/arm/dts/zynqmp-sck-kv-g-revB.dts
View file

@ -109,6 +109,7 @@
pinctrl-0 = <&pinctrl_usb0_default>;
phy-names = "usb3-phy";
phys = <&psgtr 2 PHY_TYPE_USB3 0 1>;
assigned-clock-rates = <250000000>, <20000000>;
usb5744: usb-hub { /* u43 */
status = "okay";
@ -140,6 +141,8 @@
clk-phase-sd-hs = <126>, <60>;
clk-phase-uhs-sdr25 = <120>, <60>;
clk-phase-uhs-ddr50 = <126>, <48>;
assigned-clock-rates = <187498123>;
bus-width = <8>;
};
&gem3 { /* required by spec */

1
arch/arm/dts/zynqmp-sm-k26-revA.dts
View file

@ -189,6 +189,7 @@
disable-wp;
bus-width = <8>;
xlnx,mio-bank = <0>;
assigned-clock-rates = <187498123>;
};
&spi1 { /* MIO6, 9-11 */