mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-24 21:54:01 +00:00
- splash_source warning fix when building with 64-bit toolchains
- lq123p1jx31 and nv101wxmn51 compatible in simple panel driver - remove not used mb862xx driver - add Himax HX8238D panel driver - s/video_uc_platdata/video_uc_plat/ -----BEGIN PGP SIGNATURE----- iGwEABECACwWIQSC4hxrSoIUVfFO0kRM6ATMmsalXAUCYDOevA4cYWd1c3RAZGVu eC5kZQAKCRBM6ATMmsalXNaAAJ0RUysoiZFAddxyrW7otwe+xxmdTACbBcVXCPuX W41gJtQyftU4rMGbMoo= =iAX1 -----END PGP SIGNATURE----- Merge tag 'video-for-v2021.04-rc3' of https://gitlab.denx.de/u-boot/custodians/u-boot-video - splash_source warning fix when building with 64-bit toolchains - lq123p1jx31 and nv101wxmn51 compatible in simple panel driver - remove not used mb862xx driver - add Himax HX8238D panel driver - s/video_uc_platdata/video_uc_plat/
This commit is contained in:
Tom Rini
commit
a3ddc776fa
10 changed files with 215 additions and 607 deletions
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@ -26,14 +26,12 @@
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#include <fdt_support.h>
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#include <asm/io.h>
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#include <i2c.h>
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#include <mb862xx.h>
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#include <video_fb.h>
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#include "upm_table.h"
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DECLARE_GLOBAL_DATA_PTR;
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extern flash_info_t flash_info[]; /* FLASH chips info */
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extern GraphicDevice mb862xx;
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void local_bus_init (void);
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ulong flash_get_size (ulong base, int banknum);
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@ -207,16 +205,6 @@ int ft_board_setup(void *blob, struct bd_info *bd)
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val[i++] = gd->bd->bi_flashstart;
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val[i++] = gd->bd->bi_flashsize;
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#if defined(CONFIG_VIDEO_MB862xx)
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if (mb862xx.frameAdrs == CONFIG_SYS_LIME_BASE) {
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/* Fixup LIME mapping */
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val[i++] = 2; /* chip select number */
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val[i++] = 0; /* always 0 */
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val[i++] = CONFIG_SYS_LIME_BASE;
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val[i++] = CONFIG_SYS_LIME_SIZE;
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}
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#endif
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/* Fixup FPGA mapping */
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val[i++] = 3; /* chip select number */
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val[i++] = 0; /* always 0 */
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@ -37,7 +37,7 @@ static int splash_sf_read_raw(u32 bmp_load_addr, int offset, size_t read_size)
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return -ENODEV;
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}
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return spi_flash_read(sf, offset, read_size, (void *)bmp_load_addr);
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return spi_flash_read(sf, offset, read_size, (void *)(uintptr_t)bmp_load_addr);
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}
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#else
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static int splash_sf_read_raw(u32 bmp_load_addr, int offset, size_t read_size)
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@ -98,7 +98,7 @@ static int splash_load_raw(struct splash_location *location, u32 bmp_load_addr)
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if (res < 0)
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return res;
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bmp_hdr = (struct bmp_header *)bmp_load_addr;
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bmp_hdr = (struct bmp_header *)(uintptr_t)bmp_load_addr;
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bmp_size = le32_to_cpu(bmp_hdr->file_size);
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if (bmp_load_addr + bmp_size >= gd->start_addr_sp)
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@ -30,7 +30,7 @@ config VIDEO_PCI_DEFAULT_FB_SIZE
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help
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Generally, video drivers request the amount of memory they need for
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the frame buffer when they are bound, by setting the size field in
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struct video_uc_platdata. That memory is then reserved for use after
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struct video_uc_plat. That memory is then reserved for use after
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relocation. But PCI drivers cannot be bound before relocation unless
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they are mentioned in the devicetree.
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@ -51,7 +51,7 @@ config VIDEO_COPY
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U-Boot) and then copied to the hardware frame-buffer as needed.
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To use this, your video driver must set @copy_base in
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struct video_uc_platdata.
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struct video_uc_plat.
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config BACKLIGHT_PWM
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bool "Generic PWM based Backlight Driver"
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@ -160,6 +160,16 @@ config CONSOLE_TRUETYPE
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With this option you can adjust the text size and use a variety of
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fonts. Note that this is noticeably slower than with normal console.
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config DM_PANEL_HX8238D
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bool "Enable Himax HX-8238D LCD driver"
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depends on DM_VIDEO
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help
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Support for HX-8238D LCD Panel
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The HX8238-D is a single chip controller and driver LSI that
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integrates the power circuit.
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It can drive a maximum 960x240 dot graphics on a-TFT panel
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displays in 16M colors with dithering.
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config CONSOLE_TRUETYPE_SIZE
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int "TrueType font size"
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depends on CONSOLE_TRUETYPE
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@ -15,6 +15,7 @@ obj-$(CONFIG_VIDEO_MIPI_DSI) += dsi-host-uclass.o
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obj-$(CONFIG_DM_VIDEO) += video-uclass.o vidconsole-uclass.o
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obj-$(CONFIG_DM_VIDEO) += video_bmp.o
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obj-$(CONFIG_PANEL) += panel-uclass.o
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obj-$(CONFIG_PANEL_HX8238D) += hx8238d.o
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obj-$(CONFIG_SIMPLE_PANEL) += simple_panel.o
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endif
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@ -57,7 +58,6 @@ obj-$(CONFIG_VIDEO_LCD_ORISETECH_OTM8009A) += orisetech_otm8009a.o
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obj-$(CONFIG_VIDEO_LCD_RAYDIUM_RM68200) += raydium-rm68200.o
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obj-$(CONFIG_VIDEO_LCD_SSD2828) += ssd2828.o
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obj-$(CONFIG_VIDEO_LCD_TDO_TL070WSH30) += tdo-tl070wsh30.o
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obj-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o
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obj-${CONFIG_VIDEO_MESON} += meson/
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obj-${CONFIG_VIDEO_MIPI_DSI} += mipi_dsi.o
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obj-$(CONFIG_VIDEO_MVEBU) += mvebu_lcd.o
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197
drivers/video/hx8238d.c
Normal file
197
drivers/video/hx8238d.c
Normal file
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@ -0,0 +1,197 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copied from simple-panel
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* Copyright (c) 2016 Google, Inc
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* Written by Simon Glass <sjg@chromium.org>
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* Copyright (c) 2018 Sjoerd Simons <sjoerd.simons@collabora.co.uk>
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* Modified by Moses Christopher <BollavarapuMoses.Christopher@in.bosch.com>
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*
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* Panel Initialization for HX8238D panel from Himax
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* Resolution: 320x240
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* Color-Mode: RGB
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*
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*/
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#include <common.h>
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#include <dm.h>
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#include <panel.h>
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#include <spi.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* Register Address */
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#define HX8238D_OUTPUT_CTRL_ADDR 0x01
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#define HX8238D_LCD_AC_CTRL_ADDR 0x02
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#define HX8238D_POWER_CTRL_1_ADDR 0x03
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#define HX8238D_DATA_CLR_CTRL_ADDR 0X04
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#define HX8238D_FUNCTION_CTRL_ADDR 0x05
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#define HX8238D_LED_CTRL_ADDR 0x08
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#define HX8238D_CONT_BRIGHT_CTRL_ADDR 0x0A
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#define HX8238D_FRAME_CYCLE_CTRL_ADDR 0x0B
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#define HX8238D_POWER_CTRL_2_ADDR 0x0D
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#define HX8238D_POWER_CTRL_3_ADDR 0x0E
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#define HX8238D_GATE_SCAN_POS_ADDR 0x0F
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#define HX8238D_HORIZONTAL_PORCH_ADDR 0x16
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#define HX8238D_VERTICAL_PORCH_ADDR 0x17
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#define HX8238D_POWER_CTRL_4_ADDR 0x1E
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#define HX8238D_GAMMA_CTRL_1_ADDR 0x30
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#define HX8238D_GAMMA_CTRL_2_ADDR 0x31
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#define HX8238D_GAMMA_CTRL_3_ADDR 0x32
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#define HX8238D_GAMMA_CTRL_4_ADDR 0x33
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#define HX8238D_GAMMA_CTRL_5_ADDR 0x34
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#define HX8238D_GAMMA_CTRL_6_ADDR 0x35
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#define HX8238D_GAMMA_CTRL_7_ADDR 0x36
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#define HX8238D_GAMMA_CTRL_8_ADDR 0x37
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#define HX8238D_GAMMA_CTRL_9_ADDR 0x3A
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#define HX8238D_GAMMA_CTRL_10_ADDR 0x3B
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/* Register Data */
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#define HX8238D_OUTPUT_CTRL 0x6300
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#define HX8238D_LCD_AC_CTRL 0x0200
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#define HX8238D_POWER_CTRL_1 0x6564
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#define HX8238D_DATA_CLR_CTRL 0x04C7
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#define HX8238D_FUNCTION_CTRL 0xA884
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#define HX8238D_LED_CTRL 0x00CE
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#define HX8238D_CONT_BRIGHT_CTRL 0x4008
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#define HX8238D_FRAME_CYCLE_CTRL 0xD400
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#define HX8238D_POWER_CTRL_2 0x3229
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#define HX8238D_POWER_CTRL_3 0x1200
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#define HX8238D_GATE_SCAN_POS 0x0000
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#define HX8238D_HORIZONTAL_PORCH 0x9F80
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#define HX8238D_VERTICAL_PORCH 0x3F02
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#define HX8238D_POWER_CTRL_4 0x005C
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/* Gamma Control */
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#define HX8238D_GAMMA_CTRL_1 0x0103
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#define HX8238D_GAMMA_CTRL_2 0x0407
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#define HX8238D_GAMMA_CTRL_3 0x0705
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#define HX8238D_GAMMA_CTRL_4 0x0002
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#define HX8238D_GAMMA_CTRL_5 0x0505
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#define HX8238D_GAMMA_CTRL_6 0x0303
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#define HX8238D_GAMMA_CTRL_7 0x0707
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#define HX8238D_GAMMA_CTRL_8 0x0100
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#define HX8238D_GAMMA_CTRL_9 0x1F00
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#define HX8238D_GAMMA_CTRL_10 0x000F
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/* Primary SPI register identification, 011100 */
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/* Select register, RS=0, RS=0 */
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/* Write register, RS=1, RW=0 */
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#define HX8238D_PRIMARY_SELECT_REG 0x70
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#define HX8238D_PRIMARY_WRITE_REG (HX8238D_PRIMARY_SELECT_REG | (0x1 << 1))
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#define HX8238D_REG_BIT_LEN 24
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struct hx8238d_priv {
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struct spi_slave *spi;
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};
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static int hx8238d_ofdata_to_platdata(struct udevice *dev)
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{
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struct hx8238d_priv *priv = dev_get_priv(dev);
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priv->spi = dev_get_parent_priv(dev);
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return 0;
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}
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/* data[0] => REGISTER ADDRESS */
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/* data[1] => REGISTER VALUE */
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struct hx8238d_command {
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u16 data[2];
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};
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static struct hx8238d_command hx8238d_init_commands[] = {
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{ .data = { HX8238D_OUTPUT_CTRL_ADDR, HX8238D_OUTPUT_CTRL } },
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{ .data = { HX8238D_LCD_AC_CTRL_ADDR, HX8238D_LCD_AC_CTRL } },
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{ .data = { HX8238D_POWER_CTRL_1_ADDR, HX8238D_POWER_CTRL_1 } },
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{ .data = { HX8238D_DATA_CLR_CTRL_ADDR, HX8238D_DATA_CLR_CTRL } },
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{ .data = { HX8238D_FUNCTION_CTRL_ADDR, HX8238D_FUNCTION_CTRL } },
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{ .data = { HX8238D_LED_CTRL_ADDR, HX8238D_LED_CTRL } },
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{ .data = { HX8238D_CONT_BRIGHT_CTRL_ADDR, HX8238D_CONT_BRIGHT_CTRL } },
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{ .data = { HX8238D_FRAME_CYCLE_CTRL_ADDR, HX8238D_FRAME_CYCLE_CTRL } },
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{ .data = { HX8238D_POWER_CTRL_2_ADDR, HX8238D_POWER_CTRL_2 } },
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{ .data = { HX8238D_POWER_CTRL_3_ADDR, HX8238D_POWER_CTRL_3 } },
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{ .data = { HX8238D_GATE_SCAN_POS_ADDR, HX8238D_GATE_SCAN_POS } },
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{ .data = { HX8238D_HORIZONTAL_PORCH_ADDR, HX8238D_HORIZONTAL_PORCH } },
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{ .data = { HX8238D_VERTICAL_PORCH_ADDR, HX8238D_VERTICAL_PORCH } },
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{ .data = { HX8238D_POWER_CTRL_4_ADDR, HX8238D_POWER_CTRL_4 } },
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{ .data = { HX8238D_GAMMA_CTRL_1_ADDR, HX8238D_GAMMA_CTRL_1 } },
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{ .data = { HX8238D_GAMMA_CTRL_2_ADDR, HX8238D_GAMMA_CTRL_2 } },
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{ .data = { HX8238D_GAMMA_CTRL_3_ADDR, HX8238D_GAMMA_CTRL_3 } },
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{ .data = { HX8238D_GAMMA_CTRL_4_ADDR, HX8238D_GAMMA_CTRL_4 } },
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{ .data = { HX8238D_GAMMA_CTRL_5_ADDR, HX8238D_GAMMA_CTRL_5 } },
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{ .data = { HX8238D_GAMMA_CTRL_6_ADDR, HX8238D_GAMMA_CTRL_6 } },
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{ .data = { HX8238D_GAMMA_CTRL_7_ADDR, HX8238D_GAMMA_CTRL_7 } },
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{ .data = { HX8238D_GAMMA_CTRL_8_ADDR, HX8238D_GAMMA_CTRL_8 } },
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{ .data = { HX8238D_GAMMA_CTRL_9_ADDR, HX8238D_GAMMA_CTRL_9 } },
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{ .data = { HX8238D_GAMMA_CTRL_10_ADDR, HX8238D_GAMMA_CTRL_10 } },
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};
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/*
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* Generate Primary Register Buffer for Register Select and Register Write
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* First 6 MSB bits of Primary Register is represented with 011100
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*
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*/
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static void hx8238d_generate_reg_buffers(struct hx8238d_command command,
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u8 *sr_buf, uint8_t *wr_buf)
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{
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struct hx8238d_command cmd = command;
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sr_buf[0] = HX8238D_PRIMARY_SELECT_REG;
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sr_buf[1] = (cmd.data[0] >> 8) & 0xff;
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sr_buf[2] = (cmd.data[0]) & 0xff;
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wr_buf[0] = HX8238D_PRIMARY_WRITE_REG;
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wr_buf[1] = (cmd.data[1] >> 8) & 0xff;
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wr_buf[2] = (cmd.data[1]) & 0xff;
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}
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static int hx8238d_probe(struct udevice *dev)
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{
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struct hx8238d_priv *priv = dev_get_priv(dev);
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int ret;
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ret = spi_claim_bus(priv->spi);
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if (ret) {
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debug("Failed to claim bus: %d\n", ret);
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return ret;
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}
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for (int i = 0; i < ARRAY_SIZE(hx8238d_init_commands); i++) {
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u8 sr_buf[3], wr_buf[3];
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const struct hx8238d_command cmd = hx8238d_init_commands[i];
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hx8238d_generate_reg_buffers(cmd, sr_buf, wr_buf);
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ret = spi_xfer(priv->spi, HX8238D_REG_BIT_LEN, sr_buf, NULL,
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SPI_XFER_BEGIN | SPI_XFER_END);
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if (ret) {
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debug("Failed to select register %d\n", ret);
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goto free;
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}
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|
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ret = spi_xfer(priv->spi, HX8238D_REG_BIT_LEN, wr_buf, NULL,
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SPI_XFER_BEGIN | SPI_XFER_END);
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if (ret) {
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debug("Failed to write value %d\n", ret);
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goto free;
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}
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}
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|
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free:
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spi_release_bus(priv->spi);
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return ret;
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}
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static const struct udevice_id hx8238d_ids[] = {
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{ .compatible = "himax,hx8238d" },
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{ }
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};
|
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|
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U_BOOT_DRIVER(hx8238d) = {
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.name = "hx8238d",
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.id = UCLASS_PANEL,
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.of_match = hx8238d_ids,
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.ofdata_to_platdata = hx8238d_ofdata_to_platdata,
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.probe = hx8238d_probe,
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.priv_auto_alloc_size = sizeof(struct hx8238d_priv),
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};
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|
|
@ -1,486 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* (C) Copyright 2007
|
||||
* DENX Software Engineering, Anatolij Gustschin, agust@denx.de
|
||||
*/
|
||||
|
||||
/*
|
||||
* mb862xx.c - Graphic interface for Fujitsu CoralP/Lime
|
||||
* PCI and video mode code was derived from smiLynxEM driver.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <linux/delay.h>
|
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|
||||
#include <asm/io.h>
|
||||
#include <env.h>
|
||||
#include <pci.h>
|
||||
#include <video_fb.h>
|
||||
#include "videomodes.h"
|
||||
#include <mb862xx.h>
|
||||
|
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#if defined(CONFIG_POST)
|
||||
#include <post.h>
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Graphic Device
|
||||
*/
|
||||
GraphicDevice mb862xx;
|
||||
|
||||
/*
|
||||
* 32MB external RAM - 256K Chip MMIO = 0x1FC0000 ;
|
||||
*/
|
||||
#define VIDEO_MEM_SIZE 0x01FC0000
|
||||
|
||||
#if defined(CONFIG_PCI)
|
||||
#if defined(CONFIG_VIDEO_CORALP)
|
||||
|
||||
static struct pci_device_id supported[] = {
|
||||
{ PCI_VENDOR_ID_FUJITSU, PCI_DEVICE_ID_CORAL_P },
|
||||
{ PCI_VENDOR_ID_FUJITSU, PCI_DEVICE_ID_CORAL_PA },
|
||||
{ }
|
||||
};
|
||||
|
||||
/* Internal clock frequency divider table, index is mode number */
|
||||
unsigned int fr_div[] = { 0x00000f00, 0x00000900, 0x00000500 };
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_VIDEO_CORALP)
|
||||
#define rd_io in32r
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||||
#define wr_io out32r
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#else
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#define rd_io(addr) in_be32((volatile unsigned *)(addr))
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||||
#define wr_io(addr, val) out_be32((volatile unsigned *)(addr), (val))
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#endif
|
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|
||||
#define HOST_RD_REG(off) rd_io((dev->frameAdrs + GC_HOST_BASE + (off)))
|
||||
#define HOST_WR_REG(off, val) wr_io((dev->frameAdrs + GC_HOST_BASE + (off)), \
|
||||
(val))
|
||||
#define DISP_RD_REG(off) rd_io((dev->frameAdrs + GC_DISP_BASE + (off)))
|
||||
#define DISP_WR_REG(off, val) wr_io((dev->frameAdrs + GC_DISP_BASE + (off)), \
|
||||
(val))
|
||||
#define DE_RD_REG(off) rd_io((dev->dprBase + (off)))
|
||||
#define DE_WR_REG(off, val) wr_io((dev->dprBase + (off)), (val))
|
||||
|
||||
#if defined(CONFIG_VIDEO_CORALP)
|
||||
#define DE_WR_FIFO(val) wr_io((dev->dprBase + (GC_GEO_FIFO)), (val))
|
||||
#else
|
||||
#define DE_WR_FIFO(val) wr_io((dev->dprBase + (GC_FIFO)), (val))
|
||||
#endif
|
||||
|
||||
#define L0PAL_WR_REG(idx, val) wr_io((dev->frameAdrs + \
|
||||
(GC_DISP_BASE | GC_L0PAL0) + \
|
||||
((idx) << 2)), (val))
|
||||
|
||||
#if defined(CONFIG_VIDEO_MB862xx_ACCEL)
|
||||
static void gdc_sw_reset (void)
|
||||
{
|
||||
GraphicDevice *dev = &mb862xx;
|
||||
|
||||
HOST_WR_REG (GC_SRST, 0x1);
|
||||
udelay(500);
|
||||
video_hw_init ();
|
||||
}
|
||||
|
||||
|
||||
static void de_wait (void)
|
||||
{
|
||||
GraphicDevice *dev = &mb862xx;
|
||||
int lc = 0x10000;
|
||||
|
||||
/*
|
||||
* Sync with software writes to framebuffer,
|
||||
* try to reset if engine locked
|
||||
*/
|
||||
while (DE_RD_REG (GC_CTR) & 0x00000131)
|
||||
if (lc-- < 0) {
|
||||
gdc_sw_reset ();
|
||||
puts ("gdc reset done after drawing engine lock.\n");
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static void de_wait_slots (int slots)
|
||||
{
|
||||
GraphicDevice *dev = &mb862xx;
|
||||
int lc = 0x10000;
|
||||
|
||||
/* Wait for free fifo slots */
|
||||
while (DE_RD_REG (GC_IFCNT) < slots)
|
||||
if (lc-- < 0) {
|
||||
gdc_sw_reset ();
|
||||
puts ("gdc reset done after drawing engine lock.\n");
|
||||
break;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#if !defined(CONFIG_VIDEO_CORALP)
|
||||
static void board_disp_init (void)
|
||||
{
|
||||
GraphicDevice *dev = &mb862xx;
|
||||
const gdc_regs *regs = board_get_regs ();
|
||||
|
||||
while (regs->index) {
|
||||
DISP_WR_REG (regs->index, regs->value);
|
||||
regs++;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Init drawing engine if accel enabled.
|
||||
* Also clears visible framebuffer.
|
||||
*/
|
||||
static void de_init (void)
|
||||
{
|
||||
GraphicDevice *dev = &mb862xx;
|
||||
#if defined(CONFIG_VIDEO_MB862xx_ACCEL)
|
||||
int cf = (dev->gdfBytesPP == 1) ? 0x0000 : 0x8000;
|
||||
|
||||
dev->dprBase = dev->frameAdrs + GC_DRAW_BASE;
|
||||
|
||||
/* Setup mode and fbbase, xres, fg, bg */
|
||||
de_wait_slots (2);
|
||||
DE_WR_FIFO (0xf1010108);
|
||||
DE_WR_FIFO (cf | 0x0300);
|
||||
DE_WR_REG (GC_FBR, 0x0);
|
||||
DE_WR_REG (GC_XRES, dev->winSizeX);
|
||||
DE_WR_REG (GC_FC, 0x0);
|
||||
DE_WR_REG (GC_BC, 0x0);
|
||||
/* Reset clipping */
|
||||
DE_WR_REG (GC_CXMIN, 0x0);
|
||||
DE_WR_REG (GC_CXMAX, dev->winSizeX);
|
||||
DE_WR_REG (GC_CYMIN, 0x0);
|
||||
DE_WR_REG (GC_CYMAX, dev->winSizeY);
|
||||
|
||||
/* Clear framebuffer using drawing engine */
|
||||
de_wait_slots (3);
|
||||
DE_WR_FIFO (0x09410000);
|
||||
DE_WR_FIFO (0x00000000);
|
||||
DE_WR_FIFO (dev->winSizeY << 16 | dev->winSizeX);
|
||||
/* sync with SW access to framebuffer */
|
||||
de_wait ();
|
||||
#else
|
||||
unsigned int i, *p;
|
||||
|
||||
i = dev->winSizeX * dev->winSizeY;
|
||||
p = (unsigned int *)dev->frameAdrs;
|
||||
while (i--)
|
||||
*p++ = 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
#if defined(CONFIG_VIDEO_CORALP)
|
||||
/* use CCF and MMR parameters for Coral-P Eval. Board as default */
|
||||
#ifndef CONFIG_SYS_MB862xx_CCF
|
||||
#define CONFIG_SYS_MB862xx_CCF 0x00090000
|
||||
#endif
|
||||
#ifndef CONFIG_SYS_MB862xx_MMR
|
||||
#define CONFIG_SYS_MB862xx_MMR 0x11d7fa13
|
||||
#endif
|
||||
|
||||
unsigned int pci_video_init (void)
|
||||
{
|
||||
GraphicDevice *dev = &mb862xx;
|
||||
pci_dev_t devbusfn;
|
||||
u16 device;
|
||||
|
||||
if ((devbusfn = pci_find_devices (supported, 0)) < 0) {
|
||||
puts("controller not present\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* PCI setup */
|
||||
pci_write_config_dword (devbusfn, PCI_COMMAND,
|
||||
(PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
|
||||
pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, &dev->frameAdrs);
|
||||
dev->frameAdrs = pci_mem_to_phys (devbusfn, dev->frameAdrs);
|
||||
|
||||
if (dev->frameAdrs == 0) {
|
||||
puts ("PCI config: failed to get base address\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
dev->pciBase = dev->frameAdrs;
|
||||
|
||||
puts("Coral-");
|
||||
|
||||
pci_read_config_word(devbusfn, PCI_DEVICE_ID, &device);
|
||||
switch (device) {
|
||||
case PCI_DEVICE_ID_CORAL_P:
|
||||
puts("P\n");
|
||||
break;
|
||||
case PCI_DEVICE_ID_CORAL_PA:
|
||||
puts("PA\n");
|
||||
break;
|
||||
default:
|
||||
puts("Unknown\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Setup clocks and memory mode for Coral-P(A) */
|
||||
HOST_WR_REG(GC_CCF, CONFIG_SYS_MB862xx_CCF);
|
||||
udelay(200);
|
||||
HOST_WR_REG(GC_MMR, CONFIG_SYS_MB862xx_MMR);
|
||||
udelay(100);
|
||||
return dev->frameAdrs;
|
||||
}
|
||||
|
||||
unsigned int card_init (void)
|
||||
{
|
||||
GraphicDevice *dev = &mb862xx;
|
||||
unsigned int cf, videomode, div = 0;
|
||||
unsigned long t1, hsync, vsync;
|
||||
char *penv;
|
||||
int tmp, i, bpp;
|
||||
struct ctfb_res_modes *res_mode;
|
||||
struct ctfb_res_modes var_mode;
|
||||
|
||||
memset (dev, 0, sizeof (GraphicDevice));
|
||||
|
||||
if (!pci_video_init ())
|
||||
return 0;
|
||||
|
||||
tmp = 0;
|
||||
videomode = 0x310;
|
||||
/* get video mode via environment */
|
||||
penv = env_get("videomode");
|
||||
if (penv) {
|
||||
/* decide if it is a string */
|
||||
if (penv[0] <= '9') {
|
||||
videomode = (int) simple_strtoul (penv, NULL, 16);
|
||||
tmp = 1;
|
||||
}
|
||||
} else {
|
||||
tmp = 1;
|
||||
}
|
||||
|
||||
if (tmp) {
|
||||
/* parameter are vesa modes, search params */
|
||||
for (i = 0; i < VESA_MODES_COUNT; i++) {
|
||||
if (vesa_modes[i].vesanr == videomode)
|
||||
break;
|
||||
}
|
||||
if (i == VESA_MODES_COUNT) {
|
||||
printf ("\tno VESA Mode found, fallback to mode 0x%x\n",
|
||||
videomode);
|
||||
i = 0;
|
||||
}
|
||||
res_mode = (struct ctfb_res_modes *)
|
||||
&res_mode_init[vesa_modes[i].resindex];
|
||||
if (vesa_modes[i].resindex > 2) {
|
||||
puts ("\tUnsupported resolution, using default\n");
|
||||
bpp = vesa_modes[1].bits_per_pixel;
|
||||
div = fr_div[1];
|
||||
}
|
||||
bpp = vesa_modes[i].bits_per_pixel;
|
||||
div = fr_div[vesa_modes[i].resindex];
|
||||
} else {
|
||||
res_mode = (struct ctfb_res_modes *) &var_mode;
|
||||
bpp = video_get_params (res_mode, penv);
|
||||
}
|
||||
|
||||
/* calculate hsync and vsync freq (info only) */
|
||||
t1 = (res_mode->left_margin + res_mode->xres +
|
||||
res_mode->right_margin + res_mode->hsync_len) / 8;
|
||||
t1 *= 8;
|
||||
t1 *= res_mode->pixclock;
|
||||
t1 /= 1000;
|
||||
hsync = 1000000000L / t1;
|
||||
t1 *= (res_mode->upper_margin + res_mode->yres +
|
||||
res_mode->lower_margin + res_mode->vsync_len);
|
||||
t1 /= 1000;
|
||||
vsync = 1000000000L / t1;
|
||||
|
||||
/* fill in Graphic device struct */
|
||||
sprintf (dev->modeIdent, "%dx%dx%d %ldkHz %ldHz", res_mode->xres,
|
||||
res_mode->yres, bpp, (hsync / 1000), (vsync / 1000));
|
||||
printf ("\t%s\n", dev->modeIdent);
|
||||
dev->winSizeX = res_mode->xres;
|
||||
dev->winSizeY = res_mode->yres;
|
||||
dev->memSize = VIDEO_MEM_SIZE;
|
||||
|
||||
switch (bpp) {
|
||||
case 8:
|
||||
dev->gdfIndex = GDF__8BIT_INDEX;
|
||||
dev->gdfBytesPP = 1;
|
||||
break;
|
||||
case 15:
|
||||
case 16:
|
||||
dev->gdfIndex = GDF_15BIT_555RGB;
|
||||
dev->gdfBytesPP = 2;
|
||||
break;
|
||||
default:
|
||||
printf ("\t%d bpp configured, but only 8,15 and 16 supported\n",
|
||||
bpp);
|
||||
puts ("\tfallback to 15bpp\n");
|
||||
dev->gdfIndex = GDF_15BIT_555RGB;
|
||||
dev->gdfBytesPP = 2;
|
||||
}
|
||||
|
||||
/* Setup dot clock (internal pll, division rate) */
|
||||
DISP_WR_REG (GC_DCM1, div);
|
||||
/* L0 init */
|
||||
cf = (dev->gdfBytesPP == 1) ? 0x00000000 : 0x80000000;
|
||||
DISP_WR_REG (GC_L0M, ((dev->winSizeX * dev->gdfBytesPP) / 64) << 16 |
|
||||
(dev->winSizeY - 1) | cf);
|
||||
DISP_WR_REG (GC_L0OA0, 0x0);
|
||||
DISP_WR_REG (GC_L0DA0, 0x0);
|
||||
DISP_WR_REG (GC_L0DY_L0DX, 0x0);
|
||||
DISP_WR_REG (GC_L0EM, 0x0);
|
||||
DISP_WR_REG (GC_L0WY_L0WX, 0x0);
|
||||
DISP_WR_REG (GC_L0WH_L0WW, (dev->winSizeY - 1) << 16 | dev->winSizeX);
|
||||
|
||||
/* Display timing init */
|
||||
DISP_WR_REG (GC_HTP_A, (dev->winSizeX +
|
||||
res_mode->left_margin +
|
||||
res_mode->right_margin +
|
||||
res_mode->hsync_len - 1) << 16);
|
||||
DISP_WR_REG (GC_HDB_HDP_A, (dev->winSizeX - 1) << 16 |
|
||||
(dev->winSizeX - 1));
|
||||
DISP_WR_REG (GC_VSW_HSW_HSP_A, (res_mode->vsync_len - 1) << 24 |
|
||||
(res_mode->hsync_len - 1) << 16 |
|
||||
(dev->winSizeX +
|
||||
res_mode->right_margin - 1));
|
||||
DISP_WR_REG (GC_VTR_A, (dev->winSizeY + res_mode->lower_margin +
|
||||
res_mode->upper_margin +
|
||||
res_mode->vsync_len - 1) << 16);
|
||||
DISP_WR_REG (GC_VDP_VSP_A, (dev->winSizeY-1) << 16 |
|
||||
(dev->winSizeY +
|
||||
res_mode->lower_margin - 1));
|
||||
DISP_WR_REG (GC_WY_WX, 0x0);
|
||||
DISP_WR_REG (GC_WH_WW, dev->winSizeY << 16 | dev->winSizeX);
|
||||
/* Display enable, L0 layer */
|
||||
DISP_WR_REG (GC_DCM1, 0x80010000 | div);
|
||||
|
||||
return dev->frameAdrs;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#if !defined(CONFIG_VIDEO_CORALP)
|
||||
int mb862xx_probe(unsigned int addr)
|
||||
{
|
||||
GraphicDevice *dev = &mb862xx;
|
||||
unsigned int reg;
|
||||
|
||||
dev->frameAdrs = addr;
|
||||
dev->dprBase = dev->frameAdrs + GC_DRAW_BASE;
|
||||
|
||||
/* Try to access GDC ID/Revision registers */
|
||||
reg = HOST_RD_REG (GC_CID);
|
||||
reg = HOST_RD_REG (GC_CID);
|
||||
if (reg == 0x303) {
|
||||
reg = DE_RD_REG(GC_REV);
|
||||
reg = DE_RD_REG(GC_REV);
|
||||
if ((reg & ~0xff) == 0x20050100)
|
||||
return MB862XX_TYPE_LIME;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
void *video_hw_init (void)
|
||||
{
|
||||
GraphicDevice *dev = &mb862xx;
|
||||
|
||||
puts ("Video: Fujitsu ");
|
||||
|
||||
memset (dev, 0, sizeof (GraphicDevice));
|
||||
|
||||
#if defined(CONFIG_VIDEO_CORALP)
|
||||
if (card_init () == 0)
|
||||
return NULL;
|
||||
#else
|
||||
/*
|
||||
* Preliminary init of the onboard graphic controller,
|
||||
* retrieve base address
|
||||
*/
|
||||
if ((dev->frameAdrs = board_video_init ()) == 0) {
|
||||
puts ("Controller not found!\n");
|
||||
return NULL;
|
||||
} else {
|
||||
puts ("Lime\n");
|
||||
|
||||
/* Set Change of Clock Frequency Register */
|
||||
HOST_WR_REG (GC_CCF, CONFIG_SYS_MB862xx_CCF);
|
||||
/* Delay required */
|
||||
udelay(300);
|
||||
/* Set Memory I/F Mode Register) */
|
||||
HOST_WR_REG (GC_MMR, CONFIG_SYS_MB862xx_MMR);
|
||||
}
|
||||
#endif
|
||||
|
||||
de_init ();
|
||||
|
||||
#if !defined(CONFIG_VIDEO_CORALP)
|
||||
board_disp_init ();
|
||||
#endif
|
||||
|
||||
#if (defined(CONFIG_LWMON5) || \
|
||||
defined(CONFIG_SOCRATES)) && !(CONFIG_POST & CONFIG_SYS_POST_SYSMON)
|
||||
/* Lamp on */
|
||||
board_backlight_switch (1);
|
||||
#endif
|
||||
|
||||
return dev;
|
||||
}
|
||||
|
||||
/*
|
||||
* Set a RGB color in the LUT
|
||||
*/
|
||||
void video_set_lut (unsigned int index, unsigned char r,
|
||||
unsigned char g, unsigned char b)
|
||||
{
|
||||
GraphicDevice *dev = &mb862xx;
|
||||
|
||||
L0PAL_WR_REG (index, (r << 16) | (g << 8) | (b));
|
||||
}
|
||||
|
||||
#if defined(CONFIG_VIDEO_MB862xx_ACCEL)
|
||||
/*
|
||||
* Drawing engine Fill and BitBlt screen region
|
||||
*/
|
||||
void video_hw_rectfill (unsigned int bpp, unsigned int dst_x,
|
||||
unsigned int dst_y, unsigned int dim_x,
|
||||
unsigned int dim_y, unsigned int color)
|
||||
{
|
||||
GraphicDevice *dev = &mb862xx;
|
||||
|
||||
de_wait_slots (3);
|
||||
DE_WR_REG (GC_FC, color);
|
||||
DE_WR_FIFO (0x09410000);
|
||||
DE_WR_FIFO ((dst_y << 16) | dst_x);
|
||||
DE_WR_FIFO ((dim_y << 16) | dim_x);
|
||||
de_wait ();
|
||||
}
|
||||
|
||||
void video_hw_bitblt (unsigned int bpp, unsigned int src_x,
|
||||
unsigned int src_y, unsigned int dst_x,
|
||||
unsigned int dst_y, unsigned int width,
|
||||
unsigned int height)
|
||||
{
|
||||
GraphicDevice *dev = &mb862xx;
|
||||
unsigned int ctrl = 0x0d000000L;
|
||||
|
||||
if (src_x >= dst_x && src_y >= dst_y)
|
||||
ctrl |= 0x00440000L;
|
||||
else if (src_x >= dst_x && src_y <= dst_y)
|
||||
ctrl |= 0x00460000L;
|
||||
else if (src_x <= dst_x && src_y >= dst_y)
|
||||
ctrl |= 0x00450000L;
|
||||
else
|
||||
ctrl |= 0x00470000L;
|
||||
|
||||
de_wait_slots (4);
|
||||
DE_WR_FIFO (ctrl);
|
||||
DE_WR_FIFO ((src_y << 16) | src_x);
|
||||
DE_WR_FIFO ((dst_y << 16) | dst_x);
|
||||
DE_WR_FIFO ((height << 16) | width);
|
||||
de_wait (); /* sync */
|
||||
}
|
||||
#endif
|
||||
|
|
@ -15,7 +15,7 @@
|
|||
#include <malloc.h>
|
||||
#include <linux/compat.h>
|
||||
#include <linux/err.h>
|
||||
#include <video.h> /* For struct video_uc_platdata */
|
||||
#include <video.h> /* For struct video_uc_plat */
|
||||
#include <video_fb.h>
|
||||
#include <lcd.h>
|
||||
#include <asm/global_data.h>
|
||||
|
|
|
|||
|
|
@ -108,6 +108,8 @@ static const struct udevice_id simple_panel_ids[] = {
|
|||
{ .compatible = "auo,b133htn01" },
|
||||
{ .compatible = "boe,nv140fhmn49" },
|
||||
{ .compatible = "lg,lb070wv8" },
|
||||
{ .compatible = "sharp,lq123p1jx31" },
|
||||
{ .compatible = "boe,nv101wxmn51" },
|
||||
{ }
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -1,101 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2007
|
||||
* DENX Software Engineering, Anatolij Gustschin, agust@denx.de
|
||||
*/
|
||||
|
||||
/*
|
||||
* mb862xx.h - Graphic interface for Fujitsu CoralP/Lime
|
||||
*/
|
||||
|
||||
#ifndef _MB862XX_H_
|
||||
#define _MB862XX_H_
|
||||
|
||||
#define PCI_VENDOR_ID_FUJITSU 0x10CF
|
||||
#define PCI_DEVICE_ID_CORAL_P 0x2019
|
||||
#define PCI_DEVICE_ID_CORAL_PA 0x201E
|
||||
|
||||
#define MB862XX_TYPE_LIME 0x1
|
||||
|
||||
#define GC_HOST_BASE 0x01fc0000
|
||||
#define GC_DISP_BASE 0x01fd0000
|
||||
#define GC_DRAW_BASE 0x01ff0000
|
||||
|
||||
/* Host interface registers */
|
||||
#define GC_SRST 0x0000002c
|
||||
#define GC_CCF 0x00000038
|
||||
#define GC_CID 0x000000f0
|
||||
#define GC_MMR 0x0000fffc
|
||||
|
||||
/*
|
||||
* Display Controller registers
|
||||
* _A means the offset is aligned, we use these for boards
|
||||
* with 8-/16-bit GDC access not working or buggy.
|
||||
*/
|
||||
#define GC_DCM0 0x00000000
|
||||
#define GC_HTP_A 0x00000004
|
||||
#define GC_HTP 0x00000006
|
||||
#define GC_HDB_HDP_A 0x00000008
|
||||
#define GC_HDP 0x00000008
|
||||
#define GC_HDB 0x0000000a
|
||||
#define GC_VSW_HSW_HSP_A 0x0000000c
|
||||
#define GC_HSP 0x0000000c
|
||||
#define GC_HSW 0x0000000e
|
||||
#define GC_VSW 0x0000000f
|
||||
#define GC_VTR_A 0x00000010
|
||||
#define GC_VTR 0x00000012
|
||||
#define GC_VDP_VSP_A 0x00000014
|
||||
#define GC_VSP 0x00000014
|
||||
#define GC_VDP 0x00000016
|
||||
#define GC_WY_WX 0x00000018
|
||||
#define GC_WH_WW 0x0000001c
|
||||
#define GC_L0M 0x00000020
|
||||
#define GC_L0OA0 0x00000024
|
||||
#define GC_L0DA0 0x00000028
|
||||
#define GC_L0DY_L0DX 0x0000002c
|
||||
#define GC_L2M 0x00000040
|
||||
#define GC_L2OA0 0x00000044
|
||||
#define GC_L2DA0 0x00000048
|
||||
#define GC_L2OA1 0x0000004c
|
||||
#define GC_L2DA1 0x00000050
|
||||
#define GC_L2DX 0x00000054
|
||||
#define GC_L2DY 0x00000056
|
||||
#define GC_DCM1 0x00000100
|
||||
#define GC_DCM2 0x00000104
|
||||
#define GC_DCM3 0x00000108
|
||||
#define GC_L0EM 0x00000110
|
||||
#define GC_L0WY_L0WX 0x00000114
|
||||
#define GC_L0WH_L0WW 0x00000118
|
||||
#define GC_L2EM 0x00000130
|
||||
#define GC_L2WX 0x00000134
|
||||
#define GC_L2WY 0x00000136
|
||||
#define GC_L2WW 0x00000138
|
||||
#define GC_L2WH 0x0000013a
|
||||
#define GC_L0PAL0 0x00000400
|
||||
|
||||
/* Drawing registers */
|
||||
#define GC_CTR 0x00000400
|
||||
#define GC_IFCNT 0x00000408
|
||||
#define GC_FBR 0x00000440
|
||||
#define GC_XRES 0x00000444
|
||||
#define GC_CXMIN 0x00000454
|
||||
#define GC_CXMAX 0x00000458
|
||||
#define GC_CYMIN 0x0000045c
|
||||
#define GC_CYMAX 0x00000460
|
||||
#define GC_FC 0x00000480
|
||||
#define GC_BC 0x00000484
|
||||
#define GC_FIFO 0x000004a0
|
||||
#define GC_REV 0x00008084
|
||||
#define GC_GEO_FIFO 0x00008400
|
||||
|
||||
typedef struct {
|
||||
unsigned int index;
|
||||
unsigned int value;
|
||||
} gdc_regs;
|
||||
|
||||
int mb862xx_probe(unsigned int addr);
|
||||
const gdc_regs *board_get_regs (void);
|
||||
unsigned int board_video_init (void);
|
||||
void board_backlight_switch(int);
|
||||
|
||||
#endif /* _MB862XX_H_ */
|
||||
|
|
@ -4004,8 +4004,6 @@ CONFIG_VIDEO_DA8XX
|
|||
CONFIG_VIDEO_FONT_4X6
|
||||
CONFIG_VIDEO_LCD_I2C_BUS
|
||||
CONFIG_VIDEO_LOGO
|
||||
CONFIG_VIDEO_MB862xx
|
||||
CONFIG_VIDEO_MB862xx_ACCEL
|
||||
CONFIG_VIDEO_MXS
|
||||
CONFIG_VIDEO_MXS_MODE_SYSTEM
|
||||
CONFIG_VIDEO_STD_TIMINGS
|
||||
|
|
|
|||
Loading…
Reference in a new issue