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Merge branch 'master' of git://www.denx.de/git/u-boot-imx

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This commit is contained in:
Tom Rini 2017-05-18 17:17:45 -04:00
commit a375ff8e14
54 changed files with 2991 additions and 2396 deletions
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6
arch/arm/cpu/armv7/mx6/Kconfig
View file

@ -173,8 +173,10 @@ config TARGET_MX6QARM2
config TARGET_MX6Q_ICORE
bool "Support Engicam i.Core"
select BOARD_LATE_INIT
select MX6QDL
select OF_CONTROL
select SPL_OF_LIBFDT
select DM
select DM_ETH
select DM_GPIO
@ -182,12 +184,14 @@ config TARGET_MX6Q_ICORE
select DM_MMC
select DM_THERMAL
select SUPPORT_SPL
select SPL_LOAD_FIT
config TARGET_MX6Q_ICORE_RQS
bool "Support Engicam i.Core RQS"
select BOARD_LATE_INIT
select MX6QDL
select OF_CONTROL
select SPL_OF_LIBFDT
select DM
select DM_ETH
select DM_GPIO
@ -195,6 +199,7 @@ config TARGET_MX6Q_ICORE_RQS
select DM_MMC
select DM_THERMAL
select SUPPORT_SPL
select SPL_LOAD_FIT
config TARGET_MX6QSABREAUTO
bool "mx6qsabreauto"
@ -256,6 +261,7 @@ config TARGET_MX6UL_14X14_EVK
config TARGET_MX6UL_GEAM
bool "Support Engicam GEAM6UL"
select BOARD_LATE_INIT
select MX6UL
select OF_CONTROL
select DM

3
arch/arm/dts/Makefile
View file

@ -346,7 +346,8 @@ dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \
imx6ul-isiot-nand.dtb \
imx6ul-opos6uldev.dtb
dtb-$(CONFIG_MX7) += imx7-colibri.dtb
dtb-$(CONFIG_MX7) += imx7-colibri.dtb \
imx7d-sdb.dtb
dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb

10
arch/arm/dts/imx7-colibri.dts
View file

@ -6,7 +6,7 @@
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "imx7.dtsi"
#include "imx7d.dtsi"
/ {
model = "Toradex Colibri iMX7S/D";
@ -83,15 +83,15 @@
&iomuxc_lpsr {
pinctrl_i2c1: i2c1-grp {
fsl,pins = <
MX7D_PAD_GPIO1_IO05__I2C1_SDA 0x4000007f
MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x4000007f
MX7D_PAD_LPSR_GPIO1_IO05__I2C1_SDA 0x4000007f
MX7D_PAD_LPSR_GPIO1_IO04__I2C1_SCL 0x4000007f
>;
};
pinctrl_i2c1_gpio: i2c1-gpio-grp {
fsl,pins = <
MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x4000007f
MX7D_PAD_GPIO1_IO04__GPIO1_IO4 0x4000007f
MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x4000007f
MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x4000007f
>;
};
};

194
arch/arm/dts/imx7.dtsi
View file

@ -1,194 +0,0 @@
/*
* Copyright 2016 Toradex AG
*
* SPDX-License-Identifier: GPL-2.0+ or X11
*/
#include "imx7d-pinfunc.h"
#include "skeleton.dtsi"
/ {
aliases {
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
gpio3 = &gpio4;
gpio4 = &gpio5;
gpio5 = &gpio6;
gpio6 = &gpio7;
i2c0 = &i2c1;
i2c1 = &i2c2;
i2c2 = &i2c3;
i2c3 = &i2c4;
serial0 = &uart1;
serial1 = &uart2;
serial2 = &uart3;
serial3 = &uart4;
serial4 = &uart5;
serial5 = &uart6;
serial6 = &uart7;
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges;
aips1: aips-bus@30000000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x30000000 0x400000>;
ranges;
gpio1: gpio@30200000 {
compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
reg = <0x30200000 0x10000>;
gpio-controller;
#gpio-cells = <2>;
};
gpio2: gpio@30210000 {
compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
reg = <0x30210000 0x10000>;
gpio-controller;
#gpio-cells = <2>;
};
gpio3: gpio@30220000 {
compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
reg = <0x30220000 0x10000>;
gpio-controller;
#gpio-cells = <2>;
};
gpio4: gpio@30230000 {
compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
reg = <0x30230000 0x10000>;
gpio-controller;
#gpio-cells = <2>;
};
gpio5: gpio@30240000 {
compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
reg = <0x30240000 0x10000>;
gpio-controller;
#gpio-cells = <2>;
};
gpio6: gpio@30250000 {
compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
reg = <0x30250000 0x10000>;
gpio-controller;
#gpio-cells = <2>;
};
gpio7: gpio@30260000 {
compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
reg = <0x30260000 0x10000>;
gpio-controller;
#gpio-cells = <2>;
};
iomuxc_lpsr: iomuxc-lpsr@302c0000 {
compatible = "fsl,imx7d-iomuxc-lpsr";
reg = <0x302c0000 0x10000>;
fsl,input-sel = <&iomuxc>;
};
iomuxc: iomuxc@30330000 {
compatible = "fsl,imx7d-iomuxc";
reg = <0x30330000 0x10000>;
};
};
aips3: aips-bus@30800000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x30800000 0x400000>;
ranges;
uart1: serial@30860000 {
compatible = "fsl,imx7d-uart",
"fsl,imx6q-uart";
reg = <0x30860000 0x10000>;
status = "disabled";
};
uart2: serial@30890000 {
compatible = "fsl,imx7d-uart",
"fsl,imx6q-uart";
reg = <0x30890000 0x10000>;
status = "disabled";
};
uart3: serial@30880000 {
compatible = "fsl,imx7d-uart",
"fsl,imx6q-uart";
reg = <0x30880000 0x10000>;
status = "disabled";
};
i2c1: i2c@30a20000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
reg = <0x30a20000 0x10000>;
status = "disabled";
};
i2c2: i2c@30a30000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
reg = <0x30a30000 0x10000>;
status = "disabled";
};
i2c3: i2c@30a40000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
reg = <0x30a40000 0x10000>;
status = "disabled";
};
i2c4: i2c@30a50000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
reg = <0x30a50000 0x10000>;
status = "disabled";
};
uart4: serial@30a60000 {
compatible = "fsl,imx7d-uart",
"fsl,imx6q-uart";
reg = <0x30a60000 0x10000>;
status = "disabled";
};
uart5: serial@30a70000 {
compatible = "fsl,imx7d-uart",
"fsl,imx6q-uart";
reg = <0x30a70000 0x10000>;
status = "disabled";
};
uart6: serial@30a80000 {
compatible = "fsl,imx7d-uart",
"fsl,imx6q-uart";
reg = <0x30a80000 0x10000>;
status = "disabled";
};
uart7: serial@30a90000 {
compatible = "fsl,imx7d-uart",
"fsl,imx6q-uart";
reg = <0x30a90000 0x10000>;
status = "disabled";
};
};
};
};

111
arch/arm/dts/imx7d-pinfunc.h
View file

@ -1,7 +1,10 @@
/*
* Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __DTS_IMX7D_PINFUNC_H
@ -12,57 +15,61 @@
* <mux_reg conf_reg input_reg mux_mode input_val>
*/
#define MX7D_PAD_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x0
#define MX7D_PAD_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0
#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0
#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0
#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0
#define MX7D_PAD_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x0
#define MX7D_PAD_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0
#define MX7D_PAD_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0
#define MX7D_PAD_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x0
#define MX7D_PAD_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x0000 0x4 0x0
#define MX7D_PAD_GPIO1_IO01__OBSERVE0_OUT 0x0004 0x0034 0x0000 0x6 0x0
#define MX7D_PAD_GPIO1_IO02__GPIO1_IO2 0x0008 0x0038 0x0000 0x0 0x0
#define MX7D_PAD_GPIO1_IO02__PWM2_OUT 0x0008 0x0038 0x0000 0x1 0x0
#define MX7D_PAD_GPIO1_IO02__CCM_ENET_REF_CLK1 0x0008 0x0038 0x0564 0x2 0x3
#define MX7D_PAD_GPIO1_IO02__SAI2_MCLK 0x0008 0x0038 0x0000 0x3 0x0
#define MX7D_PAD_GPIO1_IO02__CCM_CLKO1 0x0008 0x0038 0x0000 0x5 0x0
#define MX7D_PAD_GPIO1_IO02__OBSERVE1_OUT 0x0008 0x0038 0x0000 0x6 0x0
#define MX7D_PAD_GPIO1_IO02__USB_OTG1_ID 0x0008 0x0038 0x0734 0x7 0x3
#define MX7D_PAD_GPIO1_IO03__GPIO1_IO3 0x000C 0x003C 0x0000 0x0 0x0
#define MX7D_PAD_GPIO1_IO03__PWM3_OUT 0x000C 0x003C 0x0000 0x1 0x0
#define MX7D_PAD_GPIO1_IO03__CCM_ENET_REF_CLK2 0x000C 0x003C 0x0570 0x2 0x3
#define MX7D_PAD_GPIO1_IO03__SAI3_MCLK 0x000C 0x003C 0x0000 0x3 0x0
#define MX7D_PAD_GPIO1_IO03__CCM_CLKO2 0x000C 0x003C 0x0000 0x5 0x0
#define MX7D_PAD_GPIO1_IO03__OBSERVE2_OUT 0x000C 0x003C 0x0000 0x6 0x0
#define MX7D_PAD_GPIO1_IO03__USB_OTG2_ID 0x000C 0x003C 0x0730 0x7 0x3
#define MX7D_PAD_GPIO1_IO04__GPIO1_IO4 0x0010 0x0040 0x0000 0x0 0x0
#define MX7D_PAD_GPIO1_IO04__USB_OTG1_OC 0x0010 0x0040 0x072C 0x1 0x1
#define MX7D_PAD_GPIO1_IO04__FLEXTIMER1_CH4 0x0010 0x0040 0x0594 0x2 0x1
#define MX7D_PAD_GPIO1_IO04__UART5_CTS_B 0x0010 0x0040 0x0710 0x3 0x4
#define MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x0010 0x0040 0x05D4 0x4 0x2
#define MX7D_PAD_GPIO1_IO04__OBSERVE3_OUT 0x0010 0x0040 0x0000 0x6 0x0
#define MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x0014 0x0044 0x0000 0x0 0x0
#define MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR 0x0014 0x0044 0x0000 0x1 0x0
#define MX7D_PAD_GPIO1_IO05__FLEXTIMER1_CH5 0x0014 0x0044 0x0598 0x2 0x1
#define MX7D_PAD_GPIO1_IO05__UART5_RTS_B 0x0014 0x0044 0x0710 0x3 0x5
#define MX7D_PAD_GPIO1_IO05__I2C1_SDA 0x0014 0x0044 0x05D8 0x4 0x2
#define MX7D_PAD_GPIO1_IO05__OBSERVE4_OUT 0x0014 0x0044 0x0000 0x6 0x0
#define MX7D_PAD_GPIO1_IO06__GPIO1_IO6 0x0018 0x0048 0x0000 0x0 0x0
#define MX7D_PAD_GPIO1_IO06__USB_OTG2_OC 0x0018 0x0048 0x0728 0x1 0x1
#define MX7D_PAD_GPIO1_IO06__FLEXTIMER1_CH6 0x0018 0x0048 0x059C 0x2 0x1
#define MX7D_PAD_GPIO1_IO06__UART5_RX_DATA 0x0018 0x0048 0x0714 0x3 0x4
#define MX7D_PAD_GPIO1_IO06__I2C2_SCL 0x0018 0x0048 0x05DC 0x4 0x2
#define MX7D_PAD_GPIO1_IO06__CCM_WAIT 0x0018 0x0048 0x0000 0x5 0x0
#define MX7D_PAD_GPIO1_IO06__KPP_ROW4 0x0018 0x0048 0x0624 0x6 0x1
#define MX7D_PAD_GPIO1_IO07__GPIO1_IO7 0x001C 0x004C 0x0000 0x0 0x0
#define MX7D_PAD_GPIO1_IO07__USB_OTG2_PWR 0x001C 0x004C 0x0000 0x1 0x0
#define MX7D_PAD_GPIO1_IO07__FLEXTIMER1_CH7 0x001C 0x004C 0x05A0 0x2 0x1
#define MX7D_PAD_GPIO1_IO07__UART5_TX_DATA 0x001C 0x004C 0x0714 0x3 0x5
#define MX7D_PAD_GPIO1_IO07__I2C2_SDA 0x001C 0x004C 0x05E0 0x4 0x2
#define MX7D_PAD_GPIO1_IO07__CCM_STOP 0x001C 0x004C 0x0000 0x5 0x0
#define MX7D_PAD_GPIO1_IO07__KPP_COL4 0x001C 0x004C 0x0604 0x6 0x1
#define MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x0
#define MX7D_PAD_LPSR_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0
#define MX7D_PAD_LPSR_GPIO1_IO00__WDOD1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0
#define MX7D_PAD_LPSR_GPIO1_IO00__WDOD1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0
#define MX7D_PAD_LPSR_GPIO1_IO00__WDOD1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0
#define MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x0
#define MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0
#define MX7D_PAD_LPSR_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0
#define MX7D_PAD_LPSR_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x0
#define MX7D_PAD_LPSR_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x0000 0x4 0x0
#define MX7D_PAD_LPSR_GPIO1_IO01__OBSERVE0_OUT 0x0004 0x0034 0x0000 0x6 0x0
#define MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2 0x0008 0x0038 0x0000 0x0 0x0
#define MX7D_PAD_LPSR_GPIO1_IO02__PWM2_OUT 0x0008 0x0038 0x0000 0x1 0x0
#define MX7D_PAD_LPSR_GPIO1_IO02__CCM_ENET_REF_CLK1 0x0008 0x0038 0x0564 0x2 0x3
#define MX7D_PAD_LPSR_GPIO1_IO02__SAI2_MCLK 0x0008 0x0038 0x0000 0x3 0x0
#define MX7D_PAD_LPSR_GPIO1_IO02__CCM_CLKO1 0x0008 0x0038 0x0000 0x5 0x0
#define MX7D_PAD_LPSR_GPIO1_IO02__OBSERVE1_OUT 0x0008 0x0038 0x0000 0x6 0x0
#define MX7D_PAD_LPSR_GPIO1_IO02__USB_OTG1_ID 0x0008 0x0038 0x0734 0x7 0x3
#define MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3 0x000C 0x003C 0x0000 0x0 0x0
#define MX7D_PAD_LPSR_GPIO1_IO03__PWM3_OUT 0x000C 0x003C 0x0000 0x1 0x0
#define MX7D_PAD_LPSR_GPIO1_IO03__CCM_ENET_REF_CLK2 0x000C 0x003C 0x0570 0x2 0x3
#define MX7D_PAD_LPSR_GPIO1_IO03__SAI3_MCLK 0x000C 0x003C 0x0000 0x3 0x0
#define MX7D_PAD_LPSR_GPIO1_IO03__CCM_CLKO2 0x000C 0x003C 0x0000 0x5 0x0
#define MX7D_PAD_LPSR_GPIO1_IO03__OBSERVE2_OUT 0x000C 0x003C 0x0000 0x6 0x0
#define MX7D_PAD_LPSR_GPIO1_IO03__USB_OTG2_ID 0x000C 0x003C 0x0730 0x7 0x3
#define MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x0010 0x0040 0x0000 0x0 0x0
#define MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC 0x0010 0x0040 0x072C 0x1 0x1
#define MX7D_PAD_LPSR_GPIO1_IO04__FLEXTIMER1_CH4 0x0010 0x0040 0x0594 0x2 0x1
#define MX7D_PAD_LPSR_GPIO1_IO04__UART5_DCE_CTS 0x0010 0x0040 0x0000 0x3 0x0
#define MX7D_PAD_LPSR_GPIO1_IO04__UART5_DTE_RTS 0x0010 0x0040 0x0710 0x3 0x4
#define MX7D_PAD_LPSR_GPIO1_IO04__I2C1_SCL 0x0010 0x0040 0x05D4 0x4 0x2
#define MX7D_PAD_LPSR_GPIO1_IO04__OBSERVE3_OUT 0x0010 0x0040 0x0000 0x6 0x0
#define MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x0014 0x0044 0x0000 0x0 0x0
#define MX7D_PAD_LPSR_GPIO1_IO05__USB_OTG1_PWR 0x0014 0x0044 0x0000 0x1 0x0
#define MX7D_PAD_LPSR_GPIO1_IO05__FLEXTIMER1_CH5 0x0014 0x0044 0x0598 0x2 0x1
#define MX7D_PAD_LPSR_GPIO1_IO05__UART5_DCE_RTS 0x0014 0x0044 0x0710 0x3 0x5
#define MX7D_PAD_LPSR_GPIO1_IO05__UART5_DTE_CTS 0x0014 0x0044 0x0000 0x3 0x0
#define MX7D_PAD_LPSR_GPIO1_IO05__I2C1_SDA 0x0014 0x0044 0x05D8 0x4 0x2
#define MX7D_PAD_LPSR_GPIO1_IO05__OBSERVE4_OUT 0x0014 0x0044 0x0000 0x6 0x0
#define MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6 0x0018 0x0048 0x0000 0x0 0x0
#define MX7D_PAD_LPSR_GPIO1_IO06__USB_OTG2_OC 0x0018 0x0048 0x0728 0x1 0x1
#define MX7D_PAD_LPSR_GPIO1_IO06__FLEXTIMER1_CH6 0x0018 0x0048 0x059C 0x2 0x1
#define MX7D_PAD_LPSR_GPIO1_IO06__UART5_DCE_RX 0x0018 0x0048 0x0714 0x3 0x4
#define MX7D_PAD_LPSR_GPIO1_IO06__UART5_DTE_TX 0x0018 0x0048 0x0000 0x3 0x0
#define MX7D_PAD_LPSR_GPIO1_IO06__I2C2_SCL 0x0018 0x0048 0x05DC 0x4 0x2
#define MX7D_PAD_LPSR_GPIO1_IO06__CCM_WAIT 0x0018 0x0048 0x0000 0x5 0x0
#define MX7D_PAD_LPSR_GPIO1_IO06__KPP_ROW4 0x0018 0x0048 0x0624 0x6 0x1
#define MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x001C 0x004C 0x0000 0x0 0x0
#define MX7D_PAD_LPSR_GPIO1_IO07__USB_OTG2_PWR 0x001C 0x004C 0x0000 0x1 0x0
#define MX7D_PAD_LPSR_GPIO1_IO07__FLEXTIMER1_CH7 0x001C 0x004C 0x05A0 0x2 0x1
#define MX7D_PAD_LPSR_GPIO1_IO07__UART5_DCE_TX 0x001C 0x004C 0x0000 0x3 0x0
#define MX7D_PAD_LPSR_GPIO1_IO07__UART5_DTE_RX 0x001C 0x004C 0x0714 0x3 0x5
#define MX7D_PAD_LPSR_GPIO1_IO07__I2C2_SDA 0x001C 0x004C 0x05E0 0x4 0x2
#define MX7D_PAD_LPSR_GPIO1_IO07__CCM_STOP 0x001C 0x004C 0x0000 0x5 0x0
#define MX7D_PAD_LPSR_GPIO1_IO07__KPP_COL4 0x001C 0x004C 0x0604 0x6 0x1
#define MX7D_PAD_GPIO1_IO08__GPIO1_IO8 0x0014 0x026C 0x0000 0x0 0x0
#define MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x0014 0x026C 0x0000 0x1 0x0
#define MX7D_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x0014 0x026C 0x0000 0x2 0x0

309
arch/arm/dts/imx7d-sdb.dts Normal file
View file

@ -0,0 +1,309 @@
/*
* Copyright 2017 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;
#include "imx7d.dtsi"
/ {
model = "Freescale i.MX7 SabreSD Board";
compatible = "fsl,imx7d-sdb", "fsl,imx7d";
memory {
reg = <0x80000000 0x80000000>;
};
spi4 {
compatible = "spi-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1>;
status = "okay";
gpio-sck = <&gpio1 13 0>;
gpio-mosi = <&gpio1 9 0>;
cs-gpios = <&gpio1 12 0>;
num-chipselects = <1>;
#address-cells = <1>;
#size-cells = <0>;
gpio_spi: gpio_spi@0 {
compatible = "fairchild,74hc595";
gpio-controller;
#gpio-cells = <2>;
reg = <0>;
registers-number = <1>;
registers-default = /bits/ 8 <0x74>; /* Enable PERI_3V3, SENSOR_RST_B and HDMI_RST*/
spi-max-frequency = <100000>;
};
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_usb_otg1_vbus: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "usb_otg1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usb_otg2_vbus: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "usb_otg2_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_sd1_vmmc: regulator@3 {
compatible = "regulator-fixed";
regulator-name = "VDD_SD1";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
startup-delay-us = <200000>;
enable-active-high;
};
};
};
&iomuxc {
imx7d-sdb {
pinctrl_spi1: spi1grp {
fsl,pins = <
MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x59
MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x59
MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f
MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f
MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f
MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f
MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f
>;
};
pinctrl_usdhc1_gpio: usdhc1_gpiogrp {
fsl,pins = <
MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */
MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */
MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */
MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59 /* VSELECT */
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX7D_PAD_SD1_CMD__SD1_CMD 0x59
MX7D_PAD_SD1_CLK__SD1_CLK 0x19
MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX7D_PAD_SD2_CMD__SD2_CMD 0x59
MX7D_PAD_SD2_CLK__SD2_CLK 0x19
MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59
MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59
MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59
MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59
MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x19 /* WL_REG_ON */
MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x19 /* WL_HOST_WAKE */
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX7D_PAD_SD3_CMD__SD3_CMD 0x59
MX7D_PAD_SD3_CLK__SD3_CLK 0x19
MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19
>;
};
};
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
pmic: pfuze3000@08 {
compatible = "fsl,pfuze3000";
reg = <0x08>;
regulators {
sw1a_reg: sw1a {
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <6250>;
};
/* use sw1c_reg to align with pfuze100/pfuze200 */
sw1c_reg: sw1b {
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1475000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <6250>;
};
sw2_reg: sw2 {
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1850000>;
regulator-boot-on;
regulator-always-on;
};
sw3a_reg: sw3 {
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1650000>;
regulator-boot-on;
regulator-always-on;
};
swbst_reg: swbst {
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5150000>;
};
snvs_reg: vsnvs {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <3000000>;
regulator-boot-on;
regulator-always-on;
};
vref_reg: vrefddr {
regulator-boot-on;
regulator-always-on;
};
vgen1_reg: vldo1 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen2_reg: vldo2 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
regulator-always-on;
};
vgen3_reg: vccsd {
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen4_reg: v33 {
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen5_reg: vldo3 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen6_reg: vldo4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
};
&i2c4 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
status = "okay";
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
vmmc-supply = <&reg_sd1_vmmc>;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>;
non-removable;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
bus-width = <8>;
non-removable;
status = "okay";
};

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/*
* Copyright 2015 Freescale Semiconductor, Inc.
* Copyright 2016 Toradex AG
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "imx7s.dtsi"
/ {
cpus {
cpu0: cpu@0 {
operating-points = <
/* KHz uV */
996000 1075000
792000 975000
>;
clock-frequency = <996000000>;
};
cpu1: cpu@1 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <1>;
clock-frequency = <996000000>;
};
};
soc {
etm@3007d000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0x3007d000 0x1000>;
/*
* System will hang if added nosmp in kernel command line
* without arm,primecell-periphid because amba bus try to
* read id and core1 power off at this time.
*/
arm,primecell-periphid = <0xbb956>;
cpu = <&cpu1>;
clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
clock-names = "apb_pclk";
port {
etm1_out_port: endpoint {
remote-endpoint = <&ca_funnel_in_port1>;
};
};
};
};
};
&aips3 {
usbotg2: usb@30b20000 {
compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
reg = <0x30b20000 0x200>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_USB_CTRL_CLK>;
fsl,usbphy = <&usbphynop2>;
fsl,usbmisc = <&usbmisc2 0>;
phy-clkgate-delay-us = <400>;
status = "disabled";
};
usbmisc2: usbmisc@30b20200 {
#index-cells = <1>;
compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
reg = <0x30b20200 0x200>;
};
usbphynop2: usbphynop2 {
compatible = "usb-nop-xceiv";
clocks = <&clks IMX7D_USB_PHY2_CLK>;
clock-names = "main_clk";
};
fec2: ethernet@30bf0000 {
compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
reg = <0x30bf0000 0x10000>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
<&clks IMX7D_ENET_AXI_ROOT_CLK>,
<&clks IMX7D_ENET2_TIME_ROOT_CLK>,
<&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
<&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
clock-names = "ipg", "ahb", "ptp",
"enet_clk_ref", "enet_out";
fsl,num-tx-queues=<3>;
fsl,num-rx-queues=<3>;
status = "disabled";
};
};
&ca_funnel_ports {
port@1 {
reg = <1>;
ca_funnel_in_port1: endpoint {
slave-mode;
remote-endpoint = <&etm1_out_port>;
};
};
};

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/*
* Copyright 2015 Freescale Semiconductor, Inc.
* Copyright 2016 Toradex AG
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/clock/imx7d-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "imx7d-pinfunc.h"
/ {
#address-cells = <1>;
#size-cells = <1>;
/*
* The decompressor and also some bootloaders rely on a
* pre-existing /chosen node to be available to insert the
* command line and merge other ATAGS info.
* Also for U-Boot there must be a pre-existing /memory node.
*/
chosen {};
memory { device_type = "memory"; reg = <0 0>; };
aliases {
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
gpio3 = &gpio4;
gpio4 = &gpio5;
gpio5 = &gpio6;
gpio6 = &gpio7;
i2c0 = &i2c1;
i2c1 = &i2c2;
i2c2 = &i2c3;
i2c3 = &i2c4;
mmc0 = &usdhc1;
mmc1 = &usdhc2;
mmc2 = &usdhc3;
serial0 = &uart1;
serial1 = &uart2;
serial2 = &uart3;
serial3 = &uart4;
serial4 = &uart5;
serial5 = &uart6;
serial6 = &uart7;
spi0 = &ecspi1;
spi1 = &ecspi2;
spi2 = &ecspi3;
spi3 = &ecspi4;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0>;
clock-frequency = <792000000>;
clock-latency = <61036>; /* two CLK32 periods */
clocks = <&clks IMX7D_CLK_ARM>;
};
};
ckil: clock-cki {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "ckil";
};
osc: clock-osc {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
clock-output-names = "osc";
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&intc>;
ranges;
funnel@30041000 {
compatible = "arm,coresight-funnel", "arm,primecell";
reg = <0x30041000 0x1000>;
clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
clock-names = "apb_pclk";
ca_funnel_ports: ports {
#address-cells = <1>;
#size-cells = <0>;
/* funnel input ports */
port@0 {
reg = <0>;
ca_funnel_in_port0: endpoint {
slave-mode;
remote-endpoint = <&etm0_out_port>;
};
};
/* funnel output port */
port@2 {
reg = <0>;
ca_funnel_out_port0: endpoint {
remote-endpoint = <&hugo_funnel_in_port0>;
};
};
/* the other input ports are not connect to anything */
};
};
etm@3007c000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0x3007c000 0x1000>;
cpu = <&cpu0>;
clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
clock-names = "apb_pclk";
port {
etm0_out_port: endpoint {
remote-endpoint = <&ca_funnel_in_port0>;
};
};
};
funnel@30083000 {
compatible = "arm,coresight-funnel", "arm,primecell";
reg = <0x30083000 0x1000>;
clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
clock-names = "apb_pclk";
ports {
#address-cells = <1>;
#size-cells = <0>;
/* funnel input ports */
port@0 {
reg = <0>;
hugo_funnel_in_port0: endpoint {
slave-mode;
remote-endpoint = <&ca_funnel_out_port0>;
};
};
port@1 {
reg = <1>;
hugo_funnel_in_port1: endpoint {
slave-mode; /* M4 input */
};
};
port@2 {
reg = <0>;
hugo_funnel_out_port0: endpoint {
remote-endpoint = <&etf_in_port>;
};
};
/* the other input ports are not connect to anything */
};
};
etf@30084000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0x30084000 0x1000>;
clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
clock-names = "apb_pclk";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
etf_in_port: endpoint {
slave-mode;
remote-endpoint = <&hugo_funnel_out_port0>;
};
};
port@1 {
reg = <0>;
etf_out_port: endpoint {
remote-endpoint = <&replicator_in_port0>;
};
};
};
};
etr@30086000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0x30086000 0x1000>;
clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
clock-names = "apb_pclk";
port {
etr_in_port: endpoint {
slave-mode;
remote-endpoint = <&replicator_out_port1>;
};
};
};
tpiu@30087000 {
compatible = "arm,coresight-tpiu", "arm,primecell";
reg = <0x30087000 0x1000>;
clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
clock-names = "apb_pclk";
port {
tpiu_in_port: endpoint {
slave-mode;
remote-endpoint = <&replicator_out_port1>;
};
};
};
replicator {
/*
* non-configurable replicators don't show up on the
* AMBA bus. As such no need to add "arm,primecell"
*/
compatible = "arm,coresight-replicator";
ports {
#address-cells = <1>;
#size-cells = <0>;
/* replicator output ports */
port@0 {
reg = <0>;
replicator_out_port0: endpoint {
remote-endpoint = <&tpiu_in_port>;
};
};
port@1 {
reg = <1>;
replicator_out_port1: endpoint {
remote-endpoint = <&etr_in_port>;
};
};
/* replicator input port */
port@2 {
reg = <0>;
replicator_in_port0: endpoint {
slave-mode;
remote-endpoint = <&etf_out_port>;
};
};
};
};
intc: interrupt-controller@31001000 {
compatible = "arm,cortex-a7-gic";
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x31001000 0x1000>,
<0x31002000 0x2000>,
<0x31004000 0x2000>,
<0x31006000 0x2000>;
};
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
aips1: aips-bus@30000000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x30000000 0x400000>;
ranges;
gpio1: gpio@30200000 {
compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
reg = <0x30200000 0x10000>;
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* GPIO1_INT15_0 */
<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; /* GPIO1_INT31_16 */
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc_lpsr 0 0 8>, <&iomuxc 8 5 8>;
};
gpio2: gpio@30210000 {
compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
reg = <0x30210000 0x10000>;
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 13 32>;
};
gpio3: gpio@30220000 {
compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
reg = <0x30220000 0x10000>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 45 29>;
};
gpio4: gpio@30230000 {
compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
reg = <0x30230000 0x10000>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 74 24>;
};
gpio5: gpio@30240000 {
compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
reg = <0x30240000 0x10000>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 98 18>;
};
gpio6: gpio@30250000 {
compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
reg = <0x30250000 0x10000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 116 23>;
};
gpio7: gpio@30260000 {
compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
reg = <0x30260000 0x10000>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 139 16>;
};
wdog1: wdog@30280000 {
compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
reg = <0x30280000 0x10000>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_WDOG1_ROOT_CLK>;
};
wdog2: wdog@30290000 {
compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
reg = <0x30290000 0x10000>;
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_WDOG2_ROOT_CLK>;
status = "disabled";
};
wdog3: wdog@302a0000 {
compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
reg = <0x302a0000 0x10000>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_WDOG3_ROOT_CLK>;
status = "disabled";
};
wdog4: wdog@302b0000 {
compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
reg = <0x302b0000 0x10000>;
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_WDOG4_ROOT_CLK>;
status = "disabled";
};
iomuxc_lpsr: iomuxc-lpsr@302c0000 {
compatible = "fsl,imx7d-iomuxc-lpsr";
reg = <0x302c0000 0x10000>;
fsl,input-sel = <&iomuxc>;
};
gpt1: gpt@302d0000 {
compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
reg = <0x302d0000 0x10000>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_CLK_DUMMY>,
<&clks IMX7D_GPT1_ROOT_CLK>;
clock-names = "ipg", "per";
};
gpt2: gpt@302e0000 {
compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
reg = <0x302e0000 0x10000>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_CLK_DUMMY>,
<&clks IMX7D_GPT2_ROOT_CLK>;
clock-names = "ipg", "per";
status = "disabled";
};
gpt3: gpt@302f0000 {
compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
reg = <0x302f0000 0x10000>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_CLK_DUMMY>,
<&clks IMX7D_GPT3_ROOT_CLK>;
clock-names = "ipg", "per";
status = "disabled";
};
gpt4: gpt@30300000 {
compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
reg = <0x30300000 0x10000>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_CLK_DUMMY>,
<&clks IMX7D_GPT4_ROOT_CLK>;
clock-names = "ipg", "per";
status = "disabled";
};
iomuxc: iomuxc@30330000 {
compatible = "fsl,imx7d-iomuxc";
reg = <0x30330000 0x10000>;
};
gpr: iomuxc-gpr@30340000 {
compatible = "fsl,imx7d-iomuxc-gpr", "syscon";
reg = <0x30340000 0x10000>;
};
ocotp: ocotp-ctrl@30350000 {
compatible = "fsl,imx7d-ocotp", "syscon";
reg = <0x30350000 0x10000>;
clocks = <&clks IMX7D_OCOTP_CLK>;
};
anatop: anatop@30360000 {
compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop",
"syscon", "simple-bus";
reg = <0x30360000 0x10000>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
reg_1p0d: regulator-vdd1p0d {
compatible = "fsl,anatop-regulator";
regulator-name = "vdd1p0d";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1200000>;
anatop-reg-offset = <0x210>;
anatop-vol-bit-shift = <8>;
anatop-vol-bit-width = <5>;
anatop-min-bit-val = <8>;
anatop-min-voltage = <800000>;
anatop-max-voltage = <1200000>;
};
};
snvs: snvs@30370000 {
compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
reg = <0x30370000 0x10000>;
snvs_rtc: snvs-rtc-lp {
compatible = "fsl,sec-v4.0-mon-rtc-lp";
regmap = <&snvs>;
offset = <0x34>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
};
snvs_poweroff: snvs-poweroff {
compatible = "syscon-poweroff";
regmap = <&snvs>;
offset = <0x38>;
mask = <0x60>;
};
snvs_pwrkey: snvs-powerkey {
compatible = "fsl,sec-v4.0-pwrkey";
regmap = <&snvs>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
linux,keycode = <KEY_POWER>;
wakeup-source;
};
};
clks: ccm@30380000 {
compatible = "fsl,imx7d-ccm";
reg = <0x30380000 0x10000>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
#clock-cells = <1>;
clocks = <&ckil>, <&osc>;
clock-names = "ckil", "osc";
};
src: src@30390000 {
compatible = "fsl,imx7d-src", "fsl,imx51-src", "syscon";
reg = <0x30390000 0x10000>;
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
#reset-cells = <1>;
};
};
aips2: aips-bus@30400000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x30400000 0x400000>;
ranges;
adc1: adc@30610000 {
compatible = "fsl,imx7d-adc";
reg = <0x30610000 0x10000>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_ADC_ROOT_CLK>;
clock-names = "adc";
status = "disabled";
};
adc2: adc@30620000 {
compatible = "fsl,imx7d-adc";
reg = <0x30620000 0x10000>;
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_ADC_ROOT_CLK>;
clock-names = "adc";
status = "disabled";
};
ecspi4: ecspi@30630000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
reg = <0x30630000 0x10000>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_ECSPI4_ROOT_CLK>,
<&clks IMX7D_ECSPI4_ROOT_CLK>;
clock-names = "ipg", "per";
status = "disabled";
};
pwm1: pwm@30660000 {
compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
reg = <0x30660000 0x10000>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_PWM1_ROOT_CLK>,
<&clks IMX7D_PWM1_ROOT_CLK>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
status = "disabled";
};
pwm2: pwm@30670000 {
compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
reg = <0x30670000 0x10000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_PWM2_ROOT_CLK>,
<&clks IMX7D_PWM2_ROOT_CLK>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
status = "disabled";
};
pwm3: pwm@30680000 {
compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
reg = <0x30680000 0x10000>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_PWM3_ROOT_CLK>,
<&clks IMX7D_PWM3_ROOT_CLK>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
status = "disabled";
};
pwm4: pwm@30690000 {
compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
reg = <0x30690000 0x10000>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_PWM4_ROOT_CLK>,
<&clks IMX7D_PWM4_ROOT_CLK>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
status = "disabled";
};
lcdif: lcdif@30730000 {
compatible = "fsl,imx7d-lcdif", "fsl,imx28-lcdif";
reg = <0x30730000 0x10000>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>,
<&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>;
clock-names = "pix", "axi";
status = "disabled";
};
};
aips3: aips-bus@30800000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x30800000 0x400000>;
ranges;
ecspi1: ecspi@30820000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
reg = <0x30820000 0x10000>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>,
<&clks IMX7D_ECSPI1_ROOT_CLK>;
clock-names = "ipg", "per";
status = "disabled";
};
ecspi2: ecspi@30830000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
reg = <0x30830000 0x10000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>,
<&clks IMX7D_ECSPI2_ROOT_CLK>;
clock-names = "ipg", "per";
status = "disabled";
};
ecspi3: ecspi@30840000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
reg = <0x30840000 0x10000>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>,
<&clks IMX7D_ECSPI3_ROOT_CLK>;
clock-names = "ipg", "per";
status = "disabled";
};
uart1: serial@30860000 {
compatible = "fsl,imx7d-uart",
"fsl,imx6q-uart";
reg = <0x30860000 0x10000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_UART1_ROOT_CLK>,
<&clks IMX7D_UART1_ROOT_CLK>;
clock-names = "ipg", "per";
status = "disabled";
};
uart2: serial@30890000 {
compatible = "fsl,imx7d-uart",
"fsl,imx6q-uart";
reg = <0x30890000 0x10000>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_UART2_ROOT_CLK>,
<&clks IMX7D_UART2_ROOT_CLK>;
clock-names = "ipg", "per";
status = "disabled";
};
uart3: serial@30880000 {
compatible = "fsl,imx7d-uart",
"fsl,imx6q-uart";
reg = <0x30880000 0x10000>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_UART3_ROOT_CLK>,
<&clks IMX7D_UART3_ROOT_CLK>;
clock-names = "ipg", "per";
status = "disabled";
};
sai1: sai@308a0000 {
#sound-dai-cells = <0>;
compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
reg = <0x308a0000 0x10000>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_SAI1_IPG_CLK>,
<&clks IMX7D_SAI1_ROOT_CLK>,
<&clks IMX7D_CLK_DUMMY>,
<&clks IMX7D_CLK_DUMMY>;
clock-names = "bus", "mclk1", "mclk2", "mclk3";
dma-names = "rx", "tx";
dmas = <&sdma 8 24 0>, <&sdma 9 24 0>;
status = "disabled";
};
sai2: sai@308b0000 {
#sound-dai-cells = <0>;
compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
reg = <0x308b0000 0x10000>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_SAI2_IPG_CLK>,
<&clks IMX7D_SAI2_ROOT_CLK>,
<&clks IMX7D_CLK_DUMMY>,
<&clks IMX7D_CLK_DUMMY>;
clock-names = "bus", "mclk1", "mclk2", "mclk3";
dma-names = "rx", "tx";
dmas = <&sdma 10 24 0>, <&sdma 11 24 0>;
status = "disabled";
};
sai3: sai@308c0000 {
#sound-dai-cells = <0>;
compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
reg = <0x308c0000 0x10000>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_SAI3_IPG_CLK>,
<&clks IMX7D_SAI3_ROOT_CLK>,
<&clks IMX7D_CLK_DUMMY>,
<&clks IMX7D_CLK_DUMMY>;
clock-names = "bus", "mclk1", "mclk2", "mclk3";
dma-names = "rx", "tx";
dmas = <&sdma 12 24 0>, <&sdma 13 24 0>;
status = "disabled";
};
flexcan1: can@30a00000 {
compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
reg = <0x30a00000 0x10000>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_CLK_DUMMY>,
<&clks IMX7D_CAN1_ROOT_CLK>;
clock-names = "ipg", "per";
status = "disabled";
};
flexcan2: can@30a10000 {
compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
reg = <0x30a10000 0x10000>;
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_CLK_DUMMY>,
<&clks IMX7D_CAN2_ROOT_CLK>;
clock-names = "ipg", "per";
status = "disabled";
};
i2c1: i2c@30a20000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
reg = <0x30a20000 0x10000>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_I2C1_ROOT_CLK>;
status = "disabled";
};
i2c2: i2c@30a30000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
reg = <0x30a30000 0x10000>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_I2C2_ROOT_CLK>;
status = "disabled";
};
i2c3: i2c@30a40000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
reg = <0x30a40000 0x10000>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_I2C3_ROOT_CLK>;
status = "disabled";
};
i2c4: i2c@30a50000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
reg = <0x30a50000 0x10000>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_I2C4_ROOT_CLK>;
status = "disabled";
};
uart4: serial@30a60000 {
compatible = "fsl,imx7d-uart",
"fsl,imx6q-uart";
reg = <0x30a60000 0x10000>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_UART4_ROOT_CLK>,
<&clks IMX7D_UART4_ROOT_CLK>;
clock-names = "ipg", "per";
status = "disabled";
};
uart5: serial@30a70000 {
compatible = "fsl,imx7d-uart",
"fsl,imx6q-uart";
reg = <0x30a70000 0x10000>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_UART5_ROOT_CLK>,
<&clks IMX7D_UART5_ROOT_CLK>;
clock-names = "ipg", "per";
status = "disabled";
};
uart6: serial@30a80000 {
compatible = "fsl,imx7d-uart",
"fsl,imx6q-uart";
reg = <0x30a80000 0x10000>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_UART6_ROOT_CLK>,
<&clks IMX7D_UART6_ROOT_CLK>;
clock-names = "ipg", "per";
status = "disabled";
};
uart7: serial@30a90000 {
compatible = "fsl,imx7d-uart",
"fsl,imx6q-uart";
reg = <0x30a90000 0x10000>;
interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_UART7_ROOT_CLK>,
<&clks IMX7D_UART7_ROOT_CLK>;
clock-names = "ipg", "per";
status = "disabled";
};
usbotg1: usb@30b10000 {
compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
reg = <0x30b10000 0x200>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_USB_CTRL_CLK>;
fsl,usbphy = <&usbphynop1>;
fsl,usbmisc = <&usbmisc1 0>;
phy-clkgate-delay-us = <400>;
status = "disabled";
};
usbh: usb@30b30000 {
compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
reg = <0x30b30000 0x200>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_USB_CTRL_CLK>;
fsl,usbphy = <&usbphynop3>;
fsl,usbmisc = <&usbmisc3 0>;
phy_type = "hsic";
dr_mode = "host";
phy-clkgate-delay-us = <400>;
status = "disabled";
};
usbmisc1: usbmisc@30b10200 {
#index-cells = <1>;
compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
reg = <0x30b10200 0x200>;
};
usbmisc3: usbmisc@30b30200 {
#index-cells = <1>;
compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
reg = <0x30b30200 0x200>;
};
usbphynop1: usbphynop1 {
compatible = "usb-nop-xceiv";
clocks = <&clks IMX7D_USB_PHY1_CLK>;
clock-names = "main_clk";
};
usbphynop3: usbphynop3 {
compatible = "usb-nop-xceiv";
clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>;
clock-names = "main_clk";
};
usdhc1: usdhc@30b40000 {
compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
reg = <0x30b40000 0x10000>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_CLK_DUMMY>,
<&clks IMX7D_CLK_DUMMY>,
<&clks IMX7D_USDHC1_ROOT_CLK>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
};
usdhc2: usdhc@30b50000 {
compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
reg = <0x30b50000 0x10000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_CLK_DUMMY>,
<&clks IMX7D_CLK_DUMMY>,
<&clks IMX7D_USDHC2_ROOT_CLK>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
};
usdhc3: usdhc@30b60000 {
compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
reg = <0x30b60000 0x10000>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_CLK_DUMMY>,
<&clks IMX7D_CLK_DUMMY>,
<&clks IMX7D_USDHC3_ROOT_CLK>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
};
sdma: sdma@30bd0000 {
compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma";
reg = <0x30bd0000 0x10000>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_SDMA_CORE_CLK>,
<&clks IMX7D_AHB_CHANNEL_ROOT_CLK>;
clock-names = "ipg", "ahb";
#dma-cells = <3>;
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
};
fec1: ethernet@30be0000 {
compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
reg = <0x30be0000 0x10000>;
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
<&clks IMX7D_ENET_AXI_ROOT_CLK>,
<&clks IMX7D_ENET1_TIME_ROOT_CLK>,
<&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
<&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
clock-names = "ipg", "ahb", "ptp",
"enet_clk_ref", "enet_out";
fsl,num-tx-queues=<3>;
fsl,num-rx-queues=<3>;
status = "disabled";
};
};
};
};

2
arch/arm/imx-common/rdc-sema.c
View file

@ -94,7 +94,7 @@ int imx_rdc_sema_unlock(int per_id)
reg = readb(&imx_rdc_sema->gate[per_id % SEMA_GATES_NUM]);
if ((reg & RDC_SEMA_GATE_GTFSM_MASK) != RDC_SEMA_PROC_ID)
return 1; /*Not the semaphore owner */
return -EACCES; /*Not the semaphore owner */
writeb(0x0, &imx_rdc_sema->gate[per_id % SEMA_GATES_NUM]);

3
arch/arm/imx-common/timer.c
View file

@ -105,9 +105,6 @@ int timer_init(void)
#endif
__raw_writel(i, &cur_gpt->control);
gd->arch.tbl = __raw_readl(&cur_gpt->counter);
gd->arch.tbu = 0;
return 0;
}

6
arch/arm/include/asm/imx-common/iomux-v3.h
View file

@ -253,6 +253,12 @@ if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) { \
imx_iomux_v3_setup_pad(MX6Q_##def);
#define SETUP_IOMUX_PADS(x) \
imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x))
#elif defined(CONFIG_MX6UL)
#define IOMUX_PADS(x) MX6_##x
#define SETUP_IOMUX_PAD(def) \
imx_iomux_v3_setup_pad(MX6_##def);
#define SETUP_IOMUX_PADS(x) \
imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x))
#else
#define IOMUX_PADS(x) MX6DL_##x
#define SETUP_IOMUX_PAD(def) \

7
board/engicam/common/Makefile Normal file
View file

@ -0,0 +1,7 @@
# Copyright (C) 2016 Amarula Solutions B.V.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := board.o
obj-$(CONFIG_SPL_BUILD) += spl.o

82
board/engicam/common/board.c Normal file
View file

@ -0,0 +1,82 @@
/*
* Copyright (C) 2016 Amarula Solutions B.V.
* Copyright (C) 2016 Engicam S.r.l.
* Author: Jagan Teki <jagan@amarulasolutions.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <mmc.h>
#include <asm/arch/sys_proto.h>
#include "board.h"
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_ENV_IS_IN_MMC
static void mmc_late_init(void)
{
char cmd[32];
char mmcblk[32];
u32 dev_no = mmc_get_env_dev();
setenv_ulong("mmcdev", dev_no);
/* Set mmcblk env */
sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", dev_no);
setenv("mmcroot", mmcblk);
sprintf(cmd, "mmc dev %d", dev_no);
run_command(cmd, 0);
}
#endif
int board_late_init(void)
{
switch ((imx6_src_get_boot_mode() & IMX6_BMODE_MASK) >>
IMX6_BMODE_SHIFT) {
case IMX6_BMODE_SD:
case IMX6_BMODE_ESD:
case IMX6_BMODE_MMC:
case IMX6_BMODE_EMMC:
#ifdef CONFIG_ENV_IS_IN_MMC
mmc_late_init();
#endif
setenv("modeboot", "mmcboot");
break;
case IMX6_BMODE_NAND:
setenv("modeboot", "nandboot");
break;
default:
setenv("modeboot", "");
break;
}
setenv_fdt_file();
return 0;
}
int board_init(void)
{
/* Address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
#ifdef CONFIG_NAND_MXS
setup_gpmi_nand();
#endif
#ifdef CONFIG_VIDEO_IPUV3
setup_display();
#endif
return 0;
}
int dram_init(void)
{
gd->ram_size = imx_ddr_size();
return 0;
}

12
board/engicam/common/board.h Normal file
View file

@ -0,0 +1,12 @@
/*
* Copyright (C) 2016 Amarula Solutions B.V.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _BOARD_H_
#define _BOARD_H_
void setenv_fdt_file(void);
void setup_gpmi_nand(void);
void setup_display(void);
#endif /* _BOARD_H_ */

393
board/engicam/common/spl.c Normal file
View file

@ -0,0 +1,393 @@
/*
* Copyright (C) 2016 Amarula Solutions B.V.
* Copyright (C) 2016 Engicam S.r.l.
* Author: Jagan Teki <jagan@amarulasolutions.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <spl.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <linux/sizes.h>
#include <asm/arch/clock.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-ddr.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/video.h>
DECLARE_GLOBAL_DATA_PTR;
#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
static iomux_v3_cfg_t const uart_pads[] = {
#ifdef CONFIG_MX6QDL
IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
#elif CONFIG_MX6UL
IOMUX_PADS(PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL)),
IOMUX_PADS(PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL)),
#endif
};
#ifdef CONFIG_MX6QDL
/*
* Driving strength:
* 0x30 == 40 Ohm
* 0x28 == 48 Ohm
*/
#define IMX6DQ_DRIVE_STRENGTH 0x30
#define IMX6SDL_DRIVE_STRENGTH 0x28
/* configure MX6Q/DUAL mmdc DDR io registers */
static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
.dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH,
.dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH,
.dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH,
.dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH,
.dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH,
.dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH,
.dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH,
.dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH,
.dram_dqm0 = IMX6DQ_DRIVE_STRENGTH,
.dram_dqm1 = IMX6DQ_DRIVE_STRENGTH,
.dram_dqm2 = IMX6DQ_DRIVE_STRENGTH,
.dram_dqm3 = IMX6DQ_DRIVE_STRENGTH,
.dram_dqm4 = IMX6DQ_DRIVE_STRENGTH,
.dram_dqm5 = IMX6DQ_DRIVE_STRENGTH,
.dram_dqm6 = IMX6DQ_DRIVE_STRENGTH,
.dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
.dram_cas = IMX6DQ_DRIVE_STRENGTH,
.dram_ras = IMX6DQ_DRIVE_STRENGTH,
.dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH,
.dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH,
.dram_reset = IMX6DQ_DRIVE_STRENGTH,
.dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH,
.dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH,
.dram_sdba2 = 0x00000000,
.dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH,
.dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH,
};
/* configure MX6Q/DUAL mmdc GRP io registers */
static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
.grp_b0ds = IMX6DQ_DRIVE_STRENGTH,
.grp_b1ds = IMX6DQ_DRIVE_STRENGTH,
.grp_b2ds = IMX6DQ_DRIVE_STRENGTH,
.grp_b3ds = IMX6DQ_DRIVE_STRENGTH,
.grp_b4ds = IMX6DQ_DRIVE_STRENGTH,
.grp_b5ds = IMX6DQ_DRIVE_STRENGTH,
.grp_b6ds = IMX6DQ_DRIVE_STRENGTH,
.grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
.grp_addds = IMX6DQ_DRIVE_STRENGTH,
.grp_ddrmode_ctl = 0x00020000,
.grp_ddrpke = 0x00000000,
.grp_ddrmode = 0x00020000,
.grp_ctlds = IMX6DQ_DRIVE_STRENGTH,
.grp_ddr_type = 0x000c0000,
};
/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
.dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
.dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
.dram_cas = IMX6SDL_DRIVE_STRENGTH,
.dram_ras = IMX6SDL_DRIVE_STRENGTH,
.dram_reset = IMX6SDL_DRIVE_STRENGTH,
.dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
.dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
.dram_sdba2 = 0x00000000,
.dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
.dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
.dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
.dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
.dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
.dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
.dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
.dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
.dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
.dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
.dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
.dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
.dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
.dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
.dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
.dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
.dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
.dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
};
/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
.grp_ddr_type = 0x000c0000,
.grp_ddrmode_ctl = 0x00020000,
.grp_ddrpke = 0x00000000,
.grp_addds = IMX6SDL_DRIVE_STRENGTH,
.grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
.grp_ddrmode = 0x00020000,
.grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
.grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
.grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
.grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
.grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
.grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
.grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
.grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
};
/* mt41j256 */
static struct mx6_ddr3_cfg mt41j256 = {
.mem_speed = 1066,
.density = 2,
.width = 16,
.banks = 8,
.rowaddr = 13,
.coladdr = 10,
.pagesz = 2,
.trcd = 1375,
.trcmin = 4875,
.trasmin = 3500,
.SRT = 0,
};
static struct mx6_mmdc_calibration mx6dq_mmdc_calib = {
.p0_mpwldectrl0 = 0x000E0009,
.p0_mpwldectrl1 = 0x0018000E,
.p1_mpwldectrl0 = 0x00000007,
.p1_mpwldectrl1 = 0x00000000,
.p0_mpdgctrl0 = 0x43280334,
.p0_mpdgctrl1 = 0x031C0314,
.p1_mpdgctrl0 = 0x4318031C,
.p1_mpdgctrl1 = 0x030C0258,
.p0_mprddlctl = 0x3E343A40,
.p1_mprddlctl = 0x383C3844,
.p0_mpwrdlctl = 0x40404440,
.p1_mpwrdlctl = 0x4C3E4446,
};
/* DDR 64bit */
static struct mx6_ddr_sysinfo mem_q = {
.ddr_type = DDR_TYPE_DDR3,
.dsize = 2,
.cs1_mirror = 0,
/* config for full 4GB range so that get_mem_size() works */
.cs_density = 32,
.ncs = 1,
.bi_on = 1,
.rtt_nom = 2,
.rtt_wr = 2,
.ralat = 5,
.walat = 0,
.mif3_mode = 3,
.rst_to_cke = 0x23,
.sde_to_rst = 0x10,
};
static struct mx6_mmdc_calibration mx6dl_mmdc_calib = {
.p0_mpwldectrl0 = 0x001F0024,
.p0_mpwldectrl1 = 0x00110018,
.p1_mpwldectrl0 = 0x001F0024,
.p1_mpwldectrl1 = 0x00110018,
.p0_mpdgctrl0 = 0x4230022C,
.p0_mpdgctrl1 = 0x02180220,
.p1_mpdgctrl0 = 0x42440248,
.p1_mpdgctrl1 = 0x02300238,
.p0_mprddlctl = 0x44444A48,
.p1_mprddlctl = 0x46484A42,
.p0_mpwrdlctl = 0x38383234,
.p1_mpwrdlctl = 0x3C34362E,
};
/* DDR 64bit 1GB */
static struct mx6_ddr_sysinfo mem_dl = {
.dsize = 2,
.cs1_mirror = 0,
/* config for full 4GB range so that get_mem_size() works */
.cs_density = 32,
.ncs = 1,
.bi_on = 1,
.rtt_nom = 1,
.rtt_wr = 1,
.ralat = 5,
.walat = 0,
.mif3_mode = 3,
.rst_to_cke = 0x23,
.sde_to_rst = 0x10,
};
/* DDR 32bit 512MB */
static struct mx6_ddr_sysinfo mem_s = {
.dsize = 1,
.cs1_mirror = 0,
/* config for full 4GB range so that get_mem_size() works */
.cs_density = 32,
.ncs = 1,
.bi_on = 1,
.rtt_nom = 1,
.rtt_wr = 1,
.ralat = 5,
.walat = 0,
.mif3_mode = 3,
.rst_to_cke = 0x23,
.sde_to_rst = 0x10,
};
#endif /* CONFIG_MX6QDL */
#ifdef CONFIG_MX6UL
static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
.grp_addds = 0x00000030,
.grp_ddrmode_ctl = 0x00020000,
.grp_b0ds = 0x00000030,
.grp_ctlds = 0x00000030,
.grp_b1ds = 0x00000030,
.grp_ddrpke = 0x00000000,
.grp_ddrmode = 0x00020000,
.grp_ddr_type = 0x000c0000,
};
static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
.dram_dqm0 = 0x00000030,
.dram_dqm1 = 0x00000030,
.dram_ras = 0x00000030,
.dram_cas = 0x00000030,
.dram_odt0 = 0x00000030,
.dram_odt1 = 0x00000030,
.dram_sdba2 = 0x00000000,
.dram_sdclk_0 = 0x00000008,
.dram_sdqs0 = 0x00000038,
.dram_sdqs1 = 0x00000030,
.dram_reset = 0x00000030,
};
static struct mx6_mmdc_calibration mx6_mmcd_calib = {
.p0_mpwldectrl0 = 0x00070007,
.p0_mpdgctrl0 = 0x41490145,
.p0_mprddlctl = 0x40404546,
.p0_mpwrdlctl = 0x4040524D,
};
struct mx6_ddr_sysinfo ddr_sysinfo = {
.dsize = 0,
.cs_density = 20,
.ncs = 1,
.cs1_mirror = 0,
.rtt_wr = 2,
.rtt_nom = 1, /* RTT_Nom = RZQ/2 */
.walat = 1, /* Write additional latency */
.ralat = 5, /* Read additional latency */
.mif3_mode = 3, /* Command prediction working mode */
.bi_on = 1, /* Bank interleaving enabled */
.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
.ddr_type = DDR_TYPE_DDR3,
};
static struct mx6_ddr3_cfg mem_ddr = {
.mem_speed = 800,
.density = 4,
.width = 16,
.banks = 8,
#ifdef TARGET_MX6UL_ISIOT
.rowaddr = 15,
#else
.rowaddr = 13,
#endif
.coladdr = 10,
.pagesz = 2,
.trcd = 1375,
.trcmin = 4875,
.trasmin = 3500,
};
#endif /* CONFIG_MX6UL */
static void ccgr_init(void)
{
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
#ifdef CONFIG_MX6QDL
writel(0x00003F3F, &ccm->CCGR0);
writel(0x0030FC00, &ccm->CCGR1);
writel(0x000FC000, &ccm->CCGR2);
writel(0x3F300000, &ccm->CCGR3);
writel(0xFF00F300, &ccm->CCGR4);
writel(0x0F0000C3, &ccm->CCGR5);
writel(0x000003CC, &ccm->CCGR6);
#elif CONFIG_MX6UL
writel(0x00c03f3f, &ccm->CCGR0);
writel(0xfcffff00, &ccm->CCGR1);
writel(0x0cffffcc, &ccm->CCGR2);
writel(0x3f3c3030, &ccm->CCGR3);
writel(0xff00fffc, &ccm->CCGR4);
writel(0x033f30ff, &ccm->CCGR5);
writel(0x00c00fff, &ccm->CCGR6);
#endif
}
static void gpr_init(void)
{
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
/* enable AXI cache for VDOA/VPU/IPU */
writel(0xF00000CF, &iomux->gpr[4]);
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
writel(0x007F007F, &iomux->gpr[6]);
writel(0x007F007F, &iomux->gpr[7]);
}
static void spl_dram_init(void)
{
#ifdef CONFIG_MX6QDL
if (is_mx6solo()) {
mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
mx6_dram_cfg(&mem_s, &mx6dl_mmdc_calib, &mt41j256);
} else if (is_mx6dl()) {
mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41j256);
} else if (is_mx6dq()) {
mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
mx6_dram_cfg(&mem_q, &mx6dq_mmdc_calib, &mt41j256);
}
#elif CONFIG_MX6UL
mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
#endif
udelay(100);
}
void board_init_f(ulong dummy)
{
ccgr_init();
/* setup AIPS and disable watchdog */
arch_cpu_init();
gpr_init();
/* iomux */
SETUP_IOMUX_PADS(uart_pads);
/* setup GP timer */
timer_init();
/* UART clocks enabled and gd valid - init serial console */
preloader_console_init();
/* DDR initialization */
spl_dram_init();
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
/* load/boot image from boot device */
board_init_r(NULL, 0);
}

206
board/engicam/geam6ul/geam6ul.c
View file

@ -7,6 +7,7 @@
*/
#include <common.h>
#include <mmc.h>
#include <asm/io.h>
#include <asm/gpio.h>
@ -19,24 +20,10 @@
#include <asm/arch/sys_proto.h>
#include <asm/imx-common/iomux-v3.h>
#include "../common/board.h"
DECLARE_GLOBAL_DATA_PTR;
#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
static iomux_v3_cfg_t const uart1_pads[] = {
MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
int board_early_init_f(void)
{
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
return 0;
}
#ifdef CONFIG_NAND_MXS
#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
@ -45,29 +32,29 @@ int board_early_init_f(void)
#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
static iomux_v3_cfg_t const nand_pads[] = {
MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
IOMUX_PADS(PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
IOMUX_PADS(PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
IOMUX_PADS(PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
IOMUX_PADS(PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
IOMUX_PADS(PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
IOMUX_PADS(PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
IOMUX_PADS(PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
IOMUX_PADS(PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
IOMUX_PADS(PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
IOMUX_PADS(PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
IOMUX_PADS(PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
IOMUX_PADS(PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
IOMUX_PADS(PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
IOMUX_PADS(PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
IOMUX_PADS(PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
};
static void setup_gpmi_nand(void)
void setup_gpmi_nand(void)
{
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
/* config gpmi nand iomux */
imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
SETUP_IOMUX_PADS(nand_pads);
clrbits_le32(&mxc_ccm->CCGR4,
MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
@ -103,32 +90,13 @@ static void setup_gpmi_nand(void)
}
#endif /* CONFIG_NAND_MXS */
int board_init(void)
void setenv_fdt_file(void)
{
/* Address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
#ifdef CONFIG_NAND_MXS
setup_gpmi_nand();
#endif
return 0;
}
int dram_init(void)
{
gd->ram_size = imx_ddr_size();
return 0;
if (is_mx6ul())
setenv("fdt_file", "imx6ul-geam-kit.dtb");
}
#ifdef CONFIG_SPL_BUILD
#include <libfdt.h>
#include <spl.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/mx6-ddr.h>
/* MMC board initialization is needed till adding DM support in SPL */
#if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
#include <mmc.h>
@ -139,19 +107,19 @@ int dram_init(void)
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
static iomux_v3_cfg_t const usdhc1_pads[] = {
MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IOMUX_PADS(PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
/* VSELECT */
MX6_PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IOMUX_PADS(PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
/* CD */
MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
IOMUX_PADS(PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* RST_B */
MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
IOMUX_PADS(PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
};
#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 1)
@ -186,8 +154,7 @@ int board_mmc_init(bd_t *bis)
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
imx_iomux_v3_setup_multiple_pads(
usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
SETUP_IOMUX_PADS(usdhc1_pads);
gpio_direction_input(USDHC1_CD_GPIO);
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
break;
@ -207,111 +174,4 @@ int board_mmc_init(bd_t *bis)
return 0;
}
#endif /* CONFIG_FSL_ESDHC */
static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
.grp_addds = 0x00000030,
.grp_ddrmode_ctl = 0x00020000,
.grp_b0ds = 0x00000030,
.grp_ctlds = 0x00000030,
.grp_b1ds = 0x00000030,
.grp_ddrpke = 0x00000000,
.grp_ddrmode = 0x00020000,
.grp_ddr_type = 0x000c0000,
};
static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
.dram_dqm0 = 0x00000030,
.dram_dqm1 = 0x00000030,
.dram_ras = 0x00000030,
.dram_cas = 0x00000030,
.dram_odt0 = 0x00000030,
.dram_odt1 = 0x00000030,
.dram_sdba2 = 0x00000000,
.dram_sdclk_0 = 0x00000008,
.dram_sdqs0 = 0x00000038,
.dram_sdqs1 = 0x00000030,
.dram_reset = 0x00000030,
};
static struct mx6_mmdc_calibration mx6_mmcd_calib = {
.p0_mpwldectrl0 = 0x00070007,
.p0_mpdgctrl0 = 0x41490145,
.p0_mprddlctl = 0x40404546,
.p0_mpwrdlctl = 0x4040524D,
};
struct mx6_ddr_sysinfo ddr_sysinfo = {
.dsize = 0,
.cs_density = 20,
.ncs = 1,
.cs1_mirror = 0,
.rtt_wr = 2,
.rtt_nom = 1, /* RTT_Nom = RZQ/2 */
.walat = 1, /* Write additional latency */
.ralat = 5, /* Read additional latency */
.mif3_mode = 3, /* Command prediction working mode */
.bi_on = 1, /* Bank interleaving enabled */
.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
.ddr_type = DDR_TYPE_DDR3,
};
static struct mx6_ddr3_cfg mem_ddr = {
.mem_speed = 800,
.density = 4,
.width = 16,
.banks = 8,
.rowaddr = 13,
.coladdr = 10,
.pagesz = 2,
.trcd = 1375,
.trcmin = 4875,
.trasmin = 3500,
};
static void ccgr_init(void)
{
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
writel(0xFFFFFFFF, &ccm->CCGR0);
writel(0xFFFFFFFF, &ccm->CCGR1);
writel(0xFFFFFFFF, &ccm->CCGR2);
writel(0xFFFFFFFF, &ccm->CCGR3);
writel(0xFFFFFFFF, &ccm->CCGR4);
writel(0xFFFFFFFF, &ccm->CCGR5);
writel(0xFFFFFFFF, &ccm->CCGR6);
writel(0xFFFFFFFF, &ccm->CCGR7);
}
static void spl_dram_init(void)
{
mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
}
void board_init_f(ulong dummy)
{
/* setup AIPS and disable watchdog */
arch_cpu_init();
ccgr_init();
/* iomux and setup of i2c */
board_early_init_f();
/* setup GP timer */
timer_init();
/* UART clocks enabled and gd valid - init serial console */
preloader_console_init();
/* DDR initialization */
spl_dram_init();
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
/* load/boot image from boot device */
board_init_r(NULL, 0);
}
#endif /* CONFIG_SPL_BUILD */

6
board/engicam/icorem6/MAINTAINERS
View file

@ -3,10 +3,8 @@ M: Jagan Teki <jagan@amarulasolutions.com>
S: Maintained
F: board/engicam/icorem6
F: include/configs/imx6qdl_icore.h
F: configs/imx6q_icore_mmc_defconfig
F: configs/imx6q_icore_nand_defconfig
F: configs/imx6dl_icore_mmc_defconfig
F: configs/imx6dl_icore_nand_defconfig
F: configs/imx6qdl_icore_mmc_defconfig
F: configs/imx6qdl_icore_nand_defconfig
F: arch/arm/dts/imx6qdl-icore.dtsi
F: arch/arm/dts/imx6q-icore.dts
F: arch/arm/dts/imx6dl-icore.dts

330
board/engicam/icorem6/icorem6.c
View file

@ -7,6 +7,7 @@
*/
#include <common.h>
#include <mmc.h>
#include <asm/io.h>
#include <asm/gpio.h>
@ -20,17 +21,10 @@
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/video.h>
#include "../common/board.h"
DECLARE_GLOBAL_DATA_PTR;
#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
static iomux_v3_cfg_t const uart4_pads[] = {
IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
};
#ifdef CONFIG_NAND_MXS
#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
@ -56,7 +50,7 @@ iomux_v3_cfg_t gpmi_pads[] = {
IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
};
static void setup_gpmi_nand(void)
void setup_gpmi_nand(void)
{
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
@ -149,7 +143,7 @@ struct display_info_t const displays[] = {
size_t display_count = ARRAY_SIZE(displays);
static void setup_display(void)
void setup_display(void)
{
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
@ -198,43 +192,15 @@ static void setup_display(void)
}
#endif /* CONFIG_VIDEO_IPUV3 */
int board_early_init_f(void)
void setenv_fdt_file(void)
{
SETUP_IOMUX_PADS(uart4_pads);
return 0;
}
int board_init(void)
{
/* Address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
#ifdef CONFIG_NAND_MXS
setup_gpmi_nand();
#endif
#ifdef CONFIG_VIDEO_IPUV3
setup_display();
#endif
return 0;
}
int dram_init(void)
{
gd->ram_size = imx_ddr_size();
return 0;
if (is_mx6dq())
setenv("fdt_file", "imx6q-icore.dtb");
else if(is_mx6dl() || is_mx6solo())
setenv("fdt_file", "imx6dl-icore.dtb");
}
#ifdef CONFIG_SPL_BUILD
#include <libfdt.h>
#include <spl.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/mx6-ddr.h>
/* MMC board initialization is needed till adding DM support in SPL */
#if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
#include <mmc.h>
@ -307,273 +273,15 @@ int board_mmc_init(bd_t *bis)
}
#endif
/*
* Driving strength:
* 0x30 == 40 Ohm
* 0x28 == 48 Ohm
*/
#define IMX6DQ_DRIVE_STRENGTH 0x30
#define IMX6SDL_DRIVE_STRENGTH 0x28
/* configure MX6Q/DUAL mmdc DDR io registers */
static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
.dram_sdqs0 = 0x28,
.dram_sdqs1 = 0x28,
.dram_sdqs2 = 0x28,
.dram_sdqs3 = 0x28,
.dram_sdqs4 = 0x28,
.dram_sdqs5 = 0x28,
.dram_sdqs6 = 0x28,
.dram_sdqs7 = 0x28,
.dram_dqm0 = 0x28,
.dram_dqm1 = 0x28,
.dram_dqm2 = 0x28,
.dram_dqm3 = 0x28,
.dram_dqm4 = 0x28,
.dram_dqm5 = 0x28,
.dram_dqm6 = 0x28,
.dram_dqm7 = 0x28,
.dram_cas = 0x30,
.dram_ras = 0x30,
.dram_sdclk_0 = 0x30,
.dram_sdclk_1 = 0x30,
.dram_reset = 0x30,
.dram_sdcke0 = 0x3000,
.dram_sdcke1 = 0x3000,
.dram_sdba2 = 0x00000000,
.dram_sdodt0 = 0x30,
.dram_sdodt1 = 0x30,
};
/* configure MX6Q/DUAL mmdc GRP io registers */
static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
.grp_b0ds = 0x30,
.grp_b1ds = 0x30,
.grp_b2ds = 0x30,
.grp_b3ds = 0x30,
.grp_b4ds = 0x30,
.grp_b5ds = 0x30,
.grp_b6ds = 0x30,
.grp_b7ds = 0x30,
.grp_addds = 0x30,
.grp_ddrmode_ctl = 0x00020000,
.grp_ddrpke = 0x00000000,
.grp_ddrmode = 0x00020000,
.grp_ctlds = 0x30,
.grp_ddr_type = 0x000c0000,
};
/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
.dram_sdclk_0 = 0x30,
.dram_sdclk_1 = 0x30,
.dram_cas = 0x30,
.dram_ras = 0x30,
.dram_reset = 0x30,
.dram_sdcke0 = 0x30,
.dram_sdcke1 = 0x30,
.dram_sdba2 = 0x00000000,
.dram_sdodt0 = 0x30,
.dram_sdodt1 = 0x30,
.dram_sdqs0 = 0x28,
.dram_sdqs1 = 0x28,
.dram_sdqs2 = 0x28,
.dram_sdqs3 = 0x28,
.dram_sdqs4 = 0x28,
.dram_sdqs5 = 0x28,
.dram_sdqs6 = 0x28,
.dram_sdqs7 = 0x28,
.dram_dqm0 = 0x28,
.dram_dqm1 = 0x28,
.dram_dqm2 = 0x28,
.dram_dqm3 = 0x28,
.dram_dqm4 = 0x28,
.dram_dqm5 = 0x28,
.dram_dqm6 = 0x28,
.dram_dqm7 = 0x28,
};
/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
.grp_ddr_type = 0x000c0000,
.grp_ddrmode_ctl = 0x00020000,
.grp_ddrpke = 0x00000000,
.grp_addds = 0x30,
.grp_ctlds = 0x30,
.grp_ddrmode = 0x00020000,
.grp_b0ds = 0x28,
.grp_b1ds = 0x28,
.grp_b2ds = 0x28,
.grp_b3ds = 0x28,
.grp_b4ds = 0x28,
.grp_b5ds = 0x28,
.grp_b6ds = 0x28,
.grp_b7ds = 0x28,
};
/* mt41j256 */
static struct mx6_ddr3_cfg mt41j256 = {
.mem_speed = 1066,
.density = 2,
.width = 16,
.banks = 8,
.rowaddr = 13,
.coladdr = 10,
.pagesz = 2,
.trcd = 1375,
.trcmin = 4875,
.trasmin = 3500,
.SRT = 0,
};
static struct mx6_mmdc_calibration mx6dq_mmdc_calib = {
.p0_mpwldectrl0 = 0x000E0009,
.p0_mpwldectrl1 = 0x0018000E,
.p1_mpwldectrl0 = 0x00000007,
.p1_mpwldectrl1 = 0x00000000,
.p0_mpdgctrl0 = 0x43280334,
.p0_mpdgctrl1 = 0x031C0314,
.p1_mpdgctrl0 = 0x4318031C,
.p1_mpdgctrl1 = 0x030C0258,
.p0_mprddlctl = 0x3E343A40,
.p1_mprddlctl = 0x383C3844,
.p0_mpwrdlctl = 0x40404440,
.p1_mpwrdlctl = 0x4C3E4446,
};
/* DDR 64bit */
static struct mx6_ddr_sysinfo mem_q = {
.ddr_type = DDR_TYPE_DDR3,
.dsize = 2,
.cs1_mirror = 0,
/* config for full 4GB range so that get_mem_size() works */
.cs_density = 32,
.ncs = 1,
.bi_on = 1,
.rtt_nom = 2,
.rtt_wr = 2,
.ralat = 5,
.walat = 0,
.mif3_mode = 3,
.rst_to_cke = 0x23,
.sde_to_rst = 0x10,
};
static struct mx6_mmdc_calibration mx6dl_mmdc_calib = {
.p0_mpwldectrl0 = 0x001F0024,
.p0_mpwldectrl1 = 0x00110018,
.p1_mpwldectrl0 = 0x001F0024,
.p1_mpwldectrl1 = 0x00110018,
.p0_mpdgctrl0 = 0x4230022C,
.p0_mpdgctrl1 = 0x02180220,
.p1_mpdgctrl0 = 0x42440248,
.p1_mpdgctrl1 = 0x02300238,
.p0_mprddlctl = 0x44444A48,
.p1_mprddlctl = 0x46484A42,
.p0_mpwrdlctl = 0x38383234,
.p1_mpwrdlctl = 0x3C34362E,
};
/* DDR 64bit 1GB */
static struct mx6_ddr_sysinfo mem_dl = {
.dsize = 2,
.cs1_mirror = 0,
/* config for full 4GB range so that get_mem_size() works */
.cs_density = 32,
.ncs = 1,
.bi_on = 1,
.rtt_nom = 1,
.rtt_wr = 1,
.ralat = 5,
.walat = 0,
.mif3_mode = 3,
.rst_to_cke = 0x23,
.sde_to_rst = 0x10,
};
/* DDR 32bit 512MB */
static struct mx6_ddr_sysinfo mem_s = {
.dsize = 1,
.cs1_mirror = 0,
/* config for full 4GB range so that get_mem_size() works */
.cs_density = 32,
.ncs = 1,
.bi_on = 1,
.rtt_nom = 1,
.rtt_wr = 1,
.ralat = 5,
.walat = 0,
.mif3_mode = 3,
.rst_to_cke = 0x23,
.sde_to_rst = 0x10,
};
static void ccgr_init(void)
#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
writel(0x00003F3F, &ccm->CCGR0);
writel(0x0030FC00, &ccm->CCGR1);
writel(0x000FC000, &ccm->CCGR2);
writel(0x3F300000, &ccm->CCGR3);
writel(0xFF00F300, &ccm->CCGR4);
writel(0x0F0000C3, &ccm->CCGR5);
writel(0x000003CC, &ccm->CCGR6);
}
static void gpr_init(void)
{
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
/* enable AXI cache for VDOA/VPU/IPU */
writel(0xF00000CF, &iomux->gpr[4]);
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
writel(0x007F007F, &iomux->gpr[6]);
writel(0x007F007F, &iomux->gpr[7]);
}
static void spl_dram_init(void)
{
if (is_mx6solo()) {
mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
mx6_dram_cfg(&mem_s, &mx6dl_mmdc_calib, &mt41j256);
} else if (is_mx6dl()) {
mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41j256);
} else if (is_mx6dq()) {
mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
mx6_dram_cfg(&mem_q, &mx6dq_mmdc_calib, &mt41j256);
}
udelay(100);
}
void board_init_f(ulong dummy)
{
ccgr_init();
/* setup AIPS and disable watchdog */
arch_cpu_init();
gpr_init();
/* iomux */
board_early_init_f();
/* setup GP timer */
timer_init();
/* UART clocks enabled and gd valid - init serial console */
preloader_console_init();
/* DDR initialization */
spl_dram_init();
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
/* load/boot image from boot device */
board_init_r(NULL, 0);
if (is_mx6dq() && !strcmp(name, "imx6q-icore"))
return 0;
else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-icore"))
return 0;
else
return -1;
}
#endif
#endif /* CONFIG_SPL_BUILD */

3
board/engicam/icorem6_rqs/MAINTAINERS
View file

@ -3,8 +3,7 @@ M: Jagan Teki <jagan@amarulasolutions.com>
S: Maintained
F: board/engicam/icorem6_rqs
F: include/configs/imx6qdl_icore_rqs.h
F: configs/imx6q_icore_rqs_mmc_defconfig
F: configs/imx6dl_icore_rqs_mmc_defconfig
F: configs/imx6qdl_icore_rqs_mmc_defconfig
F: arch/arm/dts/imx6qdl-icore-rqs.dtsi
F: arch/arm/dts/imx6q-icore-rqs.dts
F: arch/arm/dts/imx6dl-icore-rqs.dts

352
board/engicam/icorem6_rqs/icorem6_rqs.c
View file

@ -20,91 +20,29 @@
#include <asm/arch/sys_proto.h>
#include <asm/imx-common/iomux-v3.h>
#include "../common/board.h"
DECLARE_GLOBAL_DATA_PTR;
#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
static iomux_v3_cfg_t const uart4_pads[] = {
IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
};
int board_early_init_f(void)
{
SETUP_IOMUX_PADS(uart4_pads);
return 0;
}
int board_init(void)
{
/* Address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
return 0;
}
#ifdef CONFIG_ENV_IS_IN_MMC
int board_mmc_get_env_dev(int devno)
{
/* dev 0 for SD/eSD, dev 1 for MMC/eMMC */
return (devno == 3) ? 1 : 0;
}
static void mmc_late_init(void)
{
char cmd[32];
char mmcblk[32];
u32 dev_no = mmc_get_env_dev();
setenv_ulong("mmcdev", dev_no);
/* Set mmcblk env */
sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", dev_no);
setenv("mmcroot", mmcblk);
sprintf(cmd, "mmc dev %d", dev_no);
run_command(cmd, 0);
}
#endif
int board_late_init(void)
void setenv_fdt_file(void)
{
switch ((imx6_src_get_boot_mode() & IMX6_BMODE_MASK) >>
IMX6_BMODE_SHIFT) {
case IMX6_BMODE_SD:
case IMX6_BMODE_ESD:
case IMX6_BMODE_MMC:
case IMX6_BMODE_EMMC:
#ifdef CONFIG_ENV_IS_IN_MMC
mmc_late_init();
#endif
setenv("modeboot", "mmcboot");
break;
default:
setenv("modeboot", "");
break;
}
return 0;
}
int dram_init(void)
{
gd->ram_size = imx_ddr_size();
return 0;
if (is_mx6dq())
setenv("fdt_file", "imx6q-icore-rqs.dtb");
else if(is_mx6dl() || is_mx6solo())
setenv("fdt_file", "imx6dl-icore-rqs.dtb");
}
#ifdef CONFIG_SPL_BUILD
#include <libfdt.h>
#include <spl.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/mx6-ddr.h>
/* MMC board initialization is needed till adding DM support in SPL */
#if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
#include <mmc.h>
@ -219,273 +157,15 @@ void board_boot_order(u32 *spl_boot_list)
#endif
#endif
/*
* Driving strength:
* 0x30 == 40 Ohm
* 0x28 == 48 Ohm
*/
#define IMX6DQ_DRIVE_STRENGTH 0x30
#define IMX6SDL_DRIVE_STRENGTH 0x28
/* configure MX6Q/DUAL mmdc DDR io registers */
static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
.dram_sdqs0 = 0x28,
.dram_sdqs1 = 0x28,
.dram_sdqs2 = 0x28,
.dram_sdqs3 = 0x28,
.dram_sdqs4 = 0x28,
.dram_sdqs5 = 0x28,
.dram_sdqs6 = 0x28,
.dram_sdqs7 = 0x28,
.dram_dqm0 = 0x28,
.dram_dqm1 = 0x28,
.dram_dqm2 = 0x28,
.dram_dqm3 = 0x28,
.dram_dqm4 = 0x28,
.dram_dqm5 = 0x28,
.dram_dqm6 = 0x28,
.dram_dqm7 = 0x28,
.dram_cas = 0x30,
.dram_ras = 0x30,
.dram_sdclk_0 = 0x30,
.dram_sdclk_1 = 0x30,
.dram_reset = 0x30,
.dram_sdcke0 = 0x3000,
.dram_sdcke1 = 0x3000,
.dram_sdba2 = 0x00000000,
.dram_sdodt0 = 0x30,
.dram_sdodt1 = 0x30,
};
/* configure MX6Q/DUAL mmdc GRP io registers */
static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
.grp_b0ds = 0x30,
.grp_b1ds = 0x30,
.grp_b2ds = 0x30,
.grp_b3ds = 0x30,
.grp_b4ds = 0x30,
.grp_b5ds = 0x30,
.grp_b6ds = 0x30,
.grp_b7ds = 0x30,
.grp_addds = 0x30,
.grp_ddrmode_ctl = 0x00020000,
.grp_ddrpke = 0x00000000,
.grp_ddrmode = 0x00020000,
.grp_ctlds = 0x30,
.grp_ddr_type = 0x000c0000,
};
/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
.dram_sdclk_0 = 0x30,
.dram_sdclk_1 = 0x30,
.dram_cas = 0x30,
.dram_ras = 0x30,
.dram_reset = 0x30,
.dram_sdcke0 = 0x30,
.dram_sdcke1 = 0x30,
.dram_sdba2 = 0x00000000,
.dram_sdodt0 = 0x30,
.dram_sdodt1 = 0x30,
.dram_sdqs0 = 0x28,
.dram_sdqs1 = 0x28,
.dram_sdqs2 = 0x28,
.dram_sdqs3 = 0x28,
.dram_sdqs4 = 0x28,
.dram_sdqs5 = 0x28,
.dram_sdqs6 = 0x28,
.dram_sdqs7 = 0x28,
.dram_dqm0 = 0x28,
.dram_dqm1 = 0x28,
.dram_dqm2 = 0x28,
.dram_dqm3 = 0x28,
.dram_dqm4 = 0x28,
.dram_dqm5 = 0x28,
.dram_dqm6 = 0x28,
.dram_dqm7 = 0x28,
};
/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
.grp_ddr_type = 0x000c0000,
.grp_ddrmode_ctl = 0x00020000,
.grp_ddrpke = 0x00000000,
.grp_addds = 0x30,
.grp_ctlds = 0x30,
.grp_ddrmode = 0x00020000,
.grp_b0ds = 0x28,
.grp_b1ds = 0x28,
.grp_b2ds = 0x28,
.grp_b3ds = 0x28,
.grp_b4ds = 0x28,
.grp_b5ds = 0x28,
.grp_b6ds = 0x28,
.grp_b7ds = 0x28,
};
/* mt41j256 */
static struct mx6_ddr3_cfg mt41j256 = {
.mem_speed = 1066,
.density = 2,
.width = 16,
.banks = 8,
.rowaddr = 13,
.coladdr = 10,
.pagesz = 2,
.trcd = 1375,
.trcmin = 4875,
.trasmin = 3500,
.SRT = 0,
};
static struct mx6_mmdc_calibration mx6dq_mmdc_calib = {
.p0_mpwldectrl0 = 0x000E0009,
.p0_mpwldectrl1 = 0x0018000E,
.p1_mpwldectrl0 = 0x00000007,
.p1_mpwldectrl1 = 0x00000000,
.p0_mpdgctrl0 = 0x43280334,
.p0_mpdgctrl1 = 0x031C0314,
.p1_mpdgctrl0 = 0x4318031C,
.p1_mpdgctrl1 = 0x030C0258,
.p0_mprddlctl = 0x3E343A40,
.p1_mprddlctl = 0x383C3844,
.p0_mpwrdlctl = 0x40404440,
.p1_mpwrdlctl = 0x4C3E4446,
};
/* DDR 64bit */
static struct mx6_ddr_sysinfo mem_q = {
.ddr_type = DDR_TYPE_DDR3,
.dsize = 2,
.cs1_mirror = 0,
/* config for full 4GB range so that get_mem_size() works */
.cs_density = 32,
.ncs = 1,
.bi_on = 1,
.rtt_nom = 2,
.rtt_wr = 2,
.ralat = 5,
.walat = 0,
.mif3_mode = 3,
.rst_to_cke = 0x23,
.sde_to_rst = 0x10,
};
static struct mx6_mmdc_calibration mx6dl_mmdc_calib = {
.p0_mpwldectrl0 = 0x001F0024,
.p0_mpwldectrl1 = 0x00110018,
.p1_mpwldectrl0 = 0x001F0024,
.p1_mpwldectrl1 = 0x00110018,
.p0_mpdgctrl0 = 0x4230022C,
.p0_mpdgctrl1 = 0x02180220,
.p1_mpdgctrl0 = 0x42440248,
.p1_mpdgctrl1 = 0x02300238,
.p0_mprddlctl = 0x44444A48,
.p1_mprddlctl = 0x46484A42,
.p0_mpwrdlctl = 0x38383234,
.p1_mpwrdlctl = 0x3C34362E,
};
/* DDR 64bit 1GB */
static struct mx6_ddr_sysinfo mem_dl = {
.dsize = 2,
.cs1_mirror = 0,
/* config for full 4GB range so that get_mem_size() works */
.cs_density = 32,
.ncs = 1,
.bi_on = 1,
.rtt_nom = 1,
.rtt_wr = 1,
.ralat = 5,
.walat = 0,
.mif3_mode = 3,
.rst_to_cke = 0x23,
.sde_to_rst = 0x10,
};
/* DDR 32bit 512MB */
static struct mx6_ddr_sysinfo mem_s = {
.dsize = 1,
.cs1_mirror = 0,
/* config for full 4GB range so that get_mem_size() works */
.cs_density = 32,
.ncs = 1,
.bi_on = 1,
.rtt_nom = 1,
.rtt_wr = 1,
.ralat = 5,
.walat = 0,
.mif3_mode = 3,
.rst_to_cke = 0x23,
.sde_to_rst = 0x10,
};
static void ccgr_init(void)
#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
writel(0x00003F3F, &ccm->CCGR0);
writel(0x0030FC00, &ccm->CCGR1);
writel(0x000FC000, &ccm->CCGR2);
writel(0x3F300000, &ccm->CCGR3);
writel(0xFF00F300, &ccm->CCGR4);
writel(0x0F0000C3, &ccm->CCGR5);
writel(0x000003CC, &ccm->CCGR6);
}
static void gpr_init(void)
{
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
/* enable AXI cache for VDOA/VPU/IPU */
writel(0xF00000CF, &iomux->gpr[4]);
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
writel(0x007F007F, &iomux->gpr[6]);
writel(0x007F007F, &iomux->gpr[7]);
}
static void spl_dram_init(void)
{
if (is_mx6solo()) {
mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
mx6_dram_cfg(&mem_s, &mx6dl_mmdc_calib, &mt41j256);
} else if (is_mx6dl()) {
mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41j256);
} else if (is_mx6dq()) {
mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
mx6_dram_cfg(&mem_q, &mx6dq_mmdc_calib, &mt41j256);
}
udelay(100);
}
void board_init_f(ulong dummy)
{
ccgr_init();
/* setup AIPS and disable watchdog */
arch_cpu_init();
gpr_init();
/* iomux */
board_early_init_f();
/* setup GP timer */
timer_init();
/* UART clocks enabled and gd valid - init serial console */
preloader_console_init();
/* DDR initialization */
spl_dram_init();
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
/* load/boot image from boot device */
board_init_r(NULL, 0);
if (is_mx6dq() && !strcmp(name, "imx6q-icore-rqs"))
return 0;
else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-icore-rqs"))
return 0;
else
return -1;
}
#endif
#endif /* CONFIG_SPL_BUILD */

261
board/engicam/isiotmx6ul/isiotmx6ul.c
View file

@ -20,24 +20,10 @@
#include <asm/arch/sys_proto.h>
#include <asm/imx-common/iomux-v3.h>
#include "../common/board.h"
DECLARE_GLOBAL_DATA_PTR;
#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
static iomux_v3_cfg_t const uart1_pads[] = {
MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
int board_early_init_f(void)
{
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
return 0;
}
#ifdef CONFIG_NAND_MXS
#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
@ -46,29 +32,29 @@ int board_early_init_f(void)
#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
static iomux_v3_cfg_t const nand_pads[] = {
MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
IOMUX_PADS(PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
IOMUX_PADS(PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
IOMUX_PADS(PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
IOMUX_PADS(PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
IOMUX_PADS(PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
IOMUX_PADS(PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
IOMUX_PADS(PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
IOMUX_PADS(PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
IOMUX_PADS(PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
IOMUX_PADS(PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
IOMUX_PADS(PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
IOMUX_PADS(PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
IOMUX_PADS(PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
IOMUX_PADS(PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
IOMUX_PADS(PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
};
static void setup_gpmi_nand(void)
void setup_gpmi_nand(void)
{
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
/* config gpmi nand iomux */
imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
SETUP_IOMUX_PADS(nand_pads);
clrbits_le32(&mxc_ccm->CCGR4,
MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
@ -110,73 +96,22 @@ int board_mmc_get_env_dev(int devno)
/* dev 0 for SD/eSD, dev 1 for MMC/eMMC */
return (devno == 0) ? 0 : 1;
}
static void mmc_late_init(void)
{
char cmd[32];
char mmcblk[32];
u32 dev_no = mmc_get_env_dev();
setenv_ulong("mmcdev", dev_no);
/* Set mmcblk env */
sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", dev_no);
setenv("mmcroot", mmcblk);
sprintf(cmd, "mmc dev %d", dev_no);
run_command(cmd, 0);
}
#endif
int board_late_init(void)
void setenv_fdt_file(void)
{
switch ((imx6_src_get_boot_mode() & IMX6_BMODE_MASK) >>
IMX6_BMODE_SHIFT) {
case IMX6_BMODE_SD:
case IMX6_BMODE_ESD:
case IMX6_BMODE_MMC:
case IMX6_BMODE_EMMC:
if (is_mx6ul()) {
#ifdef CONFIG_ENV_IS_IN_MMC
mmc_late_init();
setenv("fdt_file", "imx6ul-isiot-emmc.dtb");
#else
setenv("fdt_file", "imx6ul-isiot-nand.dtb");
#endif
setenv("modeboot", "mmcboot");
break;
case IMX6_BMODE_NAND:
setenv("modeboot", "nandboot");
break;
default:
setenv("modeboot", "");
break;
}
return 0;
}
int board_init(void)
{
/* Address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
#ifdef CONFIG_NAND_MXS
setup_gpmi_nand();
#endif
return 0;
}
int dram_init(void)
{
gd->ram_size = imx_ddr_size();
return 0;
}
#ifdef CONFIG_SPL_BUILD
#include <libfdt.h>
#include <spl.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/mx6-ddr.h>
/* MMC board initialization is needed till adding DM support in SPL */
#if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
#include <mmc.h>
@ -187,31 +122,31 @@ int dram_init(void)
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
static iomux_v3_cfg_t const usdhc1_pads[] = {
MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IOMUX_PADS(PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
/* VSELECT */
MX6_PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IOMUX_PADS(PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
/* CD */
MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
IOMUX_PADS(PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* RST_B */
MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
IOMUX_PADS(PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
};
static iomux_v3_cfg_t const usdhc2_pads[] = {
MX6_PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IOMUX_PADS(PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
};
#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19)
@ -252,14 +187,12 @@ int board_mmc_init(bd_t *bis)
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
imx_iomux_v3_setup_multiple_pads(
usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
SETUP_IOMUX_PADS(usdhc1_pads);
gpio_direction_input(USDHC1_CD_GPIO);
usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
break;
case 1:
imx_iomux_v3_setup_multiple_pads(
usdhc1_pads, ARRAY_SIZE(usdhc2_pads));
SETUP_IOMUX_PADS(usdhc2_pads);
gpio_direction_input(USDHC2_CD_GPIO);
usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
break;
@ -305,110 +238,4 @@ void board_boot_order(u32 *spl_boot_list)
}
#endif
#endif /* CONFIG_FSL_ESDHC */
static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
.grp_addds = 0x00000030,
.grp_ddrmode_ctl = 0x00020000,
.grp_b0ds = 0x00000030,
.grp_ctlds = 0x00000030,
.grp_b1ds = 0x00000030,
.grp_ddrpke = 0x00000000,
.grp_ddrmode = 0x00020000,
.grp_ddr_type = 0x000c0000,
};
static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
.dram_dqm0 = 0x00000030,
.dram_dqm1 = 0x00000030,
.dram_ras = 0x00000030,
.dram_cas = 0x00000030,
.dram_odt0 = 0x00000030,
.dram_odt1 = 0x00000030,
.dram_sdba2 = 0x00000000,
.dram_sdclk_0 = 0x00000008,
.dram_sdqs0 = 0x00000038,
.dram_sdqs1 = 0x00000030,
.dram_reset = 0x00000030,
};
static struct mx6_mmdc_calibration mx6_mmcd_calib = {
.p0_mpwldectrl0 = 0x00070007,
.p0_mpdgctrl0 = 0x41490145,
.p0_mprddlctl = 0x40404546,
.p0_mpwrdlctl = 0x4040524D,
};
struct mx6_ddr_sysinfo ddr_sysinfo = {
.dsize = 0,
.cs_density = 20,
.ncs = 1,
.cs1_mirror = 0,
.rtt_wr = 2,
.rtt_nom = 1, /* RTT_Nom = RZQ/2 */
.walat = 1, /* Write additional latency */
.ralat = 5, /* Read additional latency */
.mif3_mode = 3, /* Command prediction working mode */
.bi_on = 1, /* Bank interleaving enabled */
.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
.ddr_type = DDR_TYPE_DDR3,
};
static struct mx6_ddr3_cfg mem_ddr = {
.mem_speed = 800,
.density = 4,
.width = 16,
.banks = 8,
.rowaddr = 15,
.coladdr = 10,
.pagesz = 2,
.trcd = 1375,
.trcmin = 4875,
.trasmin = 3500,
};
static void ccgr_init(void)
{
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
writel(0x00c03f3f, &ccm->CCGR0);
writel(0xfcffff00, &ccm->CCGR1);
writel(0x0cffffcc, &ccm->CCGR2);
writel(0x3f3c3030, &ccm->CCGR3);
writel(0xff00fffc, &ccm->CCGR4);
writel(0x033f30ff, &ccm->CCGR5);
writel(0x00c00fff, &ccm->CCGR6);
}
static void spl_dram_init(void)
{
mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
}
void board_init_f(ulong dummy)
{
/* setup AIPS and disable watchdog */
arch_cpu_init();
ccgr_init();
/* iomux and setup of i2c */
board_early_init_f();
/* setup GP timer */
timer_init();
/* UART clocks enabled and gd valid - init serial console */
preloader_console_init();
/* DDR initialization */
spl_dram_init();
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
/* load/boot image from boot device */
board_init_r(NULL, 0);
}
#endif /* CONFIG_SPL_BUILD */

131
board/freescale/mx6sabresd/mx6dlsabresd.cfg
View file

@ -1,131 +0,0 @@
/*
* Copyright (C) 2014 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*
* Refer doc/README.imximage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
/* image version */
IMAGE_VERSION 2
/*
* Boot Device : one of
* spi, sd (the board has no nand neither onenand)
*/
BOOT_FROM sd
/*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
DATA 4 0x020e0774 0x000C0000
DATA 4 0x020e0754 0x00000000
DATA 4 0x020e04ac 0x00000030
DATA 4 0x020e04b0 0x00000030
DATA 4 0x020e0464 0x00000030
DATA 4 0x020e0490 0x00000030
DATA 4 0x020e074c 0x00000030
DATA 4 0x020e0494 0x00000030
DATA 4 0x020e04a0 0x00000000
DATA 4 0x020e04b4 0x00000030
DATA 4 0x020e04b8 0x00000030
DATA 4 0x020e076c 0x00000030
DATA 4 0x020e0750 0x00020000
DATA 4 0x020e04bc 0x00000030
DATA 4 0x020e04c0 0x00000030
DATA 4 0x020e04c4 0x00000030
DATA 4 0x020e04c8 0x00000030
DATA 4 0x020e04cc 0x00000030
DATA 4 0x020e04d0 0x00000030
DATA 4 0x020e04d4 0x00000030
DATA 4 0x020e04d8 0x00000030
DATA 4 0x020e0760 0x00020000
DATA 4 0x020e0764 0x00000030
DATA 4 0x020e0770 0x00000030
DATA 4 0x020e0778 0x00000030
DATA 4 0x020e077c 0x00000030
DATA 4 0x020e0780 0x00000030
DATA 4 0x020e0784 0x00000030
DATA 4 0x020e078c 0x00000030
DATA 4 0x020e0748 0x00000030
DATA 4 0x020e0470 0x00000030
DATA 4 0x020e0474 0x00000030
DATA 4 0x020e0478 0x00000030
DATA 4 0x020e047c 0x00000030
DATA 4 0x020e0480 0x00000030
DATA 4 0x020e0484 0x00000030
DATA 4 0x020e0488 0x00000030
DATA 4 0x020e048c 0x00000030
DATA 4 0x021b0800 0xa1390003
DATA 4 0x021b080c 0x001F001F
DATA 4 0x021b0810 0x001F001F
DATA 4 0x021b480c 0x001F001F
DATA 4 0x021b4810 0x001F001F
DATA 4 0x021b083c 0x4220021F
DATA 4 0x021b0840 0x0207017E
DATA 4 0x021b483c 0x4201020C
DATA 4 0x021b4840 0x01660172
DATA 4 0x021b0848 0x4A4D4E4D
DATA 4 0x021b4848 0x4A4F5049
DATA 4 0x021b0850 0x3F3C3D31
DATA 4 0x021b4850 0x3238372B
DATA 4 0x021b081c 0x33333333
DATA 4 0x021b0820 0x33333333
DATA 4 0x021b0824 0x33333333
DATA 4 0x021b0828 0x33333333
DATA 4 0x021b481c 0x33333333
DATA 4 0x021b4820 0x33333333
DATA 4 0x021b4824 0x33333333
DATA 4 0x021b4828 0x33333333
DATA 4 0x021b08b8 0x00000800
DATA 4 0x021b48b8 0x00000800
DATA 4 0x021b0004 0x0002002D
DATA 4 0x021b0008 0x00333030
DATA 4 0x021b000c 0x3F435313
DATA 4 0x021b0010 0xB66E8B63
DATA 4 0x021b0014 0x01FF00DB
DATA 4 0x021b0018 0x00001740
DATA 4 0x021b001c 0x00008000
DATA 4 0x021b002c 0x000026d2
DATA 4 0x021b0030 0x00431023
DATA 4 0x021b0040 0x00000027
DATA 4 0x021b0000 0x831A0000
DATA 4 0x021b001c 0x04008032
DATA 4 0x021b001c 0x00008033
DATA 4 0x021b001c 0x00048031
DATA 4 0x021b001c 0x05208030
DATA 4 0x021b001c 0x04008040
DATA 4 0x021b0020 0x00005800
DATA 4 0x021b0818 0x00011117
DATA 4 0x021b4818 0x00011117
DATA 4 0x021b0004 0x0002556D
DATA 4 0x021b0404 0x00011006
DATA 4 0x021b001c 0x00000000
/* set the default clock gate to save power */
DATA 4 0x020c4068 0x00C03F3F
DATA 4 0x020c406c 0x0030FC03
DATA 4 0x020c4070 0x0FFFC000
DATA 4 0x020c4074 0x3FF00000
DATA 4 0x020c4078 0x00FFF300
DATA 4 0x020c407c 0x0F0000C3
DATA 4 0x020c4080 0x000003FF
/* enable AXI cache for VDOA/VPU/IPU */
DATA 4 0x020e0010 0xF00000CF
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
DATA 4 0x020e0018 0x007F007F
DATA 4 0x020e001c 0x007F007F

169
board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg
View file

@ -1,169 +0,0 @@
/*
* Copyright (C) 2011 Freescale Semiconductor, Inc.
* Jason Liu <r64343@freescale.com>
*
* SPDX-License-Identifier: GPL-2.0+
*
* Refer doc/README.imximage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
/* image version */
IMAGE_VERSION 2
/*
* Boot Device : one of
* spi, sd (the board has no nand neither onenand)
*/
BOOT_FROM sd
/*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
DATA 4 0x020e05a8 0x00000030
DATA 4 0x020e05b0 0x00000030
DATA 4 0x020e0524 0x00000030
DATA 4 0x020e051c 0x00000030
DATA 4 0x020e0518 0x00000030
DATA 4 0x020e050c 0x00000030
DATA 4 0x020e05b8 0x00000030
DATA 4 0x020e05c0 0x00000030
DATA 4 0x020e05ac 0x00020030
DATA 4 0x020e05b4 0x00020030
DATA 4 0x020e0528 0x00020030
DATA 4 0x020e0520 0x00020030
DATA 4 0x020e0514 0x00020030
DATA 4 0x020e0510 0x00020030
DATA 4 0x020e05bc 0x00020030
DATA 4 0x020e05c4 0x00020030
DATA 4 0x020e056c 0x00020030
DATA 4 0x020e0578 0x00020030
DATA 4 0x020e0588 0x00020030
DATA 4 0x020e0594 0x00020030
DATA 4 0x020e057c 0x00020030
DATA 4 0x020e0590 0x00003000
DATA 4 0x020e0598 0x00003000
DATA 4 0x020e058c 0x00000000
DATA 4 0x020e059c 0x00003030
DATA 4 0x020e05a0 0x00003030
DATA 4 0x020e0784 0x00000030
DATA 4 0x020e0788 0x00000030
DATA 4 0x020e0794 0x00000030
DATA 4 0x020e079c 0x00000030
DATA 4 0x020e07a0 0x00000030
DATA 4 0x020e07a4 0x00000030
DATA 4 0x020e07a8 0x00000030
DATA 4 0x020e0748 0x00000030
DATA 4 0x020e074c 0x00000030
DATA 4 0x020e0750 0x00020000
DATA 4 0x020e0758 0x00000000
DATA 4 0x020e0774 0x00020000
DATA 4 0x020e078c 0x00000030
DATA 4 0x020e0798 0x000C0000
DATA 4 0x021b081c 0x33333333
DATA 4 0x021b0820 0x33333333
DATA 4 0x021b0824 0x33333333
DATA 4 0x021b0828 0x33333333
DATA 4 0x021b481c 0x33333333
DATA 4 0x021b4820 0x33333333
DATA 4 0x021b4824 0x33333333
DATA 4 0x021b4828 0x33333333
DATA 4 0x021b0018 0x00081740
DATA 4 0x021b001c 0x00008000
DATA 4 0x021b000c 0x555A7974
DATA 4 0x021b0010 0xDB538F64
DATA 4 0x021b0014 0x01FF00DB
DATA 4 0x021b002c 0x000026D2
DATA 4 0x021b0030 0x005A1023
DATA 4 0x021b0008 0x09444040
DATA 4 0x021b0004 0x00025576
DATA 4 0x021b0040 0x00000027
DATA 4 0x021b0000 0x831A0000
DATA 4 0x021b001c 0x04088032
DATA 4 0x021b001c 0x0408803A
DATA 4 0x021b001c 0x00008033
DATA 4 0x021b001c 0x0000803B
DATA 4 0x021b001c 0x00428031
DATA 4 0x021b001c 0x00428039
DATA 4 0x021b001c 0x19308030
DATA 4 0x021b001c 0x19308038
DATA 4 0x021b001c 0x04008040
DATA 4 0x021b001c 0x04008048
DATA 4 0x021b0800 0xA1380003
DATA 4 0x021b4800 0xA1380003
DATA 4 0x021b0020 0x00005800
DATA 4 0x021b0818 0x00022227
DATA 4 0x021b4818 0x00022227
DATA 4 0x021b083c 0x434B0350
DATA 4 0x021b0840 0x034C0359
DATA 4 0x021b483c 0x434B0350
DATA 4 0x021b4840 0x03650348
DATA 4 0x021b0848 0x4436383B
DATA 4 0x021b4848 0x39393341
DATA 4 0x021b0850 0x35373933
DATA 4 0x021b4850 0x48254A36
DATA 4 0x021b080c 0x001F001F
DATA 4 0x021b0810 0x001F001F
DATA 4 0x021b480c 0x00440044
DATA 4 0x021b4810 0x00440044
DATA 4 0x021b08b8 0x00000800
DATA 4 0x021b48b8 0x00000800
DATA 4 0x021b001c 0x00000000
DATA 4 0x021b0404 0x00011006
/* set the default clock gate to save power */
DATA 4 0x020c4068 0x00C03F3F
DATA 4 0x020c406c 0x0030FC03
DATA 4 0x020c4070 0x0FFFC000
DATA 4 0x020c4074 0x3FF00000
DATA 4 0x020c4078 0x00FFF300
DATA 4 0x020c407c 0x0F0000C3
DATA 4 0x020c4080 0x000003FF
/* enable AXI cache for VDOA/VPU/IPU */
DATA 4 0x020e0010 0xF00000CF
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
DATA 4 0x020e0018 0x007F007F
DATA 4 0x020e001c 0x007F007F
/*
* Setup CCM_CCOSR register as follows:
*
* cko1_en = 1 --> CKO1 enabled
* cko1_div = 111 --> divide by 8
* cko1_sel = 1011 --> ahb_clk_root
*
* This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
*/
DATA 4 0x020c4060 0x000000fb

341
board/freescale/mx6sabresd/mx6sabresd.c
View file

@ -28,7 +28,6 @@
#include <power/pmic.h>
#include <power/pfuze100_pmic.h>
#include "../common/pfuze.h"
#include <asm/arch/mx6-ddr.h>
#include <usb.h>
DECLARE_GLOBAL_DATA_PTR;
@ -66,33 +65,33 @@ int dram_init(void)
}
static iomux_v3_cfg_t const uart1_pads[] = {
MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
};
static iomux_v3_cfg_t const enet_pads[] = {
MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
/* AR8031 PHY Reset */
MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
};
static void setup_iomux_enet(void)
{
imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
SETUP_IOMUX_PADS(enet_pads);
/* Reset AR8031 PHY */
gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
@ -102,98 +101,98 @@ static void setup_iomux_enet(void)
}
static iomux_v3_cfg_t const usdhc2_pads[] = {
MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NANDF_D4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NANDF_D5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NANDF_D6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NANDF_D7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_NANDF_D4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_NANDF_D5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_NANDF_D6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_NANDF_D7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
};
static iomux_v3_cfg_t const usdhc3_pads[] = {
MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
};
static iomux_v3_cfg_t const usdhc4_pads[] = {
MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
};
static iomux_v3_cfg_t const ecspi1_pads[] = {
MX6_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
IOMUX_PADS(PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
IOMUX_PADS(PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
IOMUX_PADS(PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
};
static iomux_v3_cfg_t const rgb_pads[] = {
MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | MUX_PAD_CTRL(NO_PAD_CTRL),
IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_DISP0_DAT18__IPU1_DISP0_DATA18 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_DISP0_DAT19__IPU1_DISP0_DATA19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_DISP0_DAT20__IPU1_DISP0_DATA20 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | MUX_PAD_CTRL(NO_PAD_CTRL)),
};
static iomux_v3_cfg_t const bl_pads[] = {
MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL)),
};
static void enable_backlight(void)
{
imx_iomux_v3_setup_multiple_pads(bl_pads, ARRAY_SIZE(bl_pads));
SETUP_IOMUX_PADS(bl_pads);
gpio_direction_output(DISP0_PWR_EN, 1);
}
static void enable_rgb(struct display_info_t const *dev)
{
imx_iomux_v3_setup_multiple_pads(rgb_pads, ARRAY_SIZE(rgb_pads));
SETUP_IOMUX_PADS(rgb_pads);
enable_backlight();
}
@ -202,43 +201,56 @@ static void enable_lvds(struct display_info_t const *dev)
enable_backlight();
}
static struct i2c_pads_info i2c_pad_info1 = {
static struct i2c_pads_info mx6q_i2c_pad_info1 = {
.scl = {
.i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
.gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
.i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
.gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
.gp = IMX_GPIO_NR(4, 12)
},
.sda = {
.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
.gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
.i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
.gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
.gp = IMX_GPIO_NR(4, 13)
}
};
static struct i2c_pads_info mx6dl_i2c_pad_info1 = {
.scl = {
.i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
.gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
.gp = IMX_GPIO_NR(4, 12)
},
.sda = {
.i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
.gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
.gp = IMX_GPIO_NR(4, 13)
}
};
static void setup_spi(void)
{
imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
SETUP_IOMUX_PADS(ecspi1_pads);
}
iomux_v3_cfg_t const pcie_pads[] = {
MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), /* POWER */
MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), /* RESET */
IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* POWER */
IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* RESET */
};
static void setup_pcie(void)
{
imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
SETUP_IOMUX_PADS(pcie_pads);
}
iomux_v3_cfg_t const di0_pads[] = {
MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* DISP0_CLK */
MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* DISP0_HSYNC */
MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, /* DISP0_VSYNC */
IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK), /* DISP0_CLK */
IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), /* DISP0_HSYNC */
IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03), /* DISP0_VSYNC */
};
static void setup_iomux_uart(void)
{
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
SETUP_IOMUX_PADS(uart1_pads);
}
#ifdef CONFIG_FSL_ESDHC
@ -292,20 +304,17 @@ int board_mmc_init(bd_t *bis)
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
imx_iomux_v3_setup_multiple_pads(
usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
SETUP_IOMUX_PADS(usdhc2_pads);
gpio_direction_input(USDHC2_CD_GPIO);
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
break;
case 1:
imx_iomux_v3_setup_multiple_pads(
usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
SETUP_IOMUX_PADS(usdhc3_pads);
gpio_direction_input(USDHC3_CD_GPIO);
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
break;
case 2:
imx_iomux_v3_setup_multiple_pads(
usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
SETUP_IOMUX_PADS(usdhc4_pads);
usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
break;
default:
@ -335,22 +344,19 @@ int board_mmc_init(bd_t *bis)
switch (reg & 0x3) {
case 0x1:
imx_iomux_v3_setup_multiple_pads(
usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
SETUP_IOMUX_PADS(usdhc2_pads);
usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
break;
case 0x2:
imx_iomux_v3_setup_multiple_pads(
usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
SETUP_IOMUX_PADS(usdhc3_pads);
usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
break;
case 0x3:
imx_iomux_v3_setup_multiple_pads(
usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
SETUP_IOMUX_PADS(usdhc4_pads);
usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
@ -484,7 +490,7 @@ static void setup_display(void)
int reg;
/* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */
imx_iomux_v3_setup_multiple_pads(di0_pads, ARRAY_SIZE(di0_pads));
SETUP_IOMUX_PADS(di0_pads);
enable_ipu_clock();
imx_setup_hdmi();
@ -555,18 +561,17 @@ int board_eth_init(bd_t *bis)
#define UCTRL_PWR_POL (1 << 9)
static iomux_v3_cfg_t const usb_otg_pads[] = {
MX6_PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
IOMUX_PADS(PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL)),
};
static iomux_v3_cfg_t const usb_hc1_pads[] = {
MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
};
static void setup_usb(void)
{
imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
ARRAY_SIZE(usb_otg_pads));
SETUP_IOMUX_PADS(usb_otg_pads);
/*
* set daisy chain for otg_pin_id on 6q.
@ -574,8 +579,7 @@ static void setup_usb(void)
*/
imx_iomux_set_gpr_register(1, 13, 1, 0);
imx_iomux_v3_setup_multiple_pads(usb_hc1_pads,
ARRAY_SIZE(usb_hc1_pads));
SETUP_IOMUX_PADS(usb_hc1_pads);
}
int board_ehci_hcd_init(int port)
@ -631,8 +635,10 @@ int board_init(void)
#ifdef CONFIG_MXC_SPI
setup_spi();
#endif
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
if (is_mx6dq() || is_mx6dqp())
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
else
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
#ifdef CONFIG_USB_EHCI_MX6
setup_usb();
#endif
@ -714,6 +720,7 @@ int checkboard(void)
}
#ifdef CONFIG_SPL_BUILD
#include <asm/arch/mx6-ddr.h>
#include <spl.h>
#include <libfdt.h>
@ -939,6 +946,92 @@ static int mx6qp_dcd_table[] = {
0x021b001c, 0x00000000,
};
static int mx6dl_dcd_table[] = {
0x020e0774, 0x000C0000,
0x020e0754, 0x00000000,
0x020e04ac, 0x00000030,
0x020e04b0, 0x00000030,
0x020e0464, 0x00000030,
0x020e0490, 0x00000030,
0x020e074c, 0x00000030,
0x020e0494, 0x00000030,
0x020e04a0, 0x00000000,
0x020e04b4, 0x00000030,
0x020e04b8, 0x00000030,
0x020e076c, 0x00000030,
0x020e0750, 0x00020000,
0x020e04bc, 0x00000030,
0x020e04c0, 0x00000030,
0x020e04c4, 0x00000030,
0x020e04c8, 0x00000030,
0x020e04cc, 0x00000030,
0x020e04d0, 0x00000030,
0x020e04d4, 0x00000030,
0x020e04d8, 0x00000030,
0x020e0760, 0x00020000,
0x020e0764, 0x00000030,
0x020e0770, 0x00000030,
0x020e0778, 0x00000030,
0x020e077c, 0x00000030,
0x020e0780, 0x00000030,
0x020e0784, 0x00000030,
0x020e078c, 0x00000030,
0x020e0748, 0x00000030,
0x020e0470, 0x00000030,
0x020e0474, 0x00000030,
0x020e0478, 0x00000030,
0x020e047c, 0x00000030,
0x020e0480, 0x00000030,
0x020e0484, 0x00000030,
0x020e0488, 0x00000030,
0x020e048c, 0x00000030,
0x021b0800, 0xa1390003,
0x021b080c, 0x001F001F,
0x021b0810, 0x001F001F,
0x021b480c, 0x001F001F,
0x021b4810, 0x001F001F,
0x021b083c, 0x4220021F,
0x021b0840, 0x0207017E,
0x021b483c, 0x4201020C,
0x021b4840, 0x01660172,
0x021b0848, 0x4A4D4E4D,
0x021b4848, 0x4A4F5049,
0x021b0850, 0x3F3C3D31,
0x021b4850, 0x3238372B,
0x021b081c, 0x33333333,
0x021b0820, 0x33333333,
0x021b0824, 0x33333333,
0x021b0828, 0x33333333,
0x021b481c, 0x33333333,
0x021b4820, 0x33333333,
0x021b4824, 0x33333333,
0x021b4828, 0x33333333,
0x021b08b8, 0x00000800,
0x021b48b8, 0x00000800,
0x021b0004, 0x0002002D,
0x021b0008, 0x00333030,
0x021b000c, 0x3F435313,
0x021b0010, 0xB66E8B63,
0x021b0014, 0x01FF00DB,
0x021b0018, 0x00001740,
0x021b001c, 0x00008000,
0x021b002c, 0x000026d2,
0x021b0030, 0x00431023,
0x021b0040, 0x00000027,
0x021b0000, 0x831A0000,
0x021b001c, 0x04008032,
0x021b001c, 0x00008033,
0x021b001c, 0x00048031,
0x021b001c, 0x05208030,
0x021b001c, 0x04008040,
0x021b0020, 0x00005800,
0x021b0818, 0x00011117,
0x021b4818, 0x00011117,
0x021b0004, 0x0002556D,
0x021b0404, 0x00011006,
0x021b001c, 0x00000000,
};
static void ddr_init(int *table, int size)
{
int i;
@ -953,6 +1046,8 @@ static void spl_dram_init(void)
ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table));
else if (is_mx6dqp())
ddr_init(mx6qp_dcd_table, ARRAY_SIZE(mx6qp_dcd_table));
else if (is_mx6sdl())
ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
}
void board_init_f(ulong dummy)

330
board/freescale/mx7dsabresd/mx7dsabresd.c
View file

@ -23,25 +23,17 @@
#include <i2c.h>
#include <asm/imx-common/mxc_i2c.h>
#include <asm/arch/crm_regs.h>
#include <usb.h>
#include <usb/ehci-ci.h>
DECLARE_GLOBAL_DATA_PTR;
#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
#define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
#define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM)
#define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
#define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM)
#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
PAD_CTL_DSE_3P3V_49OHM)
@ -54,23 +46,8 @@ DECLARE_GLOBAL_DATA_PTR;
(PAD_CTL_HYS | PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_FAST)
#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)
#ifdef CONFIG_SYS_I2C_MXC
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
/* I2C1 for PMIC */
static struct i2c_pads_info i2c_pad_info1 = {
.scl = {
.i2c_mode = MX7D_PAD_I2C1_SCL__I2C1_SCL | PC,
.gpio_mode = MX7D_PAD_I2C1_SCL__GPIO4_IO8 | PC,
.gp = IMX_GPIO_NR(4, 8),
},
.sda = {
.i2c_mode = MX7D_PAD_I2C1_SDA__I2C1_SDA | PC,
.gpio_mode = MX7D_PAD_I2C1_SDA__GPIO4_IO9 | PC,
.gp = IMX_GPIO_NR(4, 9),
},
};
#endif
#ifdef CONFIG_MXC_SPI
static iomux_v3_cfg_t const ecspi3_pads[] = {
MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
@ -87,6 +64,7 @@ static void setup_spi(void)
{
imx_iomux_v3_setup_multiple_pads(ecspi3_pads, ARRAY_SIZE(ecspi3_pads));
}
#endif
int dram_init(void)
{
@ -104,130 +82,6 @@ static iomux_v3_cfg_t const uart1_pads[] = {
MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
static iomux_v3_cfg_t const usdhc1_pads[] = {
MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX7D_PAD_SD1_RESET_B__GPIO5_IO2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};
static iomux_v3_cfg_t const usdhc3_emmc_pads[] = {
MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX7D_PAD_SD3_STROBE__SD3_STROBE | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};
static iomux_v3_cfg_t const usb_otg1_pads[] = {
MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static iomux_v3_cfg_t const usb_otg2_pads[] = {
MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
};
#define IOX_SDI IMX_GPIO_NR(1, 9)
#define IOX_STCP IMX_GPIO_NR(1, 12)
#define IOX_SHCP IMX_GPIO_NR(1, 13)
static iomux_v3_cfg_t const iox_pads[] = {
/* IOX_SDI */
MX7D_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* IOX_STCP */
MX7D_PAD_GPIO1_IO12__GPIO1_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* IOX_SHCP */
MX7D_PAD_GPIO1_IO13__GPIO1_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
/*
* PCIE_DIS_B --> Q0
* PCIE_RST_B --> Q1
* HDMI_RST_B --> Q2
* PERI_RST_B --> Q3
* SENSOR_RST_B --> Q4
* ENET_RST_B --> Q5
* PERI_3V3_EN --> Q6
* LCD_PWR_EN --> Q7
*/
enum qn {
PCIE_DIS_B,
PCIE_RST_B,
HDMI_RST_B,
PERI_RST_B,
SENSOR_RST_B,
ENET_RST_B,
PERI_3V3_EN,
LCD_PWR_EN,
};
enum qn_func {
qn_reset,
qn_enable,
qn_disable,
};
enum qn_level {
qn_low = 0,
qn_high = 1,
};
static enum qn_level seq[3][2] = {
{0, 1}, {1, 1}, {0, 0}
};
static enum qn_func qn_output[8] = {
qn_disable, qn_reset, qn_reset, qn_reset, qn_reset, qn_reset, qn_enable,
qn_disable
};
static void iox74lv_init(void)
{
int i;
for (i = 7; i >= 0; i--) {
gpio_direction_output(IOX_SHCP, 0);
gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]);
udelay(500);
gpio_direction_output(IOX_SHCP, 1);
udelay(500);
}
gpio_direction_output(IOX_STCP, 0);
udelay(500);
/*
* shift register will be output to pins
*/
gpio_direction_output(IOX_STCP, 1);
for (i = 7; i >= 0; i--) {
gpio_direction_output(IOX_SHCP, 0);
gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]);
udelay(500);
gpio_direction_output(IOX_SHCP, 1);
udelay(500);
}
gpio_direction_output(IOX_STCP, 0);
udelay(500);
/*
* shift register will be output to pins
*/
gpio_direction_output(IOX_STCP, 1);
};
#ifdef CONFIG_NAND_MXS
static iomux_v3_cfg_t const gpmi_pads[] = {
MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
@ -306,11 +160,13 @@ static int setup_lcd(void)
imx_iomux_v3_setup_multiple_pads(pwm_pads, ARRAY_SIZE(pwm_pads));
/* Reset LCD */
gpio_request(IMX_GPIO_NR(3, 4), "lcd reset");
gpio_direction_output(IMX_GPIO_NR(3, 4) , 0);
udelay(500);
gpio_direction_output(IMX_GPIO_NR(3, 4) , 1);
/* Set Brightness to high */
gpio_request(IMX_GPIO_NR(1, 1), "lcd backlight");
gpio_direction_output(IMX_GPIO_NR(1, 1) , 1);
return 0;
@ -346,17 +202,6 @@ static void setup_iomux_uart(void)
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
}
#ifdef CONFIG_FSL_ESDHC
#define USDHC1_CD_GPIO IMX_GPIO_NR(5, 0)
#define USDHC1_PWR_GPIO IMX_GPIO_NR(5, 2)
#define USDHC3_PWR_GPIO IMX_GPIO_NR(6, 11)
static struct fsl_esdhc_cfg usdhc_cfg[3] = {
{USDHC1_BASE_ADDR, 0, 4},
{USDHC3_BASE_ADDR},
};
int board_mmc_get_env_dev(int devno)
{
if (devno == 2)
@ -365,7 +210,7 @@ int board_mmc_get_env_dev(int devno)
return devno;
}
static int mmc_map_to_kernel_blk(int dev_no)
int mmc_map_to_kernel_blk(int dev_no)
{
if (dev_no == 1)
dev_no++;
@ -373,106 +218,27 @@ static int mmc_map_to_kernel_blk(int dev_no)
return dev_no;
}
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int ret = 0;
switch (cfg->esdhc_base) {
case USDHC1_BASE_ADDR:
ret = !gpio_get_value(USDHC1_CD_GPIO);
break;
case USDHC3_BASE_ADDR:
ret = 1; /* Assume uSDHC3 emmc is always present */
break;
}
return ret;
}
int board_mmc_init(bd_t *bis)
{
int i, ret;
/*
* According to the board_mmc_init() the following map is done:
* (U-Boot device node) (Physical Port)
* mmc0 USDHC1
* mmc2 USDHC3 (eMMC)
*/
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
imx_iomux_v3_setup_multiple_pads(
usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
gpio_request(USDHC1_CD_GPIO, "usdhc1_cd");
gpio_direction_input(USDHC1_CD_GPIO);
gpio_request(USDHC1_PWR_GPIO, "usdhc1_pwr");
gpio_direction_output(USDHC1_PWR_GPIO, 0);
udelay(500);
gpio_direction_output(USDHC1_PWR_GPIO, 1);
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
break;
case 1:
imx_iomux_v3_setup_multiple_pads(
usdhc3_emmc_pads, ARRAY_SIZE(usdhc3_emmc_pads));
gpio_request(USDHC3_PWR_GPIO, "usdhc3_pwr");
gpio_direction_output(USDHC3_PWR_GPIO, 0);
udelay(500);
gpio_direction_output(USDHC3_PWR_GPIO, 1);
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
break;
default:
printf("Warning: you configured more USDHC controllers"
"(%d) than supported by the board\n", i + 1);
return -EINVAL;
}
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
if (ret)
return ret;
}
return 0;
}
static int check_mmc_autodetect(void)
{
char *autodetect_str = getenv("mmcautodetect");
if ((autodetect_str != NULL) &&
(strcmp(autodetect_str, "yes") == 0)) {
return 1;
}
return 0;
}
static void mmc_late_init(void)
{
char cmd[32];
char mmcblk[32];
u32 dev_no = mmc_get_env_dev();
if (!check_mmc_autodetect())
return;
setenv_ulong("mmcdev", dev_no);
/* Set mmcblk env */
sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw",
mmc_map_to_kernel_blk(dev_no));
setenv("mmcroot", mmcblk);
sprintf(cmd, "mmc dev %d", dev_no);
run_command(cmd, 0);
}
#endif
#ifdef CONFIG_FEC_MXC
int board_eth_init(bd_t *bis)
{
int ret;
unsigned int gpio;
ret = gpio_lookup_name("gpio_spi@0_5", NULL, NULL, &gpio);
if (ret) {
printf("GPIO: 'gpio_spi@0_5' not found\n");
return -ENODEV;
}
ret = gpio_request(gpio, "fec_rst");
if (ret && ret != -EBUSY) {
printf("gpio: requesting pin %u failed\n", gpio);
return ret;
}
gpio_direction_output(gpio, 0);
udelay(500);
gpio_direction_output(gpio, 1);
setup_iomux_fec();
@ -539,12 +305,6 @@ int board_early_init_f(void)
{
setup_iomux_uart();
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
imx_iomux_v3_setup_multiple_pads(usb_otg1_pads,
ARRAY_SIZE(usb_otg1_pads));
imx_iomux_v3_setup_multiple_pads(usb_otg2_pads,
ARRAY_SIZE(usb_otg2_pads));
return 0;
}
@ -553,10 +313,6 @@ int board_init(void)
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
imx_iomux_v3_setup_multiple_pads(iox_pads, ARRAY_SIZE(iox_pads));
iox74lv_init();
#ifdef CONFIG_FEC_MXC
setup_fec();
#endif
@ -580,29 +336,23 @@ int board_init(void)
return 0;
}
#ifdef CONFIG_POWER
#define I2C_PMIC 0
#ifdef CONFIG_DM_PMIC
int power_init_board(void)
{
struct pmic *p;
int ret;
unsigned int reg, rev_id;
struct udevice *dev;
int ret, dev_id, rev_id;
ret = power_pfuze3000_init(I2C_PMIC);
if (ret)
ret = pmic_get("pfuze3000", &dev);
if (ret == -ENODEV)
return 0;
if (ret != 0)
return ret;
p = pmic_get("PFUZE3000");
ret = pmic_probe(p);
if (ret)
return ret;
dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID);
rev_id = pmic_reg_read(dev, PFUZE3000_REVID);
printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
pmic_reg_read(p, PFUZE3000_DEVICEID, &reg);
pmic_reg_read(p, PFUZE3000_REVID, &rev_id);
printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
/* disable Low Power Mode during standby mode */
pmic_reg_write(p, PFUZE3000_LDOGCTL, 0x1);
pmic_clrsetbits(dev, PFUZE3000_LDOGCTL, 0, 1);
return 0;
}
@ -612,10 +362,6 @@ int board_late_init(void)
{
struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
#ifdef CONFIG_ENV_IS_IN_MMC
mmc_late_init();
#endif
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
set_wdog_reset(wdog);
@ -642,13 +388,3 @@ int checkboard(void)
return 0;
}
#ifdef CONFIG_USB_EHCI_MX7
int board_usb_phy_mode(int port)
{
if (port == 0)
return USB_INIT_DEVICE;
else
return USB_INIT_HOST;
}
#endif

31
board/gateworks/gw_ventana/gw_ventana.c
View file

@ -1090,6 +1090,12 @@ void ft_board_pci_fixup(void *blob, bd_t *bd)
}
#endif /* if defined(CONFIG_CMD_PCI) */
void ft_board_wdog_fixup(void *blob, const char *path)
{
ft_delprop_path(blob, path, "ext-reset-output");
ft_delprop_path(blob, path, "fsl,ext-reset-output");
}
/*
* called prior to booting kernel or by 'fdt boardsetup' command
*
@ -1172,8 +1178,7 @@ int ft_board_setup(void *blob, bd_t *bd)
/* GW51xx-E adds WDOG1_B external reset */
if (rev < 'E')
ft_delprop_path(blob, WDOG1_PATH,
"fsl,ext-reset-output");
ft_board_wdog_fixup(blob, WDOG1_PATH);
break;
case GW52xx:
@ -1203,23 +1208,19 @@ int ft_board_setup(void *blob, bd_t *bd)
strstr((const char *)info->model, "SP331-B"))
gpio_cfg[board_type].usd_vsel = 0;
/* GW520x-E adds WDOG1_B external reset */
if (info->model[4] == '0' && rev < 'E')
ft_delprop_path(blob, WDOG1_PATH,
"fsl,ext-reset-output");
/* GW522x-B adds WDOG1_B external reset */
if (info->model[4] == '2' && rev < 'B')
ft_delprop_path(blob, WDOG1_PATH,
"fsl,ext-reset-output");
ft_board_wdog_fixup(blob, WDOG1_PATH);
}
/* GW520x-E adds WDOG1_B external reset */
else if (info->model[4] == '0' && rev < 'E')
ft_board_wdog_fixup(blob, WDOG1_PATH);
break;
case GW53xx:
/* GW53xx-E adds WDOG1_B external reset */
if (rev < 'E')
ft_delprop_path(blob, WDOG1_PATH,
"fsl,ext-reset-output");
ft_board_wdog_fixup(blob, WDOG1_PATH);
break;
case GW54xx:
@ -1233,8 +1234,7 @@ int ft_board_setup(void *blob, bd_t *bd)
/* GW54xx-E adds WDOG2_B external reset */
if (rev < 'E')
ft_delprop_path(blob, WDOG2_PATH,
"fsl,ext-reset-output");
ft_board_wdog_fixup(blob, WDOG2_PATH);
break;
case GW551x:
@ -1283,8 +1283,7 @@ int ft_board_setup(void *blob, bd_t *bd)
/* GW551x-C adds WDOG1_B external reset */
if (rev < 'C')
ft_delprop_path(blob, WDOG1_PATH,
"fsl,ext-reset-output");
ft_board_wdog_fixup(blob, WDOG1_PATH);
break;
}

44
configs/imx6dl_icore_mmc_defconfig
View file

@ -1,44 +0,0 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_MX6Q_ICORE=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
# CONFIG_CMD_BMODE is not set
CONFIG_VIDEO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6dl-icore"
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_MMC"
CONFIG_BOOTDELAY=3
CONFIG_DEFAULT_FDT_FILE="imx6dl-icore.dtb"
CONFIG_SPL=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="icorem6qdl> "
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
# CONFIG_BLK is not set
CONFIG_SYS_I2C_MXC=y
# CONFIG_DM_MMC_OPS is not set
CONFIG_FEC_MXC=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_MXC_UART=y
CONFIG_IMX_THERMAL=y
CONFIG_VIDEO_IPUV3=y

45
configs/imx6dl_icore_nand_defconfig
View file

@ -1,45 +0,0 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_MX6Q_ICORE=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
# CONFIG_CMD_BMODE is not set
CONFIG_VIDEO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6dl-icore"
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_NAND"
CONFIG_BOOTDELAY=3
CONFIG_DEFAULT_FDT_FILE="imx6dl-icore.dtb"
CONFIG_SPL=y
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="icorem6qdl> "
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_UBI=y
# CONFIG_BLK is not set
CONFIG_SYS_I2C_MXC=y
# CONFIG_DM_MMC_OPS is not set
CONFIG_NAND_MXS=y
CONFIG_FEC_MXC=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_MXC_UART=y
CONFIG_IMX_THERMAL=y
CONFIG_VIDEO_IPUV3=y

41
configs/imx6dl_icore_rqs_mmc_defconfig
View file

@ -1,41 +0,0 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_MX6Q_ICORE_RQS=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
# CONFIG_CMD_BMODE is not set
CONFIG_DEFAULT_DEVICE_TREE="imx6dl-icore-rqs"
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_MMC"
CONFIG_BOOTDELAY=3
CONFIG_DEFAULT_FDT_FILE="imx6dl-icore-rqs.dtb"
CONFIG_SPL=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="icorem6qdl-rqs> "
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
# CONFIG_BLK is not set
CONFIG_SYS_I2C_MXC=y
# CONFIG_DM_MMC_OPS is not set
CONFIG_FEC_MXC=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_MXC_UART=y

45
configs/imx6q_icore_nand_defconfig
View file

@ -1,45 +0,0 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_MX6Q_ICORE=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
# CONFIG_CMD_BMODE is not set
CONFIG_VIDEO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore"
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_NAND"
CONFIG_BOOTDELAY=3
CONFIG_DEFAULT_FDT_FILE="imx6q-icore.dtb"
CONFIG_SPL=y
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="icorem6qdl> "
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_UBI=y
# CONFIG_BLK is not set
CONFIG_SYS_I2C_MXC=y
# CONFIG_DM_MMC_OPS is not set
CONFIG_NAND_MXS=y
CONFIG_FEC_MXC=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_MXC_UART=y
CONFIG_IMX_THERMAL=y
CONFIG_VIDEO_IPUV3=y

2
configs/imx6q_icore_mmc_defconfig → configs/imx6qdl_icore_mmc_defconfig
View file

@ -10,12 +10,12 @@ CONFIG_SPL_WATCHDOG_SUPPORT=y
# CONFIG_CMD_BMODE is not set
CONFIG_VIDEO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore"
CONFIG_OF_LIST="imx6q-icore imx6dl-icore"
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_MMC"
CONFIG_BOOTDELAY=3
CONFIG_DEFAULT_FDT_FILE="imx6q-icore.dtb"
CONFIG_SPL=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_HUSH_PARSER=y

2
configs/imx6q_icore_rqs_mmc_defconfig → configs/imx6qdl_icore_rqs_mmc_defconfig
View file

@ -9,12 +9,12 @@ CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
# CONFIG_CMD_BMODE is not set
CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore-rqs"
CONFIG_OF_LIST="imx6q-icore-rqs imx6dl-icore-rqs"
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_MMC"
CONFIG_BOOTDELAY=3
CONFIG_DEFAULT_FDT_FILE="imx6q-icore-rqs.dtb"
CONFIG_SPL=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_HUSH_PARSER=y

1
configs/imx6ul_geam_mmc_defconfig
View file

@ -14,7 +14,6 @@ CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_MMC"
CONFIG_BOOTDELAY=3
CONFIG_DEFAULT_FDT_FILE="imx6ul-geam-kit.dtb"
CONFIG_SPL=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_HUSH_PARSER=y

1
configs/imx6ul_geam_nand_defconfig
View file

@ -13,7 +13,6 @@ CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_NAND"
CONFIG_BOOTDELAY=3
CONFIG_DEFAULT_FDT_FILE="imx6ul-geam-kit.dtb"
CONFIG_SPL=y
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_HUSH_PARSER=y

1
configs/imx6ul_isiot_emmc_defconfig
View file

@ -14,7 +14,6 @@ CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_MMC"
CONFIG_BOOTDELAY=3
CONFIG_DEFAULT_FDT_FILE="imx6ul-isiot-emmc.dtb"
CONFIG_SPL=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_HUSH_PARSER=y

1
configs/imx6ul_isiot_mmc_defconfig
View file

@ -14,7 +14,6 @@ CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_MMC"
CONFIG_BOOTDELAY=3
CONFIG_DEFAULT_FDT_FILE="imx6ul-isiot-emmc.dtb"
CONFIG_SPL=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_HUSH_PARSER=y

1
configs/imx6ul_isiot_nand_defconfig
View file

@ -13,7 +13,6 @@ CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_NAND"
CONFIG_BOOTDELAY=3
CONFIG_DEFAULT_FDT_FILE="imx6ul-isiot-nand.dtb"
CONFIG_SPL=y
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_HUSH_PARSER=y

44
configs/mx6dlsabresd_defconfig
View file

@ -1,44 +0,0 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_MX6SABRESD=y
CONFIG_VIDEO=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6dlsabresd.cfg,MX6DL"
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_DFU=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_DFU_MMC=y
CONFIG_DFU_SF=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PCI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_G_DNL_MANUFACTURER="FSL"
CONFIG_G_DNL_VENDOR_NUM=0x0525
CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_OF_LIBFDT=y

44
configs/mx6qsabresd_defconfig
View file

@ -1,44 +0,0 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_MX6SABRESD=y
CONFIG_VIDEO=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg,MX6Q"
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_DFU=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_DFU_MMC=y
CONFIG_DFU_SF=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PCI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_G_DNL_MANUFACTURER="FSL"
CONFIG_G_DNL_VENDOR_NUM=0x0525
CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_OF_LIBFDT=y

2
configs/mx6sabresd_spl_defconfig
View file

@ -9,7 +9,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_VIDEO=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,SPL,MX6Q"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,SPL,MX6QDL"
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y

25
configs/mx7dsabresd_defconfig
View file

@ -6,6 +6,7 @@ CONFIG_IMX_RDC=y
CONFIG_IMX_BOOTAUX=y
# CONFIG_CMD_BMODE is not set
CONFIG_VIDEO=y
CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg"
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
@ -30,13 +31,35 @@ CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_BMP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
# CONFIG_BLK is not set
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DM_GPIO=y
CONFIG_DM_74X164=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
# CONFIG_DM_MMC_OPS is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX7=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_PFUZE100=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_PFUZE100=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_SPI=y
CONFIG_SOFT_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_MXC_USB_OTG_HACTIVE=y
CONFIG_USB_STORAGE=y
@ -46,4 +69,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_G_DNL_MANUFACTURER="FSL"
CONFIG_G_DNL_VENDOR_NUM=0x0525
CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
CONFIG_OF_LIBFDT=y
CONFIG_ERRNO_STR=y

26
configs/mx7dsabresd_secure_defconfig
View file

@ -1,11 +1,13 @@
CONFIG_ARM=y
CONFIG_ARCH_MX7=y
CONFIG_TARGET_MX7DSABRESD=y
CONFIG_VIDEO=y
CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
# CONFIG_ARMV7_VIRT is not set
CONFIG_IMX_RDC=y
CONFIG_IMX_BOOTAUX=y
# CONFIG_CMD_BMODE is not set
CONFIG_VIDEO=y
CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg"
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
@ -31,15 +33,35 @@ CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_BMP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
# CONFIG_BLK is not set
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DM_GPIO=y
CONFIG_DM_74X164=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
# CONFIG_DM_MMC_OPS is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX7=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_PFUZE100=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_PFUZE100=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_SPI=y
CONFIG_SOFT_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_MXC_USB_OTG_HACTIVE=y
CONFIG_USB_STORAGE=y
@ -49,4 +71,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_G_DNL_MANUFACTURER="FSL"
CONFIG_G_DNL_VENDOR_NUM=0x0525
CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
CONFIG_OF_LIBFDT=y
CONFIG_ERRNO_STR=y

3
drivers/gpio/74x164_gpio.c
View file

@ -156,8 +156,7 @@ static int gen_74x164_probe(struct udevice *dev)
ret = gpio_request_by_name(dev, "oe-gpios", 0, &priv->oe,
GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
if (ret) {
dev_err(dev, "No oe-pins property\n");
goto free_buf;
dev_dbg(dev, "No oe-pins property\n");
}
uc_priv->bank_name = str;

17
drivers/net/fec_mxc.c
View file

@ -563,7 +563,7 @@ static int fec_init(struct eth_device *dev, bd_t *bd)
writel(0x00000000, &fec->eth->gaddr2);
/* Do not access reserved register for i.MX6UL */
if (!is_mx6ul()) {
if (!is_mx6ul() && !is_mx6ull()) {
/* clear MIB RAM */
for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
writel(0, i);
@ -1023,6 +1023,7 @@ static int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
struct eth_device *edev;
struct fec_priv *fec;
unsigned char ethaddr[6];
char mac[16];
uint32_t start;
int ret = 0;
@ -1085,12 +1086,18 @@ static int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
fec->phy_id = phy_id;
#endif
eth_register(edev);
/* only support one eth device, the index number pointed by dev_id */
edev->index = fec->dev_id;
if (fec_get_hwaddr(dev_id, ethaddr) == 0) {
debug("got MAC%d address from fuse: %pM\n", dev_id, ethaddr);
if (fec_get_hwaddr(fec->dev_id, ethaddr) == 0) {
debug("got MAC%d address from fuse: %pM\n", fec->dev_id, ethaddr);
memcpy(edev->enetaddr, ethaddr, 6);
if (!getenv("ethaddr"))
eth_setenv_enetaddr("ethaddr", ethaddr);
if (fec->dev_id)
sprintf(mac, "eth%daddr", fec->dev_id);
else
strcpy(mac, "ethaddr");
if (!getenv(mac))
eth_setenv_enetaddr(mac, ethaddr);
}
return ret;
err4:

4
drivers/pinctrl/nxp/pinctrl-imx.c
View file

@ -53,6 +53,7 @@ static int imx_pinctrl_set_state(struct udevice *dev, struct udevice *config)
if (fdtdec_get_int_array(gd->fdt_blob, node, "fsl,pins",
pin_data, size >> 2)) {
dev_err(dev, "Error reading pin data.\n");
devm_kfree(dev, pin_data);
return -EINVAL;
}
@ -78,6 +79,7 @@ static int imx_pinctrl_set_state(struct udevice *dev, struct udevice *config)
if ((mux_reg == -1) || (conf_reg == -1)) {
dev_err(dev, "Error mux_reg or conf_reg\n");
devm_kfree(dev, pin_data);
return -EINVAL;
}
@ -166,6 +168,8 @@ static int imx_pinctrl_set_state(struct udevice *dev, struct udevice *config)
}
}
devm_kfree(dev, pin_data);
return 0;
}

6
drivers/spi/Kconfig
View file

@ -197,6 +197,12 @@ config OMAP3_SPI
endif # if DM_SPI
config SOFT_SPI
bool "Soft SPI driver"
help
Enable Soft SPI driver. This driver is to use GPIO simulate
the SPI protocol.
config FSL_ESPI
bool "Freescale eSPI driver"
help

44
drivers/thermal/imx_thermal.c
View file

@ -16,14 +16,16 @@
#include <dm.h>
#include <errno.h>
#include <malloc.h>
#include <linux/math64.h>
#include <thermal.h>
#include <imx_thermal.h>
/* board will busyloop until this many degrees C below CPU max temperature */
#define TEMPERATURE_HOT_DELTA 5 /* CPU maxT - 5C */
#define FACTOR0 10000000
#define FACTOR1 15976
#define FACTOR2 4297157
#define FACTOR1 15423
#define FACTOR2 4148468
#define OFFSET 3580661
#define MEASURE_FREQ 327
#define TEMPERATURE_MIN -40
#define TEMPERATURE_HOT 85
@ -54,39 +56,43 @@ static int read_cpu_temperature(struct udevice *dev)
struct thermal_data *priv = dev_get_priv(dev);
u32 fuse = priv->fuse;
int t1, n1;
u32 c1, c2;
u64 temp64;
s64 c1, c2;
s64 temp64;
s32 rem;
/*
* Sensor data layout:
* [31:20] - sensor value @ 25C
* We use universal formula now and only need sensor value @ 25C
* slope = 0.4297157 - (0.0015976 * 25C fuse)
* slope = 0.4445388 - (0.0016549 * 25C fuse)
*/
n1 = fuse >> 20;
t1 = 25; /* t1 always 25C */
/*
* Derived from linear interpolation:
* slope = 0.4297157 - (0.0015976 * 25C fuse)
* slope = 0.4445388 - (0.0016549 * 25C fuse)
* slope = (FACTOR2 - FACTOR1 * n1) / FACTOR0
* (Nmeas - n1) / (Tmeas - t1) = slope
* offset = 3.580661
* offset = OFFSET / 1000000
* (Nmeas - n1) / (Tmeas - t1 - offset) = slope
* We want to reduce this down to the minimum computation necessary
* for each temperature read. Also, we want Tmeas in millicelsius
* and we don't want to lose precision from integer division. So...
* Tmeas = (Nmeas - n1) / slope + t1
* milli_Tmeas = 1000 * (Nmeas - n1) / slope + 1000 * t1
* milli_Tmeas = -1000 * (n1 - Nmeas) / slope + 1000 * t1
* Let constant c1 = (-1000 / slope)
* milli_Tmeas = (n1 - Nmeas) * c1 + 1000 * t1
* Let constant c2 = n1 *c1 + 1000 * t1
* milli_Tmeas = c2 - Nmeas * c1
* Tmeas = (Nmeas - n1) / slope + t1 + offset
* milli_Tmeas = 1000000 * (Nmeas - n1) / slope + 1000000 * t1 + OFFSET
* milli_Tmeas = -1000000 * (n1 - Nmeas) / slope + 1000000 * t1 + OFFSET
* Let constant c1 = (-1000000 / slope)
* milli_Tmeas = (n1 - Nmeas) * c1 + 1000000 * t1 + OFFSET
* Let constant c2 = n1 *c1 + 1000000 * t1
* milli_Tmeas = (c2 - Nmeas * c1) + OFFSET
* Tmeas = ((c2 - Nmeas * c1) + OFFSET) / 1000000
*/
temp64 = FACTOR0;
temp64 *= 1000;
do_div(temp64, FACTOR1 * n1 - FACTOR2);
temp64 *= 1000000;
temp64 = div_s64_rem(temp64, FACTOR1 * n1 - FACTOR2, &rem);
c1 = temp64;
c2 = n1 * c1 + 1000 * t1;
c2 = n1 * c1 + 1000000 * t1;
/*
* now we only use single measure, every time we read
@ -118,8 +124,8 @@ static int read_cpu_temperature(struct udevice *dev)
>> TEMPSENSE0_TEMP_CNT_SHIFT;
writel(TEMPSENSE0_FINISHED, &anatop->tempsense0_clr);
/* milli_Tmeas = c2 - Nmeas * c1 */
temperature = (long)(c2 - n_meas * c1)/1000;
/* Tmeas = (c2 - Nmeas * c1 + OFFSET) / 1000000 */
temperature = div_s64_rem(c2 - n_meas * c1 + OFFSET, 1000000, &rem);
/* power down anatop thermal sensor */
writel(TEMPSENSE0_POWER_DOWN, &anatop->tempsense0_set);

39
include/configs/imx6qdl_icore.h
View file

@ -42,12 +42,9 @@
"fit_image=fit.itb\0" \
"console=ttymxc3\0" \
"fdt_high=0xffffffff\0" \
"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
"fdt_addr=0x18000000\0" \
"boot_fdt=try\0" \
"mmcdev=0\0" \
"mmcpart=1\0" \
"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
"nandroot=ubi0:rootfs rootfstype=ubifs\0" \
"mmcautodetect=yes\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
@ -64,7 +61,7 @@
"fitboot=echo Booting FIT image from mmc ...; " \
"run mmcargs; " \
"bootm ${loadaddr}\0" \
"mmcboot=echo Booting from mmc ...; " \
"_mmcboot=run mmcargs; " \
"run mmcargs; " \
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
"if run loadfdt; then " \
@ -79,6 +76,20 @@
"else " \
"bootm; " \
"fi\0" \
"mmcboot=echo Booting from mmc ...; " \
"if mmc rescan; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \
"if run loadfit; then " \
"run fitboot; " \
"else " \
"if run loadimage; then " \
"run _mmcboot; " \
"fi; " \
"fi; " \
"fi; " \
"fi\0" \
"nandboot=echo Booting from nand ...; " \
"if mtdparts; then " \
"echo Starting nand boot ...; " \
@ -90,25 +101,7 @@
"nand read ${fdt_addr} dtb 0x100000; " \
"bootm ${loadaddr} - ${fdt_addr}\0"
#ifdef CONFIG_NAND_MXS
# define CONFIG_BOOTCOMMAND "run nandboot"
#else
# define CONFIG_BOOTCOMMAND \
"mmc dev ${mmcdev};" \
"if mmc rescan; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \
"if run loadfit; then " \
"run fitboot; " \
"else " \
"if run loadimage; then " \
"run mmcboot; " \
"fi; " \
"fi; " \
"fi; " \
"fi"
#endif
#define CONFIG_BOOTCOMMAND "run $modeboot"
/* Miscellaneous configurable options */
#define CONFIG_SYS_MEMTEST_START 0x80000000

1
include/configs/imx6qdl_icore_rqs.h
View file

@ -37,7 +37,6 @@
"fit_image=fit.itb\0" \
"console=ttymxc3\0" \
"fdt_high=0xffffffff\0" \
"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
"fdt_addr=0x18000000\0" \
"boot_fdt=try\0" \
"mmcpart=1\0" \

38
include/configs/imx6ul_geam.h
View file

@ -41,12 +41,9 @@
"fit_image=fit.itb\0" \
"console=ttymxc0\0" \
"fdt_high=0xffffffff\0" \
"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
"fdt_addr=0x87800000\0" \
"boot_fdt=try\0" \
"mmcdev=0\0" \
"mmcpart=1\0" \
"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
"nandroot=ubi0:rootfs rootfstype=ubifs\0" \
"mmcautodetect=yes\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
@ -63,7 +60,7 @@
"fitboot=echo Booting FIT image from mmc ...; " \
"run mmcargs; " \
"bootm ${loadaddr}\0" \
"mmcboot=echo Booting from mmc ...; " \
"_mmcboot=run mmcargs; " \
"run mmcargs; " \
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
"if run loadfdt; then " \
@ -78,6 +75,20 @@
"else " \
"bootm; " \
"fi\0" \
"mmcboot=echo Booting from mmc ...; " \
"if mmc rescan; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \
"if run loadfit; then " \
"run fitboot; " \
"else " \
"if run loadimage; then " \
"run _mmcboot; " \
"fi; " \
"fi; " \
"fi; " \
"fi\0" \
"nandboot=echo Booting from nand ...; " \
"if mtdparts; then " \
"echo Starting nand boot ...; " \
@ -89,24 +100,7 @@
"nand read ${fdt_addr} dtb 0x100000; " \
"bootm ${loadaddr} - ${fdt_addr}\0"
#ifdef CONFIG_NAND_MXS
# define CONFIG_BOOTCOMMAND "run nandboot"
#else
# define CONFIG_BOOTCOMMAND \
"if mmc rescan; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \
"if run loadfit; then " \
"run fitboot; " \
"else " \
"if run loadimage; then " \
"run mmcboot; " \
"fi; " \
"fi; " \
"fi; " \
"fi"
#endif
#define CONFIG_BOOTCOMMAND "run $modeboot"
/* Miscellaneous configurable options */
#define CONFIG_SYS_MEMTEST_START 0x80000000

1
include/configs/imx6ul_isiot.h
View file

@ -42,7 +42,6 @@
"splashpos=m,m\0" \
"console=ttymxc0\0" \
"fdt_high=0xffffffff\0" \
"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
"fdt_addr=0x87800000\0" \
"boot_fdt=try\0" \
"mmcpart=1\0" \

4
include/configs/mx25pdk.h
View file

@ -102,6 +102,10 @@
/* RTC */
#define CONFIG_RTC_IMXDI
/* Fuse API support */
#define CONFIG_FSL_IIM
#define CONFIG_CMD_FUSE
/* Ethernet Configs */

14
include/configs/mx7dsabresd.h
View file

@ -34,20 +34,12 @@
/* MMC Config*/
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
/* PMIC */
#define CONFIG_POWER
#define CONFIG_POWER_I2C
#define CONFIG_POWER_PFUZE3000
#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08
#undef CONFIG_BOOTM_NETBSD
#undef CONFIG_BOOTM_PLAN9
#undef CONFIG_BOOTM_RTEMS
/* I2C configs */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
@ -195,9 +187,6 @@
#define CONFIG_ENV_SIZE SZ_8K
#define CONFIG_ENV_IS_IN_MMC
/* MXC SPI driver support */
#define CONFIG_MXC_SPI
/*
* If want to use nand, define CONFIG_NAND_MXS and rework board
* to support nand, since emmc has pin conflicts with nand
@ -230,12 +219,9 @@
#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */
/* USB Configs */
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_ASIX
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS 0
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_IMX_THERMAL

454
include/dt-bindings/clock/imx7d-clock.h Normal file
View file

@ -0,0 +1,454 @@
/*
* Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __DT_BINDINGS_CLOCK_IMX7D_H
#define __DT_BINDINGS_CLOCK_IMX7D_H
#define IMX7D_OSC_24M_CLK 0
#define IMX7D_PLL_ARM_MAIN 1
#define IMX7D_PLL_ARM_MAIN_CLK 2
#define IMX7D_PLL_ARM_MAIN_SRC 3
#define IMX7D_PLL_ARM_MAIN_BYPASS 4
#define IMX7D_PLL_SYS_MAIN 5
#define IMX7D_PLL_SYS_MAIN_CLK 6
#define IMX7D_PLL_SYS_MAIN_SRC 7
#define IMX7D_PLL_SYS_MAIN_BYPASS 8
#define IMX7D_PLL_SYS_MAIN_480M 9
#define IMX7D_PLL_SYS_MAIN_240M 10
#define IMX7D_PLL_SYS_MAIN_120M 11
#define IMX7D_PLL_SYS_MAIN_480M_CLK 12
#define IMX7D_PLL_SYS_MAIN_240M_CLK 13
#define IMX7D_PLL_SYS_MAIN_120M_CLK 14
#define IMX7D_PLL_SYS_PFD0_392M_CLK 15
#define IMX7D_PLL_SYS_PFD0_196M 16
#define IMX7D_PLL_SYS_PFD0_196M_CLK 17
#define IMX7D_PLL_SYS_PFD1_332M_CLK 18
#define IMX7D_PLL_SYS_PFD1_166M 19
#define IMX7D_PLL_SYS_PFD1_166M_CLK 20
#define IMX7D_PLL_SYS_PFD2_270M_CLK 21
#define IMX7D_PLL_SYS_PFD2_135M 22
#define IMX7D_PLL_SYS_PFD2_135M_CLK 23
#define IMX7D_PLL_SYS_PFD3_CLK 24
#define IMX7D_PLL_SYS_PFD4_CLK 25
#define IMX7D_PLL_SYS_PFD5_CLK 26
#define IMX7D_PLL_SYS_PFD6_CLK 27
#define IMX7D_PLL_SYS_PFD7_CLK 28
#define IMX7D_PLL_ENET_MAIN 29
#define IMX7D_PLL_ENET_MAIN_CLK 30
#define IMX7D_PLL_ENET_MAIN_SRC 31
#define IMX7D_PLL_ENET_MAIN_BYPASS 32
#define IMX7D_PLL_ENET_MAIN_500M 33
#define IMX7D_PLL_ENET_MAIN_250M 34
#define IMX7D_PLL_ENET_MAIN_125M 35
#define IMX7D_PLL_ENET_MAIN_100M 36
#define IMX7D_PLL_ENET_MAIN_50M 37
#define IMX7D_PLL_ENET_MAIN_40M 38
#define IMX7D_PLL_ENET_MAIN_25M 39
#define IMX7D_PLL_ENET_MAIN_500M_CLK 40
#define IMX7D_PLL_ENET_MAIN_250M_CLK 41
#define IMX7D_PLL_ENET_MAIN_125M_CLK 42
#define IMX7D_PLL_ENET_MAIN_100M_CLK 43
#define IMX7D_PLL_ENET_MAIN_50M_CLK 44
#define IMX7D_PLL_ENET_MAIN_40M_CLK 45
#define IMX7D_PLL_ENET_MAIN_25M_CLK 46
#define IMX7D_PLL_DRAM_MAIN 47
#define IMX7D_PLL_DRAM_MAIN_CLK 48
#define IMX7D_PLL_DRAM_MAIN_SRC 49
#define IMX7D_PLL_DRAM_MAIN_BYPASS 50
#define IMX7D_PLL_DRAM_MAIN_533M 51
#define IMX7D_PLL_DRAM_MAIN_533M_CLK 52
#define IMX7D_PLL_AUDIO_MAIN 53
#define IMX7D_PLL_AUDIO_MAIN_CLK 54
#define IMX7D_PLL_AUDIO_MAIN_SRC 55
#define IMX7D_PLL_AUDIO_MAIN_BYPASS 56
#define IMX7D_PLL_VIDEO_MAIN_CLK 57
#define IMX7D_PLL_VIDEO_MAIN 58
#define IMX7D_PLL_VIDEO_MAIN_SRC 59
#define IMX7D_PLL_VIDEO_MAIN_BYPASS 60
#define IMX7D_USB_MAIN_480M_CLK 61
#define IMX7D_ARM_A7_ROOT_CLK 62
#define IMX7D_ARM_A7_ROOT_SRC 63
#define IMX7D_ARM_A7_ROOT_CG 64
#define IMX7D_ARM_A7_ROOT_DIV 65
#define IMX7D_ARM_M4_ROOT_CLK 66
#define IMX7D_ARM_M4_ROOT_SRC 67
#define IMX7D_ARM_M4_ROOT_CG 68
#define IMX7D_ARM_M4_ROOT_DIV 69
#define IMX7D_ARM_M0_ROOT_CLK 70
#define IMX7D_ARM_M0_ROOT_SRC 71
#define IMX7D_ARM_M0_ROOT_CG 72
#define IMX7D_ARM_M0_ROOT_DIV 73
#define IMX7D_MAIN_AXI_ROOT_CLK 74
#define IMX7D_MAIN_AXI_ROOT_SRC 75
#define IMX7D_MAIN_AXI_ROOT_CG 76
#define IMX7D_MAIN_AXI_ROOT_DIV 77
#define IMX7D_DISP_AXI_ROOT_CLK 78
#define IMX7D_DISP_AXI_ROOT_SRC 79
#define IMX7D_DISP_AXI_ROOT_CG 80
#define IMX7D_DISP_AXI_ROOT_DIV 81
#define IMX7D_ENET_AXI_ROOT_CLK 82
#define IMX7D_ENET_AXI_ROOT_SRC 83
#define IMX7D_ENET_AXI_ROOT_CG 84
#define IMX7D_ENET_AXI_ROOT_DIV 85
#define IMX7D_NAND_USDHC_BUS_ROOT_CLK 86
#define IMX7D_NAND_USDHC_BUS_ROOT_SRC 87
#define IMX7D_NAND_USDHC_BUS_ROOT_CG 88
#define IMX7D_NAND_USDHC_BUS_ROOT_DIV 89
#define IMX7D_AHB_CHANNEL_ROOT_CLK 90
#define IMX7D_AHB_CHANNEL_ROOT_SRC 91
#define IMX7D_AHB_CHANNEL_ROOT_CG 92
#define IMX7D_AHB_CHANNEL_ROOT_DIV 93
#define IMX7D_DRAM_PHYM_ROOT_CLK 94
#define IMX7D_DRAM_PHYM_ROOT_SRC 95
#define IMX7D_DRAM_PHYM_ROOT_CG 96
#define IMX7D_DRAM_PHYM_ROOT_DIV 97
#define IMX7D_DRAM_ROOT_CLK 98
#define IMX7D_DRAM_ROOT_SRC 99
#define IMX7D_DRAM_ROOT_CG 100
#define IMX7D_DRAM_ROOT_DIV 101
#define IMX7D_DRAM_PHYM_ALT_ROOT_CLK 102
#define IMX7D_DRAM_PHYM_ALT_ROOT_SRC 103
#define IMX7D_DRAM_PHYM_ALT_ROOT_CG 104
#define IMX7D_DRAM_PHYM_ALT_ROOT_DIV 105
#define IMX7D_DRAM_ALT_ROOT_CLK 106
#define IMX7D_DRAM_ALT_ROOT_SRC 107
#define IMX7D_DRAM_ALT_ROOT_CG 108
#define IMX7D_DRAM_ALT_ROOT_DIV 109
#define IMX7D_USB_HSIC_ROOT_CLK 110
#define IMX7D_USB_HSIC_ROOT_SRC 111
#define IMX7D_USB_HSIC_ROOT_CG 112
#define IMX7D_USB_HSIC_ROOT_DIV 113
#define IMX7D_PCIE_CTRL_ROOT_CLK 114
#define IMX7D_PCIE_CTRL_ROOT_SRC 115
#define IMX7D_PCIE_CTRL_ROOT_CG 116
#define IMX7D_PCIE_CTRL_ROOT_DIV 117
#define IMX7D_PCIE_PHY_ROOT_CLK 118
#define IMX7D_PCIE_PHY_ROOT_SRC 119
#define IMX7D_PCIE_PHY_ROOT_CG 120
#define IMX7D_PCIE_PHY_ROOT_DIV 121
#define IMX7D_EPDC_PIXEL_ROOT_CLK 122
#define IMX7D_EPDC_PIXEL_ROOT_SRC 123
#define IMX7D_EPDC_PIXEL_ROOT_CG 124
#define IMX7D_EPDC_PIXEL_ROOT_DIV 125
#define IMX7D_LCDIF_PIXEL_ROOT_CLK 126
#define IMX7D_LCDIF_PIXEL_ROOT_SRC 127
#define IMX7D_LCDIF_PIXEL_ROOT_CG 128
#define IMX7D_LCDIF_PIXEL_ROOT_DIV 129
#define IMX7D_MIPI_DSI_ROOT_CLK 130
#define IMX7D_MIPI_DSI_ROOT_SRC 131
#define IMX7D_MIPI_DSI_ROOT_CG 132
#define IMX7D_MIPI_DSI_ROOT_DIV 133
#define IMX7D_MIPI_CSI_ROOT_CLK 134
#define IMX7D_MIPI_CSI_ROOT_SRC 135
#define IMX7D_MIPI_CSI_ROOT_CG 136
#define IMX7D_MIPI_CSI_ROOT_DIV 137
#define IMX7D_MIPI_DPHY_ROOT_CLK 138
#define IMX7D_MIPI_DPHY_ROOT_SRC 139
#define IMX7D_MIPI_DPHY_ROOT_CG 140
#define IMX7D_MIPI_DPHY_ROOT_DIV 141
#define IMX7D_SAI1_ROOT_CLK 142
#define IMX7D_SAI1_ROOT_SRC 143
#define IMX7D_SAI1_ROOT_CG 144
#define IMX7D_SAI1_ROOT_DIV 145
#define IMX7D_SAI2_ROOT_CLK 146
#define IMX7D_SAI2_ROOT_SRC 147
#define IMX7D_SAI2_ROOT_CG 148
#define IMX7D_SAI2_ROOT_DIV 149
#define IMX7D_SAI3_ROOT_CLK 150
#define IMX7D_SAI3_ROOT_SRC 151
#define IMX7D_SAI3_ROOT_CG 152
#define IMX7D_SAI3_ROOT_DIV 153
#define IMX7D_SPDIF_ROOT_CLK 154
#define IMX7D_SPDIF_ROOT_SRC 155
#define IMX7D_SPDIF_ROOT_CG 156
#define IMX7D_SPDIF_ROOT_DIV 157
#define IMX7D_ENET1_REF_ROOT_CLK 158
#define IMX7D_ENET1_REF_ROOT_SRC 159
#define IMX7D_ENET1_REF_ROOT_CG 160
#define IMX7D_ENET1_REF_ROOT_DIV 161
#define IMX7D_ENET1_TIME_ROOT_CLK 162
#define IMX7D_ENET1_TIME_ROOT_SRC 163
#define IMX7D_ENET1_TIME_ROOT_CG 164
#define IMX7D_ENET1_TIME_ROOT_DIV 165
#define IMX7D_ENET2_REF_ROOT_CLK 166
#define IMX7D_ENET2_REF_ROOT_SRC 167
#define IMX7D_ENET2_REF_ROOT_CG 168
#define IMX7D_ENET2_REF_ROOT_DIV 169
#define IMX7D_ENET2_TIME_ROOT_CLK 170
#define IMX7D_ENET2_TIME_ROOT_SRC 171
#define IMX7D_ENET2_TIME_ROOT_CG 172
#define IMX7D_ENET2_TIME_ROOT_DIV 173
#define IMX7D_ENET_PHY_REF_ROOT_CLK 174
#define IMX7D_ENET_PHY_REF_ROOT_SRC 175
#define IMX7D_ENET_PHY_REF_ROOT_CG 176
#define IMX7D_ENET_PHY_REF_ROOT_DIV 177
#define IMX7D_EIM_ROOT_CLK 178
#define IMX7D_EIM_ROOT_SRC 179
#define IMX7D_EIM_ROOT_CG 180
#define IMX7D_EIM_ROOT_DIV 181
#define IMX7D_NAND_ROOT_CLK 182
#define IMX7D_NAND_ROOT_SRC 183
#define IMX7D_NAND_ROOT_CG 184
#define IMX7D_NAND_ROOT_DIV 185
#define IMX7D_QSPI_ROOT_CLK 186
#define IMX7D_QSPI_ROOT_SRC 187
#define IMX7D_QSPI_ROOT_CG 188
#define IMX7D_QSPI_ROOT_DIV 189
#define IMX7D_USDHC1_ROOT_CLK 190
#define IMX7D_USDHC1_ROOT_SRC 191
#define IMX7D_USDHC1_ROOT_CG 192
#define IMX7D_USDHC1_ROOT_DIV 193
#define IMX7D_USDHC2_ROOT_CLK 194
#define IMX7D_USDHC2_ROOT_SRC 195
#define IMX7D_USDHC2_ROOT_CG 196
#define IMX7D_USDHC2_ROOT_DIV 197
#define IMX7D_USDHC3_ROOT_CLK 198
#define IMX7D_USDHC3_ROOT_SRC 199
#define IMX7D_USDHC3_ROOT_CG 200
#define IMX7D_USDHC3_ROOT_DIV 201
#define IMX7D_CAN1_ROOT_CLK 202
#define IMX7D_CAN1_ROOT_SRC 203
#define IMX7D_CAN1_ROOT_CG 204
#define IMX7D_CAN1_ROOT_DIV 205
#define IMX7D_CAN2_ROOT_CLK 206
#define IMX7D_CAN2_ROOT_SRC 207
#define IMX7D_CAN2_ROOT_CG 208
#define IMX7D_CAN2_ROOT_DIV 209
#define IMX7D_I2C1_ROOT_CLK 210
#define IMX7D_I2C1_ROOT_SRC 211
#define IMX7D_I2C1_ROOT_CG 212
#define IMX7D_I2C1_ROOT_DIV 213
#define IMX7D_I2C2_ROOT_CLK 214
#define IMX7D_I2C2_ROOT_SRC 215
#define IMX7D_I2C2_ROOT_CG 216
#define IMX7D_I2C2_ROOT_DIV 217
#define IMX7D_I2C3_ROOT_CLK 218
#define IMX7D_I2C3_ROOT_SRC 219
#define IMX7D_I2C3_ROOT_CG 220
#define IMX7D_I2C3_ROOT_DIV 221
#define IMX7D_I2C4_ROOT_CLK 222
#define IMX7D_I2C4_ROOT_SRC 223
#define IMX7D_I2C4_ROOT_CG 224
#define IMX7D_I2C4_ROOT_DIV 225
#define IMX7D_UART1_ROOT_CLK 226
#define IMX7D_UART1_ROOT_SRC 227
#define IMX7D_UART1_ROOT_CG 228
#define IMX7D_UART1_ROOT_DIV 229
#define IMX7D_UART2_ROOT_CLK 230
#define IMX7D_UART2_ROOT_SRC 231
#define IMX7D_UART2_ROOT_CG 232
#define IMX7D_UART2_ROOT_DIV 233
#define IMX7D_UART3_ROOT_CLK 234
#define IMX7D_UART3_ROOT_SRC 235
#define IMX7D_UART3_ROOT_CG 236
#define IMX7D_UART3_ROOT_DIV 237
#define IMX7D_UART4_ROOT_CLK 238
#define IMX7D_UART4_ROOT_SRC 239
#define IMX7D_UART4_ROOT_CG 240
#define IMX7D_UART4_ROOT_DIV 241
#define IMX7D_UART5_ROOT_CLK 242
#define IMX7D_UART5_ROOT_SRC 243
#define IMX7D_UART5_ROOT_CG 244
#define IMX7D_UART5_ROOT_DIV 245
#define IMX7D_UART6_ROOT_CLK 246
#define IMX7D_UART6_ROOT_SRC 247
#define IMX7D_UART6_ROOT_CG 248
#define IMX7D_UART6_ROOT_DIV 249
#define IMX7D_UART7_ROOT_CLK 250
#define IMX7D_UART7_ROOT_SRC 251
#define IMX7D_UART7_ROOT_CG 252
#define IMX7D_UART7_ROOT_DIV 253
#define IMX7D_ECSPI1_ROOT_CLK 254
#define IMX7D_ECSPI1_ROOT_SRC 255
#define IMX7D_ECSPI1_ROOT_CG 256
#define IMX7D_ECSPI1_ROOT_DIV 257
#define IMX7D_ECSPI2_ROOT_CLK 258
#define IMX7D_ECSPI2_ROOT_SRC 259
#define IMX7D_ECSPI2_ROOT_CG 260
#define IMX7D_ECSPI2_ROOT_DIV 261
#define IMX7D_ECSPI3_ROOT_CLK 262
#define IMX7D_ECSPI3_ROOT_SRC 263
#define IMX7D_ECSPI3_ROOT_CG 264
#define IMX7D_ECSPI3_ROOT_DIV 265
#define IMX7D_ECSPI4_ROOT_CLK 266
#define IMX7D_ECSPI4_ROOT_SRC 267
#define IMX7D_ECSPI4_ROOT_CG 268
#define IMX7D_ECSPI4_ROOT_DIV 269
#define IMX7D_PWM1_ROOT_CLK 270
#define IMX7D_PWM1_ROOT_SRC 271
#define IMX7D_PWM1_ROOT_CG 272
#define IMX7D_PWM1_ROOT_DIV 273
#define IMX7D_PWM2_ROOT_CLK 274
#define IMX7D_PWM2_ROOT_SRC 275
#define IMX7D_PWM2_ROOT_CG 276
#define IMX7D_PWM2_ROOT_DIV 277
#define IMX7D_PWM3_ROOT_CLK 278
#define IMX7D_PWM3_ROOT_SRC 279
#define IMX7D_PWM3_ROOT_CG 280
#define IMX7D_PWM3_ROOT_DIV 281
#define IMX7D_PWM4_ROOT_CLK 282
#define IMX7D_PWM4_ROOT_SRC 283
#define IMX7D_PWM4_ROOT_CG 284
#define IMX7D_PWM4_ROOT_DIV 285
#define IMX7D_FLEXTIMER1_ROOT_CLK 286
#define IMX7D_FLEXTIMER1_ROOT_SRC 287
#define IMX7D_FLEXTIMER1_ROOT_CG 288
#define IMX7D_FLEXTIMER1_ROOT_DIV 289
#define IMX7D_FLEXTIMER2_ROOT_CLK 290
#define IMX7D_FLEXTIMER2_ROOT_SRC 291
#define IMX7D_FLEXTIMER2_ROOT_CG 292
#define IMX7D_FLEXTIMER2_ROOT_DIV 293
#define IMX7D_SIM1_ROOT_CLK 294
#define IMX7D_SIM1_ROOT_SRC 295
#define IMX7D_SIM1_ROOT_CG 296
#define IMX7D_SIM1_ROOT_DIV 297
#define IMX7D_SIM2_ROOT_CLK 298
#define IMX7D_SIM2_ROOT_SRC 299
#define IMX7D_SIM2_ROOT_CG 300
#define IMX7D_SIM2_ROOT_DIV 301
#define IMX7D_GPT1_ROOT_CLK 302
#define IMX7D_GPT1_ROOT_SRC 303
#define IMX7D_GPT1_ROOT_CG 304
#define IMX7D_GPT1_ROOT_DIV 305
#define IMX7D_GPT2_ROOT_CLK 306
#define IMX7D_GPT2_ROOT_SRC 307
#define IMX7D_GPT2_ROOT_CG 308
#define IMX7D_GPT2_ROOT_DIV 309
#define IMX7D_GPT3_ROOT_CLK 310
#define IMX7D_GPT3_ROOT_SRC 311
#define IMX7D_GPT3_ROOT_CG 312
#define IMX7D_GPT3_ROOT_DIV 313
#define IMX7D_GPT4_ROOT_CLK 314
#define IMX7D_GPT4_ROOT_SRC 315
#define IMX7D_GPT4_ROOT_CG 316
#define IMX7D_GPT4_ROOT_DIV 317
#define IMX7D_TRACE_ROOT_CLK 318
#define IMX7D_TRACE_ROOT_SRC 319
#define IMX7D_TRACE_ROOT_CG 320
#define IMX7D_TRACE_ROOT_DIV 321
#define IMX7D_WDOG1_ROOT_CLK 322
#define IMX7D_WDOG_ROOT_SRC 323
#define IMX7D_WDOG_ROOT_CG 324
#define IMX7D_WDOG_ROOT_DIV 325
#define IMX7D_CSI_MCLK_ROOT_CLK 326
#define IMX7D_CSI_MCLK_ROOT_SRC 327
#define IMX7D_CSI_MCLK_ROOT_CG 328
#define IMX7D_CSI_MCLK_ROOT_DIV 329
#define IMX7D_AUDIO_MCLK_ROOT_CLK 330
#define IMX7D_AUDIO_MCLK_ROOT_SRC 331
#define IMX7D_AUDIO_MCLK_ROOT_CG 332
#define IMX7D_AUDIO_MCLK_ROOT_DIV 333
#define IMX7D_WRCLK_ROOT_CLK 334
#define IMX7D_WRCLK_ROOT_SRC 335
#define IMX7D_WRCLK_ROOT_CG 336
#define IMX7D_WRCLK_ROOT_DIV 337
#define IMX7D_CLKO1_ROOT_SRC 338
#define IMX7D_CLKO1_ROOT_CG 339
#define IMX7D_CLKO1_ROOT_DIV 340
#define IMX7D_CLKO2_ROOT_SRC 341
#define IMX7D_CLKO2_ROOT_CG 342
#define IMX7D_CLKO2_ROOT_DIV 343
#define IMX7D_MAIN_AXI_ROOT_PRE_DIV 344
#define IMX7D_DISP_AXI_ROOT_PRE_DIV 345
#define IMX7D_ENET_AXI_ROOT_PRE_DIV 346
#define IMX7D_NAND_USDHC_BUS_ROOT_PRE_DIV 347
#define IMX7D_AHB_CHANNEL_ROOT_PRE_DIV 348
#define IMX7D_USB_HSIC_ROOT_PRE_DIV 349
#define IMX7D_PCIE_CTRL_ROOT_PRE_DIV 350
#define IMX7D_PCIE_PHY_ROOT_PRE_DIV 351
#define IMX7D_EPDC_PIXEL_ROOT_PRE_DIV 352
#define IMX7D_LCDIF_PIXEL_ROOT_PRE_DIV 353
#define IMX7D_MIPI_DSI_ROOT_PRE_DIV 354
#define IMX7D_MIPI_CSI_ROOT_PRE_DIV 355
#define IMX7D_MIPI_DPHY_ROOT_PRE_DIV 356
#define IMX7D_SAI1_ROOT_PRE_DIV 357
#define IMX7D_SAI2_ROOT_PRE_DIV 358
#define IMX7D_SAI3_ROOT_PRE_DIV 359
#define IMX7D_SPDIF_ROOT_PRE_DIV 360
#define IMX7D_ENET1_REF_ROOT_PRE_DIV 361
#define IMX7D_ENET1_TIME_ROOT_PRE_DIV 362
#define IMX7D_ENET2_REF_ROOT_PRE_DIV 363
#define IMX7D_ENET2_TIME_ROOT_PRE_DIV 364
#define IMX7D_ENET_PHY_REF_ROOT_PRE_DIV 365
#define IMX7D_EIM_ROOT_PRE_DIV 366
#define IMX7D_NAND_ROOT_PRE_DIV 367
#define IMX7D_QSPI_ROOT_PRE_DIV 368
#define IMX7D_USDHC1_ROOT_PRE_DIV 369
#define IMX7D_USDHC2_ROOT_PRE_DIV 370
#define IMX7D_USDHC3_ROOT_PRE_DIV 371
#define IMX7D_CAN1_ROOT_PRE_DIV 372
#define IMX7D_CAN2_ROOT_PRE_DIV 373
#define IMX7D_I2C1_ROOT_PRE_DIV 374
#define IMX7D_I2C2_ROOT_PRE_DIV 375
#define IMX7D_I2C3_ROOT_PRE_DIV 376
#define IMX7D_I2C4_ROOT_PRE_DIV 377
#define IMX7D_UART1_ROOT_PRE_DIV 378
#define IMX7D_UART2_ROOT_PRE_DIV 379
#define IMX7D_UART3_ROOT_PRE_DIV 380
#define IMX7D_UART4_ROOT_PRE_DIV 381
#define IMX7D_UART5_ROOT_PRE_DIV 382
#define IMX7D_UART6_ROOT_PRE_DIV 383
#define IMX7D_UART7_ROOT_PRE_DIV 384
#define IMX7D_ECSPI1_ROOT_PRE_DIV 385
#define IMX7D_ECSPI2_ROOT_PRE_DIV 386
#define IMX7D_ECSPI3_ROOT_PRE_DIV 387
#define IMX7D_ECSPI4_ROOT_PRE_DIV 388
#define IMX7D_PWM1_ROOT_PRE_DIV 389
#define IMX7D_PWM2_ROOT_PRE_DIV 390
#define IMX7D_PWM3_ROOT_PRE_DIV 391
#define IMX7D_PWM4_ROOT_PRE_DIV 392
#define IMX7D_FLEXTIMER1_ROOT_PRE_DIV 393
#define IMX7D_FLEXTIMER2_ROOT_PRE_DIV 394
#define IMX7D_SIM1_ROOT_PRE_DIV 395
#define IMX7D_SIM2_ROOT_PRE_DIV 396
#define IMX7D_GPT1_ROOT_PRE_DIV 397
#define IMX7D_GPT2_ROOT_PRE_DIV 398
#define IMX7D_GPT3_ROOT_PRE_DIV 399
#define IMX7D_GPT4_ROOT_PRE_DIV 400
#define IMX7D_TRACE_ROOT_PRE_DIV 401
#define IMX7D_WDOG_ROOT_PRE_DIV 402
#define IMX7D_CSI_MCLK_ROOT_PRE_DIV 403
#define IMX7D_AUDIO_MCLK_ROOT_PRE_DIV 404
#define IMX7D_WRCLK_ROOT_PRE_DIV 405
#define IMX7D_CLKO1_ROOT_PRE_DIV 406
#define IMX7D_CLKO2_ROOT_PRE_DIV 407
#define IMX7D_DRAM_PHYM_ALT_ROOT_PRE_DIV 408
#define IMX7D_DRAM_ALT_ROOT_PRE_DIV 409
#define IMX7D_LVDS1_IN_CLK 410
#define IMX7D_LVDS1_OUT_SEL 411
#define IMX7D_LVDS1_OUT_CLK 412
#define IMX7D_CLK_DUMMY 413
#define IMX7D_GPT_3M_CLK 414
#define IMX7D_OCRAM_CLK 415
#define IMX7D_OCRAM_S_CLK 416
#define IMX7D_WDOG2_ROOT_CLK 417
#define IMX7D_WDOG3_ROOT_CLK 418
#define IMX7D_WDOG4_ROOT_CLK 419
#define IMX7D_SDMA_CORE_CLK 420
#define IMX7D_USB1_MAIN_480M_CLK 421
#define IMX7D_USB_CTRL_CLK 422
#define IMX7D_USB_PHY1_CLK 423
#define IMX7D_USB_PHY2_CLK 424
#define IMX7D_IPG_ROOT_CLK 425
#define IMX7D_SAI1_IPG_CLK 426
#define IMX7D_SAI2_IPG_CLK 427
#define IMX7D_SAI3_IPG_CLK 428
#define IMX7D_PLL_AUDIO_TEST_DIV 429
#define IMX7D_PLL_AUDIO_POST_DIV 430
#define IMX7D_PLL_VIDEO_TEST_DIV 431
#define IMX7D_PLL_VIDEO_POST_DIV 432
#define IMX7D_MU_ROOT_CLK 433
#define IMX7D_SEMA4_HS_ROOT_CLK 434
#define IMX7D_PLL_DRAM_TEST_DIV 435
#define IMX7D_ADC_ROOT_CLK 436
#define IMX7D_CLK_ARM 437
#define IMX7D_CKIL 438
#define IMX7D_OCOTP_CLK 439
#define IMX7D_CLK_END 440
#endif /* __DT_BINDINGS_CLOCK_IMX7D_H */