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https://github.com/AsahiLinux/u-boot
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tsec: use IO accessors for IO accesses
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Detlev Zundel <dzu@denx.de>
This commit is contained in:
Mingkai Hu
Andy Fleming
parent
73e5476e1e
commit
a32a6be28f
2 changed files with 129 additions and 126 deletions
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@ -5,7 +5,7 @@
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* terms of the GNU Public License, Version 2, incorporated
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* herein by reference.
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*
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* Copyright 2004-2010 Freescale Semiconductor, Inc.
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* Copyright 2004-2011 Freescale Semiconductor, Inc.
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* (C) Copyright 2003, Motorola, Inc.
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* author Andy Fleming
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*
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@ -50,7 +50,7 @@ static int tsec_recv(struct eth_device *dev);
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static int tsec_init(struct eth_device *dev, bd_t * bd);
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static int tsec_initialize(bd_t * bis, struct tsec_info_struct *tsec_info);
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static void tsec_halt(struct eth_device *dev);
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static void init_registers(volatile tsec_t * regs);
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static void init_registers(tsec_t *regs);
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static void startup_tsec(struct eth_device *dev);
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static int init_phy(struct eth_device *dev);
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void write_phy_reg(struct tsec_private *priv, uint regnum, uint value);
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@ -166,9 +166,9 @@ static int tsec_initialize(bd_t * bis, struct tsec_info_struct *tsec_info)
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eth_register(dev);
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/* Reset the MAC */
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priv->regs->maccfg1 |= MACCFG1_SOFT_RESET;
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setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
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udelay(2); /* Soft Reset must be asserted for 3 TX clocks */
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priv->regs->maccfg1 &= ~(MACCFG1_SOFT_RESET);
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clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
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#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
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&& !defined(BITBANGMII)
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@ -190,16 +190,16 @@ static int tsec_init(struct eth_device *dev, bd_t * bd)
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char tmpbuf[MAC_ADDR_LEN];
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int i;
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struct tsec_private *priv = (struct tsec_private *)dev->priv;
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volatile tsec_t *regs = priv->regs;
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tsec_t *regs = priv->regs;
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/* Make sure the controller is stopped */
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tsec_halt(dev);
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/* Init MACCFG2. Defaults to GMII */
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regs->maccfg2 = MACCFG2_INIT_SETTINGS;
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out_be32(®s->maccfg2, MACCFG2_INIT_SETTINGS);
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/* Init ECNTRL */
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regs->ecntrl = ECNTRL_INIT_SETTINGS;
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out_be32(®s->ecntrl, ECNTRL_INIT_SETTINGS);
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/* Copy the station address into the address registers.
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* Backwards, because little endian MACS are dumb */
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@ -209,11 +209,11 @@ static int tsec_init(struct eth_device *dev, bd_t * bd)
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tempval = (tmpbuf[0] << 24) | (tmpbuf[1] << 16) | (tmpbuf[2] << 8) |
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tmpbuf[3];
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regs->macstnaddr1 = tempval;
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out_be32(®s->macstnaddr1, tempval);
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tempval = *((uint *) (tmpbuf + 4));
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regs->macstnaddr2 = tempval;
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out_be32(®s->macstnaddr2, tempval);
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/* reset the indices to zero */
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rxIdx = 0;
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@ -230,17 +230,17 @@ static int tsec_init(struct eth_device *dev, bd_t * bd)
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}
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/* Writes the given phy's reg with value, using the specified MDIO regs */
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static void tsec_local_mdio_write(volatile tsec_mdio_t *phyregs, uint addr,
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static void tsec_local_mdio_write(tsec_mdio_t *phyregs, uint addr,
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uint reg, uint value)
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{
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int timeout = 1000000;
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phyregs->miimadd = (addr << 8) | reg;
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phyregs->miimcon = value;
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asm("sync");
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out_be32(&phyregs->miimadd, (addr << 8) | reg);
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out_be32(&phyregs->miimcon, value);
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timeout = 1000000;
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while ((phyregs->miimind & MIIMIND_BUSY) && timeout--) ;
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while ((in_be32(&phyregs->miimind) & MIIMIND_BUSY) && timeout--)
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;
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}
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@ -254,28 +254,26 @@ static void tsec_local_mdio_write(volatile tsec_mdio_t *phyregs, uint addr,
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* notvalid bit cleared), and the bus to cease activity (miimind
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* busy bit cleared), and then returns the value
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*/
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static uint tsec_local_mdio_read(volatile tsec_mdio_t *phyregs,
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uint phyid, uint regnum)
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static uint tsec_local_mdio_read(tsec_mdio_t *phyregs, uint phyid, uint regnum)
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{
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uint value;
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/* Put the address of the phy, and the register
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* number into MIIMADD */
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phyregs->miimadd = (phyid << 8) | regnum;
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out_be32(&phyregs->miimadd, (phyid << 8) | regnum);
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/* Clear the command register, and wait */
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phyregs->miimcom = 0;
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asm("sync");
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out_be32(&phyregs->miimcom, 0);
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/* Initiate a read command, and wait */
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phyregs->miimcom = MIIM_READ_COMMAND;
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asm("sync");
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out_be32(&phyregs->miimcom, MIIM_READ_COMMAND);
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/* Wait for the the indication that the read is done */
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while ((phyregs->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY))) ;
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while ((in_be32(&phyregs->miimind) & (MIIMIND_NOTVALID | MIIMIND_BUSY)))
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;
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/* Grab the value read from the PHY */
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value = phyregs->miimstat;
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value = in_be32(&phyregs->miimstat);
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return value;
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}
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@ -321,18 +319,16 @@ static int init_phy(struct eth_device *dev)
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{
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struct tsec_private *priv = (struct tsec_private *)dev->priv;
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struct phy_info *curphy;
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volatile tsec_t *regs = priv->regs;
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tsec_t *regs = priv->regs;
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/* Assign a Physical address to the TBI */
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regs->tbipa = CONFIG_SYS_TBIPA_VALUE;
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asm("sync");
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out_be32(®s->tbipa, CONFIG_SYS_TBIPA_VALUE);
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/* Reset MII (due to new addresses) */
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priv->phyregs->miimcfg = MIIMCFG_RESET;
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asm("sync");
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priv->phyregs->miimcfg = MIIMCFG_INIT_VALUE;
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asm("sync");
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while (priv->phyregs->miimind & MIIMIND_BUSY) ;
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out_be32(&priv->phyregs->miimcfg, MIIMCFG_RESET);
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out_be32(&priv->phyregs->miimcfg, MIIMCFG_INIT_VALUE);
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while (in_be32(&priv->phyregs->miimind) & MIIMIND_BUSY)
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;
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/* Get the cmd structure corresponding to the attached
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* PHY */
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@ -345,7 +341,7 @@ static int init_phy(struct eth_device *dev)
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return 0;
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}
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if (regs->ecntrl & ECNTRL_SGMII_MODE)
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if (in_be32(®s->ecntrl) & ECNTRL_SGMII_MODE)
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tsec_configure_serdes(priv);
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priv->phyinfo = curphy;
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@ -838,16 +834,16 @@ static uint mii_parse_dm9161_scsr(uint mii_reg, struct tsec_private * priv)
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static uint mii_cis8204_fixled(uint mii_reg, struct tsec_private * priv)
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{
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uint phyid;
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volatile tsec_mdio_t *regbase = priv->phyregs;
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tsec_mdio_t *regbase = priv->phyregs;
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int timeout = 1000000;
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for (phyid = 0; phyid < 4; phyid++) {
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regbase->miimadd = (phyid << 8) | mii_reg;
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regbase->miimcon = MIIM_CIS8204_SLEDCON_INIT;
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asm("sync");
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out_be32(®base->miimadd, (phyid << 8) | mii_reg);
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out_be32(®base->miimcon, MIIM_CIS8204_SLEDCON_INIT);
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timeout = 1000000;
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while ((regbase->miimind & MIIMIND_BUSY) && timeout--) ;
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while ((in_be32(®base->miimind) & MIIMIND_BUSY) && timeout--)
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;
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}
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return MIIM_CIS8204_SLEDCON_INIT;
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@ -874,45 +870,45 @@ static uint mii_m88e1111s_setmode(uint mii_reg, struct tsec_private *priv)
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* those we don't care about (unless zero is bad, in which case,
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* choose a more appropriate value)
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*/
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static void init_registers(volatile tsec_t * regs)
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static void init_registers(tsec_t *regs)
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{
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/* Clear IEVENT */
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regs->ievent = IEVENT_INIT_CLEAR;
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out_be32(®s->ievent, IEVENT_INIT_CLEAR);
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regs->imask = IMASK_INIT_CLEAR;
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out_be32(®s->imask, IMASK_INIT_CLEAR);
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regs->hash.iaddr0 = 0;
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regs->hash.iaddr1 = 0;
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regs->hash.iaddr2 = 0;
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regs->hash.iaddr3 = 0;
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regs->hash.iaddr4 = 0;
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regs->hash.iaddr5 = 0;
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regs->hash.iaddr6 = 0;
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regs->hash.iaddr7 = 0;
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out_be32(®s->hash.iaddr0, 0);
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out_be32(®s->hash.iaddr1, 0);
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out_be32(®s->hash.iaddr2, 0);
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out_be32(®s->hash.iaddr3, 0);
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out_be32(®s->hash.iaddr4, 0);
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out_be32(®s->hash.iaddr5, 0);
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out_be32(®s->hash.iaddr6, 0);
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out_be32(®s->hash.iaddr7, 0);
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regs->hash.gaddr0 = 0;
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regs->hash.gaddr1 = 0;
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regs->hash.gaddr2 = 0;
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regs->hash.gaddr3 = 0;
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regs->hash.gaddr4 = 0;
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regs->hash.gaddr5 = 0;
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regs->hash.gaddr6 = 0;
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regs->hash.gaddr7 = 0;
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out_be32(®s->hash.gaddr0, 0);
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out_be32(®s->hash.gaddr1, 0);
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out_be32(®s->hash.gaddr2, 0);
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out_be32(®s->hash.gaddr3, 0);
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out_be32(®s->hash.gaddr4, 0);
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out_be32(®s->hash.gaddr5, 0);
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out_be32(®s->hash.gaddr6, 0);
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out_be32(®s->hash.gaddr7, 0);
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regs->rctrl = 0x00000000;
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out_be32(®s->rctrl, 0x00000000);
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/* Init RMON mib registers */
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memset((void *)&(regs->rmon), 0, sizeof(rmon_mib_t));
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regs->rmon.cam1 = 0xffffffff;
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regs->rmon.cam2 = 0xffffffff;
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out_be32(®s->rmon.cam1, 0xffffffff);
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out_be32(®s->rmon.cam2, 0xffffffff);
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regs->mrblr = MRBLR_INIT_SETTINGS;
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out_be32(®s->mrblr, MRBLR_INIT_SETTINGS);
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regs->minflr = MINFLR_INIT_SETTINGS;
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out_be32(®s->minflr, MINFLR_INIT_SETTINGS);
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regs->attr = ATTR_INIT_SETTINGS;
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regs->attreli = ATTRELI_INIT_SETTINGS;
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out_be32(®s->attr, ATTR_INIT_SETTINGS);
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out_be32(®s->attreli, ATTRELI_INIT_SETTINGS);
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}
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@ -922,44 +918,49 @@ static void init_registers(volatile tsec_t * regs)
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static void adjust_link(struct eth_device *dev)
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{
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struct tsec_private *priv = (struct tsec_private *)dev->priv;
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volatile tsec_t *regs = priv->regs;
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tsec_t *regs = priv->regs;
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u32 ecntrl, maccfg2;
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if (priv->link) {
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if (priv->duplexity != 0)
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regs->maccfg2 |= MACCFG2_FULL_DUPLEX;
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else
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regs->maccfg2 &= ~(MACCFG2_FULL_DUPLEX);
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switch (priv->speed) {
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case 1000:
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regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF))
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| MACCFG2_GMII);
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break;
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case 100:
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case 10:
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regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF))
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| MACCFG2_MII);
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/* Set R100 bit in all modes although
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* it is only used in RGMII mode
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*/
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if (priv->speed == 100)
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regs->ecntrl |= ECNTRL_R100;
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else
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regs->ecntrl &= ~(ECNTRL_R100);
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break;
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default:
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printf("%s: Speed was bad\n", dev->name);
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break;
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}
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printf("Speed: %d, %s duplex%s\n", priv->speed,
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(priv->duplexity) ? "full" : "half",
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(priv->flags & TSEC_FIBER) ? ", fiber mode" : "");
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} else {
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if (!priv->link) {
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printf("%s: No link.\n", dev->name);
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return;
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}
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/* clear all bits relative with interface mode */
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ecntrl = in_be32(®s->ecntrl);
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ecntrl &= ~ECNTRL_R100;
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maccfg2 = in_be32(®s->maccfg2);
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maccfg2 &= ~(MACCFG2_IF | MACCFG2_FULL_DUPLEX);
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if (priv->duplexity)
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maccfg2 |= MACCFG2_FULL_DUPLEX;
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switch (priv->speed) {
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case 1000:
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maccfg2 |= MACCFG2_GMII;
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break;
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case 100:
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case 10:
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maccfg2 |= MACCFG2_MII;
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/* Set R100 bit in all modes although
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* it is only used in RGMII mode
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*/
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if (priv->speed == 100)
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ecntrl |= ECNTRL_R100;
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break;
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default:
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printf("%s: Speed was bad\n", dev->name);
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break;
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}
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out_be32(®s->ecntrl, ecntrl);
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out_be32(®s->maccfg2, maccfg2);
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printf("Speed: %d, %s duplex%s\n", priv->speed,
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(priv->duplexity) ? "full" : "half",
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(priv->flags & TSEC_FIBER) ? ", fiber mode" : "");
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}
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/* Set up the buffers and their descriptors, and bring up the
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@ -969,11 +970,11 @@ static void startup_tsec(struct eth_device *dev)
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{
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int i;
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struct tsec_private *priv = (struct tsec_private *)dev->priv;
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volatile tsec_t *regs = priv->regs;
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tsec_t *regs = priv->regs;
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/* Point to the buffer descriptors */
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regs->tbase = (unsigned int)(&rtx.txbd[txIdx]);
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regs->rbase = (unsigned int)(&rtx.rxbd[rxIdx]);
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out_be32(®s->tbase, (unsigned int)(&rtx.txbd[txIdx]));
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out_be32(®s->rbase, (unsigned int)(&rtx.rxbd[rxIdx]));
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/* Initialize the Rx Buffer descriptors */
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for (i = 0; i < PKTBUFSRX; i++) {
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@ -998,13 +999,13 @@ static void startup_tsec(struct eth_device *dev)
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adjust_link(dev);
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/* Enable Transmit and Receive */
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regs->maccfg1 |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
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setbits_be32(®s->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
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/* Tell the DMA it is clear to go */
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regs->dmactrl |= DMACTRL_INIT_SETTINGS;
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regs->tstat = TSTAT_CLEAR_THALT;
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regs->rstat = RSTAT_CLEAR_RHALT;
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regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
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setbits_be32(®s->dmactrl, DMACTRL_INIT_SETTINGS);
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out_be32(®s->tstat, TSTAT_CLEAR_THALT);
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out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
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clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
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}
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/* This returns the status bits of the device. The return value
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@ -1017,7 +1018,7 @@ static int tsec_send(struct eth_device *dev, volatile void *packet, int length)
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int i;
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int result = 0;
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struct tsec_private *priv = (struct tsec_private *)dev->priv;
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volatile tsec_t *regs = priv->regs;
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tsec_t *regs = priv->regs;
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/* Find an empty buffer descriptor */
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for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
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@ -1033,7 +1034,7 @@ static int tsec_send(struct eth_device *dev, volatile void *packet, int length)
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(TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT);
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/* Tell the DMA to go */
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regs->tstat = TSTAT_CLEAR_THALT;
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out_be32(®s->tstat, TSTAT_CLEAR_THALT);
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/* Wait for buffer to be transmitted */
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for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
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@ -1053,7 +1054,7 @@ static int tsec_recv(struct eth_device *dev)
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{
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int length;
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struct tsec_private *priv = (struct tsec_private *)dev->priv;
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volatile tsec_t *regs = priv->regs;
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tsec_t *regs = priv->regs;
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while (!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) {
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@ -1076,9 +1077,9 @@ static int tsec_recv(struct eth_device *dev)
|
|||
rxIdx = (rxIdx + 1) % PKTBUFSRX;
|
||||
}
|
||||
|
||||
if (regs->ievent & IEVENT_BSY) {
|
||||
regs->ievent = IEVENT_BSY;
|
||||
regs->rstat = RSTAT_CLEAR_RHALT;
|
||||
if (in_be32(®s->ievent) & IEVENT_BSY) {
|
||||
out_be32(®s->ievent, IEVENT_BSY);
|
||||
out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
|
||||
}
|
||||
|
||||
return -1;
|
||||
|
|
@ -1089,15 +1090,16 @@ static int tsec_recv(struct eth_device *dev)
|
|||
static void tsec_halt(struct eth_device *dev)
|
||||
{
|
||||
struct tsec_private *priv = (struct tsec_private *)dev->priv;
|
||||
volatile tsec_t *regs = priv->regs;
|
||||
tsec_t *regs = priv->regs;
|
||||
|
||||
regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
|
||||
regs->dmactrl |= (DMACTRL_GRS | DMACTRL_GTS);
|
||||
clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
|
||||
setbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
|
||||
|
||||
while ((regs->ievent & (IEVENT_GRSC | IEVENT_GTSC))
|
||||
!= (IEVENT_GRSC | IEVENT_GTSC)) ;
|
||||
while ((in_be32(®s->ievent) & (IEVENT_GRSC | IEVENT_GTSC))
|
||||
!= (IEVENT_GRSC | IEVENT_GTSC))
|
||||
;
|
||||
|
||||
regs->maccfg1 &= ~(MACCFG1_TX_EN | MACCFG1_RX_EN);
|
||||
clrbits_be32(®s->maccfg1, MACCFG1_TX_EN | MACCFG1_RX_EN);
|
||||
|
||||
/* Shut down the PHY, as needed */
|
||||
if(priv->phyinfo)
|
||||
|
|
@ -1904,13 +1906,14 @@ static void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd)
|
|||
{
|
||||
int i;
|
||||
uint result;
|
||||
volatile tsec_mdio_t *phyregs = priv->phyregs;
|
||||
tsec_mdio_t *phyregs = priv->phyregs;
|
||||
|
||||
phyregs->miimcfg = MIIMCFG_RESET;
|
||||
out_be32(&phyregs->miimcfg, MIIMCFG_RESET);
|
||||
|
||||
phyregs->miimcfg = MIIMCFG_INIT_VALUE;
|
||||
out_be32(&phyregs->miimcfg, MIIMCFG_INIT_VALUE);
|
||||
|
||||
while (phyregs->miimind & MIIMIND_BUSY) ;
|
||||
while (in_be32(&phyregs->miimind) & MIIMIND_BUSY)
|
||||
;
|
||||
|
||||
for (i = 0; cmd->mii_reg != miim_end; i++) {
|
||||
if (cmd->mii_data == miim_read) {
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@
|
|||
* terms of the GNU Public License, Version 2, incorporated
|
||||
* herein by reference.
|
||||
*
|
||||
* Copyright 2004, 2007, 2009 Freescale Semiconductor, Inc.
|
||||
* Copyright 2004, 2007, 2009, 2011 Freescale Semiconductor, Inc.
|
||||
* (C) Copyright 2003, Motorola, Inc.
|
||||
* maintained by Xianghua Xiao (x.xiao@motorola.com)
|
||||
* author Andy Fleming
|
||||
|
|
@ -587,9 +587,9 @@ typedef struct tsec
|
|||
#define TSEC_FIBER (1 << 3) /* PHY uses fiber, eg 1000 Base-X */
|
||||
|
||||
struct tsec_private {
|
||||
volatile tsec_t *regs;
|
||||
volatile tsec_mdio_t *phyregs;
|
||||
volatile tsec_mdio_t *phyregs_sgmii;
|
||||
tsec_t *regs;
|
||||
tsec_mdio_t *phyregs;
|
||||
tsec_mdio_t *phyregs_sgmii;
|
||||
struct phy_info *phyinfo;
|
||||
uint phyaddr;
|
||||
u32 flags;
|
||||
|
|
|
|||
Loading…
Reference in a new issue