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SOUND: Add WM8994 codec
This patch adds driver for audio codec WM8994 Signed-off-by: R. Chandrasekar <rcsekar@samsung.com> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This commit is contained in:
Rajeshwari Shinde
Minkyu Kang
parent
511ed5fdd3
commit
a2d8e0a717
4 changed files with 1179 additions and 0 deletions
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@ -27,6 +27,7 @@ LIB := $(obj)libsound.o
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COBJS-$(CONFIG_SOUND) += sound.o
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COBJS-$(CONFIG_I2S) += samsung-i2s.o
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COBJS-$(CONFIG_SOUND_WM8994) += wm8994.o
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COBJS := $(COBJS-y)
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SRCS := $(COBJS:.o=.c)
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792
drivers/sound/wm8994.c
Normal file
792
drivers/sound/wm8994.c
Normal file
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@ -0,0 +1,792 @@
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/*
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* Copyright (C) 2012 Samsung Electronics
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* R. Chandrasekar <rcsekar@samsung.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <asm/arch/clk.h>
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#include <asm/arch/cpu.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <common.h>
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#include <div64.h>
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#include <i2c.h>
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#include <i2s.h>
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#include <sound.h>
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#include "wm8994.h"
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#include "wm8994_registers.h"
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/* defines for wm8994 system clock selection */
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#define SEL_MCLK1 0x00
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#define SEL_MCLK2 0x08
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#define SEL_FLL1 0x10
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#define SEL_FLL2 0x18
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/* fll config to configure fll */
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struct wm8994_fll_config {
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int src; /* Source */
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int in; /* Input frequency in Hz */
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int out; /* output frequency in Hz */
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};
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/* codec private data */
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struct wm8994_priv {
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enum wm8994_type type; /* codec type of wolfson */
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int revision; /* Revision */
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int sysclk[WM8994_MAX_AIF]; /* System clock frequency in Hz */
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int mclk[WM8994_MAX_AIF]; /* master clock frequency in Hz */
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int aifclk[WM8994_MAX_AIF]; /* audio interface clock in Hz */
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struct wm8994_fll_config fll[2]; /* fll config to configure fll */
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};
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/* wm 8994 supported sampling rate values */
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static unsigned int src_rate[] = {
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8000, 11025, 12000, 16000, 22050, 24000,
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32000, 44100, 48000, 88200, 96000
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};
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/* op clock divisions */
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static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
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/* lr clock frame size ratio */
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static int fs_ratios[] = {
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64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
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};
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/* bit clock divisors */
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static int bclk_divs[] = {
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10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
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640, 880, 960, 1280, 1760, 1920
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};
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static struct wm8994_priv g_wm8994_info;
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static unsigned char g_wm8994_i2c_dev_addr;
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/*
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* Initialise I2C for wm 8994
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*
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* @param bus no i2c bus number in which wm8994 is connected
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*/
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static void wm8994_i2c_init(int bus_no)
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{
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i2c_set_bus_num(bus_no);
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}
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/*
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* Writes value to a device register through i2c
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*
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* @param reg reg number to be write
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* @param data data to be writen to the above registor
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*
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* @return int value 1 for change, 0 for no change or negative error code.
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*/
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static int wm8994_i2c_write(unsigned int reg, unsigned short data)
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{
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unsigned char val[2];
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val[0] = (unsigned char)((data >> 8) & 0xff);
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val[1] = (unsigned char)(data & 0xff);
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debug("Write Addr : 0x%04X, Data : 0x%04X\n", reg, data);
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return i2c_write(g_wm8994_i2c_dev_addr, reg, 2, val, 2);
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}
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/*
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* Read a value from a device register through i2c
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*
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* @param reg reg number to be read
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* @param data address of read data to be stored
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*
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* @return int value 0 for success, -1 in case of error.
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*/
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static unsigned int wm8994_i2c_read(unsigned int reg , unsigned short *data)
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{
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unsigned char val[2];
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int ret;
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ret = i2c_read(g_wm8994_i2c_dev_addr, reg, 2, val, 2);
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if (ret != 0) {
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debug("%s: Error while reading register %#04x\n",
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__func__, reg);
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return -1;
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}
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*data = val[0];
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*data <<= 8;
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*data |= val[1];
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return 0;
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}
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/*
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* update device register bits through i2c
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*
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* @param reg codec register
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* @param mask register mask
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* @param value new value
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*
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* @return int value 1 if change in the register value,
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* 0 for no change or negative error code.
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*/
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static int wm8994_update_bits(unsigned int reg, unsigned short mask,
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unsigned short value)
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{
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int change , ret = 0;
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unsigned short old, new;
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if (wm8994_i2c_read(reg, &old) != 0)
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return -1;
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new = (old & ~mask) | (value & mask);
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change = (old != new) ? 1 : 0;
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if (change)
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ret = wm8994_i2c_write(reg, new);
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if (ret < 0)
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return ret;
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return change;
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}
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/*
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* Sets i2s set format
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*
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* @param aif_id Interface ID
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* @param fmt i2S format
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*
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* @return -1 for error and 0 Success.
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*/
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int wm8994_set_fmt(int aif_id, unsigned int fmt)
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{
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int ms_reg;
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int aif_reg;
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int ms = 0;
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int aif = 0;
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int aif_clk = 0;
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int error = 0;
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switch (aif_id) {
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case 1:
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ms_reg = WM8994_AIF1_MASTER_SLAVE;
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aif_reg = WM8994_AIF1_CONTROL_1;
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aif_clk = WM8994_AIF1_CLOCKING_1;
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break;
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case 2:
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ms_reg = WM8994_AIF2_MASTER_SLAVE;
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aif_reg = WM8994_AIF2_CONTROL_1;
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aif_clk = WM8994_AIF2_CLOCKING_1;
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break;
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default:
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debug("%s: Invalid audio interface selection\n", __func__);
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return -1;
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}
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switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
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case SND_SOC_DAIFMT_CBS_CFS:
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break;
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case SND_SOC_DAIFMT_CBM_CFM:
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ms = WM8994_AIF1_MSTR;
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break;
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default:
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debug("%s: Invalid i2s master selection\n", __func__);
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return -1;
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}
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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case SND_SOC_DAIFMT_DSP_B:
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aif |= WM8994_AIF1_LRCLK_INV;
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case SND_SOC_DAIFMT_DSP_A:
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aif |= 0x18;
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break;
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case SND_SOC_DAIFMT_I2S:
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aif |= 0x10;
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break;
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case SND_SOC_DAIFMT_RIGHT_J:
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break;
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case SND_SOC_DAIFMT_LEFT_J:
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aif |= 0x8;
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break;
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default:
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debug("%s: Invalid i2s format selection\n", __func__);
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return -1;
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}
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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case SND_SOC_DAIFMT_DSP_A:
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case SND_SOC_DAIFMT_DSP_B:
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/* frame inversion not valid for DSP modes */
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switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
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case SND_SOC_DAIFMT_NB_NF:
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break;
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case SND_SOC_DAIFMT_IB_NF:
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aif |= WM8994_AIF1_BCLK_INV;
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break;
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default:
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debug("%s: Invalid i2s frame inverse selection\n",
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__func__);
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return -1;
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}
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break;
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case SND_SOC_DAIFMT_I2S:
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case SND_SOC_DAIFMT_RIGHT_J:
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case SND_SOC_DAIFMT_LEFT_J:
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switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
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case SND_SOC_DAIFMT_NB_NF:
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break;
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case SND_SOC_DAIFMT_IB_IF:
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aif |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
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break;
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case SND_SOC_DAIFMT_IB_NF:
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aif |= WM8994_AIF1_BCLK_INV;
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break;
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case SND_SOC_DAIFMT_NB_IF:
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aif |= WM8994_AIF1_LRCLK_INV;
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break;
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default:
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debug("%s: Invalid i2s clock polarity selection\n",
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__func__);
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return -1;
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}
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break;
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default:
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debug("%s: Invalid i2s format selection\n", __func__);
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return -1;
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}
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error = wm8994_update_bits(aif_reg, WM8994_AIF1_BCLK_INV |
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WM8994_AIF1_LRCLK_INV_MASK | WM8994_AIF1_FMT_MASK, aif);
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error |= wm8994_update_bits(ms_reg, WM8994_AIF1_MSTR_MASK, ms);
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error |= wm8994_update_bits(aif_clk, WM8994_AIF1CLK_ENA_MASK,
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WM8994_AIF1CLK_ENA);
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if (error < 0) {
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debug("%s: codec register access error\n", __func__);
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return -1;
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}
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return 0;
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}
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/*
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* Sets hw params FOR WM8994
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*
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* @param wm8994 wm8994 information pointer
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* @param aif_id Audio interface ID
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* @param sampling_rate Sampling rate
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* @param bits_per_sample Bits per sample
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* @param Channels Channels in the given audio input
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*
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* @return -1 for error and 0 Success.
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*/
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static int wm8994_hw_params(struct wm8994_priv *wm8994, int aif_id,
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unsigned int sampling_rate, unsigned int bits_per_sample,
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unsigned int channels)
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{
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int aif1_reg;
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int aif2_reg;
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int bclk_reg;
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int bclk = 0;
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int rate_reg;
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int aif1 = 0;
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int aif2 = 0;
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int rate_val = 0;
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int id = aif_id - 1;
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int i, cur_val, best_val, bclk_rate, best;
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unsigned short reg_data;
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int ret = 0;
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switch (aif_id) {
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case 1:
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aif1_reg = WM8994_AIF1_CONTROL_1;
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aif2_reg = WM8994_AIF1_CONTROL_2;
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bclk_reg = WM8994_AIF1_BCLK;
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rate_reg = WM8994_AIF1_RATE;
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break;
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case 2:
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aif1_reg = WM8994_AIF2_CONTROL_1;
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aif2_reg = WM8994_AIF2_CONTROL_2;
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bclk_reg = WM8994_AIF2_BCLK;
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rate_reg = WM8994_AIF2_RATE;
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break;
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default:
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return -1;
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}
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bclk_rate = sampling_rate * 32;
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switch (bits_per_sample) {
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case 16:
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bclk_rate *= 16;
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break;
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case 20:
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bclk_rate *= 20;
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aif1 |= 0x20;
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break;
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case 24:
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bclk_rate *= 24;
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aif1 |= 0x40;
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break;
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case 32:
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bclk_rate *= 32;
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aif1 |= 0x60;
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break;
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default:
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return -1;
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}
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/* Try to find an appropriate sample rate; look for an exact match. */
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for (i = 0; i < ARRAY_SIZE(src_rate); i++)
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if (src_rate[i] == sampling_rate)
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break;
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if (i == ARRAY_SIZE(src_rate)) {
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debug("%s: Could not get the best matching samplingrate\n",
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__func__);
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return -1;
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}
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rate_val |= i << WM8994_AIF1_SR_SHIFT;
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/* AIFCLK/fs ratio; look for a close match in either direction */
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best = 0;
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best_val = abs((fs_ratios[0] * sampling_rate)
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- wm8994->aifclk[id]);
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for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
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cur_val = abs((fs_ratios[i] * sampling_rate)
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- wm8994->aifclk[id]);
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if (cur_val >= best_val)
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continue;
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best = i;
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best_val = cur_val;
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}
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rate_val |= best;
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/*
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* We may not get quite the right frequency if using
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* approximate clocks so look for the closest match that is
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* higher than the target (we need to ensure that there enough
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* BCLKs to clock out the samples).
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*/
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best = 0;
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for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
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cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
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if (cur_val < 0) /* BCLK table is sorted */
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break;
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best = i;
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}
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if (i == ARRAY_SIZE(bclk_divs)) {
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debug("%s: Could not get the best matching bclk division\n",
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__func__);
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return -1;
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}
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bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
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bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
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if (wm8994_i2c_read(aif1_reg, ®_data) != 0) {
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debug("%s: AIF1 register read Failed\n", __func__);
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return -1;
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}
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if ((channels == 1) && ((reg_data & 0x18) == 0x18))
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aif2 |= WM8994_AIF1_MONO;
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if (wm8994->aifclk[id] == 0) {
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debug("%s:Audio interface clock not set\n", __func__);
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return -1;
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}
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ret = wm8994_update_bits(aif1_reg, WM8994_AIF1_WL_MASK, aif1);
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ret |= wm8994_update_bits(aif2_reg, WM8994_AIF1_MONO, aif2);
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ret |= wm8994_update_bits(bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
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ret |= wm8994_update_bits(rate_reg, WM8994_AIF1_SR_MASK |
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WM8994_AIF1CLK_RATE_MASK, rate_val);
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debug("rate vale = %x , bclk val= %x\n", rate_val, bclk);
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if (ret < 0) {
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debug("%s: codec register access error\n", __func__);
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return -1;
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}
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return 0;
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}
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/*
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* Configures Audio interface Clock
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*
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* @param wm8994 wm8994 information pointer
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* @param aif Audio Interface ID
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*
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* @return -1 for error and 0 Success.
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*/
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static int configure_aif_clock(struct wm8994_priv *wm8994, int aif)
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{
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int rate;
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int reg1 = 0;
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int offset;
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int ret;
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/* AIF(1/0) register adress offset calculated */
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if (aif)
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offset = 4;
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else
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offset = 0;
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switch (wm8994->sysclk[aif]) {
|
||||
case WM8994_SYSCLK_MCLK1:
|
||||
reg1 |= SEL_MCLK1;
|
||||
rate = wm8994->mclk[0];
|
||||
break;
|
||||
|
||||
case WM8994_SYSCLK_MCLK2:
|
||||
reg1 |= SEL_MCLK2;
|
||||
rate = wm8994->mclk[1];
|
||||
break;
|
||||
|
||||
case WM8994_SYSCLK_FLL1:
|
||||
reg1 |= SEL_FLL1;
|
||||
rate = wm8994->fll[0].out;
|
||||
break;
|
||||
|
||||
case WM8994_SYSCLK_FLL2:
|
||||
reg1 |= SEL_FLL2;
|
||||
rate = wm8994->fll[1].out;
|
||||
break;
|
||||
|
||||
default:
|
||||
debug("%s: Invalid input clock selection [%d]\n",
|
||||
__func__, wm8994->sysclk[aif]);
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* if input clock frequenct is more than 135Mhz then divide */
|
||||
if (rate >= WM8994_MAX_INPUT_CLK_FREQ) {
|
||||
rate /= 2;
|
||||
reg1 |= WM8994_AIF1CLK_DIV;
|
||||
}
|
||||
|
||||
wm8994->aifclk[aif] = rate;
|
||||
|
||||
ret = wm8994_update_bits(WM8994_AIF1_CLOCKING_1 + offset,
|
||||
WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
|
||||
reg1);
|
||||
|
||||
ret |= wm8994_update_bits(WM8994_CLOCKING_1,
|
||||
WM8994_SYSCLK_SRC | WM8994_AIF2DSPCLK_ENA_MASK |
|
||||
WM8994_SYSDSPCLK_ENA_MASK, WM8994_SYSCLK_SRC |
|
||||
WM8994_AIF2DSPCLK_ENA | WM8994_SYSDSPCLK_ENA);
|
||||
|
||||
if (ret < 0) {
|
||||
debug("%s: codec register access error\n", __func__);
|
||||
return -1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Configures Audio interface for the given frequency
|
||||
*
|
||||
* @param wm8994 wm8994 information
|
||||
* @param aif_id Audio Interface
|
||||
* @param clk_id Input Clock ID
|
||||
* @param freq Sampling frequency in Hz
|
||||
*
|
||||
* @return -1 for error and 0 success.
|
||||
*/
|
||||
static int wm8994_set_sysclk(struct wm8994_priv *wm8994, int aif_id,
|
||||
int clk_id, unsigned int freq)
|
||||
{
|
||||
int i;
|
||||
int ret = 0;
|
||||
|
||||
wm8994->sysclk[aif_id - 1] = clk_id;
|
||||
|
||||
switch (clk_id) {
|
||||
case WM8994_SYSCLK_MCLK1:
|
||||
wm8994->mclk[0] = freq;
|
||||
if (aif_id == 2) {
|
||||
ret = wm8994_update_bits(WM8994_AIF1_CLOCKING_2 ,
|
||||
WM8994_AIF2DAC_DIV_MASK , 0);
|
||||
}
|
||||
break;
|
||||
|
||||
case WM8994_SYSCLK_MCLK2:
|
||||
/* TODO: Set GPIO AF */
|
||||
wm8994->mclk[1] = freq;
|
||||
break;
|
||||
|
||||
case WM8994_SYSCLK_FLL1:
|
||||
case WM8994_SYSCLK_FLL2:
|
||||
break;
|
||||
|
||||
case WM8994_SYSCLK_OPCLK:
|
||||
/*
|
||||
* Special case - a division (times 10) is given and
|
||||
* no effect on main clocking.
|
||||
*/
|
||||
if (freq) {
|
||||
for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
|
||||
if (opclk_divs[i] == freq)
|
||||
break;
|
||||
if (i == ARRAY_SIZE(opclk_divs)) {
|
||||
debug("%s frequency divisor not found\n",
|
||||
__func__);
|
||||
return -1;
|
||||
}
|
||||
ret = wm8994_update_bits(WM8994_CLOCKING_2,
|
||||
WM8994_OPCLK_DIV_MASK, i);
|
||||
ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_2,
|
||||
WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
|
||||
} else {
|
||||
ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_2,
|
||||
WM8994_OPCLK_ENA, 0);
|
||||
}
|
||||
|
||||
default:
|
||||
debug("%s Invalid input clock selection [%d]\n",
|
||||
__func__, clk_id);
|
||||
return -1;
|
||||
}
|
||||
|
||||
ret |= configure_aif_clock(wm8994, aif_id - 1);
|
||||
|
||||
if (ret < 0) {
|
||||
debug("%s: codec register access error\n", __func__);
|
||||
return -1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Initializes Volume for AIF2 to HP path
|
||||
*
|
||||
* @returns -1 for error and 0 Success.
|
||||
*
|
||||
*/
|
||||
static int wm8994_init_volume_aif2_dac1(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
/* Unmute AIF2DAC */
|
||||
ret = wm8994_update_bits(WM8994_AIF2_DAC_FILTERS_1,
|
||||
WM8994_AIF2DAC_MUTE_MASK, 0);
|
||||
|
||||
|
||||
ret |= wm8994_update_bits(WM8994_AIF2_DAC_LEFT_VOLUME,
|
||||
WM8994_AIF2DAC_VU_MASK | WM8994_AIF2DACL_VOL_MASK,
|
||||
WM8994_AIF2DAC_VU | 0xff);
|
||||
|
||||
ret |= wm8994_update_bits(WM8994_AIF2_DAC_RIGHT_VOLUME,
|
||||
WM8994_AIF2DAC_VU_MASK | WM8994_AIF2DACR_VOL_MASK,
|
||||
WM8994_AIF2DAC_VU | 0xff);
|
||||
|
||||
|
||||
ret |= wm8994_update_bits(WM8994_DAC1_LEFT_VOLUME,
|
||||
WM8994_DAC1_VU_MASK | WM8994_DAC1L_VOL_MASK |
|
||||
WM8994_DAC1L_MUTE_MASK, WM8994_DAC1_VU | 0xc0);
|
||||
|
||||
ret |= wm8994_update_bits(WM8994_DAC1_RIGHT_VOLUME,
|
||||
WM8994_DAC1_VU_MASK | WM8994_DAC1R_VOL_MASK |
|
||||
WM8994_DAC1R_MUTE_MASK, WM8994_DAC1_VU | 0xc0);
|
||||
/* Head Phone Volume */
|
||||
ret |= wm8994_i2c_write(WM8994_LEFT_OUTPUT_VOLUME, 0x12D);
|
||||
ret |= wm8994_i2c_write(WM8994_RIGHT_OUTPUT_VOLUME, 0x12D);
|
||||
|
||||
if (ret < 0) {
|
||||
debug("%s: codec register access error\n", __func__);
|
||||
return -1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Intialise wm8994 codec device
|
||||
*
|
||||
* @param wm8994 wm8994 information
|
||||
*
|
||||
* @returns -1 for error and 0 Success.
|
||||
*/
|
||||
static int wm8994_device_init(struct wm8994_priv *wm8994)
|
||||
{
|
||||
const char *devname;
|
||||
unsigned short reg_data;
|
||||
int ret;
|
||||
|
||||
wm8994_i2c_write(WM8994_SOFTWARE_RESET, WM8994_SW_RESET);/* Reset */
|
||||
|
||||
ret = wm8994_i2c_read(WM8994_SOFTWARE_RESET, ®_data);
|
||||
if (ret < 0) {
|
||||
debug("Failed to read ID register\n");
|
||||
goto err;
|
||||
}
|
||||
|
||||
if (reg_data == WM8994_ID) {
|
||||
devname = "WM8994";
|
||||
debug("Device registered as type %d\n", wm8994->type);
|
||||
wm8994->type = WM8994;
|
||||
} else {
|
||||
debug("Device is not a WM8994, ID is %x\n", ret);
|
||||
ret = -1;
|
||||
goto err;
|
||||
}
|
||||
|
||||
ret = wm8994_i2c_read(WM8994_CHIP_REVISION, ®_data);
|
||||
if (ret < 0) {
|
||||
debug("Failed to read revision register: %d\n", ret);
|
||||
goto err;
|
||||
}
|
||||
wm8994->revision = reg_data;
|
||||
debug("%s revision %c\n", devname, 'A' + wm8994->revision);
|
||||
|
||||
/* VMID Selection */
|
||||
ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_1,
|
||||
WM8994_VMID_SEL_MASK | WM8994_BIAS_ENA_MASK, 0x3);
|
||||
|
||||
/* Charge Pump Enable */
|
||||
ret |= wm8994_update_bits(WM8994_CHARGE_PUMP_1, WM8994_CP_ENA_MASK,
|
||||
WM8994_CP_ENA);
|
||||
|
||||
/* Head Phone Power Enable */
|
||||
ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_1,
|
||||
WM8994_HPOUT1L_ENA_MASK, WM8994_HPOUT1L_ENA);
|
||||
|
||||
ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_1,
|
||||
WM8994_HPOUT1R_ENA_MASK, WM8994_HPOUT1R_ENA);
|
||||
|
||||
/* Power enable for AIF2 and DAC1 */
|
||||
ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_5,
|
||||
WM8994_AIF2DACL_ENA_MASK | WM8994_AIF2DACR_ENA_MASK |
|
||||
WM8994_DAC1L_ENA_MASK | WM8994_DAC1R_ENA_MASK,
|
||||
WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA | WM8994_DAC1L_ENA |
|
||||
WM8994_DAC1R_ENA);
|
||||
|
||||
/* Head Phone Initialisation */
|
||||
ret |= wm8994_update_bits(WM8994_ANALOGUE_HP_1,
|
||||
WM8994_HPOUT1L_DLY_MASK | WM8994_HPOUT1R_DLY_MASK,
|
||||
WM8994_HPOUT1L_DLY | WM8994_HPOUT1R_DLY);
|
||||
|
||||
ret |= wm8994_update_bits(WM8994_DC_SERVO_1,
|
||||
WM8994_DCS_ENA_CHAN_0_MASK |
|
||||
WM8994_DCS_ENA_CHAN_1_MASK , WM8994_DCS_ENA_CHAN_0 |
|
||||
WM8994_DCS_ENA_CHAN_1);
|
||||
|
||||
ret |= wm8994_update_bits(WM8994_ANALOGUE_HP_1,
|
||||
WM8994_HPOUT1L_DLY_MASK |
|
||||
WM8994_HPOUT1R_DLY_MASK | WM8994_HPOUT1L_OUTP_MASK |
|
||||
WM8994_HPOUT1R_OUTP_MASK |
|
||||
WM8994_HPOUT1L_RMV_SHORT_MASK |
|
||||
WM8994_HPOUT1R_RMV_SHORT_MASK, WM8994_HPOUT1L_DLY |
|
||||
WM8994_HPOUT1R_DLY | WM8994_HPOUT1L_OUTP |
|
||||
WM8994_HPOUT1R_OUTP | WM8994_HPOUT1L_RMV_SHORT |
|
||||
WM8994_HPOUT1R_RMV_SHORT);
|
||||
|
||||
/* MIXER Config DAC1 to HP */
|
||||
ret |= wm8994_update_bits(WM8994_OUTPUT_MIXER_1,
|
||||
WM8994_DAC1L_TO_HPOUT1L_MASK, WM8994_DAC1L_TO_HPOUT1L);
|
||||
|
||||
ret |= wm8994_update_bits(WM8994_OUTPUT_MIXER_2,
|
||||
WM8994_DAC1R_TO_HPOUT1R_MASK, WM8994_DAC1R_TO_HPOUT1R);
|
||||
|
||||
/* Routing AIF2 to DAC1 */
|
||||
ret |= wm8994_update_bits(WM8994_DAC1_LEFT_MIXER_ROUTING,
|
||||
WM8994_AIF2DACL_TO_DAC1L_MASK,
|
||||
WM8994_AIF2DACL_TO_DAC1L);
|
||||
|
||||
ret |= wm8994_update_bits(WM8994_DAC1_RIGHT_MIXER_ROUTING,
|
||||
WM8994_AIF2DACR_TO_DAC1R_MASK,
|
||||
WM8994_AIF2DACR_TO_DAC1R);
|
||||
|
||||
/* GPIO Settings for AIF2 */
|
||||
/* B CLK */
|
||||
ret |= wm8994_update_bits(WM8994_GPIO_3, WM8994_GPIO_DIR_MASK |
|
||||
WM8994_GPIO_FUNCTION_MASK ,
|
||||
WM8994_GPIO_DIR_OUTPUT |
|
||||
WM8994_GPIO_FUNCTION_I2S_CLK);
|
||||
|
||||
/* LR CLK */
|
||||
ret |= wm8994_update_bits(WM8994_GPIO_4, WM8994_GPIO_DIR_MASK |
|
||||
WM8994_GPIO_FUNCTION_MASK,
|
||||
WM8994_GPIO_DIR_OUTPUT |
|
||||
WM8994_GPIO_FUNCTION_I2S_CLK);
|
||||
|
||||
/* DATA */
|
||||
ret |= wm8994_update_bits(WM8994_GPIO_5, WM8994_GPIO_DIR_MASK |
|
||||
WM8994_GPIO_FUNCTION_MASK,
|
||||
WM8994_GPIO_DIR_OUTPUT |
|
||||
WM8994_GPIO_FUNCTION_I2S_CLK);
|
||||
|
||||
ret |= wm8994_init_volume_aif2_dac1();
|
||||
if (ret < 0)
|
||||
goto err;
|
||||
|
||||
debug("%s: Codec chip init ok\n", __func__);
|
||||
return 0;
|
||||
err:
|
||||
debug("%s: Codec chip init error\n", __func__);
|
||||
return -1;
|
||||
}
|
||||
|
||||
/*wm8994 Device Initialisation */
|
||||
int wm8994_init(struct sound_codec_info *pcodec_info,
|
||||
enum en_audio_interface aif_id,
|
||||
int sampling_rate, int mclk_freq,
|
||||
int bits_per_sample, unsigned int channels)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
/* shift the device address by 1 for 7 bit addressing */
|
||||
g_wm8994_i2c_dev_addr = pcodec_info->i2c_dev_addr;
|
||||
wm8994_i2c_init(pcodec_info->i2c_bus);
|
||||
|
||||
if (pcodec_info->codec_type == CODEC_WM_8994)
|
||||
g_wm8994_info.type = WM8994;
|
||||
else {
|
||||
debug("%s: Codec id [%d] not defined\n", __func__,
|
||||
pcodec_info->codec_type);
|
||||
return -1;
|
||||
}
|
||||
|
||||
ret = wm8994_device_init(&g_wm8994_info);
|
||||
if (ret < 0) {
|
||||
debug("%s: wm8994 codec chip init failed\n", __func__);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = wm8994_set_sysclk(&g_wm8994_info, aif_id, WM8994_SYSCLK_MCLK1,
|
||||
mclk_freq);
|
||||
if (ret < 0) {
|
||||
debug("%s: wm8994 codec set sys clock failed\n", __func__);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = wm8994_hw_params(&g_wm8994_info, aif_id, sampling_rate,
|
||||
bits_per_sample, channels);
|
||||
|
||||
if (ret == 0) {
|
||||
ret = wm8994_set_fmt(aif_id, SND_SOC_DAIFMT_I2S |
|
||||
SND_SOC_DAIFMT_NB_NF |
|
||||
SND_SOC_DAIFMT_CBS_CFS);
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
87
drivers/sound/wm8994.h
Normal file
87
drivers/sound/wm8994.h
Normal file
|
|
@ -0,0 +1,87 @@
|
|||
/*
|
||||
* Copyright (C) 2012 Samsung Electronics
|
||||
* R. Chadrasekar <rcsekar@samsung.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __WM8994_H__
|
||||
#define __WM8994_H__
|
||||
|
||||
/* Sources for AIF1/2 SYSCLK - use with set_dai_sysclk() */
|
||||
#define WM8994_SYSCLK_MCLK1 1
|
||||
#define WM8994_SYSCLK_MCLK2 2
|
||||
#define WM8994_SYSCLK_FLL1 3
|
||||
#define WM8994_SYSCLK_FLL2 4
|
||||
|
||||
/* Avilable audi interface ports in wm8994 codec */
|
||||
enum en_audio_interface {
|
||||
WM8994_AIF1 = 1,
|
||||
WM8994_AIF2,
|
||||
WM8994_AIF3
|
||||
};
|
||||
|
||||
/* OPCLK is also configured with set_dai_sysclk, specify division*10 as rate. */
|
||||
#define WM8994_SYSCLK_OPCLK 5
|
||||
|
||||
#define WM8994_FLL1 1
|
||||
#define WM8994_FLL2 2
|
||||
|
||||
#define WM8994_FLL_SRC_MCLK1 1
|
||||
#define WM8994_FLL_SRC_MCLK2 2
|
||||
#define WM8994_FLL_SRC_LRCLK 3
|
||||
#define WM8994_FLL_SRC_BCLK 4
|
||||
|
||||
/* maximum available digital interfac in the dac to configure */
|
||||
#define WM8994_MAX_AIF 2
|
||||
|
||||
#define WM8994_MAX_INPUT_CLK_FREQ 13500000
|
||||
#define WM8994_ID 0x8994
|
||||
|
||||
enum wm8994_vmid_mode {
|
||||
WM8994_VMID_NORMAL,
|
||||
WM8994_VMID_FORCE,
|
||||
};
|
||||
|
||||
/* wm 8994 family devices */
|
||||
enum wm8994_type {
|
||||
WM8994 = 0,
|
||||
WM8958 = 1,
|
||||
WM1811 = 2,
|
||||
};
|
||||
|
||||
/*
|
||||
* intialise wm8994 sound codec device for the given configuration
|
||||
*
|
||||
* @param pcodec_info pointer value of the sound codec info structure
|
||||
* parsed from device tree
|
||||
* @param aif_id enum value of codec interface port in which
|
||||
* soc i2s is connected
|
||||
* @param sampling_rate Sampling rate ranges between from 8khz to 96khz
|
||||
* @param mclk_freq Master clock frequency.
|
||||
* @param bits_per_sample bits per Sample can be 16 or 24
|
||||
* @param channels Number of channnels, maximum 2
|
||||
*
|
||||
* @returns -1 for error and 0 Success.
|
||||
*/
|
||||
int wm8994_init(struct sound_codec_info *pcodec_info,
|
||||
enum en_audio_interface aif_id,
|
||||
int sampling_rate, int mclk_freq,
|
||||
int bits_per_sample, unsigned int channels);
|
||||
#endif /*__WM8994_H__ */
|
||||
299
drivers/sound/wm8994_registers.h
Normal file
299
drivers/sound/wm8994_registers.h
Normal file
|
|
@ -0,0 +1,299 @@
|
|||
/*
|
||||
* (C) Copyright 2012 Samsung Electronics
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __WM8994_REGISTERS_H__
|
||||
#define __WM8994_REGISTERS_H__
|
||||
|
||||
/*
|
||||
* Register values.
|
||||
*/
|
||||
#define WM8994_SOFTWARE_RESET 0x00
|
||||
#define WM8994_POWER_MANAGEMENT_1 0x01
|
||||
#define WM8994_POWER_MANAGEMENT_2 0x02
|
||||
#define WM8994_POWER_MANAGEMENT_5 0x05
|
||||
#define WM8994_LEFT_OUTPUT_VOLUME 0x1C
|
||||
#define WM8994_RIGHT_OUTPUT_VOLUME 0x1D
|
||||
#define WM8994_OUTPUT_MIXER_1 0x2D
|
||||
#define WM8994_OUTPUT_MIXER_2 0x2E
|
||||
#define WM8994_CHARGE_PUMP_1 0x4C
|
||||
#define WM8994_DC_SERVO_1 0x54
|
||||
#define WM8994_ANALOGUE_HP_1 0x60
|
||||
#define WM8994_CHIP_REVISION 0x100
|
||||
#define WM8994_AIF1_CLOCKING_1 0x200
|
||||
#define WM8994_AIF1_CLOCKING_2 0x201
|
||||
#define WM8994_AIF2_CLOCKING_1 0x204
|
||||
#define WM8994_CLOCKING_1 0x208
|
||||
#define WM8994_CLOCKING_2 0x209
|
||||
#define WM8994_AIF1_RATE 0x210
|
||||
#define WM8994_AIF2_RATE 0x211
|
||||
#define WM8994_RATE_STATUS 0x212
|
||||
#define WM8994_AIF1_CONTROL_1 0x300
|
||||
#define WM8994_AIF1_CONTROL_2 0x301
|
||||
#define WM8994_AIF1_MASTER_SLAVE 0x302
|
||||
#define WM8994_AIF1_BCLK 0x303
|
||||
#define WM8994_AIF2_CONTROL_1 0x310
|
||||
#define WM8994_AIF2_CONTROL_2 0x311
|
||||
#define WM8994_AIF2_MASTER_SLAVE 0x312
|
||||
#define WM8994_AIF2_BCLK 0x313
|
||||
#define WM8994_AIF2_DAC_LEFT_VOLUME 0x502
|
||||
#define WM8994_AIF2_DAC_RIGHT_VOLUME 0x503
|
||||
#define WM8994_AIF2_DAC_FILTERS_1 0x520
|
||||
#define WM8994_DAC1_LEFT_MIXER_ROUTING 0x601
|
||||
#define WM8994_DAC1_RIGHT_MIXER_ROUTING 0x602
|
||||
#define WM8994_DAC1_LEFT_VOLUME 0x610
|
||||
#define WM8994_DAC1_RIGHT_VOLUME 0x611
|
||||
#define WM8994_GPIO_3 0x702
|
||||
#define WM8994_GPIO_4 0x703
|
||||
#define WM8994_GPIO_5 0x704
|
||||
|
||||
/*
|
||||
* Field Definitions.
|
||||
*/
|
||||
|
||||
/*
|
||||
* R0 (0x00) - Software Reset
|
||||
*/
|
||||
/* SW_RESET */
|
||||
#define WM8994_SW_RESET 1
|
||||
/*
|
||||
* R1 (0x01) - Power Management (1)
|
||||
*/
|
||||
/* HPOUT1L_ENA */
|
||||
#define WM8994_HPOUT1L_ENA 0x0200
|
||||
/* HPOUT1L_ENA */
|
||||
#define WM8994_HPOUT1L_ENA_MASK 0x0200
|
||||
/* HPOUT1R_ENA */
|
||||
#define WM8994_HPOUT1R_ENA 0x0100
|
||||
/* HPOUT1R_ENA */
|
||||
#define WM8994_HPOUT1R_ENA_MASK 0x0100
|
||||
/* VMID_SEL - [2:1] */
|
||||
#define WM8994_VMID_SEL_MASK 0x0006
|
||||
/* BIAS_ENA */
|
||||
#define WM8994_BIAS_ENA 0x0001
|
||||
/* BIAS_ENA */
|
||||
#define WM8994_BIAS_ENA_MASK 0x0001
|
||||
|
||||
/*
|
||||
* R2 (0x02) - Power Management (2)
|
||||
*/
|
||||
/* OPCLK_ENA */
|
||||
#define WM8994_OPCLK_ENA 0x0800
|
||||
|
||||
/*
|
||||
* R5 (0x05) - Power Management (5)
|
||||
*/
|
||||
/* AIF2DACL_ENA */
|
||||
#define WM8994_AIF2DACL_ENA 0x2000
|
||||
#define WM8994_AIF2DACL_ENA_MASK 0x2000
|
||||
/* AIF2DACR_ENA */
|
||||
#define WM8994_AIF2DACR_ENA 0x1000
|
||||
#define WM8994_AIF2DACR_ENA_MASK 0x1000
|
||||
/* DAC1L_ENA */
|
||||
#define WM8994_DAC1L_ENA 0x0002
|
||||
#define WM8994_DAC1L_ENA_MASK 0x0002
|
||||
/* DAC1R_ENA */
|
||||
#define WM8994_DAC1R_ENA 0x0001
|
||||
#define WM8994_DAC1R_ENA_MASK 0x0001
|
||||
|
||||
/*
|
||||
* R45 (0x2D) - Output Mixer (1)
|
||||
*/
|
||||
/* DAC1L_TO_HPOUT1L */
|
||||
#define WM8994_DAC1L_TO_HPOUT1L 0x0100
|
||||
#define WM8994_DAC1L_TO_HPOUT1L_MASK 0x0100
|
||||
|
||||
/*
|
||||
* R46 (0x2E) - Output Mixer (2)
|
||||
*/
|
||||
/* DAC1R_TO_HPOUT1R */
|
||||
#define WM8994_DAC1R_TO_HPOUT1R 0x0100
|
||||
#define WM8994_DAC1R_TO_HPOUT1R_MASK 0x0100
|
||||
|
||||
/*
|
||||
* R76 (0x4C) - Charge Pump (1)
|
||||
*/
|
||||
/* CP_ENA */
|
||||
#define WM8994_CP_ENA 0x8000
|
||||
#define WM8994_CP_ENA_MASK 0x8000
|
||||
/*
|
||||
* R84 (0x54) - DC Servo (1)
|
||||
*/
|
||||
/* DCS_ENA_CHAN_1 */
|
||||
#define WM8994_DCS_ENA_CHAN_1 0x0002
|
||||
#define WM8994_DCS_ENA_CHAN_1_MASK 0x0002
|
||||
/* DCS_ENA_CHAN_0 */
|
||||
#define WM8994_DCS_ENA_CHAN_0 0x0001
|
||||
#define WM8994_DCS_ENA_CHAN_0_MASK 0x0001
|
||||
|
||||
/*
|
||||
* R96 (0x60) - Analogue HP (1)
|
||||
*/
|
||||
/* HPOUT1L_RMV_SHORT */
|
||||
#define WM8994_HPOUT1L_RMV_SHORT 0x0080
|
||||
#define WM8994_HPOUT1L_RMV_SHORT_MASK 0x0080
|
||||
/* HPOUT1L_OUTP */
|
||||
#define WM8994_HPOUT1L_OUTP 0x0040
|
||||
#define WM8994_HPOUT1L_OUTP_MASK 0x0040
|
||||
/* HPOUT1L_DLY */
|
||||
#define WM8994_HPOUT1L_DLY 0x0020
|
||||
#define WM8994_HPOUT1L_DLY_MASK 0x0020
|
||||
/* HPOUT1R_RMV_SHORT */
|
||||
#define WM8994_HPOUT1R_RMV_SHORT 0x0008
|
||||
#define WM8994_HPOUT1R_RMV_SHORT_MASK 0x0008
|
||||
/* HPOUT1R_OUTP */
|
||||
#define WM8994_HPOUT1R_OUTP 0x0004
|
||||
#define WM8994_HPOUT1R_OUTP_MASK 0x0004
|
||||
/* HPOUT1R_DLY */
|
||||
#define WM8994_HPOUT1R_DLY 0x0002
|
||||
#define WM8994_HPOUT1R_DLY_MASK 0x0002
|
||||
|
||||
/*
|
||||
* R512 (0x200) - AIF1 Clocking (1)
|
||||
*/
|
||||
/* AIF1CLK_SRC - [4:3] */
|
||||
#define WM8994_AIF1CLK_SRC_MASK 0x0018
|
||||
/* AIF1CLK_DIV */
|
||||
#define WM8994_AIF1CLK_DIV 0x0002
|
||||
/* AIF1CLK_ENA */
|
||||
#define WM8994_AIF1CLK_ENA 0x0001
|
||||
#define WM8994_AIF1CLK_ENA_MASK 0x0001
|
||||
|
||||
/*
|
||||
* R517 (0x205) - AIF2 Clocking (2)
|
||||
*/
|
||||
/* AIF2DAC_DIV - [5:3] */
|
||||
#define WM8994_AIF2DAC_DIV_MASK 0x0038
|
||||
|
||||
/*
|
||||
* R520 (0x208) - Clocking (1)
|
||||
*/
|
||||
/* AIF2DSPCLK_ENA */
|
||||
#define WM8994_AIF2DSPCLK_ENA 0x0004
|
||||
#define WM8994_AIF2DSPCLK_ENA_MASK 0x0004
|
||||
/* SYSDSPCLK_ENA */
|
||||
#define WM8994_SYSDSPCLK_ENA 0x0002
|
||||
#define WM8994_SYSDSPCLK_ENA_MASK 0x0002
|
||||
/* SYSCLK_SRC */
|
||||
#define WM8994_SYSCLK_SRC 0x0001
|
||||
|
||||
/*
|
||||
* R521 (0x209) - Clocking (2)
|
||||
*/
|
||||
/* OPCLK_DIV - [2:0] */
|
||||
#define WM8994_OPCLK_DIV_MASK 0x0007
|
||||
|
||||
/*
|
||||
* R528 (0x210) - AIF1 Rate
|
||||
*/
|
||||
/* AIF1_SR - [7:4] */
|
||||
#define WM8994_AIF1_SR_MASK 0x00F0
|
||||
#define WM8994_AIF1_SR_SHIFT 4
|
||||
/* AIF1CLK_RATE - [3:0] */
|
||||
#define WM8994_AIF1CLK_RATE_MASK 0x000F
|
||||
|
||||
/*
|
||||
* R768 (0x300) - AIF1 Control (1)
|
||||
*/
|
||||
/* AIF1_BCLK_INV */
|
||||
#define WM8994_AIF1_BCLK_INV 0x0100
|
||||
/* AIF1_LRCLK_INV */
|
||||
#define WM8994_AIF1_LRCLK_INV 0x0080
|
||||
#define WM8994_AIF1_LRCLK_INV_MASK 0x0080
|
||||
/* AIF1_WL - [6:5] */
|
||||
#define WM8994_AIF1_WL_MASK 0x0060
|
||||
/* AIF1_FMT - [4:3] */
|
||||
#define WM8994_AIF1_FMT_MASK 0x0018
|
||||
|
||||
/*
|
||||
* R769 (0x301) - AIF1 Control (2)
|
||||
*/
|
||||
/* AIF1_MONO */
|
||||
#define WM8994_AIF1_MONO 0x0100
|
||||
|
||||
/*
|
||||
* R770 (0x302) - AIF1 Master/Slave
|
||||
*/
|
||||
/* AIF1_MSTR */
|
||||
#define WM8994_AIF1_MSTR 0x4000
|
||||
#define WM8994_AIF1_MSTR_MASK 0x4000
|
||||
|
||||
/*
|
||||
* R771 (0x303) - AIF1 BCLK
|
||||
*/
|
||||
/* AIF1_BCLK_DIV - [8:4] */
|
||||
#define WM8994_AIF1_BCLK_DIV_MASK 0x01F0
|
||||
#define WM8994_AIF1_BCLK_DIV_SHIFT 4
|
||||
|
||||
/*
|
||||
* R1282 (0x502) - AIF2 DAC Left Volume
|
||||
*/
|
||||
/* AIF2DAC_VU */
|
||||
#define WM8994_AIF2DAC_VU 0x0100
|
||||
#define WM8994_AIF2DAC_VU_MASK 0x0100
|
||||
/* AIF2DACL_VOL - [7:0] */
|
||||
#define WM8994_AIF2DACL_VOL_MASK 0x00FF
|
||||
|
||||
/*
|
||||
* R1283 (0x503) - AIF2 DAC Right Volume
|
||||
*/
|
||||
/* AIF2DACR_VOL - [7:0] */
|
||||
#define WM8994_AIF2DACR_VOL_MASK 0x00FF
|
||||
|
||||
/*
|
||||
* R1312 (0x520) - AIF2 DAC Filters (1)
|
||||
*/
|
||||
/* AIF2DAC_MUTE */
|
||||
#define WM8994_AIF2DAC_MUTE_MASK 0x0200
|
||||
|
||||
/*
|
||||
* R1537 (0x601) - DAC1 Left Mixer Routing
|
||||
*/
|
||||
/* AIF2DACL_TO_DAC1L */
|
||||
#define WM8994_AIF2DACL_TO_DAC1L 0x0004
|
||||
#define WM8994_AIF2DACL_TO_DAC1L_MASK 0x0004
|
||||
|
||||
/*
|
||||
* R1538 (0x602) - DAC1 Right Mixer Routing
|
||||
*/
|
||||
/* AIF2DACR_TO_DAC1R */
|
||||
#define WM8994_AIF2DACR_TO_DAC1R 0x0004
|
||||
#define WM8994_AIF2DACR_TO_DAC1R_MASK 0x0004
|
||||
|
||||
/*
|
||||
* R1552 (0x610) - DAC1 Left Volume
|
||||
*/
|
||||
/* DAC1L_MUTE */
|
||||
#define WM8994_DAC1L_MUTE_MASK 0x0200
|
||||
/* DAC1_VU */
|
||||
#define WM8994_DAC1_VU 0x0100
|
||||
#define WM8994_DAC1_VU_MASK 0x0100
|
||||
/* DAC1L_VOL - [7:0] */
|
||||
#define WM8994_DAC1L_VOL_MASK 0x00FF
|
||||
|
||||
/*
|
||||
* R1553 (0x611) - DAC1 Right Volume
|
||||
*/
|
||||
/* DAC1R_MUTE */
|
||||
#define WM8994_DAC1R_MUTE_MASK 0x0200
|
||||
/* DAC1R_VOL - [7:0] */
|
||||
#define WM8994_DAC1R_VOL_MASK 0x00FF
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
/* OUTPUT PIN */
|
||||
#define WM8994_GPIO_DIR_OUTPUT 0x8000
|
||||
/* GPIO PIN MASK */
|
||||
#define WM8994_GPIO_DIR_MASK 0xFFE0
|
||||
/* I2S CLK */
|
||||
#define WM8994_GPIO_FUNCTION_I2S_CLK 0x0000
|
||||
/* GPn FN */
|
||||
#define WM8994_GPIO_FUNCTION_MASK 0x001F
|
||||
#endif
|
||||
Loading…
Reference in a new issue