mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-01 00:49:43 +00:00
Convert CONFIG_SKIP_LOWLEVEL_INIT et al to Kconfig
This converts the following to Kconfig: CONFIG_SKIP_LOWLEVEL_INIT CONFIG_SKIP_LOWLEVEL_INIT_ONLY In order to do this, we need to introduce SPL and TPL variants of these options so that we can clearly disable these options only in SPL in some cases, and both instances in other cases. Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini
parent
ab92b38a01
commit
a2ac2b964b
457 changed files with 512 additions and 310 deletions
16
README
16
README
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@ -2741,22 +2741,6 @@ Low Level (hardware related) configuration options:
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This only takes effect if the memory commands are activated
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globally (CONFIG_CMD_MEMORY).
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- CONFIG_SKIP_LOWLEVEL_INIT
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[ARM, NDS32, MIPS, RISC-V only] If this variable is defined, then certain
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low level initializations (like setting up the memory
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controller) are omitted and/or U-Boot does not
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relocate itself into RAM.
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Normally this variable MUST NOT be defined. The only
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exception is when U-Boot is loaded (to RAM) by some
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other boot loader or by a debugger which performs
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these initializations itself.
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- CONFIG_SKIP_LOWLEVEL_INIT_ONLY
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[ARM926EJ-S only] This allows just the call to lowlevel_init()
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to be skipped. The normal CP15 init (such as enabling the
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instruction cache) is still performed.
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- CONFIG_SPL_BUILD
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Set when the currently-running compilation is for an artifact
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that will end up in the SPL (as opposed to the TPL or U-Boot
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57
arch/Kconfig
57
arch/Kconfig
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@ -351,6 +351,63 @@ config SYS_DISABLE_DCACHE_OPS
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Note that, its up to the individual architectures to implement
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this functionality.
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config SKIP_LOWLEVEL_INIT
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bool "Skip the calls to certain low level initialization functions"
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depends on ARM || NDS32 || MIPS || RISCV
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help
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If enabled, then certain low level initializations (like setting up
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the memory controller) are omitted and/or U-Boot does not relocate
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itself into RAM.
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Normally this variable MUST NOT be defined. The only exception is
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when U-Boot is loaded (to RAM) by some other boot loader or by a
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debugger which performs these initializations itself.
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config SPL_SKIP_LOWLEVEL_INIT
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bool "Skip the calls to certain low level initialization functions"
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depends on SPL && (ARM || NDS32 || MIPS || RISCV)
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help
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If enabled, then certain low level initializations (like setting up
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the memory controller) are omitted and/or U-Boot does not relocate
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itself into RAM.
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Normally this variable MUST NOT be defined. The only exception is
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when U-Boot is loaded (to RAM) by some other boot loader or by a
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debugger which performs these initializations itself.
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config TPL_SKIP_LOWLEVEL_INIT
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bool "Skip the calls to certain low level initialization functions"
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depends on SPL && ARM
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help
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If enabled, then certain low level initializations (like setting up
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the memory controller) are omitted and/or U-Boot does not relocate
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itself into RAM.
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Normally this variable MUST NOT be defined. The only exception is
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when U-Boot is loaded (to RAM) by some other boot loader or by a
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debugger which performs these initializations itself.
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config SKIP_LOWLEVEL_INIT_ONLY
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bool "Skip the call to lowlevel_init during early boot ONLY"
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depends on ARM
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help
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This allows just the call to lowlevel_init() to be skipped. The
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normal CP15 init (such as enabling the instruction cache) is still
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performed.
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config SPL_SKIP_LOWLEVEL_INIT_ONLY
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bool "Skip the call to lowlevel_init during early boot ONLY"
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depends on SPL && ARM
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help
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This allows just the call to lowlevel_init() to be skipped. The
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normal CP15 init (such as enabling the instruction cache) is still
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performed.
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config TPL_SKIP_LOWLEVEL_INIT_ONLY
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bool "Skip the call to lowlevel_init during early boot ONLY"
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depends on TPL && ARM
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help
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This allows just the call to lowlevel_init() to be skipped. The
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normal CP15 init (such as enabling the instruction cache) is still
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performed.
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source "arch/arc/Kconfig"
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source "arch/arm/Kconfig"
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source "arch/m68k/Kconfig"
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@ -39,7 +39,7 @@ reset:
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msr cpsr,r0
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/* the mask ROM code should have PLL and others stable */
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
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bl cpu_init_crit
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#endif
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@ -62,7 +62,7 @@ c_runtime_cpu_setup:
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*
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*************************************************************************
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*/
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
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cpu_init_crit:
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/*
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* flush v4 I/D caches
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@ -81,7 +81,7 @@ cpu_init_crit:
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orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
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mcr p15, 0, r0, c1, c0, 0
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
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#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
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/*
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* Jump to board specific initialization... The Mask ROM will have already initialized
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* basic memory. Go here to bump up clock rate and handle wake up conditions.
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@ -91,4 +91,4 @@ cpu_init_crit:
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mov lr, ip /* restore link */
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#endif
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mov pc, lr /* back to my caller */
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#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
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#endif /* !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */
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@ -37,8 +37,8 @@ reset:
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* we do sys-critical inits only at reboot,
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* not when booting from ram!
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*/
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#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
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!defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
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#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) && \
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!CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
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bl cpu_init_crit
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#endif
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@ -62,8 +62,8 @@ c_runtime_cpu_setup:
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*************************************************************************
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*/
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#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
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!defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
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#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) && \
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!CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
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cpu_init_crit:
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mov ip, lr
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@ -76,4 +76,4 @@ cpu_init_crit:
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mov lr, ip
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mov pc, lr
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#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
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#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */
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@ -53,7 +53,7 @@ copyex:
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* we do sys-critical inits only at reboot,
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* not when booting from ram!
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*/
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
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bl cpu_init_crit
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#endif
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@ -78,7 +78,7 @@ c_runtime_cpu_setup:
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*/
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
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cpu_init_crit:
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/*
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* flush v4 I/D caches
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@ -97,7 +97,7 @@ cpu_init_crit:
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orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
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mcr p15, 0, r0, c1, c0, 0
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
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#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
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/*
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* before relocating, we have to setup RAM timing
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* because memory timing is board-dependend, you will
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@ -109,4 +109,4 @@ cpu_init_crit:
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mov lr, ip
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#endif
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mov pc, lr
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#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
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#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */
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@ -46,7 +46,7 @@ reset:
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* we do sys-critical inits only at reboot,
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* not when booting from ram!
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*/
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
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bl cpu_init_crit
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#endif
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@ -69,7 +69,7 @@ c_runtime_cpu_setup:
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*
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*************************************************************************
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*/
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
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cpu_init_crit:
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/*
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* flush D cache before disabling it
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@ -100,7 +100,7 @@ flush_dcache:
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#endif
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mcr p15, 0, r0, c1, c0, 0
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
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#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
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/*
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* Go setup Memory and board specific bits prior to relocation.
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*/
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@ -109,4 +109,4 @@ flush_dcache:
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mov lr, r4 /* restore link */
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#endif
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mov pc, lr /* back to my caller */
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#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
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#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */
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@ -45,7 +45,7 @@ reset:
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* we do sys-critical inits only at reboot,
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* not when booting from ram!
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*/
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
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bl cpu_init_crit
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#endif
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@ -70,7 +70,7 @@ c_runtime_cpu_setup:
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*/
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
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cpu_init_crit:
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/*
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* flush v4 I/D caches
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@ -89,7 +89,7 @@ cpu_init_crit:
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orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
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mcr p15, 0, r0, c1, c0, 0
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
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#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
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/*
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* Go setup Memory and board specific bits prior to relocation.
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*/
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@ -17,7 +17,7 @@ obj-$(CONFIG_EFI_LOADER) += sctlr.o
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obj-$(CONFIG_ARMV7_NONSEC) += exception_level.o
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endif
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ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y)
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ifneq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),y)
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obj-y += lowlevel_init.o
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endif
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@ -80,11 +80,11 @@ switch_to_hypervisor_ret:
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#endif
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/* the mask ROM code should have PLL and others stable */
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
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#ifdef CONFIG_CPU_V7A
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bl cpu_init_cp15
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#endif
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
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#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
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bl cpu_init_crit
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#endif
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#endif
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@ -320,8 +320,8 @@ skip_errata_801819:
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mov pc, r5 @ back to my caller
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ENDPROC(cpu_init_cp15)
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#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
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!defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
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#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) && \
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!CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
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/*************************************************************************
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*
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* CPU_init_critical registers
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@ -5,6 +5,7 @@ config ARCH_LS1012A
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select FSL_LAYERSCAPE
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select FSL_LSCH2
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select GICV2
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select SKIP_LOWLEVEL_INIT
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select SYS_FSL_SRDS_1
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select SYS_HAS_SERDES
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select SYS_FSL_DDR_BE
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@ -62,6 +63,7 @@ config ARCH_LS1043A
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select FSL_LSCH2
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select GICV2
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select HAS_FSL_XHCI_USB if USB_HOST
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select SKIP_LOWLEVEL_INIT
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select SYS_FSL_SRDS_1
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select SYS_HAS_SERDES
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select SYS_FSL_DDR
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@ -96,6 +98,7 @@ config ARCH_LS1046A
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select FSL_LSCH2
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select GICV2
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select HAS_FSL_XHCI_USB if USB_HOST
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select SKIP_LOWLEVEL_INIT
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select SYS_FSL_SRDS_1
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select SYS_HAS_SERDES
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select SYS_FSL_DDR
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@ -134,6 +137,7 @@ config ARCH_LS1088A
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select FSL_LAYERSCAPE
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select FSL_LSCH3
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select GICV3
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select SKIP_LOWLEVEL_INIT
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select SYS_FSL_SRDS_1
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select SYS_HAS_SERDES
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select SYS_FSL_DDR
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@ -181,6 +185,7 @@ config ARCH_LS2080A
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select FSL_LAYERSCAPE
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select FSL_LSCH3
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select GICV3
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select SKIP_LOWLEVEL_INIT
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select SYS_FSL_SRDS_1
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select SYS_HAS_SERDES
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select SYS_FSL_DDR
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@ -296,6 +301,7 @@ config ARCH_LX2160A
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config FSL_LSCH2
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bool
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select SKIP_LOWLEVEL_INIT
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select SYS_FSL_HAS_CCI400
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select SYS_FSL_HAS_SEC
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select SYS_FSL_SEC_COMPAT_5
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@ -45,7 +45,7 @@ reset:
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orr r0,r0,#0xd3
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msr cpsr,r0
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
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bl cpu_init_crit
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#endif
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@ -92,7 +92,7 @@ c_runtime_cpu_setup:
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*
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*************************************************************************
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*/
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#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) || defined(CONFIG_CPU_PXA25X)
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#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) || defined(CONFIG_CPU_PXA25X)
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cpu_init_crit:
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/*
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* flush v4 I/D caches
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@ -111,7 +111,7 @@ cpu_init_crit:
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mcr p15, 0, r0, c1, c0, 0
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mov pc, lr /* back to my caller */
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#endif /* !CONFIG_SKIP_LOWLEVEL_INIT || CONFIG_CPU_PXA25X */
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#endif /* !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) || CONFIG_CPU_PXA25X */
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/*
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* Enable MMU to use DCache as DRAM.
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@ -39,7 +39,7 @@ reset:
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* we do sys-critical inits only at reboot,
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* not when booting from ram!
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*/
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
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bl cpu_init_crit
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#endif
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@ -95,7 +95,7 @@ cpu_init_crit:
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ldr r1, cpuspeed
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str r1, [r0, #PPCR]
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
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#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
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/*
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* before relocating, we have to setup RAM timing
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* because memory timing is board-dependend, you will
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@ -6,7 +6,7 @@
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#ifndef __ARCH_ARM_MACH_CHILISOM_SOM_H__
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#define __ARCH_ARM_MACH_CHILISOM_SOM_H__
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
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void chilisom_enable_pin_mux(void);
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void chilisom_spl_board_init(void);
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#endif
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@ -10,7 +10,7 @@
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#include <config.h>
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
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#include <asm/arch/hardware.h>
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#include <asm/arch/at91_mc.h>
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@ -148,4 +148,4 @@ SMRDATA1:
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.word CONFIG_SYS_SDRAM_VAL
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SMRDATA1E:
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/* SMRDATA1 is 176 bytes long */
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#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
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#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */
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@ -224,7 +224,7 @@ const struct rproc_att hostmap[] = {
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};
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#endif
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
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/* enable all periherial can be accessed in nosec mode */
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static void init_csu(void)
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{
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@ -59,7 +59,7 @@ static inline unsigned long long us_to_tick(unsigned long long usec)
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return usec;
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}
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
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int timer_init(void)
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{
|
||||
struct sctr_regs *sctr = (struct sctr_regs *)SCTR_BASE_ADDR;
|
||||
|
|
|
|||
|
|
@ -27,10 +27,6 @@
|
|||
|
||||
#define CONFIG_SYS_L2_PL310
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* By default the generated mvebu kwbimage.cfg is used
|
||||
* If for some board, different configuration file need to be used,
|
||||
|
|
|
|||
|
|
@ -120,6 +120,7 @@ config AM33XX
|
|||
select SPECIFY_CONSOLE_INDEX
|
||||
imply NAND_OMAP_ELM
|
||||
imply NAND_OMAP_GPMC
|
||||
imply SKIP_LOWLEVEL_INIT
|
||||
imply SPL_NAND_AM33XX_BCH
|
||||
imply SPL_NAND_SUPPORT
|
||||
imply SYS_I2C_OMAP24XX
|
||||
|
|
|
|||
|
|
@ -13,7 +13,7 @@ endif
|
|||
obj-$(CONFIG_TI816X) += clock_ti816x.o
|
||||
obj-y += sys_info.o
|
||||
obj-y += ddr.o
|
||||
ifeq ($(CONFIG_TI816X)$(CONFIG_SKIP_LOWLEVEL_INIT),)
|
||||
ifeq ($(CONFIG_TI816X)$(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),)
|
||||
obj-y += emif4.o
|
||||
endif
|
||||
obj-$(CONFIG_TI816X) += ti816x_emif4.o
|
||||
|
|
|
|||
|
|
@ -65,7 +65,7 @@ DECLARE_GLOBAL_DATA_PTR;
|
|||
|
||||
int dram_init(void)
|
||||
{
|
||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
|
||||
sdram_init();
|
||||
#endif
|
||||
|
||||
|
|
@ -351,7 +351,7 @@ int arch_misc_init(void)
|
|||
|
||||
#endif /* CONFIG_USB_MUSB_* && CONFIG_AM335X_USB* && !CONFIG_DM_USB */
|
||||
|
||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
|
||||
|
||||
#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) || \
|
||||
(defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT))
|
||||
|
|
@ -599,7 +599,7 @@ void board_init_f(ulong dummy)
|
|||
int arch_cpu_init_dm(void)
|
||||
{
|
||||
hw_data_init();
|
||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
|
||||
early_system_init();
|
||||
#endif
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -22,7 +22,7 @@
|
|||
#include <power/tps65217.h>
|
||||
#include <spl.h>
|
||||
|
||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
|
||||
|
||||
static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
|
||||
|
||||
|
|
@ -182,4 +182,4 @@ void sdram_init(void)
|
|||
&ddr3_chilisom_emif_reg_data, 0);
|
||||
}
|
||||
|
||||
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
|
||||
#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */
|
||||
|
|
|
|||
|
|
@ -76,8 +76,8 @@ void early_system_init(void)
|
|||
hw_data_init();
|
||||
}
|
||||
|
||||
#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
|
||||
!defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
|
||||
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) && \
|
||||
!CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
|
||||
|
||||
/******************************************************************************
|
||||
* Routine: secure_unlock
|
||||
|
|
|
|||
|
|
@ -170,8 +170,8 @@ pll_div_val5:
|
|||
go_to_speed_end:
|
||||
#endif
|
||||
|
||||
#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
|
||||
!defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
|
||||
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) && \
|
||||
!CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
|
||||
ENTRY(lowlevel_init)
|
||||
ldr sp, SRAM_STACK
|
||||
str ip, [sp] /* stash ip register */
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@ obj-y = cpu.o
|
|||
obj-y += dram.o
|
||||
obj-y += timer.o
|
||||
|
||||
ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||
ifndef CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT
|
||||
obj-y += lowlevel_init.o
|
||||
endif
|
||||
|
||||
|
|
|
|||
|
|
@ -100,6 +100,7 @@ config ROCKCHIP_RK3288
|
|||
bool "Support Rockchip RK3288"
|
||||
select CPU_V7A
|
||||
select OF_BOARD_SETUP
|
||||
select SKIP_LOWLEVEL_INIT_ONLY
|
||||
select SUPPORT_SPL
|
||||
select SPL
|
||||
select SUPPORT_TPL
|
||||
|
|
|
|||
|
|
@ -72,6 +72,7 @@ config TEGRA_ARMV7_COMMON
|
|||
select CPU_V7A
|
||||
select SPL
|
||||
select SPL_BOARD_INIT if SPL
|
||||
select SPL_SKIP_LOWLEVEL_INIT_ONLY if SPL
|
||||
select SUPPORT_SPL
|
||||
select TEGRA_CLKRST
|
||||
select TEGRA_COMMON
|
||||
|
|
|
|||
|
|
@ -233,7 +233,7 @@ wr_done:
|
|||
# endif
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
|
||||
# ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
|
||||
/* Initialize any external memory */
|
||||
PTR_LA t9, lowlevel_init
|
||||
|
|
@ -254,7 +254,7 @@ wr_done:
|
|||
nop
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
|
||||
# ifndef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
|
||||
/* Initialize any external memory */
|
||||
PTR_LA t9, lowlevel_init
|
||||
|
|
|
|||
|
|
@ -28,7 +28,7 @@
|
|||
.set noreorder
|
||||
|
||||
LEAF(mips_sram_init)
|
||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
|
||||
/* Setup CPU PLL */
|
||||
li t0, DELAY_USEC(1000000)
|
||||
li t1, KSEG1ADDR(SYSCTL_BASE + SYSCTL_ROM_STATUS_REG)
|
||||
|
|
@ -116,7 +116,7 @@ _cpu_pll_done:
|
|||
sub a1, CONFIG_SYS_DCACHE_LINE_SIZE
|
||||
bnez a1, 3b
|
||||
nop
|
||||
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
|
||||
#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */
|
||||
|
||||
jr ra
|
||||
nop
|
||||
|
|
|
|||
|
|
@ -94,7 +94,7 @@ mem_init:
|
|||
move $lp, $r11
|
||||
ret
|
||||
|
||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
|
||||
.globl lowlevel_init
|
||||
lowlevel_init:
|
||||
move $r10, $lp
|
||||
|
|
@ -144,4 +144,4 @@ enable_fpu:
|
|||
ret
|
||||
#endif
|
||||
|
||||
#endif /* #ifndef CONFIG_SKIP_LOWLEVEL_INIT */
|
||||
#endif /* #if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */
|
||||
|
|
|
|||
|
|
@ -164,7 +164,7 @@ sdram_b0_cr:
|
|||
ret
|
||||
|
||||
|
||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
|
||||
|
||||
.globl lowlevel_init
|
||||
lowlevel_init:
|
||||
|
|
@ -314,4 +314,4 @@ show_led:
|
|||
li $r8, (CONFIG_DEBUG_LED)
|
||||
swi $r7, [$r8]
|
||||
ret
|
||||
#endif /* #ifndef CONFIG_SKIP_LOWLEVEL_INIT */
|
||||
#endif /* #if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */
|
||||
|
|
|
|||
|
|
@ -174,7 +174,7 @@ set_ivb:
|
|||
|
||||
jal mem_init
|
||||
|
||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
|
||||
jal lowlevel_init
|
||||
/*
|
||||
* gp = ~VMA for burn mode
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@
|
|||
# Copyright (C) 2018 Robert Bosch Power Tools GmbH
|
||||
#
|
||||
|
||||
ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
|
||||
ifeq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),)
|
||||
obj-y := mux.o
|
||||
endif
|
||||
|
||||
|
|
|
|||
|
|
@ -40,7 +40,7 @@
|
|||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
|
||||
static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
|
||||
|
||||
static const struct ddr_data ddr3_data = {
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
|
||||
ifeq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),)
|
||||
obj-y := mux.o
|
||||
endif
|
||||
|
||||
|
|
|
|||
|
|
@ -162,7 +162,7 @@ static void set_mpu_and_core_voltage(void)
|
|||
}
|
||||
}
|
||||
|
||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
|
||||
static const struct ddr_data ddr2_data = {
|
||||
.datardsratio0 = MT47H128M16RT25E_RD_DQS,
|
||||
.datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
|
||||
|
|
@ -235,7 +235,7 @@ void sdram_init(void)
|
|||
config_ddr(266, &ioregs, &ddr2_data,
|
||||
&ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
|
||||
}
|
||||
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
|
||||
#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */
|
||||
|
||||
#ifdef CONFIG_DEBUG_UART
|
||||
void board_debug_uart_init(void)
|
||||
|
|
|
|||
|
|
@ -113,6 +113,5 @@ Start Address End Address Description Size
|
|||
|
||||
LS1021a rev1.0 Soc specific Options/Settings
|
||||
--------------------------------------------
|
||||
If the LS1021a Soc is rev1.0, you need modify the configure file.
|
||||
Add the following define in include/configs/ls1021aqds.h:
|
||||
#define CONFIG_SKIP_LOWLEVEL_INIT
|
||||
If the LS1021a Soc is rev1.0, you need modify the configuration and enable
|
||||
CONFIG_SPL_SKIP_LOWLEVEL_INIT in menuconfig or similar.
|
||||
|
|
|
|||
|
|
@ -110,6 +110,5 @@ Start Address End Address Description Size
|
|||
|
||||
LS1021a rev1.0 Soc specific Options/Settings
|
||||
--------------------------------------------
|
||||
If the LS1021a Soc is rev1.0, you need modify the configure file.
|
||||
Add the following define in include/configs/ls1021atwr.h:
|
||||
#define CONFIG_SKIP_LOWLEVEL_INIT
|
||||
If the LS1021a Soc is rev1.0, you need modify the configuration and enable
|
||||
CONFIG_SPL_SKIP_LOWLEVEL_INIT in menuconfig or similar.
|
||||
|
|
|
|||
|
|
@ -30,7 +30,7 @@ DECLARE_GLOBAL_DATA_PTR;
|
|||
static __maybe_unused struct ctrl_dev *cdev =
|
||||
(struct ctrl_dev *)CTRL_DEVICE_BASE;
|
||||
|
||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
|
||||
static struct module_pin_mux uart0_pin_mux[] = {
|
||||
{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
|
||||
{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
|
||||
|
|
@ -69,9 +69,7 @@ static void enable_board_pin_mux(void)
|
|||
configure_module_pin_mux(rmii1_pin_mux);
|
||||
configure_module_pin_mux(mmc0_pin_mux);
|
||||
}
|
||||
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
|
||||
|
||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||
void set_uart_mux_conf(void)
|
||||
{
|
||||
configure_module_pin_mux(uart0_pin_mux);
|
||||
|
|
@ -86,7 +84,7 @@ void am33xx_spl_board_init(void)
|
|||
{
|
||||
chilisom_spl_board_init();
|
||||
}
|
||||
#endif
|
||||
#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */
|
||||
|
||||
/*
|
||||
* Basic board specific setup. Pinmux has been handled already.
|
||||
|
|
|
|||
|
|
@ -66,7 +66,7 @@ int board_early_init_f(void)
|
|||
void __iomem *rst_regs = map_physmem(AR71XX_RESET_BASE,
|
||||
AR71XX_RESET_SIZE, MAP_NOCACHE);
|
||||
|
||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
|
||||
/* CPU:775, DDR:650, AHB:258 */
|
||||
qca956x_pll_init();
|
||||
qca956x_ddr_init();
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
#
|
||||
# Copyright (C) 2015 Toby Churchill Ltd - http://www.toby-churchill.com/
|
||||
|
||||
ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
|
||||
ifeq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),)
|
||||
obj-y := mux.o
|
||||
endif
|
||||
|
||||
|
|
|
|||
|
|
@ -40,7 +40,7 @@ DECLARE_GLOBAL_DATA_PTR;
|
|||
|
||||
static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
|
||||
|
||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
|
||||
|
||||
static const struct ddr_data ddr3_sl50_data = {
|
||||
.datardsratio0 = MT41K256M16HA125E_RD_DQS,
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
#
|
||||
# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
|
||||
|
||||
ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
|
||||
ifeq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),)
|
||||
obj-y := mux.o
|
||||
endif
|
||||
|
||||
|
|
|
|||
|
|
@ -95,7 +95,7 @@ struct serial_device *default_serial_console(void)
|
|||
}
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
|
||||
static const struct ddr_data ddr2_data = {
|
||||
.datardsratio0 = MT47H128M16RT25E_RD_DQS,
|
||||
.datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
#
|
||||
# Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
|
||||
|
||||
ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
|
||||
ifeq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),)
|
||||
obj-y := mux.o
|
||||
endif
|
||||
|
||||
|
|
|
|||
|
|
@ -56,7 +56,7 @@ void do_board_detect(void)
|
|||
}
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
|
||||
|
||||
const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = {
|
||||
{ /* 19.2 MHz */
|
||||
|
|
|
|||
|
|
@ -71,7 +71,7 @@ int board_early_init_f(void)
|
|||
wdr4300_pinmux_config();
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
|
||||
ar934x_pll_init(560, 480, 240);
|
||||
ar934x_ddr_init(560, 480, 240);
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
#
|
||||
# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
|
||||
|
||||
ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
|
||||
ifeq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),)
|
||||
obj-y := mux.o
|
||||
endif
|
||||
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_SYS_DCACHE_OFF=y
|
||||
CONFIG_ARCH_CPU_INIT=y
|
||||
CONFIG_ARCH_KIRKWOOD=y
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_SYS_DCACHE_OFF=y
|
||||
CONFIG_ARCH_CPU_INIT=y
|
||||
CONFIG_ARCH_KIRKWOOD=y
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
CONFIG_NDS32=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_SYS_TEXT_BASE=0x4A000000
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
CONFIG_ENV_SIZE=0x2000
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
CONFIG_NDS32=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_SYS_TEXT_BASE=0x11000000
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
CONFIG_ENV_SIZE=0x2000
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_ARCH_CPU_INIT=y
|
||||
CONFIG_ARCH_OMAP2PLUS=y
|
||||
CONFIG_TI_COMMON_CMD_OPTIONS=y
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_ARCH_CPU_INIT=y
|
||||
CONFIG_ARCH_OMAP2PLUS=y
|
||||
CONFIG_TI_COMMON_CMD_OPTIONS=y
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_ARCH_CPU_INIT=y
|
||||
CONFIG_ARCH_OMAP2PLUS=y
|
||||
CONFIG_ISW_ENTRY_ADDR=0x40300350
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_ARCH_CPU_INIT=y
|
||||
CONFIG_ARCH_OMAP2PLUS=y
|
||||
CONFIG_TI_SECURE_DEVICE=y
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_ARCH_K3=y
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_ARCH_K3=y
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_ARCH_K3=y
|
||||
CONFIG_TI_SECURE_DEVICE=y
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
|
|
|
|||
|
|
@ -1,4 +1,6 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_ARCH_CPU_INIT=y
|
||||
CONFIG_ARCH_EXYNOS=y
|
||||
CONFIG_SYS_TEXT_BASE=0x43E00000
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_ARCH_CPU_INIT=y
|
||||
CONFIG_TARGET_ASPENITE=y
|
||||
CONFIG_SYS_TEXT_BASE=0x600000
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_ARCH_CPU_INIT=y
|
||||
CONFIG_ARCH_AT91=y
|
||||
CONFIG_SYS_TEXT_BASE=0x21f00000
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_ARCH_CPU_INIT=y
|
||||
CONFIG_ARCH_AT91=y
|
||||
CONFIG_SYS_TEXT_BASE=0x21f00000
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_ARCH_CPU_INIT=y
|
||||
CONFIG_ARCH_AT91=y
|
||||
CONFIG_SYS_TEXT_BASE=0x21f00000
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_ARCH_AT91=y
|
||||
CONFIG_SYS_TEXT_BASE=0x21f00000
|
||||
CONFIG_TARGET_AT91SAM9261EK=y
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_ARCH_AT91=y
|
||||
CONFIG_SYS_TEXT_BASE=0x21f00000
|
||||
CONFIG_TARGET_AT91SAM9261EK=y
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_ARCH_AT91=y
|
||||
CONFIG_SYS_TEXT_BASE=0x21f00000
|
||||
CONFIG_TARGET_AT91SAM9261EK=y
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_ARCH_CPU_INIT=y
|
||||
CONFIG_ARCH_AT91=y
|
||||
CONFIG_SYS_TEXT_BASE=0x21F00000
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_ARCH_CPU_INIT=y
|
||||
CONFIG_ARCH_AT91=y
|
||||
CONFIG_SYS_TEXT_BASE=0x21F00000
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_ARCH_CPU_INIT=y
|
||||
CONFIG_ARCH_AT91=y
|
||||
CONFIG_SYS_TEXT_BASE=0x21F00000
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_ARCH_CPU_INIT=y
|
||||
CONFIG_ARCH_AT91=y
|
||||
CONFIG_SYS_TEXT_BASE=0x21F00000
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_ARCH_AT91=y
|
||||
CONFIG_SYS_TEXT_BASE=0x21f00000
|
||||
CONFIG_TARGET_AT91SAM9261EK=y
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_ARCH_AT91=y
|
||||
CONFIG_SYS_TEXT_BASE=0x21f00000
|
||||
CONFIG_TARGET_AT91SAM9261EK=y
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_ARCH_AT91=y
|
||||
CONFIG_SYS_TEXT_BASE=0x21f00000
|
||||
CONFIG_TARGET_AT91SAM9261EK=y
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_ARCH_CPU_INIT=y
|
||||
CONFIG_ARCH_AT91=y
|
||||
CONFIG_SYS_TEXT_BASE=0x21f00000
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_ARCH_CPU_INIT=y
|
||||
CONFIG_ARCH_AT91=y
|
||||
CONFIG_SYS_TEXT_BASE=0x21f00000
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_ARCH_CPU_INIT=y
|
||||
CONFIG_ARCH_AT91=y
|
||||
CONFIG_SYS_TEXT_BASE=0x21f00000
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_ARCH_CPU_INIT=y
|
||||
CONFIG_ARCH_AT91=y
|
||||
CONFIG_SYS_TEXT_BASE=0x21f00000
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_ARCH_CPU_INIT=y
|
||||
CONFIG_ARCH_AT91=y
|
||||
CONFIG_SYS_TEXT_BASE=0x21f00000
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_ARCH_AT91=y
|
||||
CONFIG_SYS_TEXT_BASE=0x73f00000
|
||||
CONFIG_TARGET_AT91SAM9M10G45EK=y
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_ARCH_AT91=y
|
||||
CONFIG_SYS_TEXT_BASE=0x73f00000
|
||||
CONFIG_TARGET_AT91SAM9M10G45EK=y
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_ARCH_AT91=y
|
||||
CONFIG_SYS_TEXT_BASE=0x26f00000
|
||||
CONFIG_TARGET_AT91SAM9N12EK=y
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_ARCH_AT91=y
|
||||
CONFIG_SYS_TEXT_BASE=0x26f00000
|
||||
CONFIG_TARGET_AT91SAM9N12EK=y
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_ARCH_AT91=y
|
||||
CONFIG_SYS_TEXT_BASE=0x26f00000
|
||||
CONFIG_TARGET_AT91SAM9N12EK=y
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_ARCH_CPU_INIT=y
|
||||
CONFIG_ARCH_AT91=y
|
||||
CONFIG_SYS_TEXT_BASE=0x21F00000
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_ARCH_CPU_INIT=y
|
||||
CONFIG_ARCH_AT91=y
|
||||
CONFIG_SYS_TEXT_BASE=0x21F00000
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_ARCH_CPU_INIT=y
|
||||
CONFIG_ARCH_AT91=y
|
||||
CONFIG_SYS_TEXT_BASE=0x21F00000
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_ARCH_AT91=y
|
||||
CONFIG_SYS_TEXT_BASE=0x26f00000
|
||||
CONFIG_TARGET_AT91SAM9X5EK=y
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_ARCH_AT91=y
|
||||
CONFIG_SYS_TEXT_BASE=0x26f00000
|
||||
CONFIG_TARGET_AT91SAM9X5EK=y
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_ARCH_AT91=y
|
||||
CONFIG_SYS_TEXT_BASE=0x26f00000
|
||||
CONFIG_TARGET_AT91SAM9X5EK=y
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_ARCH_AT91=y
|
||||
CONFIG_SYS_TEXT_BASE=0x26f00000
|
||||
CONFIG_TARGET_AT91SAM9X5EK=y
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_ARCH_CPU_INIT=y
|
||||
CONFIG_ARCH_AT91=y
|
||||
CONFIG_SYS_TEXT_BASE=0x21f00000
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_ARCH_CPU_INIT=y
|
||||
CONFIG_ARCH_AT91=y
|
||||
CONFIG_SYS_TEXT_BASE=0x21f00000
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_ARCH_CPU_INIT=y
|
||||
CONFIG_ARCH_AT91=y
|
||||
CONFIG_SYS_TEXT_BASE=0x21f00000
|
||||
|
|
|
|||
|
|
@ -1,4 +1,6 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT_ONLY=y
|
||||
CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y
|
||||
CONFIG_SPL_SYS_DCACHE_OFF=y
|
||||
CONFIG_ARCH_CPU_INIT=y
|
||||
CONFIG_SYS_THUMB_BUILD=y
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_ARCH_BCMSTB=y
|
||||
CONFIG_SYS_TEXT_BASE=0x10100000
|
||||
CONFIG_TARGET_BCM7260=y
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_ARCH_BCMSTB=y
|
||||
CONFIG_SYS_TEXT_BASE=0x80100000
|
||||
CONFIG_TARGET_BCM7445=y
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
# CONFIG_ARM64_SUPPORT_AARCH32 is not set
|
||||
CONFIG_ARCH_BCM63158=y
|
||||
CONFIG_SYS_TEXT_BASE=0x10000000
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_ARCH_BCM68360=y
|
||||
CONFIG_SYS_TEXT_BASE=0x10000000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x8000
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
CONFIG_MIPS=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_SYS_TEXT_BASE=0x80010000
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_ENV_SIZE=0x2000
|
||||
|
|
@ -6,6 +7,8 @@ CONFIG_DM_GPIO=y
|
|||
CONFIG_DEFAULT_DEVICE_TREE="brcm,bcm968380gerg"
|
||||
CONFIG_ARCH_BMIPS=y
|
||||
CONFIG_SOC_BMIPS_BCM6838=y
|
||||
CONFIG_MIPS_CACHE_SETUP=y
|
||||
CONFIG_MIPS_CACHE_DISABLE=y
|
||||
# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
|
||||
# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
|
||||
CONFIG_MIPS_BOOT_FDT=y
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_ARCH_BCM6858=y
|
||||
CONFIG_SYS_TEXT_BASE=0x10000000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x8000
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show more
Loading…
Reference in a new issue