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net: Add EMAC driver for H3/A83T/A64 SoCs.
This patch add EMAC driver support for H3/A83T/A64 SoCs. Tested on Pine64(A64-External PHY) and Orangepipc(H3-Internal PHY). BIG Thanks to Andre for providing some of the DT code. Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
This commit is contained in:
Amit Singh Tomar
Hans de Goede
parent
26c0c15786
commit
a29710c525
12 changed files with 902 additions and 2 deletions
arch/arm
dts
sun50i-a64-pine64-plus.dtssun50i-a64.dtsisun8i-h3-orangepi-2.dtssun8i-h3-orangepi-pc.dtssun8i-h3.dtsi
include/asm/arch-sunxi
configs
drivers/net
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@ -57,3 +57,16 @@
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reg = <0x40000000 0x40000000>;
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};
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};
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&emac {
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pinctrl-names = "default";
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pinctrl-0 = <&rgmii_pins>;
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phy-mode = "rgmii";
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phy = <&phy1>;
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status = "okay";
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phy1: ethernet-phy@1 {
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reg = <1>;
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};
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};
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@ -506,6 +506,25 @@
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allwinner,drive = <SUN4I_PINCTRL_10_MA>;
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allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
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};
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rmii_pins: rmii_pins {
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allwinner,pins = "PD10", "PD11", "PD13", "PD14",
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"PD17", "PD18", "PD19", "PD20",
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"PD22", "PD23";
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allwinner,function = "emac";
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allwinner,drive = <SUN4I_PINCTRL_40_MA>;
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allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
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};
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rgmii_pins: rgmii_pins {
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allwinner,pins = "PD8", "PD9", "PD10", "PD11",
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"PD12", "PD13", "PD15",
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"PD16", "PD17", "PD18", "PD19",
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"PD20", "PD21", "PD22", "PD23";
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allwinner,function = "emac";
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allwinner,drive = <SUN4I_PINCTRL_40_MA>;
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allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
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};
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};
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ahb_rst: reset@1c202c0 {
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@ -620,5 +639,19 @@
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#address-cells = <1>;
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#size-cells = <0>;
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};
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emac: ethernet@01c30000 {
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compatible = "allwinner,sun50i-a64-emac";
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reg = <0x01c30000 0x2000>, <0x01c00030 0x4>;
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reg-names = "emac", "syscon";
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interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&ahb_rst 17>;
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reset-names = "ahb";
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clocks = <&bus_gates 17>;
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clock-names = "ahb";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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};
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@ -184,3 +184,16 @@
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usb1_vbus-supply = <®_usb1_vbus>;
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status = "okay";
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};
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&emac {
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pinctrl-names = "default";
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pinctrl-0 = <&rgmii_pins>;
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phy-mode = "rgmii";
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phy = <&phy1>;
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status = "okay";
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phy1: ethernet-phy@1 {
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reg = <1>;
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};
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};
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@ -173,3 +173,15 @@
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/* USB VBUS is always on */
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status = "okay";
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};
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&emac {
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phy = <&phy1>;
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phy-mode = "mii";
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allwinner,use-internal-phy;
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allwinner,leds-active-low;
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status = "okay";
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phy1: ethernet-phy@1 {
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reg = <1>;
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};
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};
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@ -501,6 +501,17 @@
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interrupt-controller;
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#interrupt-cells = <3>;
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rgmii_pins: rgmii_pins {
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allwinner,pins = "PD0", "PD1", "PD2", "PD3",
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"PD4", "PD5", "PD7",
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"PD8", "PD9", "PD10",
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"PD12", "PD13", "PD15",
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"PD16", "PD17";
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allwinner,function = "emac";
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allwinner,drive = <SUN4I_PINCTRL_40_MA>;
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allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
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};
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uart0_pins_a: uart0@0 {
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allwinner,pins = "PA4", "PA5";
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allwinner,function = "uart0";
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@ -616,6 +627,20 @@
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status = "disabled";
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};
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emac: ethernet@01c30000 {
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compatible = "allwinner,sun8i-h3-emac";
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reg = <0x01c30000 0x2000>, <0x01c00030 0x4>;
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reg-names = "emac", "syscon";
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interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&ahb_rst 17>, <&ahb_rst 66>;
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reset-names = "ahb", "ephy";
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clocks = <&bus_gates 17>, <&bus_gates 128>;
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clock-names = "ahb", "ephy";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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gic: interrupt-controller@01c81000 {
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compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
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reg = <0x01c81000 0x1000>,
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@ -40,7 +40,8 @@ struct sunxi_ccm_reg {
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u32 ahb_gate1; /* 0x64 ahb module clock gating 1 */
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u32 apb1_gate; /* 0x68 apb1 module clock gating */
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u32 apb2_gate; /* 0x6c apb2 module clock gating */
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u32 reserved9[4];
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u32 bus_gate4; /* 0x70 gate 4 module clock gating */
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u8 res3[0xc];
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u32 nand0_clk_cfg; /* 0x80 nand0 clock control */
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u32 nand1_clk_cfg; /* 0x84 nand1 clock control */
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u32 sd0_clk_cfg; /* 0x88 sd0 clock control */
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@ -387,6 +388,7 @@ struct sunxi_ccm_reg {
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#define AHB_RESET_OFFSET_LCD0 4
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/* ahb_reset2 offsets */
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#define AHB_RESET_OFFSET_EPHY 2
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#define AHB_RESET_OFFSET_LVDS 0
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/* apb2 reset */
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@ -87,7 +87,8 @@
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#define SUNXI_KEYPAD_BASE 0x01c23000
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#define SUNXI_TZPC_BASE 0x01c23400
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#if defined(CONFIG_MACH_SUN8I_A83T) || defined(CONFIG_MACH_SUN8I_H3)
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#if defined(CONFIG_MACH_SUN8I_A83T) || defined(CONFIG_MACH_SUN8I_H3) || \
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defined(CONFIG_MACH_SUN50I)
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/* SID address space starts at 0x01c1400, but e-fuse is at offset 0x200 */
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#define SUNXI_SID_BASE 0x01c14200
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#else
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@ -13,3 +13,4 @@ CONFIG_SPL=y
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# CONFIG_CMD_FPGA is not set
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CONFIG_SY8106A_POWER=y
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CONFIG_USB_EHCI_HCD=y
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CONFIG_SUN8I_EMAC=y
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@ -10,3 +10,4 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pine64-plus"
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# CONFIG_CMD_FLASH is not set
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# CONFIG_CMD_FPGA is not set
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CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
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CONFIG_SUN8I_EMAC=y
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@ -152,6 +152,15 @@ config RTL8169
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This driver supports Realtek 8169 series gigabit ethernet family of
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PCI/PCIe chipsets/adapters.
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config SUN8I_EMAC
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bool "Allwinner Sun8i Ethernet MAC support"
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depends on DM_ETH
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select PHYLIB
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help
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This driver supports the Allwinner based SUN8I/SUN50I Ethernet MAC.
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It can be found in H3/A64/A83T based SoCs and compatible with both
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External and Internal PHY's.
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config XILINX_AXIEMAC
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depends on DM_ETH && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP)
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select PHYLIB
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@ -24,6 +24,7 @@ obj-$(CONFIG_E1000) += e1000.o
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obj-$(CONFIG_E1000_SPI) += e1000_spi.o
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obj-$(CONFIG_EEPRO100) += eepro100.o
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obj-$(CONFIG_SUNXI_EMAC) += sunxi_emac.o
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obj-$(CONFIG_SUN8I_EMAC) += sun8i_emac.o
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obj-$(CONFIG_ENC28J60) += enc28j60.o
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obj-$(CONFIG_EP93XX) += ep93xx_eth.o
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obj-$(CONFIG_ETHOC) += ethoc.o
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789
drivers/net/sun8i_emac.c
Normal file
789
drivers/net/sun8i_emac.c
Normal file
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@ -0,0 +1,789 @@
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/*
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* (C) Copyright 2016
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* Author: Amit Singh Tomar, amittomer25@gmail.com
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* Ethernet driver for H3/A64/A83T based SoC's
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*
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* It is derived from the work done by
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* LABBE Corentin & Chen-Yu Tsai for Linux, THANKS!
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*
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*/
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/gpio.h>
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#include <common.h>
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#include <dm.h>
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#include <fdt_support.h>
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#include <linux/err.h>
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#include <malloc.h>
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#include <miiphy.h>
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#include <net.h>
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#define SCTL_EMAC_TX_CLK_SRC_MII BIT(0)
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#define SCTL_EMAC_EPIT_MII BIT(2)
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#define SCTL_EMAC_CLK_SEL BIT(18) /* 25 Mhz */
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#define MDIO_CMD_MII_BUSY BIT(0)
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#define MDIO_CMD_MII_WRITE BIT(1)
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#define MDIO_CMD_MII_PHY_REG_ADDR_MASK 0x000001f0
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#define MDIO_CMD_MII_PHY_REG_ADDR_SHIFT 4
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#define MDIO_CMD_MII_PHY_ADDR_MASK 0x0001f000
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#define MDIO_CMD_MII_PHY_ADDR_SHIFT 12
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#define CONFIG_TX_DESCR_NUM 32
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#define CONFIG_RX_DESCR_NUM 32
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#define CONFIG_ETH_BUFSIZE 2024
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#define TX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM)
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#define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM)
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#define H3_EPHY_DEFAULT_VALUE 0x58000
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#define H3_EPHY_DEFAULT_MASK GENMASK(31, 15)
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#define H3_EPHY_ADDR_SHIFT 20
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#define REG_PHY_ADDR_MASK GENMASK(4, 0)
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#define H3_EPHY_LED_POL BIT(17) /* 1: active low, 0: active high */
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#define H3_EPHY_SHUTDOWN BIT(16) /* 1: shutdown, 0: power up */
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#define H3_EPHY_SELECT BIT(15) /* 1: internal PHY, 0: external PHY */
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#define SC_RMII_EN BIT(13)
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#define SC_EPIT BIT(2) /* 1: RGMII, 0: MII */
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#define SC_ETCS_MASK GENMASK(1, 0)
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#define SC_ETCS_EXT_GMII 0x1
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#define SC_ETCS_INT_GMII 0x2
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#define CONFIG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ)
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#define AHB_GATE_OFFSET_EPHY 0
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#if defined(CONFIG_MACH_SUN8I_H3)
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#define SUN8I_GPD8_GMAC 2
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#else
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#define SUN8I_GPD8_GMAC 4
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#endif
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/* H3/A64 EMAC Register's offset */
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#define EMAC_CTL0 0x00
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#define EMAC_CTL1 0x04
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#define EMAC_INT_STA 0x08
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#define EMAC_INT_EN 0x0c
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#define EMAC_TX_CTL0 0x10
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#define EMAC_TX_CTL1 0x14
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#define EMAC_TX_FLOW_CTL 0x1c
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#define EMAC_TX_DMA_DESC 0x20
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#define EMAC_RX_CTL0 0x24
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#define EMAC_RX_CTL1 0x28
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#define EMAC_RX_DMA_DESC 0x34
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#define EMAC_MII_CMD 0x48
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#define EMAC_MII_DATA 0x4c
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#define EMAC_ADDR0_HIGH 0x50
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#define EMAC_ADDR0_LOW 0x54
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#define EMAC_TX_DMA_STA 0xb0
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#define EMAC_TX_CUR_DESC 0xb4
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#define EMAC_TX_CUR_BUF 0xb8
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#define EMAC_RX_DMA_STA 0xc0
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#define EMAC_RX_CUR_DESC 0xc4
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DECLARE_GLOBAL_DATA_PTR;
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enum emac_variant {
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A83T_EMAC = 1,
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H3_EMAC,
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A64_EMAC,
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};
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struct emac_dma_desc {
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u32 status;
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u32 st;
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u32 buf_addr;
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u32 next;
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} __aligned(ARCH_DMA_MINALIGN);
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struct emac_eth_dev {
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struct emac_dma_desc rx_chain[CONFIG_TX_DESCR_NUM];
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struct emac_dma_desc tx_chain[CONFIG_RX_DESCR_NUM];
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char rxbuffer[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
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char txbuffer[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
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u32 interface;
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u32 phyaddr;
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u32 link;
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u32 speed;
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u32 duplex;
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u32 phy_configured;
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u32 tx_currdescnum;
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u32 rx_currdescnum;
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u32 addr;
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u32 tx_slot;
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bool use_internal_phy;
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enum emac_variant variant;
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void *mac_reg;
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phys_addr_t sysctl_reg;
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struct phy_device *phydev;
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struct mii_dev *bus;
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};
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static int sun8i_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
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{
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struct emac_eth_dev *priv = bus->priv;
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ulong start;
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u32 miiaddr = 0;
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int timeout = CONFIG_MDIO_TIMEOUT;
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miiaddr &= ~MDIO_CMD_MII_WRITE;
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miiaddr &= ~MDIO_CMD_MII_PHY_REG_ADDR_MASK;
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miiaddr |= (reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) &
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MDIO_CMD_MII_PHY_REG_ADDR_MASK;
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miiaddr &= ~MDIO_CMD_MII_PHY_ADDR_MASK;
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miiaddr |= (addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) &
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MDIO_CMD_MII_PHY_ADDR_MASK;
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miiaddr |= MDIO_CMD_MII_BUSY;
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writel(miiaddr, priv->mac_reg + EMAC_MII_CMD);
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start = get_timer(0);
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while (get_timer(start) < timeout) {
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if (!(readl(priv->mac_reg + EMAC_MII_CMD) & MDIO_CMD_MII_BUSY))
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return readl(priv->mac_reg + EMAC_MII_DATA);
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udelay(10);
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};
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return -1;
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}
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static int sun8i_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
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u16 val)
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{
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struct emac_eth_dev *priv = bus->priv;
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ulong start;
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u32 miiaddr = 0;
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int ret = -1, timeout = CONFIG_MDIO_TIMEOUT;
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miiaddr &= ~MDIO_CMD_MII_PHY_REG_ADDR_MASK;
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miiaddr |= (reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) &
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MDIO_CMD_MII_PHY_REG_ADDR_MASK;
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miiaddr &= ~MDIO_CMD_MII_PHY_ADDR_MASK;
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miiaddr |= (addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) &
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MDIO_CMD_MII_PHY_ADDR_MASK;
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miiaddr |= MDIO_CMD_MII_WRITE;
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miiaddr |= MDIO_CMD_MII_BUSY;
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writel(miiaddr, priv->mac_reg + EMAC_MII_CMD);
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writel(val, priv->mac_reg + EMAC_MII_DATA);
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start = get_timer(0);
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while (get_timer(start) < timeout) {
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if (!(readl(priv->mac_reg + EMAC_MII_CMD) &
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MDIO_CMD_MII_BUSY)) {
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ret = 0;
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break;
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}
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udelay(10);
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};
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return ret;
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}
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static int _sun8i_write_hwaddr(struct emac_eth_dev *priv, u8 *mac_id)
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{
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u32 macid_lo, macid_hi;
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macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) +
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(mac_id[3] << 24);
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macid_hi = mac_id[4] + (mac_id[5] << 8);
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writel(macid_hi, priv->mac_reg + EMAC_ADDR0_HIGH);
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||||
writel(macid_lo, priv->mac_reg + EMAC_ADDR0_LOW);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void sun8i_adjust_link(struct emac_eth_dev *priv,
|
||||
struct phy_device *phydev)
|
||||
{
|
||||
u32 v;
|
||||
|
||||
v = readl(priv->mac_reg + EMAC_CTL0);
|
||||
|
||||
if (phydev->duplex)
|
||||
v |= BIT(0);
|
||||
else
|
||||
v &= ~BIT(0);
|
||||
|
||||
v &= ~0x0C;
|
||||
|
||||
switch (phydev->speed) {
|
||||
case 1000:
|
||||
break;
|
||||
case 100:
|
||||
v |= BIT(2);
|
||||
v |= BIT(3);
|
||||
break;
|
||||
case 10:
|
||||
v |= BIT(3);
|
||||
break;
|
||||
}
|
||||
writel(v, priv->mac_reg + EMAC_CTL0);
|
||||
}
|
||||
|
||||
static int sun8i_emac_set_syscon_ephy(struct emac_eth_dev *priv, u32 *reg)
|
||||
{
|
||||
if (priv->use_internal_phy) {
|
||||
/* H3 based SoC's that has an Internal 100MBit PHY
|
||||
* needs to be configured and powered up before use
|
||||
*/
|
||||
*reg &= ~H3_EPHY_DEFAULT_MASK;
|
||||
*reg |= H3_EPHY_DEFAULT_VALUE;
|
||||
*reg |= priv->phyaddr << H3_EPHY_ADDR_SHIFT;
|
||||
*reg &= ~H3_EPHY_SHUTDOWN;
|
||||
*reg |= H3_EPHY_SELECT;
|
||||
} else
|
||||
/* This is to select External Gigabit PHY on
|
||||
* the boards with H3 SoC.
|
||||
*/
|
||||
*reg &= ~H3_EPHY_SELECT;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sun8i_emac_set_syscon(struct emac_eth_dev *priv)
|
||||
{
|
||||
int ret;
|
||||
u32 reg;
|
||||
|
||||
reg = readl(priv->sysctl_reg);
|
||||
|
||||
if (priv->variant == H3_EMAC) {
|
||||
ret = sun8i_emac_set_syscon_ephy(priv, ®);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
reg &= ~(SC_ETCS_MASK | SC_EPIT);
|
||||
if (priv->variant == H3_EMAC || priv->variant == A64_EMAC)
|
||||
reg &= ~SC_RMII_EN;
|
||||
|
||||
switch (priv->interface) {
|
||||
case PHY_INTERFACE_MODE_MII:
|
||||
/* default */
|
||||
break;
|
||||
case PHY_INTERFACE_MODE_RGMII:
|
||||
reg |= SC_EPIT | SC_ETCS_INT_GMII;
|
||||
break;
|
||||
case PHY_INTERFACE_MODE_RMII:
|
||||
if (priv->variant == H3_EMAC ||
|
||||
priv->variant == A64_EMAC) {
|
||||
reg |= SC_RMII_EN | SC_ETCS_EXT_GMII;
|
||||
break;
|
||||
}
|
||||
/* RMII not supported on A83T */
|
||||
default:
|
||||
debug("%s: Invalid PHY interface\n", __func__);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
writel(reg, priv->sysctl_reg);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sun8i_phy_init(struct emac_eth_dev *priv, void *dev)
|
||||
{
|
||||
struct phy_device *phydev;
|
||||
|
||||
phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface);
|
||||
if (!phydev)
|
||||
return -ENODEV;
|
||||
|
||||
phy_connect_dev(phydev, dev);
|
||||
|
||||
priv->phydev = phydev;
|
||||
phy_config(priv->phydev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void rx_descs_init(struct emac_eth_dev *priv)
|
||||
{
|
||||
struct emac_dma_desc *desc_table_p = &priv->rx_chain[0];
|
||||
char *rxbuffs = &priv->rxbuffer[0];
|
||||
struct emac_dma_desc *desc_p;
|
||||
u32 idx;
|
||||
|
||||
/* flush Rx buffers */
|
||||
flush_dcache_range((uintptr_t)rxbuffs, (ulong)rxbuffs +
|
||||
RX_TOTAL_BUFSIZE);
|
||||
|
||||
for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
|
||||
desc_p = &desc_table_p[idx];
|
||||
desc_p->buf_addr = (uintptr_t)&rxbuffs[idx * CONFIG_ETH_BUFSIZE]
|
||||
;
|
||||
desc_p->next = (uintptr_t)&desc_table_p[idx + 1];
|
||||
desc_p->st |= CONFIG_ETH_BUFSIZE;
|
||||
desc_p->status = BIT(31);
|
||||
}
|
||||
|
||||
/* Correcting the last pointer of the chain */
|
||||
desc_p->next = (uintptr_t)&desc_table_p[0];
|
||||
|
||||
flush_dcache_range((uintptr_t)priv->rx_chain,
|
||||
(uintptr_t)priv->rx_chain +
|
||||
sizeof(priv->rx_chain));
|
||||
|
||||
writel((uintptr_t)&desc_table_p[0], (priv->mac_reg + EMAC_RX_DMA_DESC));
|
||||
priv->rx_currdescnum = 0;
|
||||
}
|
||||
|
||||
static void tx_descs_init(struct emac_eth_dev *priv)
|
||||
{
|
||||
struct emac_dma_desc *desc_table_p = &priv->tx_chain[0];
|
||||
char *txbuffs = &priv->txbuffer[0];
|
||||
struct emac_dma_desc *desc_p;
|
||||
u32 idx;
|
||||
|
||||
for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
|
||||
desc_p = &desc_table_p[idx];
|
||||
desc_p->buf_addr = (uintptr_t)&txbuffs[idx * CONFIG_ETH_BUFSIZE]
|
||||
;
|
||||
desc_p->next = (uintptr_t)&desc_table_p[idx + 1];
|
||||
desc_p->status = (1 << 31);
|
||||
desc_p->st = 0;
|
||||
}
|
||||
|
||||
/* Correcting the last pointer of the chain */
|
||||
desc_p->next = (uintptr_t)&desc_table_p[0];
|
||||
|
||||
/* Flush all Tx buffer descriptors */
|
||||
flush_dcache_range((uintptr_t)priv->tx_chain,
|
||||
(uintptr_t)priv->tx_chain +
|
||||
sizeof(priv->tx_chain));
|
||||
|
||||
writel((uintptr_t)&desc_table_p[0], priv->mac_reg + EMAC_TX_DMA_DESC);
|
||||
priv->tx_currdescnum = 0;
|
||||
}
|
||||
|
||||
static int _sun8i_emac_eth_init(struct emac_eth_dev *priv, u8 *enetaddr)
|
||||
{
|
||||
u32 reg, v;
|
||||
int timeout = 100;
|
||||
|
||||
reg = readl((priv->mac_reg + EMAC_CTL1));
|
||||
|
||||
if (!(reg & 0x1)) {
|
||||
/* Soft reset MAC */
|
||||
setbits_le32((priv->mac_reg + EMAC_CTL1), 0x1);
|
||||
do {
|
||||
reg = readl(priv->mac_reg + EMAC_CTL1);
|
||||
} while ((reg & 0x01) != 0 && (--timeout));
|
||||
if (!timeout) {
|
||||
printf("%s: Timeout\n", __func__);
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
/* Rewrite mac address after reset */
|
||||
_sun8i_write_hwaddr(priv, enetaddr);
|
||||
|
||||
v = readl(priv->mac_reg + EMAC_TX_CTL1);
|
||||
/* TX_MD Transmission starts after a full frame located in TX DMA FIFO*/
|
||||
v |= BIT(1);
|
||||
writel(v, priv->mac_reg + EMAC_TX_CTL1);
|
||||
|
||||
v = readl(priv->mac_reg + EMAC_RX_CTL1);
|
||||
/* RX_MD RX DMA reads data from RX DMA FIFO to host memory after a
|
||||
* complete frame has been written to RX DMA FIFO
|
||||
*/
|
||||
v |= BIT(1);
|
||||
writel(v, priv->mac_reg + EMAC_RX_CTL1);
|
||||
|
||||
/* DMA */
|
||||
writel(8 << 24, priv->mac_reg + EMAC_CTL1);
|
||||
|
||||
/* Initialize rx/tx descriptors */
|
||||
rx_descs_init(priv);
|
||||
tx_descs_init(priv);
|
||||
|
||||
/* PHY Start Up */
|
||||
genphy_parse_link(priv->phydev);
|
||||
|
||||
sun8i_adjust_link(priv, priv->phydev);
|
||||
|
||||
/* Start RX DMA */
|
||||
v = readl(priv->mac_reg + EMAC_RX_CTL1);
|
||||
v |= BIT(30);
|
||||
writel(v, priv->mac_reg + EMAC_RX_CTL1);
|
||||
/* Start TX DMA */
|
||||
v = readl(priv->mac_reg + EMAC_TX_CTL1);
|
||||
v |= BIT(30);
|
||||
writel(v, priv->mac_reg + EMAC_TX_CTL1);
|
||||
|
||||
/* Enable RX/TX */
|
||||
setbits_le32(priv->mac_reg + EMAC_RX_CTL0, BIT(31));
|
||||
setbits_le32(priv->mac_reg + EMAC_TX_CTL0, BIT(31));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int parse_phy_pins(struct udevice *dev)
|
||||
{
|
||||
int offset;
|
||||
const char *pin_name;
|
||||
int drive, pull, i;
|
||||
|
||||
offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset,
|
||||
"pinctrl-0");
|
||||
if (offset < 0) {
|
||||
printf("WARNING: emac: cannot find pinctrl-0 node\n");
|
||||
return offset;
|
||||
}
|
||||
|
||||
drive = fdt_getprop_u32_default_node(gd->fdt_blob, offset, 0,
|
||||
"allwinner,drive", 4);
|
||||
pull = fdt_getprop_u32_default_node(gd->fdt_blob, offset, 0,
|
||||
"allwinner,pull", 0);
|
||||
for (i = 0; ; i++) {
|
||||
int pin;
|
||||
|
||||
if (fdt_get_string_index(gd->fdt_blob, offset,
|
||||
"allwinner,pins", i, &pin_name))
|
||||
break;
|
||||
if (pin_name[0] != 'P')
|
||||
continue;
|
||||
pin = (pin_name[1] - 'A') << 5;
|
||||
if (pin >= 26 << 5)
|
||||
continue;
|
||||
pin += simple_strtol(&pin_name[2], NULL, 10);
|
||||
|
||||
sunxi_gpio_set_cfgpin(pin, SUN8I_GPD8_GMAC);
|
||||
sunxi_gpio_set_drv(pin, drive);
|
||||
sunxi_gpio_set_pull(pin, pull);
|
||||
}
|
||||
|
||||
if (!i) {
|
||||
printf("WARNING: emac: cannot find allwinner,pins property\n");
|
||||
return -2;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int _sun8i_eth_recv(struct emac_eth_dev *priv, uchar **packetp)
|
||||
{
|
||||
u32 status, desc_num = priv->rx_currdescnum;
|
||||
struct emac_dma_desc *desc_p = &priv->rx_chain[desc_num];
|
||||
int length = -EAGAIN;
|
||||
int good_packet = 1;
|
||||
uintptr_t desc_start = (uintptr_t)desc_p;
|
||||
uintptr_t desc_end = desc_start +
|
||||
roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
|
||||
|
||||
ulong data_start = (uintptr_t)desc_p->buf_addr;
|
||||
ulong data_end;
|
||||
|
||||
/* Invalidate entire buffer descriptor */
|
||||
invalidate_dcache_range(desc_start, desc_end);
|
||||
|
||||
status = desc_p->status;
|
||||
|
||||
/* Check for DMA own bit */
|
||||
if (!(status & BIT(31))) {
|
||||
length = (desc_p->status >> 16) & 0x3FFF;
|
||||
|
||||
if (length < 0x40) {
|
||||
good_packet = 0;
|
||||
debug("RX: Bad Packet (runt)\n");
|
||||
}
|
||||
|
||||
data_end = data_start + length;
|
||||
/* Invalidate received data */
|
||||
invalidate_dcache_range(rounddown(data_start,
|
||||
ARCH_DMA_MINALIGN),
|
||||
roundup(data_end,
|
||||
ARCH_DMA_MINALIGN));
|
||||
if (good_packet) {
|
||||
if (length > CONFIG_ETH_BUFSIZE) {
|
||||
printf("Received packet is too big (len=%d)\n",
|
||||
length);
|
||||
return -EMSGSIZE;
|
||||
}
|
||||
*packetp = (uchar *)(ulong)desc_p->buf_addr;
|
||||
return length;
|
||||
}
|
||||
}
|
||||
|
||||
return length;
|
||||
}
|
||||
|
||||
static int _sun8i_emac_eth_send(struct emac_eth_dev *priv, void *packet,
|
||||
int len)
|
||||
{
|
||||
u32 v, desc_num = priv->tx_currdescnum;
|
||||
struct emac_dma_desc *desc_p = &priv->tx_chain[desc_num];
|
||||
uintptr_t desc_start = (uintptr_t)desc_p;
|
||||
uintptr_t desc_end = desc_start +
|
||||
roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
|
||||
|
||||
uintptr_t data_start = (uintptr_t)desc_p->buf_addr;
|
||||
uintptr_t data_end = data_start +
|
||||
roundup(len, ARCH_DMA_MINALIGN);
|
||||
|
||||
/* Invalidate entire buffer descriptor */
|
||||
invalidate_dcache_range(desc_start, desc_end);
|
||||
|
||||
desc_p->st = len;
|
||||
/* Mandatory undocumented bit */
|
||||
desc_p->st |= BIT(24);
|
||||
|
||||
memcpy((void *)data_start, packet, len);
|
||||
|
||||
/* Flush data to be sent */
|
||||
flush_dcache_range(data_start, data_end);
|
||||
|
||||
/* frame end */
|
||||
desc_p->st |= BIT(30);
|
||||
desc_p->st |= BIT(31);
|
||||
|
||||
/*frame begin */
|
||||
desc_p->st |= BIT(29);
|
||||
desc_p->status = BIT(31);
|
||||
|
||||
/*Descriptors st and status field has changed, so FLUSH it */
|
||||
flush_dcache_range(desc_start, desc_end);
|
||||
|
||||
/* Move to next Descriptor and wrap around */
|
||||
if (++desc_num >= CONFIG_TX_DESCR_NUM)
|
||||
desc_num = 0;
|
||||
priv->tx_currdescnum = desc_num;
|
||||
|
||||
/* Start the DMA */
|
||||
v = readl(priv->mac_reg + EMAC_TX_CTL1);
|
||||
v |= BIT(31);/* mandatory */
|
||||
v |= BIT(30);/* mandatory */
|
||||
writel(v, priv->mac_reg + EMAC_TX_CTL1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sun8i_eth_write_hwaddr(struct udevice *dev)
|
||||
{
|
||||
struct eth_pdata *pdata = dev_get_platdata(dev);
|
||||
struct emac_eth_dev *priv = dev_get_priv(dev);
|
||||
|
||||
return _sun8i_write_hwaddr(priv, pdata->enetaddr);
|
||||
}
|
||||
|
||||
static void sun8i_emac_board_setup(struct emac_eth_dev *priv)
|
||||
{
|
||||
struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
|
||||
|
||||
if (priv->use_internal_phy) {
|
||||
/* Set clock gating for ephy */
|
||||
setbits_le32(&ccm->bus_gate4, BIT(AHB_GATE_OFFSET_EPHY));
|
||||
|
||||
/* Set Tx clock source as MII with rate 25 MZ */
|
||||
setbits_le32(priv->sysctl_reg, SCTL_EMAC_TX_CLK_SRC_MII |
|
||||
SCTL_EMAC_EPIT_MII | SCTL_EMAC_CLK_SEL);
|
||||
/* Deassert EPHY */
|
||||
setbits_le32(&ccm->ahb_reset2_cfg, BIT(AHB_RESET_OFFSET_EPHY));
|
||||
}
|
||||
|
||||
/* Set clock gating for emac */
|
||||
setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_GMAC));
|
||||
|
||||
/* Set EMAC clock */
|
||||
setbits_le32(&ccm->axi_gate, (BIT(1) | BIT(0)));
|
||||
|
||||
/* De-assert EMAC */
|
||||
setbits_le32(&ccm->ahb_reset0_cfg, BIT(AHB_RESET_OFFSET_GMAC));
|
||||
}
|
||||
|
||||
static int sun8i_mdio_init(const char *name, struct emac_eth_dev *priv)
|
||||
{
|
||||
struct mii_dev *bus = mdio_alloc();
|
||||
|
||||
if (!bus) {
|
||||
debug("Failed to allocate MDIO bus\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
bus->read = sun8i_mdio_read;
|
||||
bus->write = sun8i_mdio_write;
|
||||
snprintf(bus->name, sizeof(bus->name), name);
|
||||
bus->priv = (void *)priv;
|
||||
|
||||
return mdio_register(bus);
|
||||
}
|
||||
|
||||
static int sun8i_emac_eth_start(struct udevice *dev)
|
||||
{
|
||||
struct eth_pdata *pdata = dev_get_platdata(dev);
|
||||
|
||||
return _sun8i_emac_eth_init(dev->priv, pdata->enetaddr);
|
||||
}
|
||||
|
||||
static int sun8i_emac_eth_send(struct udevice *dev, void *packet, int length)
|
||||
{
|
||||
struct emac_eth_dev *priv = dev_get_priv(dev);
|
||||
|
||||
return _sun8i_emac_eth_send(priv, packet, length);
|
||||
}
|
||||
|
||||
static int sun8i_emac_eth_recv(struct udevice *dev, int flags, uchar **packetp)
|
||||
{
|
||||
struct emac_eth_dev *priv = dev_get_priv(dev);
|
||||
|
||||
return _sun8i_eth_recv(priv, packetp);
|
||||
}
|
||||
|
||||
static int _sun8i_free_pkt(struct emac_eth_dev *priv)
|
||||
{
|
||||
u32 desc_num = priv->rx_currdescnum;
|
||||
struct emac_dma_desc *desc_p = &priv->rx_chain[desc_num];
|
||||
uintptr_t desc_start = (uintptr_t)desc_p;
|
||||
uintptr_t desc_end = desc_start +
|
||||
roundup(sizeof(u32), ARCH_DMA_MINALIGN);
|
||||
|
||||
/* Make the current descriptor valid again */
|
||||
desc_p->status |= BIT(31);
|
||||
|
||||
/* Flush Status field of descriptor */
|
||||
flush_dcache_range(desc_start, desc_end);
|
||||
|
||||
/* Move to next desc and wrap-around condition. */
|
||||
if (++desc_num >= CONFIG_RX_DESCR_NUM)
|
||||
desc_num = 0;
|
||||
priv->rx_currdescnum = desc_num;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sun8i_eth_free_pkt(struct udevice *dev, uchar *packet,
|
||||
int length)
|
||||
{
|
||||
struct emac_eth_dev *priv = dev_get_priv(dev);
|
||||
|
||||
return _sun8i_free_pkt(priv);
|
||||
}
|
||||
|
||||
static void sun8i_emac_eth_stop(struct udevice *dev)
|
||||
{
|
||||
struct emac_eth_dev *priv = dev_get_priv(dev);
|
||||
|
||||
/* Stop Rx/Tx transmitter */
|
||||
clrbits_le32(priv->mac_reg + EMAC_RX_CTL0, BIT(31));
|
||||
clrbits_le32(priv->mac_reg + EMAC_TX_CTL0, BIT(31));
|
||||
|
||||
/* Stop TX DMA */
|
||||
clrbits_le32(priv->mac_reg + EMAC_TX_CTL1, BIT(30));
|
||||
|
||||
phy_shutdown(priv->phydev);
|
||||
}
|
||||
|
||||
static int sun8i_emac_eth_probe(struct udevice *dev)
|
||||
{
|
||||
struct eth_pdata *pdata = dev_get_platdata(dev);
|
||||
struct emac_eth_dev *priv = dev_get_priv(dev);
|
||||
|
||||
priv->mac_reg = (void *)pdata->iobase;
|
||||
|
||||
sun8i_emac_board_setup(priv);
|
||||
|
||||
sun8i_mdio_init(dev->name, priv);
|
||||
priv->bus = miiphy_get_dev_by_name(dev->name);
|
||||
|
||||
sun8i_emac_set_syscon(priv);
|
||||
|
||||
return sun8i_phy_init(priv, dev);
|
||||
}
|
||||
|
||||
static const struct eth_ops sun8i_emac_eth_ops = {
|
||||
.start = sun8i_emac_eth_start,
|
||||
.write_hwaddr = sun8i_eth_write_hwaddr,
|
||||
.send = sun8i_emac_eth_send,
|
||||
.recv = sun8i_emac_eth_recv,
|
||||
.free_pkt = sun8i_eth_free_pkt,
|
||||
.stop = sun8i_emac_eth_stop,
|
||||
};
|
||||
|
||||
static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev)
|
||||
{
|
||||
struct eth_pdata *pdata = dev_get_platdata(dev);
|
||||
struct emac_eth_dev *priv = dev_get_priv(dev);
|
||||
const char *phy_mode;
|
||||
int offset = 0;
|
||||
|
||||
pdata->iobase = dev_get_addr_name(dev, "emac");
|
||||
priv->sysctl_reg = dev_get_addr_name(dev, "syscon");
|
||||
|
||||
pdata->phy_interface = -1;
|
||||
priv->phyaddr = -1;
|
||||
priv->use_internal_phy = false;
|
||||
|
||||
offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset,
|
||||
"phy");
|
||||
if (offset > 0)
|
||||
priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg",
|
||||
-1);
|
||||
|
||||
phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
|
||||
|
||||
if (phy_mode)
|
||||
pdata->phy_interface = phy_get_interface_by_name(phy_mode);
|
||||
printf("phy interface%d\n", pdata->phy_interface);
|
||||
|
||||
if (pdata->phy_interface == -1) {
|
||||
debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
priv->variant = dev_get_driver_data(dev);
|
||||
|
||||
if (!priv->variant) {
|
||||
printf("%s: Missing variant '%s'\n", __func__,
|
||||
(char *)priv->variant);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (priv->variant == H3_EMAC) {
|
||||
if (fdt_getprop(gd->fdt_blob, dev->of_offset,
|
||||
"allwinner,use-internal-phy", NULL))
|
||||
priv->use_internal_phy = true;
|
||||
}
|
||||
|
||||
priv->interface = pdata->phy_interface;
|
||||
|
||||
if (!priv->use_internal_phy)
|
||||
parse_phy_pins(dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct udevice_id sun8i_emac_eth_ids[] = {
|
||||
{.compatible = "allwinner,sun8i-h3-emac", .data = (uintptr_t)H3_EMAC },
|
||||
{.compatible = "allwinner,sun50i-a64-emac",
|
||||
.data = (uintptr_t)A64_EMAC },
|
||||
{.compatible = "allwinner,sun8i-a83t-emac",
|
||||
.data = (uintptr_t)A83T_EMAC },
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(eth_sun8i_emac) = {
|
||||
.name = "eth_sun8i_emac",
|
||||
.id = UCLASS_ETH,
|
||||
.of_match = sun8i_emac_eth_ids,
|
||||
.ofdata_to_platdata = sun8i_emac_eth_ofdata_to_platdata,
|
||||
.probe = sun8i_emac_eth_probe,
|
||||
.ops = &sun8i_emac_eth_ops,
|
||||
.priv_auto_alloc_size = sizeof(struct emac_eth_dev),
|
||||
.platdata_auto_alloc_size = sizeof(struct eth_pdata),
|
||||
.flags = DM_FLAG_ALLOC_PRIV_DMA,
|
||||
};
|
||||
Loading…
Add table
Reference in a new issue