mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-29 08:01:08 +00:00
avr32: Rework SDRAM initialization code
This cleans up the SDRAM initialization and related code a bit, and
allows faster booting.
* Add definitions for EBI and internal SRAM to asm/arch/memory-map.h
* Remove memory test from sdram_init() and make caller responsible
for verifying the SDRAM and determining its size.
* Remove base_address member from struct sdram_config (was sdram_info)
* Add data_bits member to struct sdram_config and kill CFG_SDRAM_16BIT
* Add support for a common STK1000 hack: 16MB SDRAM instead of 8.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
This commit is contained in:
Haavard Skinnemoen
parent
95107b7c02
commit
a23e277c4a
10 changed files with 162 additions and 116 deletions
|
|
@ -29,8 +29,8 @@
|
|||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
static const struct sdram_info sdram = {
|
||||
.phys_addr = CFG_SDRAM_BASE,
|
||||
static const struct sdram_config sdram_config = {
|
||||
.data_bits = SDRAM_DATA_16BIT,
|
||||
.row_bits = 13,
|
||||
.col_bits = 9,
|
||||
.bank_bits = 2,
|
||||
|
|
@ -66,7 +66,22 @@ int board_early_init_f(void)
|
|||
|
||||
long int initdram(int board_type)
|
||||
{
|
||||
return sdram_init(&sdram);
|
||||
unsigned long expected_size;
|
||||
unsigned long actual_size;
|
||||
void *sdram_base;
|
||||
|
||||
sdram_base = map_physmem(EBI_SDRAM_BASE, EBI_SDRAM_SIZE, MAP_NOCACHE);
|
||||
|
||||
expected_size = sdram_init(sdram_base, &sdram_config);
|
||||
actual_size = get_ram_size(sdram_base, expected_size);
|
||||
|
||||
unmap_physmem(sdram_base, EBI_SDRAM_SIZE);
|
||||
|
||||
if (expected_size != actual_size)
|
||||
printf("Warning: Only %u of %u MiB SDRAM is working\n",
|
||||
actual_size >> 20, expected_size >> 20);
|
||||
|
||||
return actual_size;
|
||||
}
|
||||
|
||||
void board_init_info(void)
|
||||
|
|
|
|||
|
|
@ -29,10 +29,10 @@
|
|||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#ifdef CONFIG_ATSTK1006
|
||||
/* Dual MT48LC16M16A2-7E on daughterboard */
|
||||
static const struct sdram_info sdram = {
|
||||
.phys_addr = CFG_SDRAM_BASE,
|
||||
static const struct sdram_config sdram_config = {
|
||||
#if defined(CONFIG_ATSTK1006)
|
||||
/* Dual MT48LC16M16A2-7E (64 MB) on daughterboard */
|
||||
.data_bits = SDRAM_DATA_32BIT,
|
||||
.row_bits = 13,
|
||||
.col_bits = 9,
|
||||
.bank_bits = 2,
|
||||
|
|
@ -45,12 +45,19 @@ static const struct sdram_info sdram = {
|
|||
.txsr = 7,
|
||||
/* 7.81 us */
|
||||
.refresh_period = (781 * (SDRAMC_BUS_HZ / 1000)) / 100000,
|
||||
};
|
||||
#else
|
||||
/* MT48LC2M32B2-5 on motherboard */
|
||||
static const struct sdram_info sdram = {
|
||||
.phys_addr = CFG_SDRAM_BASE,
|
||||
/* MT48LC2M32B2P-5 (8 MB) on motherboard */
|
||||
#ifdef CONFIG_ATSTK1004
|
||||
.data_bits = SDRAM_DATA_16BIT,
|
||||
#else
|
||||
.data_bits = SDRAM_DATA_32BIT,
|
||||
#endif
|
||||
#ifdef CONFIG_ATSTK1000_16MB_SDRAM
|
||||
/* MT48LC4M32B2P-6 (16 MB) on mod'ed motherboard */
|
||||
.row_bits = 12,
|
||||
#else
|
||||
.row_bits = 11,
|
||||
#endif
|
||||
.col_bits = 8,
|
||||
.bank_bits = 2,
|
||||
.cas = 3,
|
||||
|
|
@ -62,8 +69,8 @@ static const struct sdram_info sdram = {
|
|||
.txsr = 5,
|
||||
/* 15.6 us */
|
||||
.refresh_period = (156 * (SDRAMC_BUS_HZ / 1000)) / 10000,
|
||||
};
|
||||
#endif
|
||||
};
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
|
|
@ -85,7 +92,22 @@ int board_early_init_f(void)
|
|||
|
||||
long int initdram(int board_type)
|
||||
{
|
||||
return sdram_init(&sdram);
|
||||
unsigned long expected_size;
|
||||
unsigned long actual_size;
|
||||
void *sdram_base;
|
||||
|
||||
sdram_base = map_physmem(EBI_SDRAM_BASE, EBI_SDRAM_SIZE, MAP_NOCACHE);
|
||||
|
||||
expected_size = sdram_init(sdram_base, &sdram_config);
|
||||
actual_size = get_ram_size(sdram_base, expected_size);
|
||||
|
||||
unmap_physmem(sdram_base, EBI_SDRAM_SIZE);
|
||||
|
||||
if (expected_size != actual_size)
|
||||
printf("Warning: Only %u of %u MiB SDRAM is working\n",
|
||||
actual_size >> 20, expected_size >> 20);
|
||||
|
||||
return actual_size;
|
||||
}
|
||||
|
||||
void board_init_info(void)
|
||||
|
|
|
|||
|
|
@ -30,39 +30,32 @@
|
|||
|
||||
#include "hsdramc1.h"
|
||||
|
||||
unsigned long sdram_init(const struct sdram_info *info)
|
||||
unsigned long sdram_init(void *sdram_base, const struct sdram_config *config)
|
||||
{
|
||||
unsigned long *sdram = (unsigned long *)uncached(info->phys_addr);
|
||||
unsigned long sdram_size;
|
||||
unsigned long tmp;
|
||||
unsigned long bus_hz;
|
||||
uint32_t cfgreg;
|
||||
unsigned int i;
|
||||
|
||||
if (!info->refresh_period)
|
||||
panic("ERROR: SDRAM refresh period == 0. "
|
||||
"Please update the board code\n");
|
||||
cfgreg = (HSDRAMC1_BF(NC, config->col_bits - 8)
|
||||
| HSDRAMC1_BF(NR, config->row_bits - 11)
|
||||
| HSDRAMC1_BF(NB, config->bank_bits - 1)
|
||||
| HSDRAMC1_BF(CAS, config->cas)
|
||||
| HSDRAMC1_BF(TWR, config->twr)
|
||||
| HSDRAMC1_BF(TRC, config->trc)
|
||||
| HSDRAMC1_BF(TRP, config->trp)
|
||||
| HSDRAMC1_BF(TRCD, config->trcd)
|
||||
| HSDRAMC1_BF(TRAS, config->tras)
|
||||
| HSDRAMC1_BF(TXSR, config->txsr));
|
||||
|
||||
tmp = (HSDRAMC1_BF(NC, info->col_bits - 8)
|
||||
| HSDRAMC1_BF(NR, info->row_bits - 11)
|
||||
| HSDRAMC1_BF(NB, info->bank_bits - 1)
|
||||
| HSDRAMC1_BF(CAS, info->cas)
|
||||
| HSDRAMC1_BF(TWR, info->twr)
|
||||
| HSDRAMC1_BF(TRC, info->trc)
|
||||
| HSDRAMC1_BF(TRP, info->trp)
|
||||
| HSDRAMC1_BF(TRCD, info->trcd)
|
||||
| HSDRAMC1_BF(TRAS, info->tras)
|
||||
| HSDRAMC1_BF(TXSR, info->txsr));
|
||||
if (config->data_bits == SDRAM_DATA_16BIT)
|
||||
cfgreg |= HSDRAMC1_BIT(DBW);
|
||||
|
||||
#ifdef CFG_SDRAM_16BIT
|
||||
tmp |= HSDRAMC1_BIT(DBW);
|
||||
sdram_size = 1 << (info->row_bits + info->col_bits
|
||||
+ info->bank_bits + 1);
|
||||
#else
|
||||
sdram_size = 1 << (info->row_bits + info->col_bits
|
||||
+ info->bank_bits + 2);
|
||||
#endif
|
||||
hsdramc1_writel(CR, cfgreg);
|
||||
|
||||
hsdramc1_writel(CR, tmp);
|
||||
/* Send a NOP to turn on the clock (necessary on some chips) */
|
||||
hsdramc1_writel(MR, HSDRAMC1_MODE_NOP);
|
||||
hsdramc1_readl(MR);
|
||||
writel(0, sdram_base);
|
||||
|
||||
/*
|
||||
* Initialization sequence for SDRAM, from the data sheet:
|
||||
|
|
@ -77,7 +70,7 @@ unsigned long sdram_init(const struct sdram_info *info)
|
|||
*/
|
||||
hsdramc1_writel(MR, HSDRAMC1_MODE_BANKS_PRECHARGE);
|
||||
hsdramc1_readl(MR);
|
||||
writel(0, sdram);
|
||||
writel(0, sdram_base);
|
||||
|
||||
/*
|
||||
* 3. Eight auto-refresh (CBR) cycles are provided
|
||||
|
|
@ -85,58 +78,41 @@ unsigned long sdram_init(const struct sdram_info *info)
|
|||
hsdramc1_writel(MR, HSDRAMC1_MODE_AUTO_REFRESH);
|
||||
hsdramc1_readl(MR);
|
||||
for (i = 0; i < 8; i++)
|
||||
writel(0, sdram);
|
||||
writel(0, sdram_base);
|
||||
|
||||
/*
|
||||
* 4. A mode register set (MRS) cycle is issued to program
|
||||
* SDRAM parameters, in particular CAS latency and burst
|
||||
* length.
|
||||
*
|
||||
* CAS from info struct, burst length 1, serial burst type
|
||||
* The address will be chosen by the SDRAMC automatically; we
|
||||
* just have to make sure BA[1:0] are set to 0.
|
||||
*/
|
||||
hsdramc1_writel(MR, HSDRAMC1_MODE_LOAD_MODE);
|
||||
hsdramc1_readl(MR);
|
||||
writel(0, sdram + (info->cas << 4));
|
||||
writel(0, sdram_base);
|
||||
|
||||
/*
|
||||
* 5. A Normal Mode command is provided, 3 clocks after tMRD
|
||||
* is met.
|
||||
*
|
||||
* From the timing diagram, it looks like tMRD is 3
|
||||
* cycles...try a dummy read from the peripheral bus.
|
||||
* 5. The application must go into Normal Mode, setting Mode
|
||||
* to 0 in the Mode Register and performing a write access
|
||||
* at any location in the SDRAM.
|
||||
*/
|
||||
hsdramc1_readl(MR);
|
||||
hsdramc1_writel(MR, HSDRAMC1_MODE_NORMAL);
|
||||
hsdramc1_readl(MR);
|
||||
writel(0, sdram);
|
||||
writel(0, sdram_base);
|
||||
|
||||
/*
|
||||
* 6. Write refresh rate into SDRAMC refresh timer count
|
||||
* register (refresh rate = timing between refresh cycles).
|
||||
*
|
||||
* 15.6 us is a typical value for a burst of length one
|
||||
*/
|
||||
bus_hz = get_sdram_clk_rate();
|
||||
hsdramc1_writel(TR, info->refresh_period);
|
||||
hsdramc1_writel(TR, config->refresh_period);
|
||||
|
||||
printf("SDRAM: %u MB at address 0x%08lx\n",
|
||||
sdram_size >> 20, info->phys_addr);
|
||||
|
||||
printf("Testing SDRAM...");
|
||||
for (i = 0; i < sdram_size / 4; i++)
|
||||
sdram[i] = i;
|
||||
|
||||
for (i = 0; i < sdram_size / 4; i++) {
|
||||
tmp = sdram[i];
|
||||
if (tmp != i) {
|
||||
printf("FAILED at address 0x%08lx\n",
|
||||
info->phys_addr + i * 4);
|
||||
printf("SDRAM: read 0x%lx, expected 0x%lx\n", tmp, i);
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
puts("OK\n");
|
||||
if (config->data_bits == SDRAM_DATA_16BIT)
|
||||
sdram_size = 1 << (config->row_bits + config->col_bits
|
||||
+ config->bank_bits + 1);
|
||||
else
|
||||
sdram_size = 1 << (config->row_bits + config->col_bits
|
||||
+ config->bank_bits + 2);
|
||||
|
||||
return sdram_size;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -22,6 +22,26 @@
|
|||
#ifndef __AT32AP7000_MEMORY_MAP_H__
|
||||
#define __AT32AP7000_MEMORY_MAP_H__
|
||||
|
||||
/* Internal and external memories */
|
||||
#define EBI_SRAM_CS0_BASE 0x00000000
|
||||
#define EBI_SRAM_CS0_SIZE 0x04000000
|
||||
#define EBI_SRAM_CS4_BASE 0x04000000
|
||||
#define EBI_SRAM_CS4_SIZE 0x04000000
|
||||
#define EBI_SRAM_CS2_BASE 0x08000000
|
||||
#define EBI_SRAM_CS2_SIZE 0x04000000
|
||||
#define EBI_SRAM_CS3_BASE 0x0c000000
|
||||
#define EBI_SRAM_CS3_SIZE 0x04000000
|
||||
#define EBI_SRAM_CS1_BASE 0x10000000
|
||||
#define EBI_SRAM_CS1_SIZE 0x10000000
|
||||
#define EBI_SRAM_CS5_BASE 0x20000000
|
||||
#define EBI_SRAM_CS5_SIZE 0x04000000
|
||||
|
||||
#define EBI_SDRAM_BASE EBI_SRAM_CS1_BASE
|
||||
#define EBI_SDRAM_SIZE EBI_SRAM_CS1_SIZE
|
||||
|
||||
#define INTERNAL_SRAM_BASE 0x24000000
|
||||
#define INTERNAL_SRAM_SIZE 0x00008000
|
||||
|
||||
/* Devices on the High Speed Bus (HSB) */
|
||||
#define LCDC_BASE 0xFF000000
|
||||
#define DMAC_BASE 0xFF200000
|
||||
|
|
|
|||
|
|
@ -22,15 +22,32 @@
|
|||
#ifndef __ASM_AVR32_SDRAM_H
|
||||
#define __ASM_AVR32_SDRAM_H
|
||||
|
||||
struct sdram_info {
|
||||
unsigned long phys_addr;
|
||||
unsigned int row_bits, col_bits, bank_bits;
|
||||
unsigned int cas, twr, trc, trp, trcd, tras, txsr;
|
||||
struct sdram_config {
|
||||
/* Number of data bits. */
|
||||
enum {
|
||||
SDRAM_DATA_16BIT,
|
||||
SDRAM_DATA_32BIT,
|
||||
} data_bits;
|
||||
|
||||
/* Number of address bits */
|
||||
uint8_t row_bits, col_bits, bank_bits;
|
||||
|
||||
/* SDRAM timings in cycles */
|
||||
uint8_t cas, twr, trc, trp, trcd, tras, txsr;
|
||||
|
||||
/* SDRAM refresh period in cycles */
|
||||
unsigned long refresh_period;
|
||||
};
|
||||
|
||||
extern unsigned long sdram_init(const struct sdram_info *info);
|
||||
/*
|
||||
* Attempt to initialize the SDRAM controller using the specified
|
||||
* parameters. Return the expected size of the memory area based on
|
||||
* the number of address and data bits.
|
||||
*
|
||||
* The caller should verify that the configuration is correct by
|
||||
* running a memory test, e.g. get_ram_size().
|
||||
*/
|
||||
extern unsigned long sdram_init(void *sdram_base,
|
||||
const struct sdram_config *config);
|
||||
|
||||
#endif /* __ASM_AVR32_SDRAM_H */
|
||||
|
|
|
|||
|
|
@ -24,6 +24,8 @@
|
|||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#include <asm/arch/memory-map.h>
|
||||
|
||||
#define CONFIG_AVR32 1
|
||||
#define CONFIG_AT32AP 1
|
||||
#define CONFIG_AT32AP7000 1
|
||||
|
|
@ -140,11 +142,9 @@
|
|||
|
||||
#define CFG_MONITOR_BASE CFG_FLASH_BASE
|
||||
|
||||
#define CFG_INTRAM_BASE 0x24000000
|
||||
#define CFG_INTRAM_SIZE 0x8000
|
||||
|
||||
#define CFG_SDRAM_BASE 0x10000000
|
||||
#define CFG_SDRAM_16BIT 1
|
||||
#define CFG_INTRAM_BASE INTERNAL_SRAM_BASE
|
||||
#define CFG_INTRAM_SIZE INTERNAL_SRAM_SIZE
|
||||
#define CFG_SDRAM_BASE EBI_SDRAM_BASE
|
||||
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
#define CFG_ENV_SIZE 65536
|
||||
|
|
@ -153,17 +153,10 @@
|
|||
#define CFG_INIT_SP_ADDR (CFG_INTRAM_BASE + CFG_INTRAM_SIZE)
|
||||
|
||||
#define CFG_MALLOC_LEN (256*1024)
|
||||
#define CFG_MALLOC_END \
|
||||
({ \
|
||||
DECLARE_GLOBAL_DATA_PTR; \
|
||||
CFG_SDRAM_BASE + gd->sdram_size; \
|
||||
})
|
||||
#define CFG_MALLOC_START (CFG_MALLOC_END - CFG_MALLOC_LEN)
|
||||
|
||||
#define CFG_DMA_ALLOC_LEN (16384)
|
||||
|
||||
/* Allow 4MB for the kernel run-time image */
|
||||
#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00400000)
|
||||
#define CFG_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)
|
||||
#define CFG_BOOTPARAMS_LEN (16 * 1024)
|
||||
|
||||
/* Other configuration settings that shouldn't have to change all that often */
|
||||
|
|
@ -173,7 +166,7 @@
|
|||
#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
|
||||
#define CFG_LONGHELP 1
|
||||
|
||||
#define CFG_MEMTEST_START CFG_SDRAM_BASE
|
||||
#define CFG_MEMTEST_START EBI_SDRAM_BASE
|
||||
#define CFG_MEMTEST_END (CFG_MEMTEST_START + 0x1f00000)
|
||||
|
||||
#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
|
||||
|
|
|
|||
|
|
@ -24,6 +24,8 @@
|
|||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#include <asm/arch/memory-map.h>
|
||||
|
||||
#define CONFIG_AVR32 1
|
||||
#define CONFIG_AT32AP 1
|
||||
#define CONFIG_AT32AP7000 1
|
||||
|
|
@ -170,10 +172,9 @@
|
|||
|
||||
#define CFG_MONITOR_BASE CFG_FLASH_BASE
|
||||
|
||||
#define CFG_INTRAM_BASE 0x24000000
|
||||
#define CFG_INTRAM_SIZE 0x8000
|
||||
|
||||
#define CFG_SDRAM_BASE 0x10000000
|
||||
#define CFG_INTRAM_BASE INTERNAL_SRAM_BASE
|
||||
#define CFG_INTRAM_SIZE INTERNAL_SRAM_SIZE
|
||||
#define CFG_SDRAM_BASE EBI_SDRAM_BASE
|
||||
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
#define CFG_ENV_SIZE 65536
|
||||
|
|
@ -185,7 +186,7 @@
|
|||
#define CFG_DMA_ALLOC_LEN (16384)
|
||||
|
||||
/* Allow 4MB for the kernel run-time image */
|
||||
#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00400000)
|
||||
#define CFG_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)
|
||||
#define CFG_BOOTPARAMS_LEN (16 * 1024)
|
||||
|
||||
/* Other configuration settings that shouldn't have to change all that often */
|
||||
|
|
@ -195,7 +196,7 @@
|
|||
#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
|
||||
#define CFG_LONGHELP 1
|
||||
|
||||
#define CFG_MEMTEST_START CFG_SDRAM_BASE
|
||||
#define CFG_MEMTEST_START EBI_SDRAM_BASE
|
||||
#define CFG_MEMTEST_END (CFG_MEMTEST_START + 0x700000)
|
||||
#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
|
||||
|
||||
|
|
|
|||
|
|
@ -24,6 +24,8 @@
|
|||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#include <asm/arch/memory-map.h>
|
||||
|
||||
#define CONFIG_AVR32 1
|
||||
#define CONFIG_AT32AP 1
|
||||
#define CONFIG_AT32AP7001 1
|
||||
|
|
@ -153,10 +155,9 @@
|
|||
|
||||
#define CFG_MONITOR_BASE CFG_FLASH_BASE
|
||||
|
||||
#define CFG_INTRAM_BASE 0x24000000
|
||||
#define CFG_INTRAM_SIZE 0x8000
|
||||
|
||||
#define CFG_SDRAM_BASE 0x10000000
|
||||
#define CFG_INTRAM_BASE INTERNAL_SRAM_BASE
|
||||
#define CFG_INTRAM_SIZE INTERNAL_SRAM_SIZE
|
||||
#define CFG_SDRAM_BASE EBI_SDRAM_BASE
|
||||
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
#define CFG_ENV_SIZE 65536
|
||||
|
|
@ -167,7 +168,7 @@
|
|||
#define CFG_MALLOC_LEN (256*1024)
|
||||
|
||||
/* Allow 4MB for the kernel run-time image */
|
||||
#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00400000)
|
||||
#define CFG_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)
|
||||
#define CFG_BOOTPARAMS_LEN (16 * 1024)
|
||||
|
||||
/* Other configuration settings that shouldn't have to change all that often */
|
||||
|
|
@ -177,7 +178,7 @@
|
|||
#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
|
||||
#define CFG_LONGHELP 1
|
||||
|
||||
#define CFG_MEMTEST_START CFG_SDRAM_BASE
|
||||
#define CFG_MEMTEST_START EBI_SDRAM_BASE
|
||||
#define CFG_MEMTEST_END (CFG_MEMTEST_START + 0x700000)
|
||||
#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
|
||||
|
||||
|
|
|
|||
|
|
@ -24,6 +24,8 @@
|
|||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#include <asm/arch/memory-map.h>
|
||||
|
||||
#define CONFIG_AVR32 1
|
||||
#define CONFIG_AT32AP 1
|
||||
#define CONFIG_AT32AP7002 1
|
||||
|
|
@ -153,11 +155,9 @@
|
|||
|
||||
#define CFG_MONITOR_BASE CFG_FLASH_BASE
|
||||
|
||||
#define CFG_INTRAM_BASE 0x24000000
|
||||
#define CFG_INTRAM_SIZE 0x8000
|
||||
|
||||
#define CFG_SDRAM_BASE 0x10000000
|
||||
#define CFG_SDRAM_16BIT 1
|
||||
#define CFG_INTRAM_BASE INTERNAL_SRAM_BASE
|
||||
#define CFG_INTRAM_SIZE INTERNAL_SRAM_SIZE
|
||||
#define CFG_SDRAM_BASE EBI_SDRAM_BASE
|
||||
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
#define CFG_ENV_SIZE 65536
|
||||
|
|
@ -168,7 +168,7 @@
|
|||
#define CFG_MALLOC_LEN (256*1024)
|
||||
|
||||
/* Allow 2MB for the kernel run-time image */
|
||||
#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00200000)
|
||||
#define CFG_LOAD_ADDR (EBI_SDRAM_BASE + 0x00200000)
|
||||
#define CFG_BOOTPARAMS_LEN (16 * 1024)
|
||||
|
||||
/* Other configuration settings that shouldn't have to change all that often */
|
||||
|
|
@ -178,7 +178,7 @@
|
|||
#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
|
||||
#define CFG_LONGHELP 1
|
||||
|
||||
#define CFG_MEMTEST_START CFG_SDRAM_BASE
|
||||
#define CFG_MEMTEST_START EBI_SDRAM_BASE
|
||||
#define CFG_MEMTEST_END (CFG_MEMTEST_START + 0x700000)
|
||||
#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
|
||||
|
||||
|
|
|
|||
|
|
@ -24,6 +24,8 @@
|
|||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#include <asm/arch/memory-map.h>
|
||||
|
||||
#define CONFIG_AVR32 1
|
||||
#define CONFIG_AT32AP 1
|
||||
#define CONFIG_AT32AP7000 1
|
||||
|
|
@ -170,10 +172,9 @@
|
|||
|
||||
#define CFG_MONITOR_BASE CFG_FLASH_BASE
|
||||
|
||||
#define CFG_INTRAM_BASE 0x24000000
|
||||
#define CFG_INTRAM_SIZE 0x8000
|
||||
|
||||
#define CFG_SDRAM_BASE 0x10000000
|
||||
#define CFG_INTRAM_BASE INTERNAL_SRAM_BASE
|
||||
#define CFG_INTRAM_SIZE INTERNAL_SRAM_SIZE
|
||||
#define CFG_SDRAM_BASE EBI_SDRAM_BASE
|
||||
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
#define CFG_ENV_SIZE 65536
|
||||
|
|
@ -185,7 +186,7 @@
|
|||
#define CFG_DMA_ALLOC_LEN (16384)
|
||||
|
||||
/* Allow 4MB for the kernel run-time image */
|
||||
#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00400000)
|
||||
#define CFG_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)
|
||||
#define CFG_BOOTPARAMS_LEN (16 * 1024)
|
||||
|
||||
/* Other configuration settings that shouldn't have to change all that often */
|
||||
|
|
@ -195,7 +196,7 @@
|
|||
#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
|
||||
#define CFG_LONGHELP 1
|
||||
|
||||
#define CFG_MEMTEST_START CFG_SDRAM_BASE
|
||||
#define CFG_MEMTEST_START EBI_SDRAM_BASE
|
||||
#define CFG_MEMTEST_END (CFG_MEMTEST_START + 0x3f00000)
|
||||
#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue