mirror of
https://github.com/AsahiLinux/u-boot
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arm: add mach-nexell (header files)
Changes in relation to FriendlyARM's U-Boot nanopi2-v2016.01: - DM_VIDEO support (display_dev.h). - boot0.h added, handles NSIH --> tools/nexell obsolete. - gpio.h: Include-path to errno.h changed. Signed-off-by: Stefan Bosch <stefan_b@posteo.net>
This commit is contained in:
Stefan Bosch
Tom Rini
parent
2e2c2a5e72
commit
a1ce9ed063
12 changed files with 1624 additions and 0 deletions
40
arch/arm/mach-nexell/include/mach/boot0.h
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40
arch/arm/mach-nexell/include/mach/boot0.h
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@ -0,0 +1,40 @@
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/* SPDX-License-Identifier: GPL-2.0+
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*
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* NSIH (Nexell System Information Header) for FriendlyArm nanopi2 board
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*
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* The NSIH (first 512 Bytes of u-boot.bin) is necessary for the
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* 2nd-Bootloader to get information like load address of U-Boot.
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*
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* 0x400 must be added to CONFIG_SYS_TEXT_BASE to have the actual load and
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* start address because 2nd-Bootloader loads with an offset of 0x400
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* (NSIH + 0x200 bytes are not loaded into RAM).
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*
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* It has been tested / is working with the following 2nd-Bootloader:
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* "BL1 by Nexell V1.0.0-gd551e13 [Built on 2018-01-25 16:58:29]"
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*
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* (C) Copyright 2020 Stefan Bosch <stefan_b@posteo.net>
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*/
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#ifndef __BOOT0_H
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#define __BOOT0_H
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ARM_VECTORS
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.space 0x30
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.word (_end - _start) + 20 * 1024 /* 0x50: load size
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* (bin + 20k for DTB) */
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.space 0x4
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.word CONFIG_SYS_TEXT_BASE + 0x400 /* 0x58: load address */
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.word 0x00000000
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.word CONFIG_SYS_TEXT_BASE + 0x400 /* 0x60: start address */
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.space 0x198
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.byte 'N' /* 0x1FC: "NSIH" signature */
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.byte 'S'
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.byte 'I'
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.byte 'H'
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/* The NSIH + 0x200 bytes are omitted by the 2nd-Bootloader */
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.space 0x200
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_start:
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ARM_VECTORS
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#endif /* __BOOT0_H */
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24
arch/arm/mach-nexell/include/mach/clk.h
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arch/arm/mach-nexell/include/mach/clk.h
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/* SPDX-License-Identifier: GPL-2.0+
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*
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* (C) Copyright 2016 Nexell
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* Hyunseok, Jung <hsjung@nexell.co.kr>
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*/
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#ifndef __ASM_ARM_ARCH_CLK_H_
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#define __ASM_ARM_ARCH_CLK_H_
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struct clk {
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unsigned long rate;
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};
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void clk_init(void);
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struct clk *clk_get(const char *id);
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void clk_put(struct clk *clk);
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unsigned long clk_get_rate(struct clk *clk);
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long clk_round_rate(struct clk *clk, unsigned long rate);
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int clk_set_rate(struct clk *clk, unsigned long rate);
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int clk_enable(struct clk *clk);
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void clk_disable(struct clk *clk);
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#endif
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273
arch/arm/mach-nexell/include/mach/display.h
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arch/arm/mach-nexell/include/mach/display.h
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/* SPDX-License-Identifier: GPL-2.0+
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*
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* Copyright (C) 2016 Nexell Co., Ltd.
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*
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* Author: junghyun, kim <jhkim@nexell.co.kr>
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*/
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#ifndef _NX__DISPLAY_H_
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#define _NX__DISPLAY_H_
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#define DP_PLANS_NUM 3
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/* the display output format. */
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#define DPC_FORMAT_RGB555 0 /* RGB555 Format */
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#define DPC_FORMAT_RGB565 1 /* RGB565 Format */
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#define DPC_FORMAT_RGB666 2 /* RGB666 Format */
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#define DPC_FORMAT_RGB888 3 /* RGB888 Format */
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#define DPC_FORMAT_MRGB555A 4 /* MRGB555A Format */
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#define DPC_FORMAT_MRGB555B 5 /* MRGB555B Format */
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#define DPC_FORMAT_MRGB565 6 /* MRGB565 Format */
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#define DPC_FORMAT_MRGB666 7 /* MRGB666 Format */
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#define DPC_FORMAT_MRGB888A 8 /* MRGB888A Format */
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#define DPC_FORMAT_MRGB888B 9 /* MRGB888B Format */
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#define DPC_FORMAT_CCIR656 10 /* ITU-R BT.656 / 601(8-bit) */
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#define DPC_FORMAT_CCIR601A 12 /* ITU-R BT.601A */
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#define DPC_FORMAT_CCIR601B 13 /* ITU-R BT.601B */
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#define DPC_FORMAT_4096COLOR 1 /* 4096 Color Format */
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#define DPC_FORMAT_16GRAY 3 /* 16 Level Gray Format */
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/* layer pixel format. */
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#define MLC_RGBFMT_R5G6B5 0x44320000 /* {R5,G6,B5 }. */
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#define MLC_RGBFMT_B5G6R5 0xC4320000 /* {B5,G6,R5 }. */
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#define MLC_RGBFMT_X1R5G5B5 0x43420000 /* {X1,R5,G5,B5}. */
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#define MLC_RGBFMT_X1B5G5R5 0xC3420000 /* {X1,B5,G5,R5}. */
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#define MLC_RGBFMT_X4R4G4B4 0x42110000 /* {X4,R4,G4,B4}. */
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#define MLC_RGBFMT_X4B4G4R4 0xC2110000 /* {X4,B4,G4,R4}. */
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#define MLC_RGBFMT_X8R3G3B2 0x41200000 /* {X8,R3,G3,B2}. */
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#define MLC_RGBFMT_X8B3G3R2 0xC1200000 /* {X8,B3,G3,R2}. */
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#define MLC_RGBFMT_A1R5G5B5 0x33420000 /* {A1,R5,G5,B5}. */
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#define MLC_RGBFMT_A1B5G5R5 0xB3420000 /* {A1,B5,G5,R5}. */
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#define MLC_RGBFMT_A4R4G4B4 0x22110000 /* {A4,R4,G4,B4}. */
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#define MLC_RGBFMT_A4B4G4R4 0xA2110000 /* {A4,B4,G4,R4}. */
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#define MLC_RGBFMT_A8R3G3B2 0x11200000 /* {A8,R3,G3,B2}. */
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#define MLC_RGBFMT_A8B3G3R2 0x91200000 /* {A8,B3,G3,R2}. */
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#define MLC_RGBFMT_R8G8B8 0x46530000 /* {R8,G8,B8 }. */
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#define MLC_RGBFMT_B8G8R8 0xC6530000 /* {B8,G8,R8 }. */
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#define MLC_RGBFMT_X8R8G8B8 0x46530000 /* {X8,R8,G8,B8}. */
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#define MLC_RGBFMT_X8B8G8R8 0xC6530000 /* {X8,B8,G8,R8}. */
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#define MLC_RGBFMT_A8R8G8B8 0x06530000 /* {A8,R8,G8,B8}. */
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#define MLC_RGBFMT_A8B8G8R8 0x86530000 /* {A8,B8,G8,R8}. */
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/* the data output order in case of ITU-R BT.656 / 601. */
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#define DPC_YCORDER_CBYCRY 0
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#define DPC_YCORDER_CRYCBY 1
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#define DPC_YCORDER_YCBYCR 2
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#define DPC_YCORDER_YCRYCB 3
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/* the PAD output clock. */
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#define DPC_PADCLKSEL_VCLK 0 /* VCLK */
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#define DPC_PADCLKSEL_VCLK2 1 /* VCLK2 */
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/* display sync info for DPC */
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struct dp_sync_info {
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int interlace;
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int h_active_len;
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int h_sync_width;
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int h_back_porch;
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int h_front_porch;
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int h_sync_invert; /* default active low */
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int v_active_len;
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int v_sync_width;
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int v_back_porch;
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int v_front_porch;
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int v_sync_invert; /* default active low */
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int pixel_clock_hz; /* HZ */
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};
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/* syncgen control (DPC) */
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#define DP_SYNC_DELAY_RGB_PVD (1 << 0)
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#define DP_SYNC_DELAY_HSYNC_CP1 (1 << 1)
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#define DP_SYNC_DELAY_VSYNC_FRAM (1 << 2)
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#define DP_SYNC_DELAY_DE_CP (1 << 3)
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struct dp_ctrl_info {
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/* clock gen */
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int clk_src_lv0;
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int clk_div_lv0;
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int clk_src_lv1;
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int clk_div_lv1;
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/* scan format */
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int interlace;
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/* syncgen format */
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unsigned int out_format;
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int invert_field; /* 0:normal(Low odd), 1:invert (low even) */
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int swap_RB;
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unsigned int yc_order; /* for CCIR output */
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/* extern sync delay */
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int delay_mask; /* if 0, set defalut delays */
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int d_rgb_pvd; /* delay for RGB/PVD, 0~16, default 0 */
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int d_hsync_cp1; /* delay for HSYNC/CP1, 0~63, default 12 */
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int d_vsync_fram; /* delay for VSYNC/FRAM, 0~63, default 12 */
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int d_de_cp2; /* delay for DE/CP2, 0~63, default 12 */
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/* sync offset */
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int vs_start_offset; /* start vsync offset, defatult 0 */
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int vs_end_offset; /* end vsync offset, default 0 */
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int ev_start_offset; /* start even vsync offset, default 0 */
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int ev_end_offset; /* end even vsync offset , default 0 */
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/* pad clock seletor */
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int vck_select; /* 0=vclk0, 1=vclk2 */
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int clk_inv_lv0; /* OUTCLKINVn */
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int clk_delay_lv0; /* OUTCLKDELAYn */
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int clk_inv_lv1; /* OUTCLKINVn */
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int clk_delay_lv1; /* OUTCLKDELAYn */
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int clk_sel_div1; /* 0=clk1_inv, 1=clk1_div_2_ns */
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};
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/* multi layer control (MLC) */
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struct dp_plane_top {
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int screen_width;
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int screen_height;
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int video_prior; /* 0: video>RGBn, 1: RGB0>video>RGB1,
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* 2: RGB0 > RGB1 > video .. */
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int interlace;
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int plane_num;
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unsigned int back_color;
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};
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struct dp_plane_info {
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int layer;
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unsigned int fb_base;
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int left;
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int top;
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int width;
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int height;
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int pixel_byte;
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unsigned int format;
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int alpha_on;
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int alpha_depth;
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int tp_on; /* transparency color enable */
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unsigned int tp_color;
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unsigned int mem_lock_size; /* memory burst access (4,8,16) */
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int video_layer;
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int enable;
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};
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/*
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* LCD device dependency struct
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* RGB, LVDS, MiPi, HDMI
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*/
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enum {
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DP_DEVICE_RESCONV = 0,
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DP_DEVICE_RGBLCD = 1,
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DP_DEVICE_HDMI = 2,
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DP_DEVICE_MIPI = 3,
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DP_DEVICE_LVDS = 4,
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DP_DEVICE_CVBS = 5,
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DP_DEVICE_DP0 = 6,
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DP_DEVICE_DP1 = 7,
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DP_DEVICE_END,
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};
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enum {
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DP_CLOCK_RESCONV = 0,
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DP_CLOCK_LCDIF = 1,
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DP_CLOCK_MIPI = 2,
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DP_CLOCK_LVDS = 3,
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DP_CLOCK_HDMI = 4,
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DP_CLOCK_END,
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};
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enum dp_lvds_format {
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DP_LVDS_FORMAT_VESA = 0,
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DP_LVDS_FORMAT_JEIDA = 1,
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DP_LVDS_FORMAT_LOC = 2,
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};
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#define DEF_VOLTAGE_LEVEL (0x20)
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struct dp_lvds_dev {
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enum dp_lvds_format lvds_format; /* 0:VESA, 1:JEIDA, 2: Location */
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int pol_inv_hs; /* hsync polarity invert for VESA, JEIDA */
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int pol_inv_vs; /* bsync polarity invert for VESA, JEIDA */
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int pol_inv_de; /* de polarity invert for VESA, JEIDA */
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int pol_inv_ck; /* input clock(pixel clock) polarity invert */
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int voltage_level;
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/* Location setting */
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unsigned int loc_map[9]; /* Location Setting */
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unsigned int loc_mask[2]; /* Location Setting, 0 ~ 34 */
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unsigned int loc_pol[2]; /* Location Setting, 0 ~ 34 */
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};
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#include "mipi_display.h"
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struct dp_mipi_dev {
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int lp_bitrate; /* to lcd setup, low power bitrate (150, 100, 80 Mhz) */
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int hs_bitrate; /* to lcd data, high speed bitrate (1000, ... Mhz) */
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int lpm_trans;
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int command_mode;
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unsigned int hs_pllpms;
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unsigned int hs_bandctl;
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unsigned int lp_pllpms;
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unsigned int lp_bandctl;
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struct mipi_dsi_device dsi;
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};
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struct dp_rgb_dev {
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int lcd_mpu_type;
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};
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struct dp_hdmi_dev {
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int preset;
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};
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/* platform data for the driver model */
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struct nx_display_platdata {
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int module;
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struct dp_sync_info sync;
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struct dp_ctrl_info ctrl;
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struct dp_plane_top top;
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struct dp_plane_info plane[DP_PLANS_NUM];
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int dev_type;
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void *device;
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};
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/* Lcd api */
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void nx_lvds_display(int module,
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struct dp_sync_info *sync, struct dp_ctrl_info *ctrl,
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struct dp_plane_top *top,
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struct dp_plane_info *planes,
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struct dp_lvds_dev *dev);
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void nx_rgb_display(int module,
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struct dp_sync_info *sync, struct dp_ctrl_info *ctrl,
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struct dp_plane_top *top, struct dp_plane_info *planes,
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struct dp_rgb_dev *dev);
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void nx_hdmi_display(int module,
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struct dp_sync_info *sync, struct dp_ctrl_info *ctrl,
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struct dp_plane_top *top,
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struct dp_plane_info *planes,
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struct dp_hdmi_dev *dev);
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void nx_mipi_display(int module,
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struct dp_sync_info *sync, struct dp_ctrl_info *ctrl,
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struct dp_plane_top *top,
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struct dp_plane_info *planes,
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struct dp_mipi_dev *dev);
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int nx_mipi_dsi_lcd_bind(struct mipi_dsi_device *dsi);
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/* disaply api */
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void dp_control_init(int module);
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int dp_control_setup(int module, struct dp_sync_info *sync,
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struct dp_ctrl_info *ctrl);
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void dp_control_enable(int module, int on);
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void dp_plane_init(int module);
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int dp_plane_screen_setup(int module, struct dp_plane_top *top);
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void dp_plane_screen_enable(int module, int on);
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int dp_plane_layer_setup(int module, struct dp_plane_info *plane);
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void dp_plane_layer_enable(int module, struct dp_plane_info *plane, int on);
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||||||
|
int dp_plane_set_enable(int module, int layer, int on);
|
||||||
|
int dp_plane_set_address(int module, int layer, unsigned int address);
|
||||||
|
int dp_plane_wait_vsync(int module, int layer, int fps);
|
||||||
|
|
||||||
|
#if defined CONFIG_SPL_BUILD || \
|
||||||
|
(!defined(CONFIG_DM) && !defined(CONFIG_OF_CONTROL))
|
||||||
|
int nx_display_probe(struct nx_display_platdata *plat);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
37
arch/arm/mach-nexell/include/mach/display_dev.h
Normal file
37
arch/arm/mach-nexell/include/mach/display_dev.h
Normal file
|
|
@ -0,0 +1,37 @@
|
||||||
|
/* SPDX-License-Identifier: GPL-2.0+
|
||||||
|
*
|
||||||
|
* Copyright (C) 2016 Nexell Co., Ltd.
|
||||||
|
*
|
||||||
|
* Author: junghyun, kim <jhkim@nexell.co.kr>
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _NX__DISPLAY_DEV_H_
|
||||||
|
#define _NX__DISPLAY_DEV_H_
|
||||||
|
|
||||||
|
#if defined CONFIG_VIDEO || defined CONFIG_DM_VIDEO
|
||||||
|
#include <video_fb.h>
|
||||||
|
#elif defined CONFIG_LCD
|
||||||
|
#include <lcd.h>
|
||||||
|
#endif
|
||||||
|
|
||||||
|
struct nx_display_dev {
|
||||||
|
#if defined CONFIG_VIDEO || defined CONFIG_DM_VIDEO
|
||||||
|
GraphicDevice graphic_device;
|
||||||
|
#elif defined CONFIG_LCD
|
||||||
|
vidinfo_t *panel_info;
|
||||||
|
#endif
|
||||||
|
unsigned long base;
|
||||||
|
int module;
|
||||||
|
struct dp_sync_info sync;
|
||||||
|
struct dp_ctrl_info ctrl;
|
||||||
|
struct dp_plane_top top;
|
||||||
|
struct dp_plane_info planes[DP_PLANS_NUM];
|
||||||
|
int dev_type;
|
||||||
|
void *device;
|
||||||
|
struct dp_plane_info *fb_plane;
|
||||||
|
unsigned int depth; /* byte per pixel */
|
||||||
|
unsigned int fb_addr;
|
||||||
|
unsigned int fb_size;
|
||||||
|
};
|
||||||
|
|
||||||
|
#endif
|
||||||
106
arch/arm/mach-nexell/include/mach/ehci.h
Normal file
106
arch/arm/mach-nexell/include/mach/ehci.h
Normal file
|
|
@ -0,0 +1,106 @@
|
||||||
|
/* SPDX-License-Identifier: GPL-2.0+
|
||||||
|
*
|
||||||
|
* NEXELL USB HOST EHCI Controller
|
||||||
|
*
|
||||||
|
* (C) Copyright 2016 Nexell
|
||||||
|
* Hyunseok, Jung <hsjung@nexell.co.kr>
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __ASM_ARM_ARCH_EHCI_H__
|
||||||
|
#define __ASM_ARM_ARCH_EHCI_H__
|
||||||
|
|
||||||
|
/* Nexell USBHOST PHY registers */
|
||||||
|
|
||||||
|
/* USBHOST Configuration 0 Register */
|
||||||
|
#define NX_HOST_CON0 0x14
|
||||||
|
#define NX_HOST_CON0_SS_WORD_IF BIT(26)
|
||||||
|
#define NX_HOST_CON0_SS_WORD_IF_ENB BIT(25)
|
||||||
|
#define NX_HOST_CON0_SS_WORD_IF_16 ( \
|
||||||
|
NX_HOST_CON0_SS_WORD_IF | \
|
||||||
|
NX_HOST_CON0_SS_WORD_IF_ENB)
|
||||||
|
|
||||||
|
#define NX_HOST_CON0_HSIC_480M_FROM_OTG_PHY BIT(24)
|
||||||
|
#define NX_HOST_CON0_HSIC_FREE_CLOCK_ENB BIT(23)
|
||||||
|
#define NX_HOST_CON0_HSIC_CLK_MASK (0x3 << 23)
|
||||||
|
|
||||||
|
#define NX_HOST_CON0_N_HOST_HSIC_RESET_SYNC BIT(22)
|
||||||
|
#define NX_HOST_CON0_N_HOST_UTMI_RESET_SYNC BIT(21)
|
||||||
|
#define NX_HOST_CON0_N_HOST_PHY_RESET_SYNC BIT(20)
|
||||||
|
#define NX_HOST_CON0_UTMI_RESET_SYNC ( \
|
||||||
|
NX_HOST_CON0_N_HOST_HSIC_RESET_SYNC | \
|
||||||
|
NX_HOST_CON0_N_HOST_UTMI_RESET_SYNC | \
|
||||||
|
NX_HOST_CON0_N_HOST_PHY_RESET_SYNC)
|
||||||
|
|
||||||
|
#define NX_HOST_CON0_N_AUXWELL_RESET_SYNC BIT(19)
|
||||||
|
#define NX_HOST_CON0_N_OHCI_RESET_SYNC BIT(18)
|
||||||
|
#define NX_HOST_CON0_N_RESET_SYNC BIT(17)
|
||||||
|
#define NX_HOST_CON0_AHB_RESET_SYNC ( \
|
||||||
|
NX_HOST_CON0_N_AUXWELL_RESET_SYNC | \
|
||||||
|
NX_HOST_CON0_N_OHCI_RESET_SYNC | \
|
||||||
|
NX_HOST_CON0_N_RESET_SYNC)
|
||||||
|
|
||||||
|
#define NX_HOST_CON0_HSIC_EN_PORT1 (0x2 << 14)
|
||||||
|
#define NX_HOST_CON0_HSIC_EN_MASK (0x7 << 14)
|
||||||
|
|
||||||
|
/* USBHOST Configuration 1 Register */
|
||||||
|
#define NX_HOST_CON1 0x18
|
||||||
|
|
||||||
|
/* USBHOST Configuration 2 Register */
|
||||||
|
#define NX_HOST_CON2 0x1C
|
||||||
|
#define NX_HOST_CON2_SS_ENA_INCRX_ALIGN (0x1 << 28)
|
||||||
|
#define NX_HOST_CON2_SS_ENA_INCR4 (0x1 << 27)
|
||||||
|
#define NX_HOST_CON2_SS_ENA_INCR8 (0x1 << 26)
|
||||||
|
#define NX_HOST_CON2_SS_ENA_INCR16 (0x1 << 25)
|
||||||
|
#define NX_HOST_CON2_SS_DMA_BURST_MASK \
|
||||||
|
(NX_HOST_CON2_SS_ENA_INCR16 | NX_HOST_CON2_SS_ENA_INCR8 | \
|
||||||
|
NX_HOST_CON2_SS_ENA_INCR4 | NX_HOST_CON2_SS_ENA_INCRX_ALIGN)
|
||||||
|
|
||||||
|
#define NX_HOST_CON2_EHCI_SS_ENABLE_DMA_BURST \
|
||||||
|
(NX_HOST_CON2_SS_ENA_INCR16 | NX_HOST_CON2_SS_ENA_INCR8 | \
|
||||||
|
NX_HOST_CON2_SS_ENA_INCR4 | NX_HOST_CON2_SS_ENA_INCRX_ALIGN)
|
||||||
|
|
||||||
|
#define NX_HOST_CON2_OHCI_SS_ENABLE_DMA_BURST \
|
||||||
|
(NX_HOST_CON2_SS_ENA_INCR4 | NX_HOST_CON2_SS_ENA_INCRX_ALIGN)
|
||||||
|
|
||||||
|
#define NX_HOST_CON2_SS_FLADJ_VAL_0_OFFSET (21)
|
||||||
|
#define NX_HOST_CON2_SS_FLADJ_VAL_OFFSET (3)
|
||||||
|
#define NX_HOST_CON2_SS_FLADJ_VAL_NUM (6)
|
||||||
|
#define NX_HOST_CON2_SS_FLADJ_VAL_0_SEL BIT(5)
|
||||||
|
#define NX_HOST_CON2_SS_FLADJ_VAL_MAX 0x7
|
||||||
|
|
||||||
|
/* USBHOST Configuration 3 Register */
|
||||||
|
#define NX_HOST_CON3 0x20
|
||||||
|
#define NX_HOST_CON3_POR BIT(8)
|
||||||
|
#define NX_HOST_CON3_POR_ENB BIT(7)
|
||||||
|
#define NX_HOST_CON3_POR_MASK (0x3 << 7)
|
||||||
|
|
||||||
|
/* USBHOST Configuration 4 Register */
|
||||||
|
#define NX_HOST_CON4 0x24
|
||||||
|
#define NX_HOST_CON4_WORDINTERFACE BIT(9)
|
||||||
|
#define NX_HOST_CON4_WORDINTERFACE_ENB BIT(8)
|
||||||
|
#define NX_HOST_CON4_WORDINTERFACE_16 ( \
|
||||||
|
NX_HOST_CON4_WORDINTERFACE | \
|
||||||
|
NX_HOST_CON4_WORDINTERFACE_ENB)
|
||||||
|
|
||||||
|
/* USBHOST Configuration 5 Register */
|
||||||
|
#define NX_HOST_CON5 0x28
|
||||||
|
#define NX_HOST_CON5_HSIC_POR BIT(19)
|
||||||
|
#define NX_HOST_CON5_HSIC_POR_ENB BIT(18)
|
||||||
|
#define NX_HOST_CON5_HSIC_POR_MASK (0x3 << 18)
|
||||||
|
|
||||||
|
/* USBHOST Configuration 6 Register */
|
||||||
|
#define NX_HOST_CON6 0x2C
|
||||||
|
#define NX_HOST_CON6_HSIC_WORDINTERFACE BIT(13)
|
||||||
|
#define NX_HOST_CON6_HSIC_WORDINTERFACE_ENB BIT(12)
|
||||||
|
#define NX_HOST_CON6_HSIC_WORDINTERFACE_16 ( \
|
||||||
|
NX_HOST_CON6_HSIC_WORDINTERFACE | \
|
||||||
|
NX_HOST_CON6_HSIC_WORDINTERFACE_ENB)
|
||||||
|
|
||||||
|
/* Register map for PHY control */
|
||||||
|
struct nx_usb_phy {
|
||||||
|
unsigned int reserved;
|
||||||
|
unsigned int others[4];
|
||||||
|
unsigned int usbhost_con[7];
|
||||||
|
};
|
||||||
|
|
||||||
|
#endif /* __ASM_ARM_ARCH_EHCI_H__ */
|
||||||
17
arch/arm/mach-nexell/include/mach/gpio.h
Normal file
17
arch/arm/mach-nexell/include/mach/gpio.h
Normal file
|
|
@ -0,0 +1,17 @@
|
||||||
|
/* SPDX-License-Identifier: GPL-2.0+
|
||||||
|
*
|
||||||
|
* (C) Copyright 2016 Nexell
|
||||||
|
* DeokJin, Lee <truevirtue@nexell.co.kr>
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __ASM_ARCH_NEXELL_GPIO_H
|
||||||
|
#define __ASM_ARCH_NEXELL_GPIO_H
|
||||||
|
|
||||||
|
#include <asm/io.h>
|
||||||
|
#include <linux/errno.h>
|
||||||
|
|
||||||
|
#define PIN_BASE 0
|
||||||
|
|
||||||
|
#define MAX_GPIO_BANKS 5
|
||||||
|
|
||||||
|
#endif /* __ASM_ARCH_NEXELL_GPIO_H */
|
||||||
215
arch/arm/mach-nexell/include/mach/mipi_display.h
Normal file
215
arch/arm/mach-nexell/include/mach/mipi_display.h
Normal file
|
|
@ -0,0 +1,215 @@
|
||||||
|
/* SPDX-License-Identifier: GPL-2.0+
|
||||||
|
*
|
||||||
|
* Defines for Mobile Industry Processor Interface (MIPI(R))
|
||||||
|
* Display Working Group standards: DSI, DCS, DBI, DPI
|
||||||
|
*
|
||||||
|
* Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
|
||||||
|
* Copyright (C) 2006 Nokia Corporation
|
||||||
|
* Author: Imre Deak <imre.deak@nokia.com>
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef MIPI_DISPLAY_H
|
||||||
|
#define MIPI_DISPLAY_H
|
||||||
|
|
||||||
|
/* MIPI DSI Processor-to-Peripheral transaction types */
|
||||||
|
enum {
|
||||||
|
MIPI_DSI_V_SYNC_START = 0x01,
|
||||||
|
MIPI_DSI_V_SYNC_END = 0x11,
|
||||||
|
MIPI_DSI_H_SYNC_START = 0x21,
|
||||||
|
MIPI_DSI_H_SYNC_END = 0x31,
|
||||||
|
|
||||||
|
MIPI_DSI_COLOR_MODE_OFF = 0x02,
|
||||||
|
MIPI_DSI_COLOR_MODE_ON = 0x12,
|
||||||
|
MIPI_DSI_SHUTDOWN_PERIPHERAL = 0x22,
|
||||||
|
MIPI_DSI_TURN_ON_PERIPHERAL = 0x32,
|
||||||
|
|
||||||
|
MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM = 0x03,
|
||||||
|
MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM = 0x13,
|
||||||
|
MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM = 0x23,
|
||||||
|
|
||||||
|
MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM = 0x04,
|
||||||
|
MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM = 0x14,
|
||||||
|
MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM = 0x24,
|
||||||
|
|
||||||
|
MIPI_DSI_DCS_SHORT_WRITE = 0x05,
|
||||||
|
MIPI_DSI_DCS_SHORT_WRITE_PARAM = 0x15,
|
||||||
|
|
||||||
|
MIPI_DSI_DCS_READ = 0x06,
|
||||||
|
|
||||||
|
MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE = 0x37,
|
||||||
|
|
||||||
|
MIPI_DSI_END_OF_TRANSMISSION = 0x08,
|
||||||
|
|
||||||
|
MIPI_DSI_NULL_PACKET = 0x09,
|
||||||
|
MIPI_DSI_BLANKING_PACKET = 0x19,
|
||||||
|
MIPI_DSI_GENERIC_LONG_WRITE = 0x29,
|
||||||
|
MIPI_DSI_DCS_LONG_WRITE = 0x39,
|
||||||
|
|
||||||
|
MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20 = 0x0c,
|
||||||
|
MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24 = 0x1c,
|
||||||
|
MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16 = 0x2c,
|
||||||
|
|
||||||
|
MIPI_DSI_PACKED_PIXEL_STREAM_30 = 0x0d,
|
||||||
|
MIPI_DSI_PACKED_PIXEL_STREAM_36 = 0x1d,
|
||||||
|
MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12 = 0x3d,
|
||||||
|
|
||||||
|
MIPI_DSI_PACKED_PIXEL_STREAM_16 = 0x0e,
|
||||||
|
MIPI_DSI_PACKED_PIXEL_STREAM_18 = 0x1e,
|
||||||
|
MIPI_DSI_PIXEL_STREAM_3BYTE_18 = 0x2e,
|
||||||
|
MIPI_DSI_PACKED_PIXEL_STREAM_24 = 0x3e,
|
||||||
|
};
|
||||||
|
|
||||||
|
/* MIPI DSI Peripheral-to-Processor transaction types */
|
||||||
|
enum {
|
||||||
|
MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT = 0x02,
|
||||||
|
MIPI_DSI_RX_END_OF_TRANSMISSION = 0x08,
|
||||||
|
MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE = 0x11,
|
||||||
|
MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE = 0x12,
|
||||||
|
MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE = 0x1a,
|
||||||
|
MIPI_DSI_RX_DCS_LONG_READ_RESPONSE = 0x1c,
|
||||||
|
MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE = 0x21,
|
||||||
|
MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE = 0x22,
|
||||||
|
};
|
||||||
|
|
||||||
|
/* MIPI DCS commands */
|
||||||
|
enum {
|
||||||
|
MIPI_DCS_NOP = 0x00,
|
||||||
|
MIPI_DCS_SOFT_RESET = 0x01,
|
||||||
|
MIPI_DCS_GET_DISPLAY_ID = 0x04,
|
||||||
|
MIPI_DCS_GET_RED_CHANNEL = 0x06,
|
||||||
|
MIPI_DCS_GET_GREEN_CHANNEL = 0x07,
|
||||||
|
MIPI_DCS_GET_BLUE_CHANNEL = 0x08,
|
||||||
|
MIPI_DCS_GET_DISPLAY_STATUS = 0x09,
|
||||||
|
MIPI_DCS_GET_POWER_MODE = 0x0A,
|
||||||
|
MIPI_DCS_GET_ADDRESS_MODE = 0x0B,
|
||||||
|
MIPI_DCS_GET_PIXEL_FORMAT = 0x0C,
|
||||||
|
MIPI_DCS_GET_DISPLAY_MODE = 0x0D,
|
||||||
|
MIPI_DCS_GET_SIGNAL_MODE = 0x0E,
|
||||||
|
MIPI_DCS_GET_DIAGNOSTIC_RESULT = 0x0F,
|
||||||
|
MIPI_DCS_ENTER_SLEEP_MODE = 0x10,
|
||||||
|
MIPI_DCS_EXIT_SLEEP_MODE = 0x11,
|
||||||
|
MIPI_DCS_ENTER_PARTIAL_MODE = 0x12,
|
||||||
|
MIPI_DCS_ENTER_NORMAL_MODE = 0x13,
|
||||||
|
MIPI_DCS_EXIT_INVERT_MODE = 0x20,
|
||||||
|
MIPI_DCS_ENTER_INVERT_MODE = 0x21,
|
||||||
|
MIPI_DCS_SET_GAMMA_CURVE = 0x26,
|
||||||
|
MIPI_DCS_SET_DISPLAY_OFF = 0x28,
|
||||||
|
MIPI_DCS_SET_DISPLAY_ON = 0x29,
|
||||||
|
MIPI_DCS_SET_COLUMN_ADDRESS = 0x2A,
|
||||||
|
MIPI_DCS_SET_PAGE_ADDRESS = 0x2B,
|
||||||
|
MIPI_DCS_WRITE_MEMORY_START = 0x2C,
|
||||||
|
MIPI_DCS_WRITE_LUT = 0x2D,
|
||||||
|
MIPI_DCS_READ_MEMORY_START = 0x2E,
|
||||||
|
MIPI_DCS_SET_PARTIAL_AREA = 0x30,
|
||||||
|
MIPI_DCS_SET_SCROLL_AREA = 0x33,
|
||||||
|
MIPI_DCS_SET_TEAR_OFF = 0x34,
|
||||||
|
MIPI_DCS_SET_TEAR_ON = 0x35,
|
||||||
|
MIPI_DCS_SET_ADDRESS_MODE = 0x36,
|
||||||
|
MIPI_DCS_SET_SCROLL_START = 0x37,
|
||||||
|
MIPI_DCS_EXIT_IDLE_MODE = 0x38,
|
||||||
|
MIPI_DCS_ENTER_IDLE_MODE = 0x39,
|
||||||
|
MIPI_DCS_SET_PIXEL_FORMAT = 0x3A,
|
||||||
|
MIPI_DCS_WRITE_MEMORY_CONTINUE = 0x3C,
|
||||||
|
MIPI_DCS_READ_MEMORY_CONTINUE = 0x3E,
|
||||||
|
MIPI_DCS_SET_TEAR_SCANLINE = 0x44,
|
||||||
|
MIPI_DCS_GET_SCANLINE = 0x45,
|
||||||
|
MIPI_DCS_READ_DDB_START = 0xA1,
|
||||||
|
MIPI_DCS_READ_DDB_CONTINUE = 0xA8,
|
||||||
|
};
|
||||||
|
|
||||||
|
/* MIPI DCS pixel formats */
|
||||||
|
#define MIPI_DCS_PIXEL_FMT_24BIT 7
|
||||||
|
#define MIPI_DCS_PIXEL_FMT_18BIT 6
|
||||||
|
#define MIPI_DCS_PIXEL_FMT_16BIT 5
|
||||||
|
#define MIPI_DCS_PIXEL_FMT_12BIT 3
|
||||||
|
#define MIPI_DCS_PIXEL_FMT_8BIT 2
|
||||||
|
#define MIPI_DCS_PIXEL_FMT_3BIT 1
|
||||||
|
|
||||||
|
/* request ACK from peripheral */
|
||||||
|
#define MIPI_DSI_MSG_REQ_ACK BIT(0)
|
||||||
|
/* use Low Power Mode to transmit message */
|
||||||
|
#define MIPI_DSI_MSG_USE_LPM BIT(1)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* struct mipi_dsi_msg - read/write DSI buffer
|
||||||
|
* @channel: virtual channel id
|
||||||
|
* @type: payload data type
|
||||||
|
* @flags: flags controlling this message transmission
|
||||||
|
* @tx_len: length of @tx_buf
|
||||||
|
* @tx_buf: data to be written
|
||||||
|
* @rx_len: length of @rx_buf
|
||||||
|
* @rx_buf: data to be read, or NULL
|
||||||
|
*/
|
||||||
|
struct mipi_dsi_msg {
|
||||||
|
u8 channel; /* virtual channel id */
|
||||||
|
u8 type; /* payload data type */
|
||||||
|
u16 flags; /* flags controlling this message transmission */
|
||||||
|
size_t tx_len;
|
||||||
|
const void *tx_buf;
|
||||||
|
size_t rx_len;
|
||||||
|
void *rx_buf;
|
||||||
|
};
|
||||||
|
|
||||||
|
/* DSI mode flags */
|
||||||
|
|
||||||
|
/* video mode */
|
||||||
|
#define MIPI_DSI_MODE_VIDEO BIT(0)
|
||||||
|
/* video burst mode */
|
||||||
|
#define MIPI_DSI_MODE_VIDEO_BURST BIT(1)
|
||||||
|
/* video pulse mode */
|
||||||
|
#define MIPI_DSI_MODE_VIDEO_SYNC_PULSE BIT(2)
|
||||||
|
/* enable auto vertical count mode */
|
||||||
|
#define MIPI_DSI_MODE_VIDEO_AUTO_VERT BIT(3)
|
||||||
|
/* enable hsync-end packets in vsync-pulse and v-porch area */
|
||||||
|
#define MIPI_DSI_MODE_VIDEO_HSE BIT(4)
|
||||||
|
/* disable hfront-porch area */
|
||||||
|
#define MIPI_DSI_MODE_VIDEO_HFP BIT(5)
|
||||||
|
/* disable hback-porch area */
|
||||||
|
#define MIPI_DSI_MODE_VIDEO_HBP BIT(6)
|
||||||
|
/* disable hsync-active area */
|
||||||
|
#define MIPI_DSI_MODE_VIDEO_HSA BIT(7)
|
||||||
|
/* flush display FIFO on vsync pulse */
|
||||||
|
#define MIPI_DSI_MODE_VSYNC_FLUSH BIT(8)
|
||||||
|
/* disable EoT packets in HS mode */
|
||||||
|
#define MIPI_DSI_MODE_EOT_PACKET BIT(9)
|
||||||
|
/* device supports non-continuous clock behavior (DSI spec 5.6.1) */
|
||||||
|
#define MIPI_DSI_CLOCK_NON_CONTINUOUS BIT(10)
|
||||||
|
/* transmit data in low power */
|
||||||
|
#define MIPI_DSI_MODE_LPM BIT(11) /* DSI mode flags */
|
||||||
|
|
||||||
|
enum mipi_dsi_pixel_format {
|
||||||
|
MIPI_DSI_FMT_RGB888,
|
||||||
|
MIPI_DSI_FMT_RGB666,
|
||||||
|
MIPI_DSI_FMT_RGB666_PACKED,
|
||||||
|
MIPI_DSI_FMT_RGB565,
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* struct mipi_dsi_device - DSI peripheral device
|
||||||
|
* @host: DSI host for this peripheral
|
||||||
|
* @dev: driver model device node for this peripheral
|
||||||
|
* @channel: virtual channel assigned to the peripheral
|
||||||
|
* @format: pixel format for video mode
|
||||||
|
* @lanes: number of active data lanes
|
||||||
|
* @mode_flags: DSI operation mode related flags
|
||||||
|
*/
|
||||||
|
struct mipi_dsi_device {
|
||||||
|
unsigned int channel;
|
||||||
|
unsigned int lanes;
|
||||||
|
enum mipi_dsi_pixel_format format;
|
||||||
|
unsigned long mode_flags;
|
||||||
|
struct mipi_panel_ops *ops;
|
||||||
|
ssize_t (*write_buffer)(struct mipi_dsi_device *dsi,
|
||||||
|
const void *data, size_t len);
|
||||||
|
};
|
||||||
|
|
||||||
|
struct mipi_panel_ops {
|
||||||
|
int (*init)(struct mipi_dsi_device *dsi, int width, int height);
|
||||||
|
int (*prepare)(struct mipi_dsi_device *dsi);
|
||||||
|
int (*unprepare)(struct mipi_dsi_device *dsi);
|
||||||
|
int (*enable)(struct mipi_dsi_device *dsi);
|
||||||
|
int (*disable)(struct mipi_dsi_device *dsi);
|
||||||
|
void *private_data;
|
||||||
|
};
|
||||||
|
|
||||||
|
#endif
|
||||||
352
arch/arm/mach-nexell/include/mach/nexell.h
Normal file
352
arch/arm/mach-nexell/include/mach/nexell.h
Normal file
|
|
@ -0,0 +1,352 @@
|
||||||
|
/* SPDX-License-Identifier: GPL-2.0+
|
||||||
|
*
|
||||||
|
* (C) Copyright 2016 Nexell
|
||||||
|
* Hyunseok, Jung <hsjung@nexell.co.kr>
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __NEXELL_H__
|
||||||
|
#define __NEXELL_H__
|
||||||
|
|
||||||
|
#define PHY_BASEADDR_DMA0 (0xC0000000)
|
||||||
|
#define PHY_BASEADDR_DMA1 (0xC0001000)
|
||||||
|
#if defined(CONFIG_ARCH_S5P4418)
|
||||||
|
#define PHY_BASEADDR_INTC0 (0xC0002000)
|
||||||
|
#define PHY_BASEADDR_INTC1 (0xC0003000)
|
||||||
|
#elif defined(CONFIG_ARCH_S5P6818)
|
||||||
|
#define PHY_BASEADDR_INTC (0xC0008000)
|
||||||
|
#endif
|
||||||
|
#define PHY_BASEADDR_CLKPWR (0xC0010000)
|
||||||
|
#define PHY_BASEADDR_RTC (0xC0010C00)
|
||||||
|
#define PHY_BASEADDR_ALIVE (0xC0010800)
|
||||||
|
#define PHY_BASEADDR_RSTCON (0xC0012000)
|
||||||
|
#define PHY_BASEADDR_TIEOFF (0xC0011000)
|
||||||
|
#define PHY_BASEADDR_PDM (0xC0014000)
|
||||||
|
#define PHY_BASEADDR_CRYPTO (0xC0015000)
|
||||||
|
#define PHY_BASEADDR_TIMER (0xC0017000)
|
||||||
|
#define PHY_BASEADDR_PWM (0xC0018000)
|
||||||
|
#define PHY_BASEADDR_WDT (0xC0019000)
|
||||||
|
#define PHY_BASEADDR_GPIOA (0xC001A000)
|
||||||
|
#define PHY_BASEADDR_GPIOB (0xC001B000)
|
||||||
|
#define PHY_BASEADDR_GPIOC (0xC001C000)
|
||||||
|
#define PHY_BASEADDR_GPIOD (0xC001D000)
|
||||||
|
#define PHY_BASEADDR_GPIOE (0xC001E000)
|
||||||
|
#define PHY_BASEADDR_OHCI (0xC0020000)
|
||||||
|
#define PHY_BASEADDR_EHCI (0xC0030000)
|
||||||
|
#define PHY_BASEADDR_HSOTG (0xC0040000)
|
||||||
|
#define PHY_BASEADDR_ADC (0xC0053000)
|
||||||
|
#define PHY_BASEADDR_PPM (0xC0054000)
|
||||||
|
#define PHY_BASEADDR_I2S0 (0xC0055000)
|
||||||
|
#define PHY_BASEADDR_I2S1 (0xC0056000)
|
||||||
|
#define PHY_BASEADDR_I2S2 (0xC0057000)
|
||||||
|
#define PHY_BASEADDR_AC97 (0xC0058000)
|
||||||
|
#define PHY_BASEADDR_SPDIF_TX (0xC0059000)
|
||||||
|
#define PHY_BASEADDR_SPDIF_RX (0xC005A000)
|
||||||
|
#define PHY_BASEADDR_SSP0 (0xC005B000)
|
||||||
|
#define PHY_BASEADDR_SSP1 (0xC005C000)
|
||||||
|
#define PHY_BASEADDR_SSP2 (0xC005F000)
|
||||||
|
#define PHY_BASEADDR_MPEGTSI (0xC005D000)
|
||||||
|
#define PHY_BASEADDR_GMAC (0xC0060000)
|
||||||
|
#define PHY_BASEADDR_VIP0 (0xC0063000)
|
||||||
|
#define PHY_BASEADDR_VIP1 (0xC0064000)
|
||||||
|
#if defined(CONFIG_ARCH_S5P6818)
|
||||||
|
#define PHY_BASEADDR_VIP2 (0xC0099000)
|
||||||
|
#endif
|
||||||
|
#define PHY_BASEADDR_DEINTERLACE (0xC0065000)
|
||||||
|
#define PHY_BASEADDR_SCALER (0xC0066000)
|
||||||
|
#define PHY_BASEADDR_ECID (0xC0067000)
|
||||||
|
#define PHY_BASEADDR_SDMMC0 (0xC0062000)
|
||||||
|
#define PHY_BASEADDR_SDMMC1 (0xC0068000)
|
||||||
|
#define PHY_BASEADDR_SDMMC2 (0xC0069000)
|
||||||
|
#define PHY_BASEADDR_MALI400 (0xC0070000)
|
||||||
|
#define PHY_BASEADDR_CODA_APB0 (0xC0080000)
|
||||||
|
#define PHY_BASEADDR_CODA_APB1 (0xC0081000)
|
||||||
|
#define PHY_BASEADDR_CODA_APB2 (0xC0082000)
|
||||||
|
#define PHY_BASEADDR_CODA_APB3 (0xC0083000)
|
||||||
|
/* dma (O), modem(X), UART0_MODULE */
|
||||||
|
#define PHY_BASEADDR_UART0 (0xC00A1000)
|
||||||
|
/* dma (O), modem(O), pl01115_Uart_modem_MODULE */
|
||||||
|
#define PHY_BASEADDR_UART1 (0xC00A0000)
|
||||||
|
/* dma (O), modem(X), UART1_MODULE */
|
||||||
|
#define PHY_BASEADDR_UART2 (0xC00A2000)
|
||||||
|
/* dma (X), modem(X), pl01115_Uart_nodma0_MODULE */
|
||||||
|
#define PHY_BASEADDR_UART3 (0xC00A3000)
|
||||||
|
/* dma (X), modem(X), pl01115_Uart_nodma1_MODULE */
|
||||||
|
#define PHY_BASEADDR_UART4 (0xC006D000)
|
||||||
|
/* dma (X), modem(X), pl01115_Uart_nodma2_MODULE */
|
||||||
|
#define PHY_BASEADDR_UART5 (0xC006F000)
|
||||||
|
#define PHY_BASEADDR_I2C0 (0xC00A4000)
|
||||||
|
#define PHY_BASEADDR_I2C1 (0xC00A5000)
|
||||||
|
#define PHY_BASEADDR_I2C2 (0xC00A6000)
|
||||||
|
#define PHY_BASEADDR_CAN0 (0xC00CE000)
|
||||||
|
#define PHY_BASEADDR_CAN1 (0xC00CF000)
|
||||||
|
#define PHY_BASEADDR_MIPI (0xC00D0000)
|
||||||
|
#define PHY_BASEADDR_DISPLAYTOP (0xC0100000)
|
||||||
|
|
||||||
|
#define PHY_BASEADDR_CLKGEN0 (0xC00BB000) /* TIMER_1 */
|
||||||
|
#define PHY_BASEADDR_CLKGEN1 (0xC00BC000) /* TIMER_2 */
|
||||||
|
#define PHY_BASEADDR_CLKGEN2 (0xC00BD000) /* TIMER_3 */
|
||||||
|
#define PHY_BASEADDR_CLKGEN3 (0xC00BE000) /* PWM_1 */
|
||||||
|
#define PHY_BASEADDR_CLKGEN4 (0xC00BF000) /* PWM_2 */
|
||||||
|
#define PHY_BASEADDR_CLKGEN5 (0xC00C0000) /* PWM_3 */
|
||||||
|
#define PHY_BASEADDR_CLKGEN6 (0xC00AE000) /* I2C_0 */
|
||||||
|
#define PHY_BASEADDR_CLKGEN7 (0xC00AF000) /* I2C_1 */
|
||||||
|
#define PHY_BASEADDR_CLKGEN8 (0xC00B0000) /* I2C_2 */
|
||||||
|
#define PHY_BASEADDR_CLKGEN9 (0xC00CA000) /* MIPI */
|
||||||
|
#define PHY_BASEADDR_CLKGEN10 (0xC00C8000) /* GMAC */
|
||||||
|
#define PHY_BASEADDR_CLKGEN11 (0xC00B8000) /* SPDIF_TX */
|
||||||
|
#define PHY_BASEADDR_CLKGEN12 (0xC00B7000) /* MPEGTSI */
|
||||||
|
#define PHY_BASEADDR_CLKGEN13 (0xC00BA000) /* PWM_0 */
|
||||||
|
#define PHY_BASEADDR_CLKGEN14 (0xC00B9000) /* TIMER_0 */
|
||||||
|
#define PHY_BASEADDR_CLKGEN15 (0xC00B2000) /* I2S_0 */
|
||||||
|
#define PHY_BASEADDR_CLKGEN16 (0xC00B3000) /* I2S_1 */
|
||||||
|
#define PHY_BASEADDR_CLKGEN17 (0xC00B4000) /* I2S_2 */
|
||||||
|
#define PHY_BASEADDR_CLKGEN18 (0xC00C5000) /* SDHC_0 */
|
||||||
|
#define PHY_BASEADDR_CLKGEN19 (0xC00CC000) /* SDHC_1 */
|
||||||
|
#define PHY_BASEADDR_CLKGEN20 (0xC00CD000) /* SDHC_2 */
|
||||||
|
#define PHY_BASEADDR_CLKGEN21 (0xC00C3000) /* MALI */
|
||||||
|
#define PHY_BASEADDR_CLKGEN22 (0xC00A9000) /* UART_0 */
|
||||||
|
#define PHY_BASEADDR_CLKGEN23 (0xC00AA000) /* UART_2 */
|
||||||
|
#define PHY_BASEADDR_CLKGEN24 (0xC00A8000) /* UART_1 */
|
||||||
|
#define PHY_BASEADDR_CLKGEN25 (0xC00AB000) /* UART_3 */
|
||||||
|
#define PHY_BASEADDR_CLKGEN26 (0xC006E000) /* UART_4 */
|
||||||
|
#define PHY_BASEADDR_CLKGEN27 (0xC00B1000) /* UART_5 */
|
||||||
|
#define PHY_BASEADDR_CLKGEN28 (0xC00B5000) /* DEINTERLACE */
|
||||||
|
#define PHY_BASEADDR_CLKGEN29 (0xC00C4000) /* PPM */
|
||||||
|
#define PHY_BASEADDR_CLKGEN30 (0xC00C1000) /* VIP_0 */
|
||||||
|
#define PHY_BASEADDR_CLKGEN31 (0xC00C2000) /* VIP_1 */
|
||||||
|
#define PHY_BASEADDR_CLKGEN32 (0xC006B000) /* USB2HOST */
|
||||||
|
#define PHY_BASEADDR_CLKGEN33 (0xC00C7000) /* CODA */
|
||||||
|
#define PHY_BASEADDR_CLKGEN34 (0xC00C6000) /* CRYPTO */
|
||||||
|
#define PHY_BASEADDR_CLKGEN35 (0xC00B6000) /* SCALER */
|
||||||
|
#define PHY_BASEADDR_CLKGEN36 (0xC00CB000) /* PDM */
|
||||||
|
#define PHY_BASEADDR_CLKGEN37 (0xC00AC000) /* SPI0 */
|
||||||
|
#define PHY_BASEADDR_CLKGEN38 (0xC00AD000) /* SPI1 */
|
||||||
|
#define PHY_BASEADDR_CLKGEN39 (0xC00A7000) /* SPI2 */
|
||||||
|
#if defined(CONFIG_ARCH_S5P6818)
|
||||||
|
#define PHY_BASEADDR_CLKGEN40 (0xC009A000)
|
||||||
|
#endif
|
||||||
|
#define PHY_BASEADDR_DREX (0xC00E0000)
|
||||||
|
|
||||||
|
#define PHY_BASEADDR_CS_NAND (0x2C000000)
|
||||||
|
|
||||||
|
#define PHY_BASEADDR_SRAM (0xFFFF0000)
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Nexell clock generator
|
||||||
|
*/
|
||||||
|
#define CLK_ID_TIMER_1 0
|
||||||
|
#define CLK_ID_TIMER_2 1
|
||||||
|
#define CLK_ID_TIMER_3 2
|
||||||
|
#define CLK_ID_PWM_1 3
|
||||||
|
#define CLK_ID_PWM_2 4
|
||||||
|
#define CLK_ID_PWM_3 5
|
||||||
|
#define CLK_ID_I2C_0 6
|
||||||
|
#define CLK_ID_I2C_1 7
|
||||||
|
#define CLK_ID_I2C_2 8
|
||||||
|
#define CLK_ID_MIPI 9
|
||||||
|
#define CLK_ID_GMAC 10 /* External Clock 1 */
|
||||||
|
#define CLK_ID_SPDIF_TX 11
|
||||||
|
#define CLK_ID_MPEGTSI 12
|
||||||
|
#define CLK_ID_PWM_0 13
|
||||||
|
#define CLK_ID_TIMER_0 14
|
||||||
|
#define CLK_ID_I2S_0 15 /* External Clock 1 */
|
||||||
|
#define CLK_ID_I2S_1 16 /* External Clock 1 */
|
||||||
|
#define CLK_ID_I2S_2 17 /* External Clock 1 */
|
||||||
|
#define CLK_ID_SDHC_0 18
|
||||||
|
#define CLK_ID_SDHC_1 19
|
||||||
|
#define CLK_ID_SDHC_2 20
|
||||||
|
#define CLK_ID_MALI 21
|
||||||
|
#define CLK_ID_UART_0 22 /* UART0_MODULE */
|
||||||
|
#define CLK_ID_UART_2 23 /* UART1_MODULE */
|
||||||
|
#define CLK_ID_UART_1 24 /* pl01115_Uart_modem_MODULE */
|
||||||
|
#define CLK_ID_UART_3 25 /* pl01115_Uart_nodma0_MODULE */
|
||||||
|
#define CLK_ID_UART_4 26 /* pl01115_Uart_nodma1_MODULE */
|
||||||
|
#define CLK_ID_UART_5 27 /* pl01115_Uart_nodma2_MODULE */
|
||||||
|
#define CLK_ID_DIT 28
|
||||||
|
#define CLK_ID_PPM 29
|
||||||
|
#define CLK_ID_VIP_0 30 /* External Clock 1 */
|
||||||
|
#define CLK_ID_VIP_1 31 /* External Clock 1, 2 */
|
||||||
|
#define CLK_ID_USB2HOST 32 /* External Clock 2 */
|
||||||
|
#define CLK_ID_CODA 33
|
||||||
|
#define CLK_ID_CRYPTO 34
|
||||||
|
#define CLK_ID_SCALER 35
|
||||||
|
#define CLK_ID_PDM 36
|
||||||
|
#define CLK_ID_SPI_0 37
|
||||||
|
#define CLK_ID_SPI_1 38
|
||||||
|
#define CLK_ID_SPI_2 39
|
||||||
|
#define CLK_ID_MAX 39
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Nexell Reset control
|
||||||
|
*/
|
||||||
|
#define RESET_ID_AC97 0
|
||||||
|
#define RESET_ID_CPU1 1
|
||||||
|
#define RESET_ID_CPU2 2
|
||||||
|
#define RESET_ID_CPU3 3
|
||||||
|
#define RESET_ID_WD1 4
|
||||||
|
#define RESET_ID_WD2 5
|
||||||
|
#define RESET_ID_WD3 6
|
||||||
|
#define RESET_ID_CRYPTO 7
|
||||||
|
#define RESET_ID_DEINTERLACE 8
|
||||||
|
#define RESET_ID_DISP_TOP 9
|
||||||
|
#define RESET_ID_DISPLAY 10
|
||||||
|
#define RESET_ID_RESCONV 11
|
||||||
|
#define RESET_ID_LCDIF 12
|
||||||
|
#define RESET_ID_HDMI 13
|
||||||
|
#define RESET_ID_HDMI_VIDEO 14
|
||||||
|
#define RESET_ID_HDMI_SPDIF 15
|
||||||
|
#define RESET_ID_HDMI_TMDS 16
|
||||||
|
#define RESET_ID_HDMI_PHY 17
|
||||||
|
#define RESET_ID_LVDS 18
|
||||||
|
#define RESET_ID_ECID 19
|
||||||
|
#define RESET_ID_I2C0 20
|
||||||
|
#define RESET_ID_I2C1 21
|
||||||
|
#define RESET_ID_I2C2 22
|
||||||
|
#define RESET_ID_I2S0 23
|
||||||
|
#define RESET_ID_I2S1 24
|
||||||
|
#define RESET_ID_I2S2 25
|
||||||
|
#define RESET_ID_DREX_C 26
|
||||||
|
#define RESET_ID_DREX_A 27
|
||||||
|
#define RESET_ID_DREX 28
|
||||||
|
#define RESET_ID_MIPI 29
|
||||||
|
#define RESET_ID_MIPI_DSI 30
|
||||||
|
#define RESET_ID_MIPI_CSI 31
|
||||||
|
#define RESET_ID_MIPI_PHY_S 32
|
||||||
|
#define RESET_ID_MIPI_PHY_M 33
|
||||||
|
#define RESET_ID_MPEGTSI 34
|
||||||
|
#define RESET_ID_PDM 35
|
||||||
|
#define RESET_ID_TIMER 36
|
||||||
|
#define RESET_ID_PWM 37
|
||||||
|
#define RESET_ID_SCALER 38
|
||||||
|
#define RESET_ID_SDMMC0 39
|
||||||
|
#define RESET_ID_SDMMC1 40
|
||||||
|
#define RESET_ID_SDMMC2 41
|
||||||
|
#define RESET_ID_SPDIFRX 42
|
||||||
|
#define RESET_ID_SPDIFTX 43
|
||||||
|
#define RESET_ID_SSP0_P 44
|
||||||
|
#define RESET_ID_SSP0 45
|
||||||
|
#define RESET_ID_SSP1_P 46
|
||||||
|
#define RESET_ID_SSP1 47
|
||||||
|
#define RESET_ID_SSP2_P 48
|
||||||
|
#define RESET_ID_SSP2 49
|
||||||
|
#define RESET_ID_UART0 50 /* UART1 */
|
||||||
|
#define RESET_ID_UART1 51 /* pl01115_Uart_modem */
|
||||||
|
#define RESET_ID_UART2 52 /* UART1 */
|
||||||
|
#define RESET_ID_UART3 53 /* pl01115_Uart_nodma0 */
|
||||||
|
#define RESET_ID_UART4 54 /* pl01115_Uart_nodma1 */
|
||||||
|
#define RESET_ID_UART5 55 /* pl01115_Uart_nodma2 */
|
||||||
|
#define RESET_ID_USB20HOST 56
|
||||||
|
#define RESET_ID_USB20OTG 57
|
||||||
|
#define RESET_ID_WDT 58
|
||||||
|
#define RESET_ID_WDT_POR 59
|
||||||
|
#define RESET_ID_ADC 60
|
||||||
|
#define RESET_ID_CODA_A 61
|
||||||
|
#define RESET_ID_CODA_P 62
|
||||||
|
#define RESET_ID_CODA_C 63
|
||||||
|
#define RESET_ID_DWC_GMAC 64
|
||||||
|
#define RESET_ID_MALI400 65
|
||||||
|
#define RESET_ID_PPM 66
|
||||||
|
#define RESET_ID_VIP1 67
|
||||||
|
#define RESET_ID_VIP0 68
|
||||||
|
#if defined(CONFIG_ARCH_S5P6818)
|
||||||
|
#define RESET_ID_VIP2 69
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
* device name
|
||||||
|
*/
|
||||||
|
#define DEV_NAME_UART "nx-uart" /* pl0115 (amba-pl011.c) */
|
||||||
|
#define DEV_NAME_FB "nx-fb"
|
||||||
|
#define DEV_NAME_DISP "nx-disp"
|
||||||
|
#define DEV_NAME_LCD "nx-lcd"
|
||||||
|
#define DEV_NAME_LVDS "nx-lvds"
|
||||||
|
#define DEV_NAME_HDMI "nx-hdmi"
|
||||||
|
#define DEV_NAME_RESCONV "nx-resconv"
|
||||||
|
#define DEV_NAME_MIPI "nx-mipi"
|
||||||
|
#define DEV_NAME_PCM "nx-pcm"
|
||||||
|
#define DEV_NAME_I2S "nx-i2s"
|
||||||
|
#define DEV_NAME_SPDIF_TX "nx-spdif-tx"
|
||||||
|
#define DEV_NAME_SPDIF_RX "nx-spdif-rx"
|
||||||
|
#define DEV_NAME_I2C "nx-i2c"
|
||||||
|
#define DEV_NAME_NAND "nx-nand"
|
||||||
|
#define DEV_NAME_KEYPAD "nx-keypad"
|
||||||
|
#define DEV_NAME_SDHC "nx-sdhc"
|
||||||
|
#define DEV_NAME_PWM "nx-pwm"
|
||||||
|
#define DEV_NAME_TIMER "nx-timer"
|
||||||
|
#define DEV_NAME_SOC_PWM "nx-soc-pwm"
|
||||||
|
#define DEV_NAME_GPIO "nx-gpio"
|
||||||
|
#define DEV_NAME_RTC "nx-rtc"
|
||||||
|
#define DEV_NAME_GMAC "nx-gmac"
|
||||||
|
#define DEV_NAME_MPEGTSI "nx-mpegtsi"
|
||||||
|
#define DEV_NAME_MALI "nx-mali"
|
||||||
|
#define DEV_NAME_DIT "nx-deinterlace"
|
||||||
|
#define DEV_NAME_PPM "nx-ppm"
|
||||||
|
#define DEV_NAME_VIP "nx-vip"
|
||||||
|
#define DEV_NAME_CODA "nx-coda"
|
||||||
|
#define DEV_NAME_USB2HOST "nx-usb2h"
|
||||||
|
#define DEV_NAME_CRYPTO "nx-crypto"
|
||||||
|
#define DEV_NAME_SCALER "nx-scaler"
|
||||||
|
#define DEV_NAME_PDM "nx-pdm"
|
||||||
|
#define DEV_NAME_SPI "nx-spi"
|
||||||
|
#define DEV_NAME_CPUFREQ "nx-cpufreq"
|
||||||
|
|
||||||
|
/*
|
||||||
|
* clock generator
|
||||||
|
*/
|
||||||
|
#define CORECLK_NAME_PLL0 "pll0" /* cpu clock */
|
||||||
|
#define CORECLK_NAME_PLL1 "pll1"
|
||||||
|
#define CORECLK_NAME_PLL2 "pll2"
|
||||||
|
#define CORECLK_NAME_PLL3 "pll3"
|
||||||
|
#define CORECLK_NAME_FCLK "fclk"
|
||||||
|
#define CORECLK_NAME_MCLK "mclk"
|
||||||
|
#define CORECLK_NAME_BCLK "bclk"
|
||||||
|
#define CORECLK_NAME_PCLK "pclk"
|
||||||
|
#define CORECLK_NAME_HCLK "hclk"
|
||||||
|
|
||||||
|
#define CORECLK_ID_PLL0 0
|
||||||
|
#define CORECLK_ID_PLL1 1
|
||||||
|
#define CORECLK_ID_PLL2 2
|
||||||
|
#define CORECLK_ID_PLL3 3
|
||||||
|
#define CORECLK_ID_FCLK 4
|
||||||
|
#define CORECLK_ID_MCLK 5
|
||||||
|
#define CORECLK_ID_BCLK 6
|
||||||
|
#define CORECLK_ID_PCLK 7
|
||||||
|
#define CORECLK_ID_HCLK 8
|
||||||
|
|
||||||
|
#define ALIVEPWRGATEREG (PHY_BASEADDR_ALIVE + 0x0)
|
||||||
|
|
||||||
|
#if defined(CONFIG_ARCH_S5P4418)
|
||||||
|
#define SCR_ARM_SECOND_BOOT (0xC0010C1C) /* PWR scratch */
|
||||||
|
#define SCR_ARM_SECOND_BOOT_REG1 (0xc0010234) /* ToDo : Check Address */
|
||||||
|
#elif defined(CONFIG_ARCH_S5P6818)
|
||||||
|
#define SCR_ARM_SECOND_BOOT (0xc0010230) /* PWR scratch */
|
||||||
|
#define SCR_ARM_SECOND_BOOT_REG1 (0xc0010234) /* PWR scratch */
|
||||||
|
#define SCR_ARM_SECOND_BOOT_REG2 (0xc0010238) /* PWR scratch */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define SCR_ALIVE_BASE (PHY_BASEADDR_ALIVE)
|
||||||
|
#define SCR_SIGNAGURE_RESET (SCR_ALIVE_BASE + 0x068)
|
||||||
|
#define SCR_SIGNAGURE_SET (SCR_ALIVE_BASE + 0x06C)
|
||||||
|
#define SCR_SIGNAGURE_READ (SCR_ALIVE_BASE + 0x070)
|
||||||
|
|
||||||
|
#define SYSRSTCONFIG (0x23C)
|
||||||
|
#define DEVICEBOOTINFO (0x50)
|
||||||
|
#define BOOTMODE_MASK (0x7)
|
||||||
|
#define BOOTMODE_SDMMC 5
|
||||||
|
#define BOOTMODE_USB 6
|
||||||
|
#define BOOTMODE_SDMMC_PORT_VAL(x) ((((x) >> 3) & 1) | \
|
||||||
|
(((x) >> 19 & 1) << 1))
|
||||||
|
#define EMMC_PORT_NUM 2
|
||||||
|
#define SD_PORT_NUM 0
|
||||||
|
#define ID_REG_EC0 (0x54)
|
||||||
|
#define WIRE0_MASK (0x1)
|
||||||
|
|
||||||
|
#ifndef __ASSEMBLY__
|
||||||
|
|
||||||
|
#define NS_IN_HZ (1000000000UL)
|
||||||
|
#define TO_PERIOD_NS(freq) (NS_IN_HZ / (freq))
|
||||||
|
#define TO_DUTY_NS(duty, freq) (duty ? TO_PERIOD_NS(freq) / (100 / duty) : 0)
|
||||||
|
|
||||||
|
#endif /* __ASSEMBLY__ */
|
||||||
|
|
||||||
|
#endif /* __NEXELL_H__ */
|
||||||
103
arch/arm/mach-nexell/include/mach/nx_gpio.h
Normal file
103
arch/arm/mach-nexell/include/mach/nx_gpio.h
Normal file
|
|
@ -0,0 +1,103 @@
|
||||||
|
/* SPDX-License-Identifier: GPL-2.0+
|
||||||
|
*
|
||||||
|
* (C) Copyright 2016 Nexell
|
||||||
|
* Youngbok, Park <ybpark@nexell.co.kr>
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <linux/types.h>
|
||||||
|
#include <asm/io.h>
|
||||||
|
|
||||||
|
#ifndef __nx_gpio_h__
|
||||||
|
#define __nx_gpio_h__
|
||||||
|
|
||||||
|
struct nx_gpio_register_set {
|
||||||
|
u32 gpioxout;
|
||||||
|
u32 gpioxoutenb;
|
||||||
|
u32 gpioxdetmode[2];
|
||||||
|
u32 gpioxintenb;
|
||||||
|
u32 gpioxdet;
|
||||||
|
u32 gpioxpad;
|
||||||
|
u32 gpioxpuenb;
|
||||||
|
u32 gpioxaltfn[2];
|
||||||
|
u32 gpioxdetmodeex;
|
||||||
|
u32 __reserved[4];
|
||||||
|
u32 gpioxdetenb;
|
||||||
|
u32 gpiox_slew;
|
||||||
|
u32 gpiox_slew_disable_default;
|
||||||
|
u32 gpiox_drv1;
|
||||||
|
u32 gpiox_drv1_disable_default;
|
||||||
|
u32 gpiox_drv0;
|
||||||
|
u32 gpiox_drv0_disable_default;
|
||||||
|
u32 gpiox_pullsel;
|
||||||
|
u32 gpiox_pullsel_disable_default;
|
||||||
|
u32 gpiox_pullenb;
|
||||||
|
u32 gpiox_pullenb_disable_default;
|
||||||
|
u32 gpiox_input_mux_select0;
|
||||||
|
u32 gpiox_input_mux_select1;
|
||||||
|
u8 __reserved1[0x1000 - 0x70];
|
||||||
|
};
|
||||||
|
|
||||||
|
enum {
|
||||||
|
nx_gpio_padfunc_0 = 0ul,
|
||||||
|
nx_gpio_padfunc_1 = 1ul,
|
||||||
|
nx_gpio_padfunc_2 = 2ul,
|
||||||
|
nx_gpio_padfunc_3 = 3ul
|
||||||
|
};
|
||||||
|
|
||||||
|
enum {
|
||||||
|
nx_gpio_drvstrength_0 = 0ul,
|
||||||
|
nx_gpio_drvstrength_1 = 1ul,
|
||||||
|
nx_gpio_drvstrength_2 = 2ul,
|
||||||
|
nx_gpio_drvstrength_3 = 3ul
|
||||||
|
};
|
||||||
|
|
||||||
|
enum {
|
||||||
|
nx_gpio_pull_down = 0ul,
|
||||||
|
nx_gpio_pull_up = 1ul,
|
||||||
|
nx_gpio_pull_off = 2ul
|
||||||
|
};
|
||||||
|
|
||||||
|
int nx_gpio_initialize(void);
|
||||||
|
u32 nx_gpio_get_number_of_module(void);
|
||||||
|
u32 nx_gpio_get_size_of_register_set(void);
|
||||||
|
void nx_gpio_set_base_address(u32 module_index, void *base_address);
|
||||||
|
void *nx_gpio_get_base_address(u32 module_index);
|
||||||
|
int nx_gpio_open_module(u32 module_index);
|
||||||
|
int nx_gpio_close_module(u32 module_index);
|
||||||
|
int nx_gpio_check_busy(u32 module_index);
|
||||||
|
void nx_gpio_set_detect_enable(u32 module_index, u32 bit_number,
|
||||||
|
int detect_enb);
|
||||||
|
void nx_gpio_set_pad_function(u32 module_index, u32 bit_number, u32 padfunc);
|
||||||
|
void nx_gpio_set_pad_function32(u32 module_index, u32 msbvalue, u32 lsbvalue);
|
||||||
|
int nx_gpio_get_pad_function(u32 module_index, u32 bit_number);
|
||||||
|
void nx_gpio_set_output_enable(u32 module_index, u32 bit_number,
|
||||||
|
int output_enb);
|
||||||
|
int nx_gpio_get_detect_enable(u32 module_index, u32 bit_number);
|
||||||
|
u32 nx_gpio_get_detect_enable32(u32 module_index);
|
||||||
|
void nx_gpio_set_detect_enable(u32 module_index, u32 bit_number,
|
||||||
|
int detect_enb);
|
||||||
|
void nx_gpio_set_detect_enable32(u32 module_index, u32 enable_flag);
|
||||||
|
int nx_gpio_get_output_enable(u32 module_index, u32 bit_number);
|
||||||
|
void nx_gpio_set_output_enable32(u32 module_index, int output_enb);
|
||||||
|
u32 nx_gpio_get_output_enable32(u32 module_index);
|
||||||
|
void nx_gpio_set_output_value(u32 module_index, u32 bit_number, int value);
|
||||||
|
int nx_gpio_get_output_value(u32 module_index, u32 bit_number);
|
||||||
|
void nx_gpio_set_output_value32(u32 module_index, u32 value);
|
||||||
|
u32 nx_gpio_get_output_value32(u32 module_index);
|
||||||
|
int nx_gpio_get_input_value(u32 module_index, u32 bit_number);
|
||||||
|
void nx_gpio_set_pull_select(u32 module_index, u32 bit_number, int enable);
|
||||||
|
void nx_gpio_set_pull_select32(u32 module_index, u32 value);
|
||||||
|
int nx_gpio_get_pull_select(u32 module_index, u32 bit_number);
|
||||||
|
u32 nx_gpio_get_pull_select32(u32 module_index);
|
||||||
|
void nx_gpio_set_pull_mode(u32 module_index, u32 bit_number, u32 mode);
|
||||||
|
void nx_gpio_set_fast_slew(u32 module_index, u32 bit_number, int enable);
|
||||||
|
void nx_gpio_set_drive_strength_disable_default(u32 module_index,
|
||||||
|
u32 bit_number, int enable);
|
||||||
|
void nx_gpio_set_drive_strength_disable_default(u32 module_index,
|
||||||
|
u32 bit_number, int enable);
|
||||||
|
void nx_gpio_set_drive_strength(u32 module_index, u32 bit_number,
|
||||||
|
u32 drvstrength);
|
||||||
|
void nx_gpio_set_drive_strength_disable_default(u32 module_index,
|
||||||
|
u32 bit_number, int enable);
|
||||||
|
u32 nx_gpio_get_drive_strength(u32 module_index, u32 bit_number);
|
||||||
|
#endif
|
||||||
19
arch/arm/mach-nexell/include/mach/reset.h
Normal file
19
arch/arm/mach-nexell/include/mach/reset.h
Normal file
|
|
@ -0,0 +1,19 @@
|
||||||
|
/* SPDX-License-Identifier: GPL-2.0+
|
||||||
|
*
|
||||||
|
* (C) Copyright 2016 Nexell
|
||||||
|
* Youngbok, Park <ybpark@nexell.co.kr>
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __NEXELL_RESET__
|
||||||
|
#define __NEXELL_RESET__
|
||||||
|
|
||||||
|
#define NUMBER_OF_RESET_MODULE_PIN 69
|
||||||
|
|
||||||
|
enum rstcon {
|
||||||
|
RSTCON_ASSERT = 0UL,
|
||||||
|
RSTCON_NEGATE = 1UL
|
||||||
|
};
|
||||||
|
|
||||||
|
void nx_rstcon_setrst(u32 rstindex, enum rstcon status);
|
||||||
|
|
||||||
|
#endif /* __NEXELL_RESET__ */
|
||||||
15
arch/arm/mach-nexell/include/mach/sec_reg.h
Normal file
15
arch/arm/mach-nexell/include/mach/sec_reg.h
Normal file
|
|
@ -0,0 +1,15 @@
|
||||||
|
/* SPDX-License-Identifier: GPL-2.0+
|
||||||
|
*
|
||||||
|
* (C) Copyright 2016 Nexell
|
||||||
|
* Youngbok, Park <park@nexell.co.kr>
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define NEXELL_L2C_SEC_ID 0
|
||||||
|
#define NEXELL_MALI_SEC_ID 2
|
||||||
|
#define NEXELL_MIPI_SEC_ID 4
|
||||||
|
#define NEXELL_TOFF_SEC_ID 6
|
||||||
|
|
||||||
|
int write_sec_reg_by_id(void __iomem *reg, int val, int id);
|
||||||
|
int read_sec_reg_by_id(void __iomem *reg, int id);
|
||||||
|
int read_sec_reg(void __iomem *reg);
|
||||||
|
int write_sec_reg(void __iomem *reg, int val);
|
||||||
423
arch/arm/mach-nexell/include/mach/tieoff.h
Normal file
423
arch/arm/mach-nexell/include/mach/tieoff.h
Normal file
|
|
@ -0,0 +1,423 @@
|
||||||
|
/* SPDX-License-Identifier: GPL-2.0+
|
||||||
|
*
|
||||||
|
* (C) Copyright 2016 Nexell
|
||||||
|
* Youngbok, Park <park@nexell.co.kr>
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _NEXELL_TIEOFF_H
|
||||||
|
#define _NEXELL_TIEOFF_H
|
||||||
|
|
||||||
|
void nx_tieoff_set(u32 tieoff_index, u32 tieoff_value);
|
||||||
|
u32 nx_tieoff_get(u32 tieoff_index);
|
||||||
|
|
||||||
|
#if defined(CONFIG_ARCH_S5P4418)
|
||||||
|
#define NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_CLAMPCOREOUT ((1 << 16) | 0)
|
||||||
|
#define NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_CLAMPCPU0 ((1 << 16) | 1)
|
||||||
|
#define NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_CLAMPCPU1 ((1 << 16) | 2)
|
||||||
|
#define NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_CLAMPCPU2 ((1 << 16) | 3)
|
||||||
|
#define NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_CLAMPCPU3 ((1 << 16) | 4)
|
||||||
|
#define NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_COREPWRDOWN ((1 << 16) | 5)
|
||||||
|
#define NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_CPU0PWRDOWN ((1 << 16) | 6)
|
||||||
|
#define NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_CPU1PWRDOWN ((1 << 16) | 7)
|
||||||
|
#define NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_CPU2PWRDOWN ((1 << 16) | 8)
|
||||||
|
#define NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_CPU3PWRDOWN ((1 << 16) | 9)
|
||||||
|
#define NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_L2_CFGENDIAN ((1 << 16) | 10)
|
||||||
|
#define NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_L1EMAS ((1 << 16) | 11)
|
||||||
|
#define NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_L2RET1N_0 ((1 << 16) | 12)
|
||||||
|
#define NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_L2RET1N_1 ((1 << 16) | 13)
|
||||||
|
#define NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_L2PGEN_0 ((1 << 16) | 14)
|
||||||
|
#define NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_L2PGEN_1 ((1 << 16) | 15)
|
||||||
|
#define NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_CLAMPL2_0 ((1 << 16) | 16)
|
||||||
|
#define NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_CLAMPL2_1 ((1 << 16) | 17)
|
||||||
|
#define NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_VINITHI ((4 << 16) | 18)
|
||||||
|
#define NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_L2EMA ((3 << 16) | 22)
|
||||||
|
#define NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_TEINIT ((4 << 16) | 25)
|
||||||
|
#define NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_L1EMAW ((2 << 16) | 29)
|
||||||
|
#define NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_L2EMAW ((2 << 16) | 32)
|
||||||
|
#define NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_L1EMA ((3 << 16) | 34)
|
||||||
|
#define NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_CPUCLKOFF ((4 << 16) | 37)
|
||||||
|
#define NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_PWRCTLI0 ((2 << 16) | 41)
|
||||||
|
#define NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_PWRCTLI1 ((2 << 16) | 43)
|
||||||
|
#define NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_PWRCTLI2 ((2 << 16) | 45)
|
||||||
|
#elif defined(CONFIG_ARCH_S5P6818)
|
||||||
|
#define NX_TIEOFF_MMC_8BIT ((1 << 16) | 5)
|
||||||
|
#endif
|
||||||
|
#define NX_TIEOFF_AXISRAM0_i_TIE_ra2w_EMAA ((3 << 16) | 47)
|
||||||
|
#define NX_TIEOFF_AXISRAM0_i_TIE_ra2w_EMAB ((3 << 16) | 50)
|
||||||
|
#define NX_TIEOFF_AXISRAM0_i_TIE_ra2w_EMAWA ((2 << 16) | 53)
|
||||||
|
#define NX_TIEOFF_AXISRAM0_i_TIE_ra2w_EMAWB ((2 << 16) | 55)
|
||||||
|
#define NX_TIEOFF_AXISRAM0_i_nPowerDown ((1 << 16) | 57)
|
||||||
|
#define NX_TIEOFF_AXISRAM0_i_nSleep ((1 << 16) | 58)
|
||||||
|
#define NX_TIEOFF_CAN0_i_TIE_rf1_EMA ((3 << 16) | 59)
|
||||||
|
#define NX_TIEOFF_CAN0_i_TIE_rf1_EMAW ((2 << 16) | 62)
|
||||||
|
#define NX_TIEOFF_CAN0_i_nPowerDown ((1 << 16) | 64)
|
||||||
|
#define NX_TIEOFF_CAN0_i_nSleep ((1 << 16) | 65)
|
||||||
|
#define NX_TIEOFF_CAN1_i_TIE_rf1_EMA ((3 << 16) | 66)
|
||||||
|
#define NX_TIEOFF_CAN1_i_TIE_rf1_EMAW ((2 << 16) | 69)
|
||||||
|
#define NX_TIEOFF_CAN1_i_nPowerDown ((1 << 16) | 71)
|
||||||
|
#define NX_TIEOFF_CAN1_i_nSleep ((1 << 16) | 72)
|
||||||
|
#define NX_TIEOFF_DEINTERLACE0_i_NX_RF1_EMA ((3 << 16) | 73)
|
||||||
|
#define NX_TIEOFF_DEINTERLACE0_i_NX_RF1_EMAW ((2 << 16) | 76)
|
||||||
|
#define NX_TIEOFF_DEINTERLACE0_i_NX_RF2_EMAA ((3 << 16) | 78)
|
||||||
|
#define NX_TIEOFF_DEINTERLACE0_i_NX_RF2_EMAB ((3 << 16) | 81)
|
||||||
|
#define NX_TIEOFF_DEINTERLACE0_i_NX_RF2W_EMAA ((3 << 16) | 84)
|
||||||
|
#define NX_TIEOFF_DEINTERLACE0_i_NX_RF2W_EMAB ((3 << 16) | 87)
|
||||||
|
#define NX_TIEOFF_DISPLAYTOP0_i_ResConv_nPowerDown ((1 << 16) | 90)
|
||||||
|
#define NX_TIEOFF_DISPLAYTOP0_i_ResConv_nSleep ((1 << 16) | 91)
|
||||||
|
#define NX_TIEOFF_DISPLAYTOP0_i_HDMI_nPowerDown ((2 << 16) | 92)
|
||||||
|
#define NX_TIEOFF_DISPLAYTOP0_i_HDMI_nSleep ((2 << 16) | 94)
|
||||||
|
#define NX_TIEOFF_DISPLAYTOP0_i_HDMI_PHY_REFCLK_SEL ((1 << 16) | 96)
|
||||||
|
#define NX_TIEOFF_DISPLAYTOP0_i_TIEOFF_SPSRAM_EMA ((3 << 16) | 97)
|
||||||
|
#define NX_TIEOFF_DISPLAYTOP0_i_TIEOFF_SPSRAM_EMAW ((2 << 16) | 100)
|
||||||
|
#define NX_TIEOFF_DISPLAYTOP0_i_TIEOFF_DPSRAM_1R1W_EMAA ((3 << 16) | 102)
|
||||||
|
#define NX_TIEOFF_DISPLAYTOP0_i_TIEOFF_DPSRAM_1R1W_EMAB ((3 << 16) | 105)
|
||||||
|
#define NX_TIEOFF_DISPLAYTOP0_i_TIEOFF_DPSRAM_EMAA ((3 << 16) | 108)
|
||||||
|
#define NX_TIEOFF_DISPLAYTOP0_i_TIEOFF_DPSRAM_EMAB ((3 << 16) | 111)
|
||||||
|
#define NX_TIEOFF_DISPLAYTOP0_i_TIEOFF_DPSRAM_EMAWA ((2 << 16) | 114)
|
||||||
|
#define NX_TIEOFF_DISPLAYTOP0_i_TIEOFF_DPSRAM_EMAWB ((2 << 16) | 116)
|
||||||
|
#define NX_TIEOFF_MCUSTOP0_i_vrom_EMA ((3 << 16) | 118)
|
||||||
|
#define NX_TIEOFF_DREX0_CKE_INIT ((1 << 16) | 121)
|
||||||
|
#define NX_TIEOFF_DREX0_CA_SWAP ((1 << 16) | 122)
|
||||||
|
#define NX_TIEOFF_DREX0_CSYSREQ ((1 << 16) | 123)
|
||||||
|
#define NX_TIEOFF_DREX0_PAUSE_REQ ((1 << 16) | 124)
|
||||||
|
#define NX_TIEOFF_DREX0_PEREV_TRIGGER ((1 << 16) | 125)
|
||||||
|
#define NX_TIEOFF_DREX0_CTRL_HCKE ((1 << 16) | 126)
|
||||||
|
#define NX_TIEOFF_DREX0_DFI_RESET_N_P0 ((1 << 16) | 127)
|
||||||
|
#define NX_TIEOFF_DREX0_DFI_RESET_N_P1 ((1 << 16) | 128)
|
||||||
|
#define NX_TIEOFF_MIPI0_NX_DPSRAM_1R1W_EMAA ((3 << 16) | 129)
|
||||||
|
#define NX_TIEOFF_MIPI0_NX_DPSRAM_1R1W_EMAB ((3 << 16) | 132)
|
||||||
|
#define NX_TIEOFF_MIPI0_i_NX_NPOWERDOWN ((4 << 16) | 135)
|
||||||
|
#define NX_TIEOFF_MIPI0_i_NX_NSLEEP ((4 << 16) | 139)
|
||||||
|
#define NX_TIEOFF_SCALER0_i_NX_EMA ((3 << 16) | 143)
|
||||||
|
#define NX_TIEOFF_SCALER0_i_NX_EMAW ((2 << 16) | 146)
|
||||||
|
#define NX_TIEOFF_UART0_USESMC ((1 << 16) | 148)
|
||||||
|
#define NX_TIEOFF_UART0_SMCTXENB ((1 << 16) | 149)
|
||||||
|
#define NX_TIEOFF_UART0_SMCRXENB ((1 << 16) | 150)
|
||||||
|
#define NX_TIEOFF_UART1_USESMC ((1 << 16) | 151)
|
||||||
|
#define NX_TIEOFF_UART1_SMCTXENB ((1 << 16) | 152)
|
||||||
|
#define NX_TIEOFF_UART1_SMCRXENB ((1 << 16) | 153)
|
||||||
|
#define NX_TIEOFF_UART2_USESMC ((1 << 16) | 154)
|
||||||
|
#define NX_TIEOFF_UART2_SMCTXENB ((1 << 16) | 155)
|
||||||
|
#define NX_TIEOFF_UART2_SMCRXENB ((1 << 16) | 156)
|
||||||
|
#define NX_TIEOFF_UART3_USESMC ((1 << 16) | 157)
|
||||||
|
#define NX_TIEOFF_UART3_SMCTXENB ((1 << 16) | 158)
|
||||||
|
#define NX_TIEOFF_UART3_SMCRXENB ((1 << 16) | 159)
|
||||||
|
#define NX_TIEOFF_UART4_USESMC ((1 << 16) | 160)
|
||||||
|
#define NX_TIEOFF_UART4_SMCTXENB ((1 << 16) | 161)
|
||||||
|
#define NX_TIEOFF_UART4_SMCRXENB ((1 << 16) | 162)
|
||||||
|
#define NX_TIEOFF_UART5_USESMC ((1 << 16) | 163)
|
||||||
|
#define NX_TIEOFF_UART5_SMCTXENB ((1 << 16) | 164)
|
||||||
|
#define NX_TIEOFF_UART5_SMCRXENB ((1 << 16) | 165)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_nPowerDown ((1 << 16) | 166)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_nSleep ((1 << 16) | 167)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_NX_RF1_EMA ((3 << 16) | 168)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_NX_RF1_EMAW ((2 << 16) | 171)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_sys_interrupt_i ((1 << 16) | 173)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_hsic_en ((3 << 16) | 174)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_nResetSync ((1 << 16) | 177)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_nResetSync_ohci ((1 << 16) | 178)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_nAuxWellResetSync ((1 << 16) | 179)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_nHostPhyResetSync ((1 << 16) | 180)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_nHostUtmiResetSync ((1 << 16) | 181)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_nHostHsicResetSync ((1 << 16) | 182)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_HSIC_FREE_CLOCK_ENB ((1 << 16) | 183)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_HSIC_480M_FROM_OTG_PHY ((1 << 16) | 184)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_ss_word_if_enb_i ((1 << 16) | 185)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_ss_word_if_i ((1 << 16) | 186)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_ss_utmi_backward_enb_i ((1 << 16) | 187)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_ss_resume_utmi_pls_dis_i ((1 << 16) | 188)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_phy_vstatus_0_i ((3 << 16) | 189)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_phy_vstatus_1_i ((3 << 16) | 192)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_phy_vstatus_2_i ((3 << 16) | 195)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_phy_vstatus_3_i ((3 << 16) | 198)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_phy_vstatus_4_i ((3 << 16) | 201)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_phy_vstatus_5_i ((3 << 16) | 204)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_phy_vstatus_6_i ((3 << 16) | 207)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_phy_vstatus_7_i ((3 << 16) | 210)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_ss_power_state_valid_i ((1 << 16) | 213)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_ss_nxt_power_state_valid_i ((1 << 16) | 214)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_ss_power_state_i ((2 << 16) | 215)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_ss_next_power_state_i ((2 << 16) | 217)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_app_prt_ovrcur_i ((3 << 16) | 219)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_ss_simulation_mode_i ((1 << 16) | 222)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_ss_fladj_val_host_i ((6 << 16) | 224)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_ss_fladj_val_5_i ((3 << 16) | 230)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_ss_fladj_val_4_i ((3 << 16) | 233)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_ss_fladj_val_3_i ((3 << 16) | 236)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_ss_fladj_val_2_i ((3 << 16) | 239)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_ss_fladj_val_1_i ((3 << 16) | 242)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_ss_fladj_val_0_i ((3 << 16) | 245)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_ss_autoppd_on_overcur_en_i ((1 << 16) | 248)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_ss_ena_incr16_i ((1 << 16) | 249)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_ss_ena_incr8_i ((1 << 16) | 250)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_ss_ena_incr4_i ((1 << 16) | 251)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_ss_ena_incrx_align_i ((1 << 16) | 252)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_ohci_0_cntsel_n ((1 << 16) | 253)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_ohci_0_app_irq1_i ((1 << 16) | 254)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_ohci_0_app_irq12_i ((1 << 16) | 255)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_ohci_0_app_io_hit_i ((1 << 16) | 256)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_ss_hubsetup_min_i ((1 << 16) | 257)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_app_start_clk_i ((1 << 16) | 258)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_ohci_susp_lgcy_i ((1 << 16) | 259)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_SIDDQ ((1 << 16) | 260)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_VATESTENB ((2 << 16) | 261)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_POR_ENB ((1 << 16) | 263)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_POR ((1 << 16) | 264)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_REFCLKSEL ((2 << 16) | 265)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_FSEL ((3 << 16) | 267)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_COMMONONN ((1 << 16) | 270)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_RESREQIN ((1 << 16) | 271)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_PORTRESET ((1 << 16) | 272)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_OTGDISABLE ((1 << 16) | 273)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_LOOPBACKENB ((1 << 16) | 274)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_IDPULLUPi ((1 << 16) | 275)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_DRVVBUS ((1 << 16) | 276)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_ADPCHRG ((1 << 16) | 277)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_ADPDISCHRG ((1 << 16) | 278)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_ADPPRBENB ((1 << 16) | 279)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_VBUSVLDEXT ((1 << 16) | 280)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_VBUSVLDEXTSEL ((1 << 16) | 281)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_DPPULLDOWN ((1 << 16) | 282)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_DMPULLDOWN ((1 << 16) | 283)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_SUSPENDM_ENB ((1 << 16) | 284)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_SUSPENDM ((1 << 16) | 285)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_SLEEPM_ENB ((1 << 16) | 286)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_SLEEPM ((1 << 16) | 287)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_OPMODE_ENB ((1 << 16) | 288)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_OPMODE ((2 << 16) | 289)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_TERMSEL_ENB ((1 << 16) | 291)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_TERMSEL ((1 << 16) | 292)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_XCVRSEL_ENB ((1 << 16) | 293)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_XCVRSEL ((2 << 16) | 294)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_WORDINTERFACE_ENB ((1 << 16) | 296)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_WORDINTERFACE ((1 << 16) | 297)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_TXBITSTUFFEN ((1 << 16) | 298)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_TXBITSTUFFENH ((1 << 16) | 299)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_BYPASSDPDATA ((1 << 16) | 300)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_BYPASSDMDATA ((1 << 16) | 301)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_BYPASSDPEN ((1 << 16) | 302)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_BYPASSDMEN ((1 << 16) | 303)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_BYPASSSEL ((1 << 16) | 304)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_COMPDISTUNE ((3 << 16) | 305)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_SQRXTUNE ((3 << 16) | 308)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_OTGTUNE ((3 << 16) | 311)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_TXHSXVTUNE ((2 << 16) | 314)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_TXFSLSTUNE ((4 << 16) | 316)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_TXVREFTUNE ((4 << 16) | 320)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_TXRISETUNE ((2 << 16) | 324)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_TXRESTUNE ((2 << 16) | 326)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_TXPREEMPAMPTUNE ((2 << 16) | 328)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_TXPREEMPPULSETUNE ((1 << 16) | 330)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_CHRGSEL ((1 << 16) | 331)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_VDATDETENB ((1 << 16) | 332)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_VDATSRCENB ((1 << 16) | 333)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_DCDENB ((1 << 16) | 334)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_ACAENB ((1 << 16) | 335)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_HSIC_MSTRXCVR ((1 << 16) | 336)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_HSIC_SIDDQ ((1 << 16) | 337)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_HSIC_POR_ENB ((1 << 16) | 338)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_HSIC_POR ((1 << 16) | 339)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_HSIC_REFCLKDIV ((7 << 16) | 340)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_HSIC_REFCLKSEL ((2 << 16) | 347)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_HSIC_COMMONONN ((1 << 16) | 349)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_HSIC_PORTRESET ((1 << 16) | 350)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_HSIC_LOOPBACKENB ((1 << 16) | 351)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_HSIC_DPPULLDOWN ((1 << 16) | 352)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_HSIC_DMPULLDOWN ((1 << 16) | 353)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_HSIC_SUSPENDM_ENB ((1 << 16) | 354)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_HSIC_SUSPENDM ((1 << 16) | 355)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_HSIC_SLEEPM_ENB ((1 << 16) | 356)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_HSIC_SLEEPM ((1 << 16) | 357)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_HSIC_MSTRXOPU ((1 << 16) | 358)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_HSIC_OPMODE_ENB ((1 << 16) | 359)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_HSIC_OPMODE ((2 << 16) | 360)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_HSIC_XCVRSELECT_ENB ((1 << 16) | 362)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_HSIC_XCVRSELECT ((1 << 16) | 363)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_HSIC_WORDINTERFACE_ENB ((1 << 16) | 364)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_HSIC_WORDINTERFACE ((1 << 16) | 365)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_HSIC_TXBITSTUFFEN ((1 << 16) | 366)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_HSIC_TXBITSTUFFENH ((1 << 16) | 367)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_HSIC_TXRPUTUNE ((2 << 16) | 368)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_HSIC_TXRPDTUNE ((2 << 16) | 370)
|
||||||
|
#define NX_TIEOFF_USB20HOST0_i_HSIC_TXSRTUNE ((4 << 16) | 372)
|
||||||
|
#define NX_TIEOFF_USB20OTG0_i_nPowerDown ((1 << 16) | 376)
|
||||||
|
#define NX_TIEOFF_USB20OTG0_i_nSleep ((1 << 16) | 377)
|
||||||
|
#define NX_TIEOFF_USB20OTG0_i_NX_RF1_EMA ((3 << 16) | 378)
|
||||||
|
#define NX_TIEOFF_USB20OTG0_i_NX_RF1_EMAW ((2 << 16) | 381)
|
||||||
|
#define NX_TIEOFF_USB20OTG0_i_ss_scaledown_mode ((2 << 16) | 384)
|
||||||
|
#define NX_TIEOFF_USB20OTG0_i_gp_in ((16 << 16) | 386)
|
||||||
|
#define NX_TIEOFF_USB20OTG0_i_sof_count ((14 << 16) | 402)
|
||||||
|
#define NX_TIEOFF_USB20OTG0_i_sys_dma_done ((1 << 16) | 416)
|
||||||
|
#define NX_TIEOFF_USB20OTG0_i_if_select_hsic ((1 << 16) | 417)
|
||||||
|
#define NX_TIEOFF_USB20OTG0_i_nResetSync ((1 << 16) | 418)
|
||||||
|
#define NX_TIEOFF_USB20OTG0_i_nUtmiResetSync ((1 << 16) | 419)
|
||||||
|
#define NX_TIEOFF_USB20OTG0_i_SIDDQ ((1 << 16) | 420)
|
||||||
|
#define NX_TIEOFF_USB20OTG0_i_VATESTENB ((2 << 16) | 421)
|
||||||
|
#define NX_TIEOFF_USB20OTG0_i_POR_ENB ((1 << 16) | 423)
|
||||||
|
#define NX_TIEOFF_USB20OTG0_i_POR ((1 << 16) | 424)
|
||||||
|
#define NX_TIEOFF_USB20OTG0_i_REFCLKSEL ((2 << 16) | 425)
|
||||||
|
#define NX_TIEOFF_USB20OTG0_i_FSEL ((3 << 16) | 427)
|
||||||
|
#define NX_TIEOFF_USB20OTG0_i_COMMONONN ((1 << 16) | 430)
|
||||||
|
#define NX_TIEOFF_USB20OTG0_i_RESREQIN ((1 << 16) | 431)
|
||||||
|
#define NX_TIEOFF_USB20OTG0_i_PORTRESET ((1 << 16) | 432)
|
||||||
|
#define NX_TIEOFF_USB20OTG0_i_OTGDISABLE ((1 << 16) | 433)
|
||||||
|
#define NX_TIEOFF_USB20OTG0_i_LOOPBACKENB ((1 << 16) | 434)
|
||||||
|
#define NX_TIEOFF_USB20OTG0_i_IDPULLUP ((1 << 16) | 435)
|
||||||
|
#define NX_TIEOFF_USB20OTG0_i_DRVVBUS ((1 << 16) | 436)
|
||||||
|
#define NX_TIEOFF_USB20OTG0_i_ADPCHRG ((1 << 16) | 437)
|
||||||
|
#define NX_TIEOFF_USB20OTG0_i_ADPDISCHRG ((1 << 16) | 438)
|
||||||
|
#define NX_TIEOFF_USB20OTG0_i_ADPPRBENB ((1 << 16) | 439)
|
||||||
|
#define NX_TIEOFF_USB20OTG0_i_VBUSVLDEXT ((1 << 16) | 440)
|
||||||
|
#define NX_TIEOFF_USB20OTG0_i_VBUSVLDEXTSEL ((1 << 16) | 441)
|
||||||
|
#define NX_TIEOFF_USB20OTG0_i_DPPULLDOWN ((1 << 16) | 442)
|
||||||
|
#define NX_TIEOFF_USB20OTG0_i_DMPULLDOWN ((1 << 16) | 443)
|
||||||
|
#define NX_TIEOFF_USB20OTG0_i_SUSPENDM_ENB ((1 << 16) | 444)
|
||||||
|
#define NX_TIEOFF_USB20OTG0_i_SUSPENDM ((1 << 16) | 445)
|
||||||
|
#define NX_TIEOFF_USB20OTG0_i_SLEEPM_ENB ((1 << 16) | 446)
|
||||||
|
#define NX_TIEOFF_USB20OTG0_i_SLEEPM ((1 << 16) | 447)
|
||||||
|
#define NX_TIEOFF_USB20OTG0_i_OPMODE_ENB ((1 << 16) | 448)
|
||||||
|
#define NX_TIEOFF_USB20OTG0_i_OPMODE ((2 << 16) | 449)
|
||||||
|
#define NX_TIEOFF_USB20OTG0_i_TERMSEL_ENB ((1 << 16) | 451)
|
||||||
|
#define NX_TIEOFF_USB20OTG0_i_TERMSEL ((1 << 16) | 452)
|
||||||
|
#define NX_TIEOFF_USB20OTG0_i_XCVRSEL_ENB ((1 << 16) | 453)
|
||||||
|
#define NX_TIEOFF_USB20OTG0_i_XCVRSEL ((2 << 16) | 454)
|
||||||
|
#define NX_TIEOFF_USB20OTG0_i_WORDINTERFACE_ENB ((1 << 16) | 456)
|
||||||
|
#define NX_TIEOFF_USB20OTG0_i_WORDINTERFACE ((1 << 16) | 457)
|
||||||
|
#define NX_TIEOFF_USB20OTG0_i_TXBITSTUFFEN ((1 << 16) | 458)
|
||||||
|
#define NX_TIEOFF_USB20OTG0_i_TXBITSTUFFENH ((1 << 16) | 459)
|
||||||
|
#define NX_TIEOFF_USB20OTG0_i_BYPASSDPDATA ((1 << 16) | 460)
|
||||||
|
#define NX_TIEOFF_USB20OTG0_i_BYPASSDMDATA ((1 << 16) | 461)
|
||||||
|
#define NX_TIEOFF_USB20OTG0_i_BYPASSDPEN ((1 << 16) | 462)
|
||||||
|
#define NX_TIEOFF_USB20OTG0_i_BYPASSDMEN ((1 << 16) | 463)
|
||||||
|
#define NX_TIEOFF_USB20OTG0_i_BYPASSSEL ((1 << 16) | 464)
|
||||||
|
#define NX_TIEOFF_USB20OTG0_i_COMPDISTUNE ((3 << 16) | 465)
|
||||||
|
#define NX_TIEOFF_USB20OTG0_i_SQRXTUNE ((3 << 16) | 468)
|
||||||
|
#define NX_TIEOFF_USB20OTG0_i_OTGTUNE ((3 << 16) | 471)
|
||||||
|
#define NX_TIEOFF_USB20OTG0_i_TXHSXVTUNE ((2 << 16) | 474)
|
||||||
|
#define NX_TIEOFF_USB20OTG0_i_TXFSLSTUNE ((4 << 16) | 476)
|
||||||
|
#define NX_TIEOFF_USB20OTG0_i_TXVREFTUNE ((4 << 16) | 480)
|
||||||
|
#define NX_TIEOFF_USB20OTG0_i_TXRISETUNE ((2 << 16) | 484)
|
||||||
|
#define NX_TIEOFF_USB20OTG0_i_TXRESTUNE ((2 << 16) | 486)
|
||||||
|
#define NX_TIEOFF_USB20OTG0_i_TXPREEMPAMPTUNE ((2 << 16) | 488)
|
||||||
|
#define NX_TIEOFF_USB20OTG0_i_TXPREEMPPULSETUNE ((1 << 16) | 490)
|
||||||
|
#define NX_TIEOFF_USB20OTG0_i_CHRGSEL ((1 << 16) | 491)
|
||||||
|
#define NX_TIEOFF_USB20OTG0_i_VDATDETENB ((1 << 16) | 492)
|
||||||
|
#define NX_TIEOFF_USB20OTG0_i_VDATSRCENB ((1 << 16) | 493)
|
||||||
|
#define NX_TIEOFF_USB20OTG0_i_DCDENB ((1 << 16) | 494)
|
||||||
|
#define NX_TIEOFF_USB20OTG0_i_ACAENB ((1 << 16) | 495)
|
||||||
|
#define NX_TIEOFF_USB20OTG0_i_IDPULLUP_ENB ((1 << 16) | 496)
|
||||||
|
#define NX_TIEOFF_USB20OTG0_i_DPPULLDOWN_ENB ((1 << 16) | 497)
|
||||||
|
#define NX_TIEOFF_USB20OTG0_i_DMPULLDOWN_ENB ((1 << 16) | 498)
|
||||||
|
#define NX_TIEOFF_USB20OTG0_i_DRVVBUS_ENB ((1 << 16) | 499)
|
||||||
|
#define NX_TIEOFF_USB20OTG0_i_LPMClkMuxCntrl ((1 << 16) | 500)
|
||||||
|
#define NX_TIEOFF_USB20OTG0_i_GLITCHLESSMUXCntrl ((1 << 16) | 501)
|
||||||
|
#define NX_TIEOFF_CODA9600_i_nPWRDN00 ((4 << 16) | 502)
|
||||||
|
#define NX_TIEOFF_CODA9600_i_nSLEEP00 ((4 << 16) | 506)
|
||||||
|
#define NX_TIEOFF_CODA9600_i_nPWRDN01 ((8 << 16) | 512)
|
||||||
|
#define NX_TIEOFF_CODA9600_i_nSLEEP01 ((8 << 16) | 520)
|
||||||
|
#define NX_TIEOFF_CODA9600_i_nPWRDN02 ((10 << 16) | 528)
|
||||||
|
#define NX_TIEOFF_CODA9600_i_nSLEEP02 ((10 << 16) | 544)
|
||||||
|
#define NX_TIEOFF_CODA9600_i_nPWRDN03 ((2 << 16) | 554)
|
||||||
|
#define NX_TIEOFF_CODA9600_i_nSLEEP03 ((2 << 16) | 556)
|
||||||
|
#define NX_TIEOFF_CODA9600_i_nPWRDN04 ((8 << 16) | 558)
|
||||||
|
#define NX_TIEOFF_CODA9600_i_nSLEEP04 ((8 << 16) | 566)
|
||||||
|
#define NX_TIEOFF_CODA9600_i_nPWRDN05 ((3 << 16) | 576)
|
||||||
|
#define NX_TIEOFF_CODA9600_i_nSLEEP05 ((3 << 16) | 579)
|
||||||
|
#define NX_TIEOFF_CODA9600_i_nPWRDN06 ((7 << 16) | 582)
|
||||||
|
#define NX_TIEOFF_CODA9600_i_nSLEEP06 ((7 << 16) | 589)
|
||||||
|
#define NX_TIEOFF_CODA9600_i_nPWRDN07 ((12 << 16) | 596)
|
||||||
|
#define NX_TIEOFF_CODA9600_i_nSLEEP07 ((12 << 16) | 608)
|
||||||
|
#define NX_TIEOFF_CODA9600_i_nPWRDN08 ((1 << 16) | 620)
|
||||||
|
#define NX_TIEOFF_CODA9600_i_nSLEEP08 ((1 << 16) | 621)
|
||||||
|
#define NX_TIEOFF_CODA9600_i_nPWRDN09 ((2 << 16) | 622)
|
||||||
|
#define NX_TIEOFF_CODA9600_i_nSLEEP09 ((2 << 16) | 624)
|
||||||
|
#define NX_TIEOFF_CODA9600_i_nPWRDN10 ((10 << 16) | 626)
|
||||||
|
#define NX_TIEOFF_CODA9600_i_nSLEEP10 ((10 << 16) | 640)
|
||||||
|
#define NX_TIEOFF_CODA9600_i_nPWRDN11 ((1 << 16) | 650)
|
||||||
|
#define NX_TIEOFF_CODA9600_i_nSLEEP11 ((1 << 16) | 651)
|
||||||
|
#define NX_TIEOFF_CODA9600_i_TIE_rf2_EMAA ((3 << 16) | 652)
|
||||||
|
#define NX_TIEOFF_CODA9600_i_TIE_rf2_EMAB ((3 << 16) | 655)
|
||||||
|
#define NX_TIEOFF_CODA9600_i_TIE_rf2w_EMAA ((3 << 16) | 658)
|
||||||
|
#define NX_TIEOFF_CODA9600_i_TIE_rf2w_EMAB ((3 << 16) | 661)
|
||||||
|
#define NX_TIEOFF_CODA9600_i_TIE_ra2_EMAA ((3 << 16) | 664)
|
||||||
|
#define NX_TIEOFF_CODA9600_i_TIE_ra2_EMAB ((3 << 16) | 667)
|
||||||
|
#define NX_TIEOFF_CODA9600_i_TIE_ra2_EMAWA ((2 << 16) | 670)
|
||||||
|
#define NX_TIEOFF_CODA9600_i_TIE_ra2_EMAWB ((2 << 16) | 672)
|
||||||
|
#define NX_TIEOFF_CODA9600_i_TIE_ra2w_EMAA ((3 << 16) | 674)
|
||||||
|
#define NX_TIEOFF_CODA9600_i_TIE_ra2w_EMAB ((3 << 16) | 677)
|
||||||
|
#define NX_TIEOFF_CODA9600_i_TIE_ra2w_EMAWA ((2 << 16) | 680)
|
||||||
|
#define NX_TIEOFF_CODA9600_i_TIE_ra2w_EMAWB ((2 << 16) | 682)
|
||||||
|
#define NX_TIEOFF_CODA9600_i_TIE_rf1_EMA ((3 << 16) | 684)
|
||||||
|
#define NX_TIEOFF_CODA9600_i_TIE_rf1_EMAW ((2 << 16) | 687)
|
||||||
|
#define NX_TIEOFF_CODA9600_i_TIE_rf1w_EMA ((3 << 16) | 689)
|
||||||
|
#define NX_TIEOFF_CODA9600_i_TIE_rf1w_EMAW ((2 << 16) | 692)
|
||||||
|
#define NX_TIEOFF_DWC_GMAC0_sbd_flowctrl_i ((1 << 16) | 694)
|
||||||
|
#define NX_TIEOFF_DWC_GMAC0_phy_intf_sel_i ((3 << 16) | 695)
|
||||||
|
#define NX_TIEOFF_DWC_GMAC0_i_NX_RF2_EMAA ((3 << 16) | 698)
|
||||||
|
#define NX_TIEOFF_DWC_GMAC0_i_NX_RF2_EMAB ((3 << 16) | 701)
|
||||||
|
#define NX_TIEOFF_MALI4000_NX_DPSRAM_1R1W_EMAA ((3 << 16) | 704)
|
||||||
|
#define NX_TIEOFF_MALI4000_NX_DPSRAM_1R1W_EMAB ((3 << 16) | 707)
|
||||||
|
#define NX_TIEOFF_MALI4000_NX_SPSRAM_EMA ((3 << 16) | 710)
|
||||||
|
#define NX_TIEOFF_MALI4000_NX_SPSRAM_EMAW ((2 << 16) | 713)
|
||||||
|
#define NX_TIEOFF_MALI4000_NX_SPSRAM_BW_EMA ((3 << 16) | 715)
|
||||||
|
#define NX_TIEOFF_MALI4000_NX_SPSRAM_BW_EMAW ((2 << 16) | 718)
|
||||||
|
#define NX_TIEOFF_MALI4000_PWRDNBYPASS ((1 << 16) | 720)
|
||||||
|
#define NX_TIEOFF_MALI4000_GP_NX_NPOWERDOWN ((15 << 16) | 721)
|
||||||
|
#define NX_TIEOFF_MALI4000_GP_NX_NSLEEP ((15 << 16) | 736)
|
||||||
|
#define NX_TIEOFF_MALI4000_L2_NX_NPOWERDOWN ((3 << 16) | 751)
|
||||||
|
#define NX_TIEOFF_MALI4000_L2_NX_NSLEEP ((3 << 16) | 754)
|
||||||
|
#define NX_TIEOFF_MALI4000_PP0_NX_NPOWERDOWN ((32 << 16) | 768)
|
||||||
|
#define NX_TIEOFF_MALI4000_PP0_NX_NSLEEP ((32 << 16) | 800)
|
||||||
|
#define NX_TIEOFF_MALI4000_PP1_NX_NPOWERDOWN ((32 << 16) | 832)
|
||||||
|
#define NX_TIEOFF_MALI4000_PP1_NX_NSLEEP ((32 << 16) | 864)
|
||||||
|
#define NX_TIEOFF_MALI4000_PP2_NX_NPOWERDOWN ((32 << 16) | 896)
|
||||||
|
#define NX_TIEOFF_MALI4000_PP2_NX_NSLEEP ((32 << 16) | 928)
|
||||||
|
#define NX_TIEOFF_MALI4000_PP3_NX_NPOWERDOWN ((32 << 16) | 960)
|
||||||
|
#define NX_TIEOFF_MALI4000_PP3_NX_NSLEEP ((32 << 16) | 992)
|
||||||
|
#define NX_TIEOFF_A3BM_AXI_PERI_BUS0_SYNCMODEREQm9 ((1 << 16) | 1024)
|
||||||
|
#define NX_TIEOFF_A3BM_AXI_PERI_BUS0_SYNCMODEREQm10 ((1 << 16) | 1025)
|
||||||
|
#define NX_TIEOFF_A3BM_AXI_PERI_BUS0_SYNCMODEREQm16 ((1 << 16) | 1026)
|
||||||
|
#define NX_TIEOFF_A3BM_AXI_TOP_MASTER_BUS0_REMAP ((2 << 16) | 1027)
|
||||||
|
#if defined(CONFIG_ARCH_S5P6818)
|
||||||
|
#define NX_TIEOFF_Inst_ARMTOP_SMPEN ((4 << 16) | 2816)
|
||||||
|
#define NX_TIEOFF_Inst_ARMTOP_STANBYWFI ((4 << 16) | 2880)
|
||||||
|
#define NX_TIEOFF_Inst_ARMTOP_STANBYWFIL2 ((1 << 16) | 2884)
|
||||||
|
#define NX_TIEOFF_Inst_ARMTOP_DBGNOPWRDWN ((4 << 16) | 2889)
|
||||||
|
#define NX_TIEOFF_Inst_ARMTOP_DBGPWRUPREQ ((4 << 16) | 2893)
|
||||||
|
#define NX_TIEOFF_Inst_ARMTOP_COREPWRDOWNPRE ((1 << 16) | 2901)
|
||||||
|
#define NX_TIEOFF_Inst_ARMTOP_CPU0PWRDOWNPRE ((1 << 16) | 2902)
|
||||||
|
#define NX_TIEOFF_Inst_ARMTOP_CPU1PWRDOWNPRE ((1 << 16) | 2903)
|
||||||
|
#define NX_TIEOFF_Inst_ARMTOP_CPU2PWRDOWNPRE ((1 << 16) | 2904)
|
||||||
|
#define NX_TIEOFF_Inst_ARMTOP_CPU3PWRDOWNPRE ((1 << 16) | 2905)
|
||||||
|
#define NX_TIEOFF_Inst_ARMTOP_COREPWRDOWNALL ((1 << 16) | 2906)
|
||||||
|
#define NX_TIEOFF_Inst_ARMTOP_CPU0PWRDOWNALL ((1 << 16) | 2907)
|
||||||
|
#define NX_TIEOFF_Inst_ARMTOP_CPU1PWRDOWNALL ((1 << 16) | 2908)
|
||||||
|
#define NX_TIEOFF_Inst_ARMTOP_CPU2PWRDOWNALL ((1 << 16) | 2909)
|
||||||
|
#define NX_TIEOFF_Inst_ARMTOP_CPU3PWRDOWNALL ((1 << 16) | 2910)
|
||||||
|
#define NX_TIEOFF_Inst_ARMTOP_CLAMPL2 ((1 << 16) | 2920)
|
||||||
|
#define NX_TIEOFF_Inst_ARMTOP_L2FLUSHREQ ((1 << 16) | 3018)
|
||||||
|
#define NX_TIEOFF_Inst_ARMTOP_L2FLUSHDONE ((1 << 16) | 3019)
|
||||||
|
#define NX_TIEOFF_Inst_ARMTOP_ACINACTM ((1 << 16) | 3023)
|
||||||
|
#define NX_TIEOFF_Inst_ARMTOP_P1_SMPEN ((4 << 16) | 3360)
|
||||||
|
#define NX_TIEOFF_Inst_ARMTOP_P1_STANBYWFI ((4 << 16) | 3424)
|
||||||
|
#define NX_TIEOFF_Inst_ARMTOP_P1_STANBYWFIL2 ((1 << 16) | 3428)
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#define NX_TIEOFF_Inst_ARMTOP_P1_DBGNOPWRDWN ((4 << 16) | 3442)
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#define NX_TIEOFF_Inst_ARMTOP_P1_DBGPWRUPREQ ((4 << 16) | 3443)
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#define NX_TIEOFF_Inst_ARMTOP_P1_DBGPWRDUP ((4 << 16) | 3444)
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#define NX_TIEOFF_Inst_ARMTOP_P1_COREPWRDOWNPRE ((1 << 16) | 3445)
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#define NX_TIEOFF_Inst_ARMTOP_P1_CPU0PWRDOWNPRE ((1 << 16) | 3446)
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#define NX_TIEOFF_Inst_ARMTOP_P1_CPU1PWRDOWNPRE ((1 << 16) | 3447)
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#define NX_TIEOFF_Inst_ARMTOP_P1_CPU2PWRDOWNPRE ((1 << 16) | 3448)
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#define NX_TIEOFF_Inst_ARMTOP_P1_CPU3PWRDOWNPRE ((1 << 16) | 3449)
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#define NX_TIEOFF_Inst_ARMTOP_P1_COREPWRDOWNALL ((1 << 16) | 3450)
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#define NX_TIEOFF_Inst_ARMTOP_P1_CPU0PWRDOWNALL ((1 << 16) | 3451)
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#define NX_TIEOFF_Inst_ARMTOP_P1_CPU1PWRDOWNALL ((1 << 16) | 3452)
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#define NX_TIEOFF_Inst_ARMTOP_P1_CPU2PWRDOWNALL ((1 << 16) | 3453)
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#define NX_TIEOFF_Inst_ARMTOP_P1_CPU3PWRDOWNALL ((1 << 16) | 3454)
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#define NX_TIEOFF_Inst_ARMTOP_P1_CLAMPL2 ((1 << 16) | 3464)
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#define NX_TIEOFF_Inst_ARMTOP_P1_L2FLUSHREQ ((1 << 16) | 3562)
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#define NX_TIEOFF_Inst_ARMTOP_P1_L2FLUSHDONE ((1 << 16) | 3563)
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#define NX_TIEOFF_Inst_ARMTOP_P1_ACINACTM ((1 << 16) | 3567)
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#endif
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#endif /* _NEXELL_TIEOFF_H */
|
||||||
Loading…
Reference in a new issue