mirror of
https://github.com/AsahiLinux/u-boot
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board: gateworks: venice: add imx8mm-gw7903 support
The GW7903 is based on the i.MX 8M Mini SoC featuring: - LPDDR4 DRAM - eMMC FLASH - microSD socket with voltage select support - Gateworks System Controller - M.2 A-E Socket with USB2.0 and PCIe - MiniPCIe Socket with PCIe, USB2.0, and SIM - IMX8M FEC - RS232/RS485/RS422 serial transceiver - LIS2DE12 3-axis accelerometer - front panel LED's - off-board isolated digital I/O - Wide range DC power input - 802.3at PoE - PMIC Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Fabio Estevam <festevam@denx.de>
This commit is contained in:
Tim Harvey
Stefano Babic
parent
2c6ae0a15f
commit
a1c711046b
9 changed files with 3859 additions and 625 deletions
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@ -913,6 +913,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
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imx8mm-venice-gw73xx-0x.dtb \
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imx8mm-venice-gw7901.dtb \
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imx8mm-venice-gw7902.dtb \
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imx8mm-venice-gw7903.dtb \
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imx8mm-verdin.dtb \
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phycore-imx8mm.dtb \
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imx8mn-bsh-smm-s2.dtb \
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28
arch/arm/dts/imx8mm-venice-gw7903-u-boot.dtsi
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28
arch/arm/dts/imx8mm-venice-gw7903-u-boot.dtsi
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@ -0,0 +1,28 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2022 Gateworks Corporation
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*/
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#include "imx8mm-venice-u-boot.dtsi"
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&fec1 {
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phy-reset-gpios = <&gpio4 25 GPIO_ACTIVE_LOW>;
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phy-reset-duration = <1>;
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phy-reset-post-delay = <300>;
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};
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&pinctrl_fec1 {
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u-boot,dm-spl;
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};
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&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b} {
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u-boot,dm-spl;
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};
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&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b/regulators} {
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u-boot,dm-spl;
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};
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&pinctrl_pmic {
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u-boot,dm-spl;
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};
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832
arch/arm/dts/imx8mm-venice-gw7903.dts
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832
arch/arm/dts/imx8mm-venice-gw7903.dts
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@ -0,0 +1,832 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2022 Gateworks Corporation
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*/
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/linux-event-codes.h>
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#include <dt-bindings/leds/common.h>
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#include <dt-bindings/phy/phy-imx8-pcie.h>
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#include "imx8mm.dtsi"
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/ {
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model = "Gateworks Venice GW7903 i.MX8MM board";
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compatible = "gw,imx8mm-gw7903", "fsl,imx8mm";
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aliases {
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ethernet0 = &fec1;
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usb0 = &usbotg1;
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};
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chosen {
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stdout-path = &uart2;
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};
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memory@40000000 {
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device_type = "memory";
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reg = <0x0 0x40000000 0 0x80000000>;
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};
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gpio-keys {
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compatible = "gpio-keys";
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user-pb {
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label = "user_pb";
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gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
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linux,code = <BTN_0>;
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};
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user-pb1x {
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label = "user_pb1x";
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linux,code = <BTN_1>;
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interrupt-parent = <&gsc>;
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interrupts = <0>;
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};
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key-erased {
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label = "key_erased";
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linux,code = <BTN_2>;
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interrupt-parent = <&gsc>;
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interrupts = <1>;
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};
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eeprom-wp {
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label = "eeprom_wp";
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linux,code = <BTN_3>;
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interrupt-parent = <&gsc>;
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interrupts = <2>;
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};
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switch-hold {
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label = "switch_hold";
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linux,code = <BTN_5>;
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interrupt-parent = <&gsc>;
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interrupts = <7>;
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};
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};
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led-controller {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpio_leds>;
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led-0 {
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function = LED_FUNCTION_STATUS;
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color = <LED_COLOR_ID_RED>;
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label = "led01_red";
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gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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led-1 {
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function = LED_FUNCTION_STATUS;
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color = <LED_COLOR_ID_GREEN>;
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label = "led01_grn";
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gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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led-2 {
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function = LED_FUNCTION_STATUS;
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color = <LED_COLOR_ID_RED>;
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label = "led02_red";
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gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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led-3 {
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function = LED_FUNCTION_STATUS;
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color = <LED_COLOR_ID_GREEN>;
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label = "led02_grn";
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gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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led-4 {
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function = LED_FUNCTION_STATUS;
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color = <LED_COLOR_ID_RED>;
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label = "led03_red";
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gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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led-5 {
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function = LED_FUNCTION_STATUS;
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color = <LED_COLOR_ID_GREEN>;
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label = "led03_grn";
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gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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led-6 {
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function = LED_FUNCTION_STATUS;
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color = <LED_COLOR_ID_RED>;
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label = "led04_red";
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gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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led-7 {
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function = LED_FUNCTION_STATUS;
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color = <LED_COLOR_ID_GREEN>;
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label = "led04_grn";
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gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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led-8 {
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function = LED_FUNCTION_STATUS;
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color = <LED_COLOR_ID_RED>;
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label = "led05_red";
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gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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led-9 {
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function = LED_FUNCTION_STATUS;
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color = <LED_COLOR_ID_GREEN>;
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label = "led05_grn";
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gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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led-a {
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function = LED_FUNCTION_STATUS;
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color = <LED_COLOR_ID_RED>;
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label = "led06_red";
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gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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led-b {
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function = LED_FUNCTION_STATUS;
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color = <LED_COLOR_ID_GREEN>;
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label = "led06_grn";
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gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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};
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pcie0_refclk: pcie0-refclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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};
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reg_3p3v: regulator-3p3v {
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compatible = "regulator-fixed";
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regulator-name = "3P3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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};
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&A53_0 {
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cpu-supply = <&buck2>;
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};
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&A53_1 {
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cpu-supply = <&buck2>;
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};
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&A53_2 {
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cpu-supply = <&buck2>;
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};
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&A53_3 {
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cpu-supply = <&buck2>;
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};
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&ddrc {
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operating-points-v2 = <&ddrc_opp_table>;
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ddrc_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-25M {
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opp-hz = /bits/ 64 <25000000>;
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};
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opp-100M {
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opp-hz = /bits/ 64 <100000000>;
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};
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opp-750M {
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opp-hz = /bits/ 64 <750000000>;
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};
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};
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec1>;
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phy-mode = "rgmii-id";
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phy-handle = <ðphy0>;
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local-mac-address = [00 00 00 00 00 00];
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0>;
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rx-internal-delay-ps = <2000>;
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tx-internal-delay-ps = <2500>;
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};
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};
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};
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&gpio1 {
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gpio-line-names = "", "", "", "", "", "", "", "",
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"", "", "rs422_en#", "rs485_en#", "rs232_en#", "", "", "",
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"", "", "", "", "", "", "", "",
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"", "", "", "", "", "", "", "";
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};
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&gpio2 {
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gpio-line-names = "dig2_in", "dig2_out#", "", "", "", "", "", "",
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"dig1_out#", "dig1_in", "", "", "", "", "", "",
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"", "", "", "", "", "", "", "",
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"", "", "", "", "", "", "", "";
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};
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&gpio5 {
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gpio-line-names = "", "", "", "", "", "", "", "sim1_det#",
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"sim2_det#", "sim2_sel", "", "", "pci_wdis#", "", "", "",
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"", "", "", "", "", "", "", "",
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"", "", "", "", "", "", "", "";
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};
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&i2c1 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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status = "okay";
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gsc: gsc@20 {
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compatible = "gw,gsc";
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reg = <0x20>;
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pinctrl-0 = <&pinctrl_gsc>;
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interrupt-parent = <&gpio4>;
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interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
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interrupt-controller;
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#interrupt-cells = <1>;
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adc {
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compatible = "gw,gsc-adc";
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#address-cells = <1>;
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#size-cells = <0>;
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channel@6 {
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gw,mode = <0>;
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reg = <0x06>;
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label = "temp";
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};
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channel@8 {
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gw,mode = <1>;
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reg = <0x08>;
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label = "vdd_bat";
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};
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channel@82 {
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gw,mode = <2>;
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reg = <0x82>;
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label = "vin";
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gw,voltage-divider-ohms = <22100 1000>;
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gw,voltage-offset-microvolt = <700000>;
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};
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channel@84 {
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gw,mode = <2>;
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reg = <0x84>;
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label = "vdd_5p0";
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gw,voltage-divider-ohms = <10000 10000>;
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};
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channel@86 {
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gw,mode = <2>;
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reg = <0x86>;
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label = "vdd_3p3";
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gw,voltage-divider-ohms = <10000 10000>;
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};
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channel@88 {
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gw,mode = <2>;
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reg = <0x88>;
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label = "vdd_0p9";
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};
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channel@8c {
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gw,mode = <2>;
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reg = <0x8c>;
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label = "vdd_soc";
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};
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channel@8e {
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gw,mode = <2>;
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reg = <0x8e>;
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label = "vdd_arm";
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};
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channel@90 {
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gw,mode = <2>;
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reg = <0x90>;
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label = "vdd_1p8";
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};
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channel@92 {
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gw,mode = <2>;
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reg = <0x92>;
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label = "vdd_dram";
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};
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channel@a2 {
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gw,mode = <2>;
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reg = <0xa2>;
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label = "vdd_gsc";
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gw,voltage-divider-ohms = <10000 10000>;
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};
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};
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};
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gpio: gpio@23 {
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compatible = "nxp,pca9555";
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reg = <0x23>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-parent = <&gsc>;
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interrupts = <4>;
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};
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eeprom@50 {
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compatible = "atmel,24c02";
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reg = <0x50>;
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pagesize = <16>;
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};
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eeprom@51 {
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compatible = "atmel,24c02";
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reg = <0x51>;
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pagesize = <16>;
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};
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eeprom@52 {
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compatible = "atmel,24c02";
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reg = <0x52>;
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pagesize = <16>;
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};
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eeprom@53 {
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compatible = "atmel,24c02";
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reg = <0x53>;
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pagesize = <16>;
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};
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rtc@68 {
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compatible = "dallas,ds1672";
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reg = <0x68>;
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};
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};
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&i2c2 {
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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status = "okay";
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pmic@4b {
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compatible = "rohm,bd71847";
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reg = <0x4b>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pmic>;
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interrupt-parent = <&gpio3>;
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interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
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rohm,reset-snvs-powered;
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#clock-cells = <0>;
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clocks = <&osc_32k 0>;
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clock-output-names = "clk-32k-out";
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regulators {
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/* vdd_soc: 0.805-0.900V (typ=0.8V) */
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BUCK1 {
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regulator-name = "buck1";
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regulator-min-microvolt = <700000>;
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regulator-max-microvolt = <1300000>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <1250>;
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};
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/* vdd_arm: 0.805-1.0V (typ=0.9V) */
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buck2: BUCK2 {
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regulator-name = "buck2";
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regulator-min-microvolt = <700000>;
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regulator-max-microvolt = <1300000>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <1250>;
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rohm,dvs-run-voltage = <1000000>;
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rohm,dvs-idle-voltage = <900000>;
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};
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/* vdd_0p9: 0.805-1.0V (typ=0.9V) */
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BUCK3 {
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regulator-name = "buck3";
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regulator-min-microvolt = <700000>;
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regulator-max-microvolt = <1350000>;
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regulator-boot-on;
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regulator-always-on;
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};
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/* vdd_3p3 */
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BUCK4 {
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regulator-name = "buck4";
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regulator-min-microvolt = <3000000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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/* vdd_1p8 */
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BUCK5 {
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regulator-name = "buck5";
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||||
regulator-min-microvolt = <1605000>;
|
||||
regulator-max-microvolt = <1995000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
/* vdd_dram */
|
||||
BUCK6 {
|
||||
regulator-name = "buck6";
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1400000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
/* nvcc_snvs_1p8 */
|
||||
LDO1 {
|
||||
regulator-name = "ldo1";
|
||||
regulator-min-microvolt = <1600000>;
|
||||
regulator-max-microvolt = <1900000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
/* vdd_snvs_0p8 */
|
||||
LDO2 {
|
||||
regulator-name = "ldo2";
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
/* vdda_1p8 */
|
||||
LDO3 {
|
||||
regulator-name = "ldo3";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
LDO4 {
|
||||
regulator-name = "ldo4";
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
LDO6 {
|
||||
regulator-name = "ldo6";
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c3>;
|
||||
status = "okay";
|
||||
|
||||
accelerometer@19 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_accel>;
|
||||
compatible = "st,lis2de12";
|
||||
reg = <0x19>;
|
||||
st,drdy-int-pin = <1>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
|
||||
interrupt-names = "INT1";
|
||||
};
|
||||
};
|
||||
|
||||
&pcie_phy {
|
||||
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
|
||||
fsl,clkreq-unsupported;
|
||||
clocks = <&pcie0_refclk>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pcie0>;
|
||||
reset-gpio = <&gpio5 11 GPIO_ACTIVE_LOW>;
|
||||
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
|
||||
<&pcie0_refclk>;
|
||||
clock-names = "pcie", "pcie_aux", "pcie_bus";
|
||||
assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
|
||||
<&clk IMX8MM_CLK_PCIE1_CTRL>;
|
||||
assigned-clock-rates = <10000000>, <250000000>;
|
||||
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
|
||||
<&clk IMX8MM_SYS_PLL2_250M>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* off-board RS232/RS485/RS422 */
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
cts-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
|
||||
rts-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
|
||||
dtr-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
|
||||
dsr-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
|
||||
dcd-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
|
||||
uart-has-rtscts;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* console */
|
||||
&uart2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg1 {
|
||||
dr_mode = "host";
|
||||
disable-over-current;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* microSD */
|
||||
&usdhc2 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
|
||||
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
|
||||
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
|
||||
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
|
||||
bus-width = <4>;
|
||||
vmmc-supply = <®_3p3v>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* eMMC */
|
||||
&usdhc3 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc3>;
|
||||
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
|
||||
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wdog1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_wdog>;
|
||||
fsl,ext-reset-output;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x40000041 /* RS422# */
|
||||
MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x40000041 /* RS485# */
|
||||
MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x40000041 /* RS232# */
|
||||
MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x40000041 /* DIG1_IN */
|
||||
MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* DIG1_OUT */
|
||||
MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0 0x40000041 /* DIG2_IN */
|
||||
MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1 0x40000041 /* DIG2_OUT */
|
||||
MX8MM_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x40000041 /* SIM1DET# */
|
||||
MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x40000041 /* SIM2DET# */
|
||||
MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40000041 /* SIM2SEL */
|
||||
MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x40000041 /* PCI_WDIS# */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_accel: accelgrp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x159
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_fec1: fec1grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
|
||||
MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
|
||||
MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
|
||||
MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
|
||||
MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
|
||||
MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
|
||||
MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
|
||||
MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
|
||||
MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
|
||||
MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
|
||||
MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
|
||||
MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
|
||||
MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
|
||||
MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
|
||||
MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x19 /* IRQ# */
|
||||
MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x19 /* RST# */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_gsc: gscgrp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x159
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1: i2c1grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
|
||||
MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2: i2c2grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
|
||||
MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c3: i2c3grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
|
||||
MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_gpio_leds: gpioledgrp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19
|
||||
MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x19
|
||||
MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19
|
||||
MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x19
|
||||
MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
|
||||
MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x19
|
||||
MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19
|
||||
MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19
|
||||
MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19
|
||||
MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x19
|
||||
MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x19
|
||||
MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pcie0: pciegrp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x41
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pmic: pmicgrp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x41
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
|
||||
MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
|
||||
MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x140
|
||||
MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x140
|
||||
MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x140
|
||||
MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x140
|
||||
MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x140
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart2: uart2grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
|
||||
MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2: usdhc2grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
|
||||
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
|
||||
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
|
||||
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
|
||||
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
|
||||
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
|
||||
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
|
||||
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
|
||||
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
|
||||
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
|
||||
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
|
||||
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
|
||||
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
|
||||
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
|
||||
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
|
||||
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
|
||||
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3: usdhc3grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
|
||||
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
|
||||
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
|
||||
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
|
||||
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
|
||||
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
|
||||
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
|
||||
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
|
||||
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
|
||||
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
|
||||
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
|
||||
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
|
||||
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
|
||||
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
|
||||
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
|
||||
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
|
||||
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
|
||||
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
|
||||
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
|
||||
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
|
||||
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
|
||||
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
|
||||
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
|
||||
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
|
||||
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
|
||||
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
|
||||
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
|
||||
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
|
||||
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
|
||||
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
|
||||
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_wdog: wdoggrp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
@ -584,7 +584,7 @@ int gsc_init(int quiet)
|
|||
if (ret)
|
||||
hang();
|
||||
|
||||
return ((16 << som_info.sdram_size) / 1024);
|
||||
return (16 << som_info.sdram_size);
|
||||
}
|
||||
|
||||
const char *gsc_get_model(void)
|
||||
|
|
|
|||
|
|
@ -7,6 +7,7 @@
|
|||
#define __LPDDR4_TIMING_H__
|
||||
|
||||
#ifdef CONFIG_IMX8MM
|
||||
extern struct dram_timing_info dram_timing_512mb;
|
||||
extern struct dram_timing_info dram_timing_1gb;
|
||||
extern struct dram_timing_info dram_timing_2gb;
|
||||
extern struct dram_timing_info dram_timing_4gb;
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
1849
board/gateworks/venice/lpddr4_timing_imx8mm_512mb.c
Normal file
1849
board/gateworks/venice/lpddr4_timing_imx8mm_512mb.c
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -43,25 +43,28 @@ static void spl_dram_init(int size)
|
|||
|
||||
switch (size) {
|
||||
#ifdef CONFIG_IMX8MM
|
||||
case 1:
|
||||
case 512:
|
||||
dram_timing = &dram_timing_512mb;
|
||||
break;
|
||||
case 1024:
|
||||
dram_timing = &dram_timing_1gb;
|
||||
break;
|
||||
case 2:
|
||||
case 2048:
|
||||
dram_timing = &dram_timing_2gb;
|
||||
break;
|
||||
case 4:
|
||||
case 4096:
|
||||
dram_timing = &dram_timing_4gb;
|
||||
break;
|
||||
default:
|
||||
printf("Unknown DDR configuration: %d GiB\n", size);
|
||||
printf("Unknown DDR configuration: %d MiB\n", size);
|
||||
dram_timing = &dram_timing_1gb;
|
||||
size = 1;
|
||||
size = 1024;
|
||||
#endif
|
||||
#ifdef CONFIG_IMX8MN
|
||||
case 1:
|
||||
case 1024:
|
||||
dram_timing = &dram_timing_1gb_single_die;
|
||||
break;
|
||||
case 2:
|
||||
case 2048:
|
||||
if (!strcmp(gsc_get_model(), "GW7902-SP466-A") ||
|
||||
!strcmp(gsc_get_model(), "GW7902-SP466-B")) {
|
||||
dram_timing = &dram_timing_2gb_dual_die;
|
||||
|
|
@ -70,13 +73,17 @@ static void spl_dram_init(int size)
|
|||
}
|
||||
break;
|
||||
default:
|
||||
printf("Unknown DDR configuration: %d GiB\n", size);
|
||||
printf("Unknown DDR configuration: %d MiB\n", size);
|
||||
dram_timing = &dram_timing_2gb_dual_die;
|
||||
size = 2;
|
||||
size = 2048;
|
||||
#endif
|
||||
}
|
||||
|
||||
printf("DRAM : LPDDR4 %d GiB\n", size);
|
||||
printf("DRAM : LPDDR4 ");
|
||||
if (size > 512)
|
||||
printf("%d GiB\n", size / 1024);
|
||||
else
|
||||
printf("%d MiB\n", size);
|
||||
ddr_init(dram_timing);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -57,7 +57,7 @@ CONFIG_CMD_EXT4_WRITE=y
|
|||
# CONFIG_SPL_EFI_PARTITION is not set
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_OF_LIST="imx8mm-venice imx8mm-venice-gw71xx-0x imx8mm-venice-gw72xx-0x imx8mm-venice-gw73xx-0x imx8mm-venice-gw7901 imx8mm-venice-gw7902"
|
||||
CONFIG_OF_LIST="imx8mm-venice imx8mm-venice-gw71xx-0x imx8mm-venice-gw72xx-0x imx8mm-venice-gw73xx-0x imx8mm-venice-gw7901 imx8mm-venice-gw7902 imx8mm-venice-gw7903"
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
|
||||
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue