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Merge git://git.denx.de/u-boot-rockchip

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This commit is contained in:
Tom Rini 2017-11-01 09:32:14 -04:00
commit a0cdb534e1
7 changed files with 114 additions and 102 deletions
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2
arch/arm/mach-rockchip/rk3328/clk_rk3328.c
View file

@ -25,7 +25,7 @@ void *rockchip_get_cru(void)
if (ret)
return ERR_PTR(ret);
priv = devfdt_get_addr_ptr(dev);
priv = dev_get_priv(dev);
return priv->cru;
}

1
configs/lion-rk3368_defconfig
View file

@ -67,6 +67,7 @@ CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_RGMII=y

1
configs/puma-rk3399_defconfig
View file

@ -57,6 +57,7 @@ CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y

157
drivers/clk/rockchip/clk_rk3399.c
View file

@ -398,84 +398,6 @@ static int pll_para_config(u32 freq_hz, struct pll_div *div)
return 0;
}
#ifdef CONFIG_SPL_BUILD
static void rkclk_init(struct rk3399_cru *cru)
{
u32 aclk_div;
u32 hclk_div;
u32 pclk_div;
/*
* some cru registers changed by bootrom, we'd better reset them to
* reset/default values described in TRM to avoid confusion in kernel.
* Please consider these three lines as a fix of bootrom bug.
*/
rk_clrsetreg(&cru->clksel_con[12], 0xffff, 0x4101);
rk_clrsetreg(&cru->clksel_con[19], 0xffff, 0x033f);
rk_clrsetreg(&cru->clksel_con[56], 0x0003, 0x0003);
/* configure gpll cpll */
rkclk_set_pll(&cru->gpll_con[0], &gpll_init_cfg);
rkclk_set_pll(&cru->cpll_con[0], &cpll_init_cfg);
/* configure perihp aclk, hclk, pclk */
aclk_div = GPLL_HZ / PERIHP_ACLK_HZ - 1;
assert((aclk_div + 1) * PERIHP_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
hclk_div = PERIHP_ACLK_HZ / PERIHP_HCLK_HZ - 1;
assert((hclk_div + 1) * PERIHP_HCLK_HZ ==
PERIHP_ACLK_HZ && (hclk_div < 0x4));
pclk_div = PERIHP_ACLK_HZ / PERIHP_PCLK_HZ - 1;
assert((pclk_div + 1) * PERIHP_PCLK_HZ ==
PERIHP_ACLK_HZ && (pclk_div < 0x7));
rk_clrsetreg(&cru->clksel_con[14],
PCLK_PERIHP_DIV_CON_MASK | HCLK_PERIHP_DIV_CON_MASK |
ACLK_PERIHP_PLL_SEL_MASK | ACLK_PERIHP_DIV_CON_MASK,
pclk_div << PCLK_PERIHP_DIV_CON_SHIFT |
hclk_div << HCLK_PERIHP_DIV_CON_SHIFT |
ACLK_PERIHP_PLL_SEL_GPLL << ACLK_PERIHP_PLL_SEL_SHIFT |
aclk_div << ACLK_PERIHP_DIV_CON_SHIFT);
/* configure perilp0 aclk, hclk, pclk */
aclk_div = GPLL_HZ / PERILP0_ACLK_HZ - 1;
assert((aclk_div + 1) * PERILP0_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
hclk_div = PERILP0_ACLK_HZ / PERILP0_HCLK_HZ - 1;
assert((hclk_div + 1) * PERILP0_HCLK_HZ ==
PERILP0_ACLK_HZ && (hclk_div < 0x4));
pclk_div = PERILP0_ACLK_HZ / PERILP0_PCLK_HZ - 1;
assert((pclk_div + 1) * PERILP0_PCLK_HZ ==
PERILP0_ACLK_HZ && (pclk_div < 0x7));
rk_clrsetreg(&cru->clksel_con[23],
PCLK_PERILP0_DIV_CON_MASK | HCLK_PERILP0_DIV_CON_MASK |
ACLK_PERILP0_PLL_SEL_MASK | ACLK_PERILP0_DIV_CON_MASK,
pclk_div << PCLK_PERILP0_DIV_CON_SHIFT |
hclk_div << HCLK_PERILP0_DIV_CON_SHIFT |
ACLK_PERILP0_PLL_SEL_GPLL << ACLK_PERILP0_PLL_SEL_SHIFT |
aclk_div << ACLK_PERILP0_DIV_CON_SHIFT);
/* perilp1 hclk select gpll as source */
hclk_div = GPLL_HZ / PERILP1_HCLK_HZ - 1;
assert((hclk_div + 1) * PERILP1_HCLK_HZ ==
GPLL_HZ && (hclk_div < 0x1f));
pclk_div = PERILP1_HCLK_HZ / PERILP1_HCLK_HZ - 1;
assert((pclk_div + 1) * PERILP1_HCLK_HZ ==
PERILP1_HCLK_HZ && (hclk_div < 0x7));
rk_clrsetreg(&cru->clksel_con[25],
PCLK_PERILP1_DIV_CON_MASK | HCLK_PERILP1_DIV_CON_MASK |
HCLK_PERILP1_PLL_SEL_MASK,
pclk_div << PCLK_PERILP1_DIV_CON_SHIFT |
hclk_div << HCLK_PERILP1_DIV_CON_SHIFT |
HCLK_PERILP1_PLL_SEL_GPLL << HCLK_PERILP1_PLL_SEL_SHIFT);
}
#endif
void rk3399_configure_cpu(struct rk3399_cru *cru,
enum apll_l_frequencies apll_l_freq)
{
@ -1004,6 +926,85 @@ static struct clk_ops rk3399_clk_ops = {
.enable = rk3399_clk_enable,
};
#ifdef CONFIG_SPL_BUILD
static void rkclk_init(struct rk3399_cru *cru)
{
u32 aclk_div;
u32 hclk_div;
u32 pclk_div;
rk3399_configure_cpu(cru, APLL_L_600_MHZ);
/*
* some cru registers changed by bootrom, we'd better reset them to
* reset/default values described in TRM to avoid confusion in kernel.
* Please consider these three lines as a fix of bootrom bug.
*/
rk_clrsetreg(&cru->clksel_con[12], 0xffff, 0x4101);
rk_clrsetreg(&cru->clksel_con[19], 0xffff, 0x033f);
rk_clrsetreg(&cru->clksel_con[56], 0x0003, 0x0003);
/* configure gpll cpll */
rkclk_set_pll(&cru->gpll_con[0], &gpll_init_cfg);
rkclk_set_pll(&cru->cpll_con[0], &cpll_init_cfg);
/* configure perihp aclk, hclk, pclk */
aclk_div = GPLL_HZ / PERIHP_ACLK_HZ - 1;
assert((aclk_div + 1) * PERIHP_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
hclk_div = PERIHP_ACLK_HZ / PERIHP_HCLK_HZ - 1;
assert((hclk_div + 1) * PERIHP_HCLK_HZ ==
PERIHP_ACLK_HZ && (hclk_div < 0x4));
pclk_div = PERIHP_ACLK_HZ / PERIHP_PCLK_HZ - 1;
assert((pclk_div + 1) * PERIHP_PCLK_HZ ==
PERIHP_ACLK_HZ && (pclk_div < 0x7));
rk_clrsetreg(&cru->clksel_con[14],
PCLK_PERIHP_DIV_CON_MASK | HCLK_PERIHP_DIV_CON_MASK |
ACLK_PERIHP_PLL_SEL_MASK | ACLK_PERIHP_DIV_CON_MASK,
pclk_div << PCLK_PERIHP_DIV_CON_SHIFT |
hclk_div << HCLK_PERIHP_DIV_CON_SHIFT |
ACLK_PERIHP_PLL_SEL_GPLL << ACLK_PERIHP_PLL_SEL_SHIFT |
aclk_div << ACLK_PERIHP_DIV_CON_SHIFT);
/* configure perilp0 aclk, hclk, pclk */
aclk_div = GPLL_HZ / PERILP0_ACLK_HZ - 1;
assert((aclk_div + 1) * PERILP0_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
hclk_div = PERILP0_ACLK_HZ / PERILP0_HCLK_HZ - 1;
assert((hclk_div + 1) * PERILP0_HCLK_HZ ==
PERILP0_ACLK_HZ && (hclk_div < 0x4));
pclk_div = PERILP0_ACLK_HZ / PERILP0_PCLK_HZ - 1;
assert((pclk_div + 1) * PERILP0_PCLK_HZ ==
PERILP0_ACLK_HZ && (pclk_div < 0x7));
rk_clrsetreg(&cru->clksel_con[23],
PCLK_PERILP0_DIV_CON_MASK | HCLK_PERILP0_DIV_CON_MASK |
ACLK_PERILP0_PLL_SEL_MASK | ACLK_PERILP0_DIV_CON_MASK,
pclk_div << PCLK_PERILP0_DIV_CON_SHIFT |
hclk_div << HCLK_PERILP0_DIV_CON_SHIFT |
ACLK_PERILP0_PLL_SEL_GPLL << ACLK_PERILP0_PLL_SEL_SHIFT |
aclk_div << ACLK_PERILP0_DIV_CON_SHIFT);
/* perilp1 hclk select gpll as source */
hclk_div = GPLL_HZ / PERILP1_HCLK_HZ - 1;
assert((hclk_div + 1) * PERILP1_HCLK_HZ ==
GPLL_HZ && (hclk_div < 0x1f));
pclk_div = PERILP1_HCLK_HZ / PERILP1_HCLK_HZ - 1;
assert((pclk_div + 1) * PERILP1_HCLK_HZ ==
PERILP1_HCLK_HZ && (hclk_div < 0x7));
rk_clrsetreg(&cru->clksel_con[25],
PCLK_PERILP1_DIV_CON_MASK | HCLK_PERILP1_DIV_CON_MASK |
HCLK_PERILP1_PLL_SEL_MASK,
pclk_div << PCLK_PERILP1_DIV_CON_SHIFT |
hclk_div << HCLK_PERILP1_DIV_CON_SHIFT |
HCLK_PERILP1_PLL_SEL_GPLL << HCLK_PERILP1_PLL_SEL_SHIFT);
}
#endif
static int rk3399_clk_probe(struct udevice *dev)
{
#ifdef CONFIG_SPL_BUILD

6
include/configs/evb_rk3328.h
View file

@ -10,12 +10,6 @@
#include <configs/rk3328_common.h>
#define CONFIG_SYS_MMC_ENV_DEV 1
/*
* SPL @ 32k for ~36k
* ENV @ 96k
* u-boot @ 128K
*/
#define CONFIG_ENV_OFFSET (96 * 1024)
#define SDRAM_BANK_SIZE (2UL << 30)

6
include/configs/rk3368_common.h
View file

@ -7,6 +7,8 @@
#ifndef __CONFIG_RK3368_COMMON_H
#define __CONFIG_RK3368_COMMON_H
#include "rockchip-common.h"
#define CONFIG_SYS_CACHELINE_SIZE 64
#include <asm/arch/hardware.h>
@ -44,10 +46,6 @@
"kernel_addr_r=0x280000\0" \
"ramdisk_addr_r=0x5bf0000\0"
#include <config_distro_defaults.h>
#define BOOT_TARGET_DEVICES(func)
#include <config_distro_bootcmd.h>
#define CONFIG_EXTRA_ENV_SETTINGS \

43
include/configs/rockchip-common.h
View file

@ -11,22 +11,39 @@
#ifndef CONFIG_SPL_BUILD
#include <config_distro_defaults.h>
/* First try to boot from SD (index 0), then eMMC (index 1 */
#ifdef CONFIG_CMD_USB
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0) \
func(MMC, mmc, 1) \
func(USB, usb, 0) \
func(PXE, pxe, na) \
func(DHCP, dchp, na)
/* First try to boot from SD (index 0), then eMMC (index 1) */
#if CONFIG_IS_ENABLED(CMD_MMC)
#define BOOT_TARGET_MMC(func) \
func(MMC, mmc, 0) \
func(MMC, mmc, 1)
#else
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0) \
func(MMC, mmc, 1) \
func(PXE, pxe, na) \
func(DHCP, dchp, na)
#define BOOT_TARGET_MMC(func)
#endif
#if CONFIG_IS_ENABLED(CMD_USB)
#define BOOT_TARGET_USB(func) func(USB, usb, 0)
#else
#define BOOT_TARGET_USB(func)
#endif
#if CONFIG_IS_ENABLED(CMD_PXE)
#define BOOT_TARGET_PXE(func) func(PXE, pxe, na)
#else
#define BOOT_TARGET_PXE(func)
#endif
#if CONFIG_IS_ENABLED(CMD_DHCP)
#define BOOT_TARGET_DHCP(func) func(DHCP, dhcp, na)
#else
#define BOOT_TARGET_DHCP(func)
#endif
#define BOOT_TARGET_DEVICES(func) \
BOOT_TARGET_MMC(func) \
BOOT_TARGET_USB(func) \
BOOT_TARGET_PXE(func) \
BOOT_TARGET_DHCP(func)
#ifdef CONFIG_ARM64
#define ROOT_UUID "B921B045-1DF0-41C3-AF44-4C6F280D3FAE;\0"
#else