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net: dwc_eth_qos: add Kconfig option to select supported configuration

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Add configuration flag to select the supported dwc driver configuration:
- CONFIG_DWC_ETH_QOS_TEGRA186
- CONFIG_DWC_ETH_QOS_IMX
- CONFIG_DWC_ETH_QOS_STM32

See Linux driver ethernet/stmicro/stmmac and associated glue layers
for other configuration examples.

This patch removes the not-selected compatibles and lets the linker remove
the unused functions to reduce the size of the driver.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
This commit is contained in:
Patrick Delaunay 2020-06-08 11:27:19 +02:00 committed by Tom Rini
parent 9996cea75f
commit a08f2f7b94
2 changed files with 33 additions and 6 deletions
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27
drivers/net/Kconfig
View file

@ -156,9 +156,30 @@ config DWC_ETH_QOS
help
This driver supports the Synopsys Designware Ethernet QOS (Quality
Of Service) IP block. The IP supports many options for bus type,
clocking/reset structure, and feature list. This driver currently
supports the specific configuration used in NVIDIA's Tegra186 chip,
but should be extensible to other combinations quite easily.
clocking/reset structure, and feature list.
config DWC_ETH_QOS_IMX
bool "Synopsys DWC Ethernet QOS device support for IMX"
depends on DWC_ETH_QOS
help
The Synopsys Designware Ethernet QOS IP block with the specific
configuration used in IMX soc.
config DWC_ETH_QOS_STM32
bool "Synopsys DWC Ethernet QOS device support for STM32"
depends on DWC_ETH_QOS
default y if ARCH_STM32MP
help
The Synopsys Designware Ethernet QOS IP block with the specific
configuration used in STM32MP soc.
config DWC_ETH_QOS_TEGRA186
bool "Synopsys DWC Ethernet QOS device support for TEGRA186"
depends on DWC_ETH_QOS
default y if TEGRA186
help
The Synopsys Designware Ethernet QOS IP block with specific
configuration used in NVIDIA's Tegra186 chip.
config E1000
bool "Intel PRO/1000 Gigabit Ethernet support"

12
drivers/net/dwc_eth_qos.c
View file

@ -2100,7 +2100,7 @@ static struct eqos_ops eqos_tegra186_ops = {
.eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_tegra186
};
static const struct eqos_config eqos_tegra186_config = {
static const struct eqos_config __maybe_unused eqos_tegra186_config = {
.reg_access_always_ok = false,
.mdio_wait = 10,
.swr_wait = 10,
@ -2127,7 +2127,7 @@ static struct eqos_ops eqos_stm32_ops = {
.eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_stm32
};
static const struct eqos_config eqos_stm32_config = {
static const struct eqos_config __maybe_unused eqos_stm32_config = {
.reg_access_always_ok = false,
.mdio_wait = 10000,
.swr_wait = 50,
@ -2154,7 +2154,7 @@ static struct eqos_ops eqos_imx_ops = {
.eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_imx
};
struct eqos_config eqos_imx_config = {
struct eqos_config __maybe_unused eqos_imx_config = {
.reg_access_always_ok = false,
.mdio_wait = 10000,
.swr_wait = 50,
@ -2165,18 +2165,24 @@ struct eqos_config eqos_imx_config = {
};
static const struct udevice_id eqos_ids[] = {
#if IS_ENABLED(CONFIG_DWC_ETH_QOS_TEGRA186)
{
.compatible = "nvidia,tegra186-eqos",
.data = (ulong)&eqos_tegra186_config
},
#endif
#if IS_ENABLED(CONFIG_DWC_ETH_QOS_STM32)
{
.compatible = "st,stm32mp1-dwmac",
.data = (ulong)&eqos_stm32_config
},
#endif
#if IS_ENABLED(CONFIG_DWC_ETH_QOS_IMX)
{
.compatible = "fsl,imx-eqos",
.data = (ulong)&eqos_imx_config
},
#endif
{ }
};