mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-28 15:41:40 +00:00
ColdFire: Implement SBF feature for M5445EVB
Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
This commit is contained in:
TsiChung Liew
John Rigby
parent
a7323bba22
commit
9f75155145
7 changed files with 538 additions and 45 deletions
16
Makefile
16
Makefile
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@ -1913,7 +1913,8 @@ M54455EVB_intel_config \
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M54455EVB_a33_config \
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M54455EVB_a66_config \
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M54455EVB_i33_config \
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M54455EVB_i66_config : unconfig
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M54455EVB_i66_config \
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M54455EVB_stm33_config : unconfig
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@case "$@" in \
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M54455EVB_config) FLASH=ATMEL; FREQ=33333333;; \
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M54455EVB_atmel_config) FLASH=ATMEL; FREQ=33333333;; \
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@ -1922,18 +1923,27 @@ M54455EVB_i66_config : unconfig
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M54455EVB_a66_config) FLASH=ATMEL; FREQ=66666666;; \
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M54455EVB_i33_config) FLASH=INTEL; FREQ=33333333;; \
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M54455EVB_i66_config) FLASH=INTEL; FREQ=66666666;; \
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M54455EVB_stm33_config) FLASH=STMICRO; FREQ=33333333;; \
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esac; \
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if [ "$${FLASH}" = "INTEL" ] ; then \
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echo "#undef CFG_ATMEL_BOOT" >> $(obj)include/config.h ; \
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echo "#define CFG_INTEL_BOOT" >> $(obj)include/config.h ; \
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echo "TEXT_BASE = 0x00000000" > $(obj)board/freescale/m54455evb/config.tmp ; \
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cp $(obj)board/freescale/m54455evb/u-boot.int $(obj)board/freescale/m54455evb/u-boot.lds ; \
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$(XECHO) "... with INTEL boot..." ; \
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else \
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fi; \
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if [ "$${FLASH}" = "ATMEL" ] ; then \
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echo "#define CFG_ATMEL_BOOT" >> $(obj)include/config.h ; \
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echo "TEXT_BASE = 0x04000000" > $(obj)board/freescale/m54455evb/config.tmp ; \
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cp $(obj)board/freescale/m54455evb/u-boot.atm $(obj)board/freescale/m54455evb/u-boot.lds ; \
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$(XECHO) "... with ATMEL boot..." ; \
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fi; \
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if [ "$${FLASH}" = "STMICRO" ] ; then \
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echo "#define CONFIG_CF_SBF" >> $(obj)include/config.h ; \
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echo "#define CFG_STMICRO_BOOT" >> $(obj)include/config.h ; \
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echo "TEXT_BASE = 0x4FE00000" > $(obj)board/freescale/m54455evb/config.tmp ; \
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cp $(obj)board/freescale/m54455evb/u-boot.stm $(obj)board/freescale/m54455evb/u-boot.lds ; \
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$(XECHO) "... with ST Micro boot..." ; \
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fi; \
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echo "#define CFG_INPUT_CLKSRC $${FREQ}" >> $(obj)include/config.h ; \
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$(XECHO) "... with $${FREQ}Hz input clock"
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@$(MKCONFIG) -a M54455EVB m68k mcf5445x m54455evb freescale
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@ -39,9 +39,17 @@ int checkboard(void)
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phys_size_t initdram(int board_type)
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{
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u32 dramsize;
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#ifdef CONFIG_CF_SBF
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/*
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* Serial Boot: The dram is already initialized in start.S
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* only require to return DRAM size
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*/
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dramsize = CFG_SDRAM_SIZE * 0x100000 >> 1;
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#else
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volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM);
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volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO);
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u32 dramsize, i;
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u32 i;
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dramsize = CFG_SDRAM_SIZE * 0x100000 >> 1;
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@ -51,7 +59,7 @@ phys_size_t initdram(int board_type)
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}
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i--;
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gpio->mscr_sdram = 0xAA;
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gpio->mscr_sdram = CFG_SDRAM_DRV_STRENGTH;
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sdram->sdcs0 = (CFG_SDRAM_BASE | i);
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sdram->sdcs1 = (CFG_SDRAM_BASE1 | i);
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@ -80,7 +88,7 @@ phys_size_t initdram(int board_type)
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sdram->sdcr = (CFG_SDRAM_CTRL & ~0x80000000) | 0x10000c00;
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udelay(100);
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#endif
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return (dramsize << 1);
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};
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136
board/freescale/m54455evb/u-boot.stm
Normal file
136
board/freescale/m54455evb/u-boot.stm
Normal file
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@ -0,0 +1,136 @@
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/*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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OUTPUT_ARCH(m68k)
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/* Do we need any of these for elf?
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__DYNAMIC = 0; */
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SECTIONS
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{
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/* Read-only sections, merged into text segment: */
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. = + SIZEOF_HEADERS;
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.interp : { *(.interp) }
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.hash : { *(.hash) }
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.dynsym : { *(.dynsym) }
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.dynstr : { *(.dynstr) }
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.rel.text : { *(.rel.text) }
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.rela.text : { *(.rela.text) }
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.rel.data : { *(.rel.data) }
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.rela.data : { *(.rela.data) }
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.rel.rodata : { *(.rel.rodata) }
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.rela.rodata : { *(.rela.rodata) }
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.rel.got : { *(.rel.got) }
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.rela.got : { *(.rela.got) }
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.rel.ctors : { *(.rel.ctors) }
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.rela.ctors : { *(.rela.ctors) }
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.rel.dtors : { *(.rel.dtors) }
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.rela.dtors : { *(.rela.dtors) }
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.rel.bss : { *(.rel.bss) }
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.rela.bss : { *(.rela.bss) }
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.rel.plt : { *(.rel.plt) }
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.rela.plt : { *(.rela.plt) }
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.init : { *(.init) }
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.plt : { *(.plt) }
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.text :
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{
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/* WARNING - the following is hand-optimized to fit within */
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/* the sector layout of our flash chips! XXX FIXME XXX */
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cpu/mcf5445x/start.o (.text)
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*(.text)
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*(.fixup)
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*(.got1)
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}
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_etext = .;
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PROVIDE (etext = .);
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.rodata :
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{
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*(.rodata)
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*(.rodata1)
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}
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.fini : { *(.fini) } =0
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.ctors : { *(.ctors) }
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.dtors : { *(.dtors) }
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/* Read-write section, merged into data segment: */
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. = (. + 0x00FF) & 0xFFFFFF00;
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_erotext = .;
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PROVIDE (erotext = .);
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.reloc :
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{
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__got_start = .;
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*(.got)
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__got_end = .;
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_GOT2_TABLE_ = .;
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*(.got2)
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_FIXUP_TABLE_ = .;
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*(.fixup)
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}
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__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
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__fixup_entries = (. - _FIXUP_TABLE_)>>2;
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.data :
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{
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*(.data)
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*(.data1)
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*(.sdata)
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*(.sdata2)
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*(.dynamic)
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CONSTRUCTORS
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}
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_edata = .;
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PROVIDE (edata = .);
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. = .;
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__u_boot_cmd_start = .;
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.u_boot_cmd : { *(.u_boot_cmd) }
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__u_boot_cmd_end = .;
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. = .;
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__start___ex_table = .;
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__ex_table : { *(__ex_table) }
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__stop___ex_table = .;
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. = ALIGN(256);
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__init_begin = .;
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.text.init : { *(.text.init) }
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.data.init : { *(.data.init) }
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. = ALIGN(256);
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__init_end = .;
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__bss_start = .;
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.bss :
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{
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_sbss = .;
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*(.sbss) *(.scommon)
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*(.dynbss)
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*(.bss)
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*(COMMON)
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. = ALIGN(4);
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_ebss = .;
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}
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_end = . ;
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PROVIDE (end = .);
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}
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@ -61,11 +61,13 @@ void cpu_init_f(void)
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GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA | GPIO_PAR_FBCTL_RW_RW |
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GPIO_PAR_FBCTL_TS_TS;
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#if !defined(CONFIG_CF_SBF)
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#if (defined(CFG_CS0_BASE) && defined(CFG_CS0_MASK) && defined(CFG_CS0_CTRL))
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fbcs->csar0 = CFG_CS0_BASE;
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fbcs->cscr0 = CFG_CS0_CTRL;
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fbcs->csmr0 = CFG_CS0_MASK;
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#endif
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#endif
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#if (defined(CFG_CS1_BASE) && defined(CFG_CS1_MASK) && defined(CFG_CS1_CTRL))
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/* Latch chipselect */
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@ -84,26 +84,29 @@ void clock_exit_limp(void)
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*/
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int get_clocks(void)
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{
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volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM;
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volatile pll_t *pll = (volatile pll_t *)MMAP_PLL;
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volatile u8 *cpld = (volatile u8 *)(CFG_CS2_BASE + 3);
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volatile u8 *fpga = (volatile u8 *)(CFG_CS3_BASE + 14);
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int pllmult_nopci[] = { 20, 10, 24, 18, 12, 6, 16, 8 };
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int pllmult_pci[] = { 12, 6, 16, 8 };
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int vco, bPci, temp, fbtemp, pcrvalue;
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int vco = 0, bPci, temp, fbtemp, pcrvalue;
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int *pPllmult = NULL;
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u16 fbpll_mask;
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u8 cpldmode;
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#ifdef CONFIG_M54455EVB
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volatile u8 *cpld = (volatile u8 *)(CFG_CS2_BASE + 3);
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#endif
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u8 bootmode;
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/* To determine PCI is present or not */
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if (((ccm->ccr & CCM_CCR_360_FBCONFIG_MASK) == 0x00e0) ||
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((ccm->ccr & CCM_CCR_360_FBCONFIG_MASK) == 0x0060)) {
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pPllmult = &pllmult_pci[0];
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fbpll_mask = 3;
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fbpll_mask = 3; /* 11b */
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bPci = 1;
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} else {
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pPllmult = &pllmult_nopci[0];
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fbpll_mask = 7;
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fbpll_mask = 7; /* 111b */
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#ifdef CONFIG_PCI
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gd->pci_clk = 0;
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#endif
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@ -111,7 +114,9 @@ int get_clocks(void)
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}
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#ifdef CONFIG_M54455EVB
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/* Temporary place here, belongs in board/freescale/... */
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bootmode = (*cpld & 0x03);
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if (bootmode != 3) {
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/* Temporary read from CCR- fixed fb issue, must be the same clock
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as pci or input clock, causing cpld/fpga read inconsistancy */
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fbtemp = pPllmult[ccm->ccr & fbpll_mask];
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@ -122,9 +127,23 @@ int get_clocks(void)
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pcrvalue |= PLL_PCR_OUTDIV3(temp);
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pll->pcr = pcrvalue;
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}
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#endif
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#ifdef CONFIG_M54451EVB
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/* No external logic to read the bootmode, hard coded from built */
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#ifdef CONFIG_CF_SBF
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bootmode = 3;
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#else
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bootmode = 2;
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cpldmode = *cpld & 0x03;
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if (cpldmode == 0) {
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/* default value is 16 mul, set to 20 mul */
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pcrvalue = (pll->pcr & 0x00FFFFFF) | 0x14000000;
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pll->pcr = pcrvalue;
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while ((pll->psr & PLL_PSR_LOCK) != PLL_PSR_LOCK);
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#endif
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#endif
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if (bootmode == 0) {
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/* RCON mode */
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vco = pPllmult[ccm->rcon & fbpll_mask] * CFG_INPUT_CLKSRC;
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@ -151,14 +170,22 @@ int get_clocks(void)
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pll->pcr = pcrvalue;
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}
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gd->vco_clk = vco; /* Vco clock */
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} else if (cpldmode == 2) {
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} else if (bootmode == 2) {
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/* Normal mode */
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vco = pPllmult[ccm->ccr & fbpll_mask] * CFG_INPUT_CLKSRC;
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gd->vco_clk = vco; /* Vco clock */
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} else if (cpldmode == 3) {
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/* serial mode */
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vco = ((pll->pcr & 0xFF000000) >> 24) * CFG_INPUT_CLKSRC;
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if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
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/* Default value */
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pcrvalue = (pll->pcr & 0x00FFFFFF);
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pcrvalue |= pPllmult[ccm->ccr & fbpll_mask] << 24;
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pll->pcr = pcrvalue;
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vco = ((pll->pcr & 0xFF000000) >> 24) * CFG_INPUT_CLKSRC;
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}
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gd->vco_clk = vco; /* Vco clock */
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} else if (bootmode == 3) {
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/* serial mode */
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vco = ((pll->pcr & 0xFF000000) >> 24) * CFG_INPUT_CLKSRC;
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gd->vco_clk = vco; /* Vco clock */
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}
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#endif /* CONFIG_M54455EVB */
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if ((ccm->ccr & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) {
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/* Limp mode */
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@ -46,15 +46,30 @@
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addl #60,%sp; /* space for 15 regs */ \
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rte;
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#if defined(CONFIG_CF_SBF)
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#define ASM_DRAMINIT (asm_dram_init - TEXT_BASE + CFG_INIT_RAM_ADDR)
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#define ASM_SBF_IMG_HDR (asm_sbf_img_hdr - TEXT_BASE + CFG_INIT_RAM_ADDR)
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#endif
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.text
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/*
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* Vector table. This is used for initial platform startup.
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* These vectors are to catch any un-intended traps.
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*/
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_vectors:
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#if defined(CONFIG_CF_SBF)
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INITSP: .long 0x00000000 /* Initial SP */
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INITSP: .long 0 /* Initial SP */
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INITPC: .long ASM_DRAMINIT /* Initial PC */
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#else
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INITSP: .long 0 /* Initial SP */
|
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INITPC: .long _START /* Initial PC */
|
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#endif
|
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vector02: .long _FAULT /* Access Error */
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vector03: .long _FAULT /* Address Error */
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vector04: .long _FAULT /* Illegal Instruction */
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@ -83,6 +98,8 @@ vector1D: .long _FAULT /* Autovector Level 5 */
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vector1E: .long _FAULT /* Autovector Level 6 */
|
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vector1F: .long _FAULT /* Autovector Level 7 */
|
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#if !defined(CONFIG_CF_SBF)
|
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|
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/* TRAP #0 - #15 */
|
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vector20_2F:
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.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
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|
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@ -122,9 +139,237 @@ vector192_255:
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.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
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.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
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.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
|
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#endif
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#if defined(CONFIG_CF_SBF)
|
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/* Image header: chksum 4 bytes, len 4 bytes, img dest 4 bytes */
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asm_sbf_img_hdr:
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.long 0x00000000 /* checksum, not yet implemented */
|
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.long 0x00030000 /* image length */
|
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.long TEXT_BASE /* image to be relocated at */
|
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|
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asm_dram_init:
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move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_RAM_CTRL), %d0
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movec %d0, %RAMBAR1 /* init Rambar */
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move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp
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clr.l %sp@-
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/* Must disable global address */
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move.l #0xFC008000, %a1
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move.l #(CFG_CS0_BASE), (%a1)
|
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move.l #0xFC008008, %a1
|
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move.l #(CFG_CS0_CTRL), (%a1)
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move.l #0xFC008004, %a1
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move.l #(CFG_CS0_MASK), (%a1)
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/*
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* Dram Initialization
|
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* a1, a2, and d0
|
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*/
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/* mscr sdram */
|
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move.l #0xFC0A4074, %a1
|
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move.b #(CFG_SDRAM_DRV_STRENGTH), (%a1)
|
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nop
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/* SDRAM Chip 0 and 1 */
|
||||
move.l #0xFC0B8110, %a1
|
||||
move.l #0xFC0B8114, %a2
|
||||
|
||||
/* calculate the size */
|
||||
move.l #0x13, %d1
|
||||
move.l #(CFG_SDRAM_SIZE), %d2
|
||||
#ifdef CFG_SDRAM_BASE1
|
||||
lsr.l #1, %d2
|
||||
#endif
|
||||
|
||||
dramsz_loop:
|
||||
lsr.l #1, %d2
|
||||
add.l #1, %d1
|
||||
cmp.l #1, %d2
|
||||
bne dramsz_loop
|
||||
|
||||
/* SDRAM Chip 0 and 1 */
|
||||
move.l #(CFG_SDRAM_BASE), (%a1)
|
||||
or.l %d1, (%a1)
|
||||
#ifdef CFG_SDRAM_BASE1
|
||||
move.l #(CFG_SDRAM_BASE1), (%a2)
|
||||
or.l %d1, (%a2)
|
||||
#endif
|
||||
nop
|
||||
|
||||
/* dram cfg1 and cfg2 */
|
||||
move.l #0xFC0B8008, %a1
|
||||
move.l #(CFG_SDRAM_CFG1), (%a1)
|
||||
nop
|
||||
move.l #0xFC0B800C, %a2
|
||||
move.l #(CFG_SDRAM_CFG2), (%a2)
|
||||
nop
|
||||
|
||||
move.l #0xFC0B8000, %a1 /* Mode */
|
||||
move.l #0xFC0B8004, %a2 /* Ctrl */
|
||||
|
||||
#ifdef CONFIG_M54455EVB
|
||||
/* Issue PALL */
|
||||
move.l #(CFG_SDRAM_CTRL + 2), (%a2)
|
||||
nop
|
||||
|
||||
/* Issue LEMR */
|
||||
move.l #(CFG_SDRAM_EMOD + 0x408), (%a1)
|
||||
nop
|
||||
move.l #(CFG_SDRAM_MODE + 0x300), (%a1)
|
||||
nop
|
||||
|
||||
move.l #1000, %d0
|
||||
wait1000:
|
||||
nop
|
||||
subq.l #1, %d0
|
||||
bne wait1000
|
||||
#endif
|
||||
|
||||
/* Issue PALL */
|
||||
move.l #(CFG_SDRAM_CTRL + 2), (%a2)
|
||||
nop
|
||||
|
||||
/* Perform two refresh cycles */
|
||||
move.l #(CFG_SDRAM_CTRL + 4), %d0
|
||||
nop
|
||||
move.l %d0, (%a2)
|
||||
move.l %d0, (%a2)
|
||||
nop
|
||||
|
||||
#ifdef CONFIG_M54455EVB
|
||||
move.l #(CFG_SDRAM_MODE + 0x200), (%a1)
|
||||
nop
|
||||
#elif defined(CONFIG_M54451EVB)
|
||||
/* Issue LEMR */
|
||||
move.l #(CFG_SDRAM_MODE), (%a2)
|
||||
nop
|
||||
move.l #(CFG_SDRAM_EMOD), (%a2)
|
||||
nop
|
||||
#endif
|
||||
|
||||
move.l #500, %d0
|
||||
wait500:
|
||||
nop
|
||||
subq.l #1, %d0
|
||||
bne wait500
|
||||
|
||||
move.l #(CFG_SDRAM_CTRL), %d0
|
||||
and.l #0x7FFFFFFF, %d0
|
||||
#ifdef CONFIG_M54455EVB
|
||||
or.l #0x10000c00, %d0
|
||||
#elif defined(CONFIG_M54451EVB)
|
||||
or.l #0x10000000, %d0
|
||||
#endif
|
||||
move.l %d0, (%a2)
|
||||
nop
|
||||
|
||||
/*
|
||||
* DSPI Initialization
|
||||
* a0 - general, sram - 0x80008000 - 32, see M54455EVB.h
|
||||
* a1 - dspi status
|
||||
* a2 - dtfr
|
||||
* a3 - drfr
|
||||
* a4 - Dst addr
|
||||
*/
|
||||
/* Enable pins for DSPI mode - chip-selects are enabled later */
|
||||
move.l #0xFC0A4063, %a0
|
||||
move.b #0x7F, (%a0)
|
||||
|
||||
/* Configure DSPI module */
|
||||
move.l #0xFC05C000, %a0
|
||||
move.l #0x80FF0C00, (%a0) /* Master, clear TX/RX FIFO */
|
||||
|
||||
move.l #0xFC05C00C, %a0
|
||||
move.l #0x3E000011, (%a0)
|
||||
|
||||
move.l #0xFC05C034, %a2 /* dtfr */
|
||||
move.l #0xFC05C03B, %a3 /* drfr */
|
||||
|
||||
move.l #(ASM_SBF_IMG_HDR + 4), %a1
|
||||
move.l (%a1)+, %d5
|
||||
move.l (%a1), %a4
|
||||
|
||||
move.l #(CFG_INIT_RAM_ADDR + CFG_SBFHDR_DATA_OFFSET), %a0
|
||||
move.l #(CFG_SBFHDR_SIZE), %d4
|
||||
|
||||
move.l #0xFC05C02C, %a1 /* dspi status */
|
||||
|
||||
/* Issue commands and address */
|
||||
move.l #0x8002000B, %d2 /* Fast Read Cmd */
|
||||
jsr asm_dspi_wr_status
|
||||
jsr asm_dspi_rd_status
|
||||
|
||||
move.l #0x80020000, %d2 /* Address byte 2 */
|
||||
jsr asm_dspi_wr_status
|
||||
jsr asm_dspi_rd_status
|
||||
|
||||
move.l #0x80020000, %d2 /* Address byte 1 */
|
||||
jsr asm_dspi_wr_status
|
||||
jsr asm_dspi_rd_status
|
||||
|
||||
move.l #0x80020000, %d2 /* Address byte 0 */
|
||||
jsr asm_dspi_wr_status
|
||||
jsr asm_dspi_rd_status
|
||||
|
||||
move.l #0x80020000, %d2 /* Dummy Wr and Rd */
|
||||
jsr asm_dspi_wr_status
|
||||
jsr asm_dspi_rd_status
|
||||
|
||||
/* Transfer serial boot header to sram */
|
||||
asm_dspi_rd_loop1:
|
||||
move.l #0x80020000, %d2
|
||||
jsr asm_dspi_wr_status
|
||||
jsr asm_dspi_rd_status
|
||||
|
||||
move.b %d1, (%a0) /* read, copy to dst */
|
||||
|
||||
add.l #1, %a0 /* inc dst by 1 */
|
||||
sub.l #1, %d4 /* dec cnt by 1 */
|
||||
bne asm_dspi_rd_loop1
|
||||
|
||||
/* Transfer u-boot from serial flash to memory */
|
||||
asm_dspi_rd_loop2:
|
||||
move.l #0x80020000, %d2
|
||||
jsr asm_dspi_wr_status
|
||||
jsr asm_dspi_rd_status
|
||||
|
||||
move.b %d1, (%a4) /* read, copy to dst */
|
||||
|
||||
add.l #1, %a4 /* inc dst by 1 */
|
||||
sub.l #1, %d5 /* dec cnt by 1 */
|
||||
bne asm_dspi_rd_loop2
|
||||
|
||||
move.l #0x00020000, %d2 /* Terminate */
|
||||
jsr asm_dspi_wr_status
|
||||
jsr asm_dspi_rd_status
|
||||
|
||||
/* jump to memory and execute */
|
||||
move.l #(TEXT_BASE + 0x400), %a0
|
||||
jmp (%a0)
|
||||
|
||||
asm_dspi_wr_status:
|
||||
move.l (%a1), %d0 /* status */
|
||||
and.l #0x0000F000, %d0
|
||||
cmp.l #0x00003000, %d0
|
||||
bgt asm_dspi_wr_status
|
||||
|
||||
move.l %d2, (%a2)
|
||||
rts
|
||||
|
||||
asm_dspi_rd_status:
|
||||
move.l (%a1), %d0 /* status */
|
||||
and.l #0x000000F0, %d0
|
||||
lsr.l #4, %d0
|
||||
cmp.l #0, %d0
|
||||
beq asm_dspi_rd_status
|
||||
|
||||
move.b (%a3), %d1
|
||||
rts
|
||||
#endif /* CONFIG_CF_SBF */
|
||||
|
||||
.text
|
||||
|
||||
. = 0x400
|
||||
.globl _start
|
||||
_start:
|
||||
nop
|
||||
|
|
@ -132,11 +377,16 @@ _start:
|
|||
move.w #0x2700,%sr /* Mask off Interrupt */
|
||||
|
||||
/* Set vector base register at the beginning of the Flash */
|
||||
#if defined(CONFIG_CF_SBF)
|
||||
move.l #TEXT_BASE, %d0
|
||||
movec %d0, %VBR
|
||||
#else
|
||||
move.l #CFG_FLASH_BASE, %d0
|
||||
movec %d0, %VBR
|
||||
|
||||
move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_RAM_CTRL), %d0
|
||||
movec %d0, %RAMBAR1
|
||||
#endif
|
||||
|
||||
/* initialize general use internal ram */
|
||||
move.l #0, %d0
|
||||
|
|
|
|||
|
|
@ -121,18 +121,45 @@
|
|||
#endif
|
||||
|
||||
#define CONFIG_HOSTNAME M54455EVB
|
||||
#ifdef CFG_STMICRO_BOOT
|
||||
/* ST Micro serial flash */
|
||||
#define CFG_LOAD_ADDR2 0x40010013
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"netdev=eth0\0" \
|
||||
"inpclk=" MK_STR(CFG_INPUT_CLKSRC) "\0" \
|
||||
"loadaddr=40010000\0" \
|
||||
"u-boot=u-boot.bin\0" \
|
||||
"load=tftp ${loadaddr) ${u-boot}\0" \
|
||||
"loadaddr=0x40010000\0" \
|
||||
"sbfhdr=sbfhdr.bin\0" \
|
||||
"uboot=u-boot.bin\0" \
|
||||
"load=tftp ${loadaddr} ${sbfhdr};" \
|
||||
"tftp " MK_STR(CFG_LOAD_ADDR2) " ${uboot} \0" \
|
||||
"upd=run load; run prog\0" \
|
||||
"prog=prot off 4000000 402ffff;" \
|
||||
"era 4000000 402ffff;" \
|
||||
"cp.b ${loadaddr} 0 ${filesize};" \
|
||||
"prog=sf probe 0:1 10000 1;" \
|
||||
"sf erase 0 30000;" \
|
||||
"sf write ${loadaddr} 0 0x30000;" \
|
||||
"save\0" \
|
||||
""
|
||||
#else
|
||||
/* Atmel and Intel */
|
||||
#ifdef CFG_ATMEL_BOOT
|
||||
# define CFG_UBOOT_END 0x0403FFFF
|
||||
#elif defined(CFG_INTEL_BOOT)
|
||||
# define CFG_UBOOT_END 0x3FFFF
|
||||
#endif
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"netdev=eth0\0" \
|
||||
"inpclk=" MK_STR(CFG_INPUT_CLKSRC) "\0" \
|
||||
"loadaddr=0x40010000\0" \
|
||||
"uboot=u-boot.bin\0" \
|
||||
"load=tftp ${loadaddr} ${uboot}\0" \
|
||||
"upd=run load; run prog\0" \
|
||||
"prog=prot off " MK_STR(CFG_FLASH_BASE) \
|
||||
" " MK_STR(CFG_UBOOT_END) ";" \
|
||||
"era " MK_STR(CFG_FLASH_BASE) " " \
|
||||
MK_STR(CFG_UBOOT_END) ";" \
|
||||
"cp.b ${loadaddr} " MK_STR(CFG_FLASH_BASE)\
|
||||
" ${filesize}; save\0" \
|
||||
""
|
||||
#endif
|
||||
|
||||
/* ATA configuration */
|
||||
#define CONFIG_ISO_PARTITION
|
||||
|
|
@ -175,6 +202,8 @@
|
|||
/* DSPI and Serial Flash */
|
||||
#define CONFIG_CF_DSPI
|
||||
#define CONFIG_HARD_SPI
|
||||
#define CFG_SER_FLASH_BASE 0x01000000
|
||||
#define CFG_SBFHDR_SIZE 0x13
|
||||
#ifdef CONFIG_CMD_SPI
|
||||
# define CFG_DSPI_DCTAR0 (DSPI_DCTAR_TRSZ(7) | \
|
||||
DSPI_DCTAR_CPOL | \
|
||||
|
|
@ -221,7 +250,7 @@
|
|||
/* Input, PCI, Flexbus, and VCO */
|
||||
#define CONFIG_EXTRA_CLOCK
|
||||
|
||||
#define CONFIG_PRAM 512 /* 512 KB */
|
||||
#define CONFIG_PRAM 2048 /* 2048 KB */
|
||||
|
||||
#define CFG_PROMPT "-> "
|
||||
#define CFG_LONGHELP /* undef to save memory */
|
||||
|
|
@ -254,8 +283,9 @@
|
|||
#define CFG_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */
|
||||
#define CFG_INIT_RAM_CTRL 0x221
|
||||
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
|
||||
#define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - 16)
|
||||
#define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - 32)
|
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
|
||||
#define CFG_SBFHDR_DATA_OFFSET (CFG_INIT_RAM_END - 32)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration
|
||||
|
|
@ -270,11 +300,16 @@
|
|||
#define CFG_SDRAM_CTRL 0xEA0B2000
|
||||
#define CFG_SDRAM_EMOD 0x40010000
|
||||
#define CFG_SDRAM_MODE 0x00010033
|
||||
#define CFG_SDRAM_DRV_STRENGTH 0xAA
|
||||
|
||||
#define CFG_MEMTEST_START CFG_SDRAM_BASE + 0x400
|
||||
#define CFG_MEMTEST_END ((CFG_SDRAM_SIZE - 3) << 20)
|
||||
|
||||
#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400)
|
||||
#ifdef CONFIG_CF_SBF
|
||||
# define CFG_MONITOR_BASE (TEXT_BASE + 0x400)
|
||||
#else
|
||||
# define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400)
|
||||
#endif
|
||||
#define CFG_BOOTPARAMS_LEN 64*1024
|
||||
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
|
||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
|
||||
|
|
@ -287,27 +322,44 @@
|
|||
/* Initial Memory map for Linux */
|
||||
#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
|
||||
|
||||
/* Configuration for environment
|
||||
/*
|
||||
* Configuration for environment
|
||||
* Environment is embedded in u-boot in the second sector of the flash
|
||||
*/
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
#define CONFIG_ENV_OVERWRITE 1
|
||||
#ifdef CONFIG_CF_SBF
|
||||
# define CFG_ENV_IS_IN_SPI_FLASH
|
||||
# define CFG_ENV_SPI_CS 1
|
||||
#else
|
||||
# define CFG_ENV_IS_IN_FLASH 1
|
||||
#endif
|
||||
#undef CONFIG_ENV_OVERWRITE
|
||||
#undef CFG_ENV_IS_EMBEDDED
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization
|
||||
*/
|
||||
#ifdef CFG_STMICRO_BOOT
|
||||
# define CFG_FLASH_BASE CFG_SER_FLASH_BASE
|
||||
# define CFG_FLASH0_BASE CFG_SER_FLASH_BASE
|
||||
# define CFG_FLASH1_BASE CFG_CS0_BASE
|
||||
# define CFG_FLASH2_BASE CFG_CS1_BASE
|
||||
# define CFG_ENV_OFFSET 0x30000
|
||||
# define CFG_ENV_SIZE 0x2000
|
||||
# define CFG_ENV_SECT_SIZE 0x10000
|
||||
#endif
|
||||
#ifdef CFG_ATMEL_BOOT
|
||||
# define CFG_FLASH_BASE CFG_CS0_BASE
|
||||
# define CFG_FLASH0_BASE CFG_CS0_BASE
|
||||
# define CFG_FLASH1_BASE CFG_CS1_BASE
|
||||
# define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x4000)
|
||||
# define CFG_ENV_SECT_SIZE 0x2000
|
||||
#else
|
||||
#endif
|
||||
#ifdef CFG_INTEL_BOOT
|
||||
# define CFG_FLASH_BASE CFG_CS0_BASE
|
||||
# define CFG_FLASH0_BASE CFG_CS0_BASE
|
||||
# define CFG_FLASH1_BASE CFG_CS1_BASE
|
||||
# define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x60000)
|
||||
# define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x40000)
|
||||
# define CFG_ENV_SIZE 0x2000
|
||||
# define CFG_ENV_SECT_SIZE 0x20000
|
||||
#endif
|
||||
|
||||
|
|
@ -339,15 +391,23 @@
|
|||
* This is setting for JFFS2 support in u-boot.
|
||||
* NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
|
||||
*/
|
||||
#ifdef CONFIG_CMD_JFFS2
|
||||
#ifdef CF_STMICRO_BOOT
|
||||
# define CONFIG_JFFS2_DEV "nor1"
|
||||
# define CONFIG_JFFS2_PART_SIZE 0x01000000
|
||||
# define CONFIG_JFFS2_PART_OFFSET (CFG_FLASH2_BASE + 0x500000)
|
||||
#endif
|
||||
#ifdef CFG_ATMEL_BOOT
|
||||
# define CONFIG_JFFS2_DEV "nor1"
|
||||
# define CONFIG_JFFS2_PART_SIZE 0x01000000
|
||||
# define CONFIG_JFFS2_PART_OFFSET (CFG_FLASH1_BASE + 0x500000)
|
||||
#else
|
||||
#endif
|
||||
#ifdef CFG_INTEL_BOOT
|
||||
# define CONFIG_JFFS2_DEV "nor0"
|
||||
# define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x500000)
|
||||
# define CONFIG_JFFS2_PART_OFFSET (CFG_FLASH0_BASE + 0x500000)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration
|
||||
|
|
@ -366,7 +426,7 @@
|
|||
* CS5 - Available
|
||||
*/
|
||||
|
||||
#ifdef CFG_ATMEL_BOOT
|
||||
#if defined(CFG_ATMEL_BOOT) || defined(CFG_STMICRO_BOOT)
|
||||
/* Atmel Flash */
|
||||
#define CFG_CS0_BASE 0x04000000
|
||||
#define CFG_CS0_MASK 0x00070001
|
||||
|
|
|
|||
Loading…
Reference in a new issue