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MXC: Correct SPI_CPOL setting in SPI driver

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The handling of the SPI_CPOL bit inside the SPI
driver was wrong. As reported by the manual,
the meaning of the SSPOL inside the
configuration register is the same as reported
by SPI specification (0 if low in idle, 1 is high
on idle). The driver inverts this logic.

Because this patch sets the logic as specified, it is required
to clear the CPOL bit in the configuration file to adapt
to the correct logic.

Signed-off-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: David Jander <david.jander@protonic.nl>
This commit is contained in:
Stefano Babic 2010-08-23 20:41:19 +02:00
parent 4d0e49d336
commit 9f481e95ba
6 changed files with 11 additions and 11 deletions
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4
drivers/spi/mxc_spi.c
View file

@ -215,7 +215,7 @@ static s32 spi_cfg(struct mxc_spi_slave *mxcs, unsigned int cs,
if (mode & SPI_CS_HIGH)
ss_pol = 1;
if (!(mode & SPI_CPOL))
if (mode & SPI_CPOL)
sclkpol = 1;
if (mode & SPI_CPHA)
@ -412,7 +412,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
if (mode & SPI_CPHA)
ctrl_reg |= MXC_CSPICTRL_PHA;
if (!(mode & SPI_CPOL))
if (mode & SPI_CPOL)
ctrl_reg |= MXC_CSPICTRL_POL;
if (mode & SPI_CS_HIGH)
ctrl_reg |= MXC_CSPICTRL_SSPOL;

4
include/configs/imx31_litekit.h
View file

@ -66,13 +66,13 @@
#define CONFIG_HARD_SPI 1
#define CONFIG_MXC_SPI 1
#define CONFIG_DEFAULT_SPI_BUS 1
#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH)
#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)
#define CONFIG_FSL_PMIC
#define CONFIG_FSL_PMIC_BUS 1
#define CONFIG_FSL_PMIC_CS 0
#define CONFIG_FSL_PMIC_CLK 1000000
#define CONFIG_FSL_PMIC_MODE (SPI_MODE_2 | SPI_CS_HIGH)
#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
#define CONFIG_RTC_MC13783 1

4
include/configs/mx31ads.h
View file

@ -63,13 +63,13 @@
#define CONFIG_HARD_SPI 1
#define CONFIG_MXC_SPI 1
#define CONFIG_DEFAULT_SPI_BUS 1
#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH)
#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)
#define CONFIG_FSL_PMIC
#define CONFIG_FSL_PMIC_BUS 1
#define CONFIG_FSL_PMIC_CS 0
#define CONFIG_FSL_PMIC_CLK 1000000
#define CONFIG_FSL_PMIC_MODE (SPI_MODE_2 | SPI_CS_HIGH)
#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
#define CONFIG_RTC_MC13783 1
/* allow to overwrite serial and ethaddr */

4
include/configs/mx31pdk.h
View file

@ -67,13 +67,13 @@
#define CONFIG_HARD_SPI 1
#define CONFIG_MXC_SPI 1
#define CONFIG_DEFAULT_SPI_BUS 1
#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH)
#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)
#define CONFIG_FSL_PMIC
#define CONFIG_FSL_PMIC_BUS 1
#define CONFIG_FSL_PMIC_CS 2
#define CONFIG_FSL_PMIC_CLK 1000000
#define CONFIG_FSL_PMIC_MODE (SPI_MODE_2 | SPI_CS_HIGH)
#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
#define CONFIG_RTC_MC13783 1
/* allow to overwrite serial and ethaddr */

2
include/configs/mx51evk.h
View file

@ -73,7 +73,7 @@
#define CONFIG_FSL_PMIC_BUS 0
#define CONFIG_FSL_PMIC_CS 0
#define CONFIG_FSL_PMIC_CLK 2500000
#define CONFIG_FSL_PMIC_MODE (SPI_CPOL | SPI_CS_HIGH)
#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
/*
* MMC Configs

4
include/configs/qong.h
View file

@ -56,14 +56,14 @@
#define CONFIG_MXC_SPI
#define CONFIG_DEFAULT_SPI_BUS 1
#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH)
#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)
#define CONFIG_RTC_MC13783
#define CONFIG_FSL_PMIC
#define CONFIG_FSL_PMIC_BUS 1
#define CONFIG_FSL_PMIC_CS 0
#define CONFIG_FSL_PMIC_CLK 100000
#define CONFIG_FSL_PMIC_MODE (SPI_MODE_2 | SPI_CS_HIGH)
#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
/* FPGA */
#define CONFIG_QONG_FPGA 1