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https://github.com/AsahiLinux/u-boot
synced 2024-11-28 15:41:40 +00:00
stm32: stm32f4: move flash driver to mtd driver location
Same flash driver can be used by other stm32 families like stm32f7. Better place for this driver would be mtd driver location. Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
This commit is contained in:
parent
f9d0fd8a56
commit
9ecb0c416c
8 changed files with 59 additions and 50 deletions
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@ -82,16 +82,6 @@ struct stm32_pwr_regs {
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u32 csr;
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};
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struct stm32_flash_regs {
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u32 acr;
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u32 key;
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u32 optkeyr;
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u32 sr;
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u32 cr;
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u32 optcr;
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u32 optcr1;
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};
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/*
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* Registers access macros
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*/
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@ -104,18 +94,6 @@ struct stm32_flash_regs {
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#define STM32_PWR_BASE (STM32_APB1PERIPH_BASE + 0x7000)
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#define STM32_PWR ((struct stm32_pwr_regs *)STM32_PWR_BASE)
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#define STM32_FLASH_BASE (STM32_AHB1PERIPH_BASE + 0x3C00)
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#define STM32_FLASH ((struct stm32_flash_regs *)STM32_FLASH_BASE)
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#define STM32_FLASH_SR_BSY (1 << 16)
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#define STM32_FLASH_CR_PG (1 << 0)
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#define STM32_FLASH_CR_SER (1 << 1)
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#define STM32_FLASH_CR_STRT (1 << 16)
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#define STM32_FLASH_CR_LOCK (1 << 31)
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#define STM32_FLASH_CR_SNB_OFFSET 3
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#define STM32_FLASH_CR_SNB_MASK (15 << STM32_FLASH_CR_SNB_OFFSET)
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/*
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* Peripheral base addresses
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*/
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@ -124,6 +102,14 @@ struct stm32_flash_regs {
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#define STM32_USART3_BASE (STM32_APB1PERIPH_BASE + 0x4800)
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#define STM32_USART6_BASE (STM32_APB2PERIPH_BASE + 0x1400)
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#define FLASH_CNTL_BASE (STM32_AHB1PERIPH_BASE + 0x3C00)
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static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = {
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[0 ... 3] = 16 * 1024,
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[4] = 64 * 1024,
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[5 ... 11] = 128 * 1024
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};
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enum clock {
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CLOCK_CORE,
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CLOCK_AHB,
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@ -133,5 +119,6 @@ enum clock {
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int configure_clocks(void);
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unsigned long clock_get(enum clock clck);
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void stm32_flash_latency_cfg(int latency);
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#endif /* _MACH_STM32_H_ */
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@ -8,4 +8,4 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += soc.o clock.o timer.o flash.o
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obj-y += soc.o clock.o timer.o
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@ -66,11 +66,6 @@
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#define PWR_CR_VOS_SCALE_MODE_2 (PWR_CR_VOS1)
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#define PWR_CR_VOS_SCALE_MODE_3 (PWR_CR_VOS0)
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#define FLASH_ACR_WS(n) n
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#define FLASH_ACR_PRFTEN (1 << 8)
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#define FLASH_ACR_ICEN (1 << 9)
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#define FLASH_ACR_DCEN (1 << 10)
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/*
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* RCC GPIO specific definitions
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*/
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@ -181,10 +176,7 @@ int configure_clocks(void)
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while (!(readl(&STM32_RCC->cr) & RCC_CR_PLLRDY))
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;
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/* 5 wait states, Prefetch enabled, D-Cache enabled, I-Cache enabled */
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writel(FLASH_ACR_WS(5) | FLASH_ACR_PRFTEN | FLASH_ACR_ICEN
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| FLASH_ACR_DCEN, &STM32_FLASH->acr);
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stm32_flash_latency_cfg(5);
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clrbits_le32(&STM32_RCC->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1));
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setbits_le32(&STM32_RCC->cfgr, RCC_CFGR_SW_PLL);
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@ -20,3 +20,4 @@ obj-$(CONFIG_FTSMC020) += ftsmc020.o
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obj-$(CONFIG_FLASH_CFI_LEGACY) += jedec_flash.o
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obj-$(CONFIG_MW_EEPROM) += mw_eeprom.o
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obj-$(CONFIG_ST_SMI) += st_smi.o
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obj-$(CONFIG_STM32_FLASH) += stm32_flash.o
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@ -8,19 +8,20 @@
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/stm32.h>
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#define STM32_FLASH_KEY1 0x45670123
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#define STM32_FLASH_KEY2 0xCDEF89AB
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#include "stm32_flash.h"
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flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
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const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = {
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[0 ... 3] = 16 * 1024,
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[4] = 64 * 1024,
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[5 ... 11] = 128 * 1024
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};
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#define STM32_FLASH ((struct stm32_flash_regs *)FLASH_CNTL_BASE)
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static void stm32f4_flash_lock(u8 lock)
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void stm32_flash_latency_cfg(int latency)
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{
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/* 5 wait states, Prefetch enabled, D-Cache enabled, I-Cache enabled */
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writel(FLASH_ACR_WS(5) | FLASH_ACR_PRFTEN | FLASH_ACR_ICEN
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| FLASH_ACR_DCEN, &STM32_FLASH->acr);
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}
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static void stm32_flash_lock(u8 lock)
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{
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if (lock) {
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setbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_LOCK);
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@ -36,7 +37,7 @@ unsigned long flash_init(void)
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u8 i, j;
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for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
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flash_info[i].flash_id = FLASH_STM32F4;
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flash_info[i].flash_id = FLASH_STM32;
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flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
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flash_info[i].start[0] = CONFIG_SYS_FLASH_BASE + (i << 20);
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flash_info[i].size = sect_sz_kb[0];
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@ -58,8 +59,8 @@ void flash_print_info(flash_info_t *info)
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if (info->flash_id == FLASH_UNKNOWN) {
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printf("missing or unknown FLASH type\n");
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return;
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} else if (info->flash_id == FLASH_STM32F4) {
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printf("STM32F4 Embedded Flash\n");
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} else if (info->flash_id == FLASH_STM32) {
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printf("stm32 Embedded Flash\n");
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}
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printf(" Size: %ld MB in %d Sectors\n",
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@ -91,7 +92,7 @@ int flash_erase(flash_info_t *info, int first, int last)
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if (bank == 0xFF)
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return -1;
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stm32f4_flash_lock(0);
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stm32_flash_lock(0);
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for (i = first; i <= last; i++) {
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while (readl(&STM32_FLASH->sr) & STM32_FLASH_SR_BSY)
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@ -107,7 +108,7 @@ int flash_erase(flash_info_t *info, int first, int last)
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setbits_le32(&STM32_FLASH->cr,
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((0x10 | i) << STM32_FLASH_CR_SNB_OFFSET));
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} else {
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stm32f4_flash_lock(1);
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stm32_flash_lock(1);
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return -1;
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}
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setbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_SER);
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@ -119,7 +120,7 @@ int flash_erase(flash_info_t *info, int first, int last)
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clrbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_SER);
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}
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stm32f4_flash_lock(1);
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stm32_flash_lock(1);
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return 0;
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}
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@ -130,7 +131,7 @@ int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
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while (readl(&STM32_FLASH->sr) & STM32_FLASH_SR_BSY)
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;
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stm32f4_flash_lock(0);
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stm32_flash_lock(0);
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setbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_PG);
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/* To make things simple use byte writes only */
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@ -140,7 +141,7 @@ int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
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;
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}
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clrbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_PG);
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stm32f4_flash_lock(1);
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stm32_flash_lock(1);
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return 0;
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}
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27
drivers/mtd/stm32_flash.h
Normal file
27
drivers/mtd/stm32_flash.h
Normal file
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@ -0,0 +1,27 @@
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struct stm32_flash_regs {
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u32 acr;
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u32 key;
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u32 optkeyr;
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u32 sr;
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u32 cr;
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u32 optcr;
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u32 optcr1;
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};
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#define STM32_FLASH_KEY1 0x45670123
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#define STM32_FLASH_KEY2 0xCDEF89AB
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#define STM32_FLASH_SR_BSY (1 << 16)
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#define STM32_FLASH_CR_PG (1 << 0)
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#define STM32_FLASH_CR_SER (1 << 1)
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#define STM32_FLASH_CR_STRT (1 << 16)
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#define STM32_FLASH_CR_LOCK (1 << 31)
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#define STM32_FLASH_CR_SNB_OFFSET 3
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#define STM32_FLASH_CR_SNB_MASK (15 << STM32_FLASH_CR_SNB_OFFSET)
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/* Flash ACR: Access control register */
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#define FLASH_ACR_WS(n) n
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#define FLASH_ACR_PRFTEN (1 << 8)
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#define FLASH_ACR_ICEN (1 << 9)
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#define FLASH_ACR_DCEN (1 << 10)
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@ -47,6 +47,7 @@
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#define CONFIG_GREEN_LED 109
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#define CONFIG_STM32_GPIO
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#define CONFIG_STM32_FLASH
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#define CONFIG_STM32_SERIAL
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#define CONFIG_STM32_HSE_HZ 8000000
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@ -465,7 +465,7 @@ extern flash_info_t *flash_get_info(ulong base);
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#define FLASH_S29GL064M 0x00F0 /* Spansion S29GL064M-R6 */
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#define FLASH_S29GL128N 0x00F1 /* Spansion S29GL128N */
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#define FLASH_STM32F4 0x00F2 /* STM32F4 Embedded Flash */
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#define FLASH_STM32 0x00F2 /* STM32 Embedded Flash */
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#define FLASH_STM32F1 0x00F3 /* STM32F1 Embedded Flash */
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#define FLASH_UNKNOWN 0xFFFF /* unknown flash type */
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