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sunxi: A64: enable USB support
Mostly by adding MACH_SUN50I to some existing #ifdefs enable support for the the HCI0 USB host controller on the A64. Fix up some minor 64-bit hiccups on the way. Add the bare minimum DT bits to the A64 .dtsi and enable the controllers and the PHY on the Pine64. This is limited to the first USB controller at the moment, which is connected to the lower USB socket on the Pine64 board. [Andre: remove unneeded defines, enable OHCI, add commit message] Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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parent
06de070130
commit
9d6c9d988f
8 changed files with 56 additions and 6 deletions
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@ -79,3 +79,15 @@
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pinctrl-0 = <&i2c1_pins>;
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status = "okay";
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};
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&usbphy {
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status = "okay";
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};
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&ohci1 {
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status = "okay";
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};
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&ehci1 {
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status = "okay";
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};
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@ -653,5 +653,34 @@
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#address-cells = <1>;
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#size-cells = <0>;
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};
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usbphy: phy@1c1b810 {
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compatible = "allwinner,sun50i-a64-usb-phy",
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"allwinner,sun8i-a33-usb-phy";
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reg = <0x01c1b810 0x14>, <0x01c1b800 0x4>;
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reg-names = "phy_ctrl", "pmu1";
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status = "disabled";
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#phy-cells = <1>;
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};
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ehci1: usb@01c1b000 {
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compatible = "allwinner,sun50i-a64-ehci",
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"generic-ehci";
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reg = <0x01c1b000 0x100>;
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interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
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phys = <&usbphy 1>;
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phy-names = "usb";
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status = "disabled";
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};
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ohci1: usb@01c1b400 {
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compatible = "allwinner,sun50i-a64-ohci",
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"generic-ohci";
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reg = <0x01c1b400 0x100>;
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interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
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phys = <&usbphy 1>;
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phy-names = "usb";
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status = "enabled";
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};
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};
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};
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@ -56,7 +56,7 @@
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#define SUNXI_USB2_BASE 0x01c1c000
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#endif
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#ifdef CONFIG_SUNXI_GEN_SUN6I
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#ifdef CONFIG_MACH_SUN8I_H3
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#if defined(CONFIG_MACH_SUN8I_H3) || defined(CONFIG_MACH_SUN50I)
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#define SUNXI_USBPHY_BASE 0x01c19000
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#define SUNXI_USB0_BASE 0x01c1a000
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#define SUNXI_USB1_BASE 0x01c1b000
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@ -146,12 +146,13 @@ __maybe_unused static void usb_phy_write(struct sunxi_usb_phy *phy, int addr,
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}
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}
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#if defined CONFIG_MACH_SUN8I_H3
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#if defined(CONFIG_MACH_SUN8I_H3) || defined(CONFIG_MACH_SUN50I)
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static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy)
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{
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#if defined CONFIG_MACH_SUN8I_H3
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if (phy->id == 0)
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clrbits_le32(SUNXI_USBPHY_BASE + REG_PHY_UNK_H3, 0x01);
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#endif
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clrbits_le32(phy->base + REG_PMU_UNK_H3, 0x02);
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}
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#elif defined CONFIG_MACH_SUN8I_A83T
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@ -11,3 +11,4 @@ CONFIG_CONSOLE_MUX=y
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# CONFIG_CMD_FLASH is not set
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# CONFIG_CMD_FPGA is not set
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CONFIG_SUN8I_EMAC=y
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CONFIG_USB_EHCI_HCD=y
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@ -45,10 +45,10 @@ static int ehci_usb_probe(struct udevice *dev)
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* clocks resp. phys.
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*/
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priv->ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0;
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#ifdef CONFIG_MACH_SUN8I_H3
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#if defined(CONFIG_MACH_SUN8I_H3) || defined(CONFIG_MACH_SUN50I)
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extra_ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_OHCI0;
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#endif
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priv->phy_index = ((u32)hccr - SUNXI_USB1_BASE) / BASE_DIST;
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priv->phy_index = ((uintptr_t)hccr - SUNXI_USB1_BASE) / BASE_DIST;
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priv->ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST;
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extra_ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST;
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priv->phy_index++; /* Non otg phys start at 1 */
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@ -63,7 +63,7 @@ static int ehci_usb_probe(struct udevice *dev)
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sunxi_usb_phy_init(priv->phy_index);
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sunxi_usb_phy_power_on(priv->phy_index);
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hcor = (struct ehci_hcor *)((uint32_t)hccr +
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hcor = (struct ehci_hcor *)((uintptr_t)hccr +
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HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
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return ehci_register(dev, hccr, hcor, NULL, 0, plat->init_type);
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@ -98,6 +98,7 @@ static const struct udevice_id ehci_usb_ids[] = {
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{ .compatible = "allwinner,sun8i-a83t-ehci", },
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{ .compatible = "allwinner,sun8i-h3-ehci", },
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{ .compatible = "allwinner,sun9i-a80-ehci", },
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{ .compatible = "allwinner,sun50i-a64-ehci", },
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{ }
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};
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@ -101,6 +101,7 @@ static const struct udevice_id ohci_usb_ids[] = {
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{ .compatible = "allwinner,sun8i-a83t-ohci", },
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{ .compatible = "allwinner,sun8i-h3-ohci", },
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{ .compatible = "allwinner,sun9i-a80-ohci", },
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{ .compatible = "allwinner,sun50i-a64-ohci", },
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{ }
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};
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@ -11,6 +11,11 @@
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* A64 specific configuration
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*/
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#ifdef CONFIG_USB_EHCI
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#define CONFIG_USB_EHCI_SUNXI
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
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#endif
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#define CONFIG_SUNXI_USB_PHYS 1
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#define COUNTER_FREQUENCY CONFIG_TIMER_CLK_FREQ
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