Merge branch 'master' of git://git.denx.de/u-boot-arm

Conflicts:
	arch/arm/include/asm/mach-types.h
	common/serial.c

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

MAINTAINERS

@@ -471,6 +471,10 @@ Josef Wagner <Wagner@Microsys.de>
 	CPC45		MPC8245
 	PM520		MPC5200
 
+Michael Weiss <michael.weiss@ifm.com>
+
+	PDM360NG	MPC5121e
+
 Stephen Williams <steve@icarus.com>
 
 	JSE		PPC405GPr
@@ -866,6 +870,7 @@ Scott McNutt <smcnutt@psyent.com>
 	EP1C20		Nios-II
 	EP1S10		Nios-II
 	EP1S40		Nios-II
+	nios2-generic	Nios-II
 
 #########################################################################
 # MicroBlaze Systems:							#

MAKEALL

@@ -92,6 +92,7 @@ LIST_512x="		\
 	aria		\
 	mecp5123	\
 	mpc5121ads	\
+	pdm360ng	\
 "
 
 #########################################################################
@@ -489,7 +490,7 @@ LIST_TSEC="		\
 	${LIST_86xx}	\
 "
 
-LIST_ppc="		\
+LIST_powerpc="		\
 	${LIST_5xx}	\
 	${LIST_512x}	\
 	${LIST_5xxx}	\
@@ -505,6 +506,12 @@ LIST_ppc="		\
 	${LIST_7xx}	\
 "
 
+# Alias "ppc" -> "powerpc" to not break compatibility with older scripts
+# still using "ppc" instead of "powerpc"
+LIST_ppc="		\
+	${LIST_powerpc}	\
+"
+
 #########################################################################
 ## StrongARM Systems
 #########################################################################
@@ -826,6 +833,7 @@ LIST_nios2="		\
 	EP1S40		\
 	PCI5441		\
 	PK1C20		\
+	nios2-generic	\
 "
 
 #########################################################################
@@ -951,8 +959,8 @@ LIST_sparc="gr_xc3s_1500	gr_cpci_ax2000	gr_ep2s60	grsim	grsim_leon2"
 
 #-----------------------------------------------------------------------
 
-#----- for now, just run PPC by default -----
-[ $# = 0 ] && set $LIST_ppc
+#----- for now, just run PowerPC by default -----
+[ $# = 0 ] && set $LIST_powerpc
 
 #-----------------------------------------------------------------------
 
@@ -1008,7 +1016,7 @@ do
 	|microblaze \
 	|mips|mips_el \
 	|nios|nios2 \
-	|ppc|5xx|5xxx|512x|8xx|8220|824x|8260|83xx|85xx|86xx|4xx|7xx|74xx|TSEC \
+	|ppc|powerpc|5xx|5xxx|512x|8xx|8220|824x|8260|83xx|85xx|86xx|4xx|7xx|74xx|TSEC \
 	|sh|sh2|sh3|sh4 \
 	|sparc \
 	|x86|I486 \

README

@@ -183,7 +183,7 @@ Directory Hierarchy:
   /nios2		Files generic to Altera NIOS2 architecture
     /cpu		CPU specific files
     /lib		Architecture specific library files
-  /ppc			Files generic to PowerPC architecture
+  /powerpc		Files generic to PowerPC architecture
     /cpu		CPU specific files
       /74xx_7xx		Files specific to Freescale MPC74xx and 7xx CPUs
       /mpc5xx		Files specific to Freescale MPC5xx CPUs
@@ -1417,7 +1417,7 @@ The following options need to be configured:
 		the CPU's i2c node address).
 
 		Now, the u-boot i2c code for the mpc8xx
-		(arch/ppc/cpu/mpc8xx/i2c.c) sets the CPU up as a master node
+		(arch/powerpc/cpu/mpc8xx/i2c.c) sets the CPU up as a master node
 		and so its address should therefore be cleared to 0 (See,
 		eg, MPC823e User's Manual p.16-473). So, set
 		CONFIG_SYS_I2C_SLAVE to 0.
@@ -1509,6 +1509,17 @@ The following options need to be configured:
 		custom i2c_init_board() routine in boards/xxx/board.c
 		is run early in the boot sequence.
 
+		CONFIG_SYS_I2C_BOARD_LATE_INIT
+
+		An alternative to CONFIG_SYS_I2C_INIT_BOARD. If this option is
+		defined a custom i2c_board_late_init() routine in
+		boards/xxx/board.c is run AFTER the operations in i2c_init()
+		is completed. This callpoint can be used to unreset i2c bus
+		using CPU i2c controller register accesses for CPUs whose i2c
+		controller provide such a method. It is called at the end of
+		i2c_init() to allow i2c_init operations to setup the i2c bus
+		controller on the CPU (e.g. setting bus speed & slave address).
+
 		CONFIG_I2CFAST (PPC405GP|PPC405EP only)
 
 		This option enables configuration of bi_iic_fast[] flags
@@ -1966,7 +1977,7 @@ Legacy uImage format:
 
    15	arch/<arch>/lib/bootm.c	All preparation done, transferring control to OS
 
-  -30	arch/ppc/lib/board.c	Fatal error, hang the system
+  -30	arch/powerpc/lib/board.c	Fatal error, hang the system
   -31	post/post.c		POST test failed, detected by post_output_backlog()
   -32	post/post.c		POST test failed, detected by post_run_single()
 
@@ -2727,7 +2738,7 @@ Low Level (hardware related) configuration options:
   CONFIG_SYS_PCI_MSTR_MEMIO_SIZE, CONFIG_SYS_POCMR1_MASK_ATTRIB, CONFIG_SYS_PCI_MSTR_IO_LOCAL,
   CONFIG_SYS_PCI_MSTR_IO_BUS, CONFIG_SYS_CPU_PCI_IO_START, CONFIG_SYS_PCI_MSTR_IO_SIZE,
   CONFIG_SYS_POCMR2_MASK_ATTRIB: (MPC826x only)
-		Overrides the default PCI memory map in arch/ppc/cpu/mpc8260/pci.c if set.
+		Overrides the default PCI memory map in arch/powerpc/cpu/mpc8260/pci.c if set.
 
 - CONFIG_PCI_DISABLE_PCIE:
 		Disable PCI-Express on systems where it is supported but not
@@ -3373,7 +3384,7 @@ configure the Linux device drivers for use with your target hardware
 (no, we don't intend to provide a full virtual machine interface to
 Linux :-).
 
-But now you can ignore ALL boot loader code (in arch/ppc/mbxboot).
+But now you can ignore ALL boot loader code (in arch/powerpc/mbxboot).
 
 Just make sure your machine specific header file (for instance
 include/asm-ppc/tqm8xx.h) includes the same definition of the Board
@@ -3471,7 +3482,7 @@ So a typical call to build a U-Boot image would read:
 
 	-> tools/mkimage -n '2.4.4 kernel for TQM850L' \
 	> -A ppc -O linux -T kernel -C gzip -a 0 -e 0 \
-	> -d /opt/elsk/ppc_8xx/usr/src/linux-2.4.4/arch/ppc/coffboot/vmlinux.gz \
+	> -d /opt/elsk/ppc_8xx/usr/src/linux-2.4.4/arch/powerpc/coffboot/vmlinux.gz \
 	> examples/uImage.TQM850L
 	Image Name:   2.4.4 kernel for TQM850L
 	Created:      Wed Jul 19 02:34:59 2000
@@ -3495,10 +3506,10 @@ speed for memory and install an UNCOMPRESSED image instead: this
 needs more space in Flash, but boots much faster since it does not
 need to be uncompressed:
 
-	-> gunzip /opt/elsk/ppc_8xx/usr/src/linux-2.4.4/arch/ppc/coffboot/vmlinux.gz
+	-> gunzip /opt/elsk/ppc_8xx/usr/src/linux-2.4.4/arch/powerpc/coffboot/vmlinux.gz
 	-> tools/mkimage -n '2.4.4 kernel for TQM850L' \
 	> -A ppc -O linux -T kernel -C none -a 0 -e 0 \
-	> -d /opt/elsk/ppc_8xx/usr/src/linux-2.4.4/arch/ppc/coffboot/vmlinux \
+	> -d /opt/elsk/ppc_8xx/usr/src/linux-2.4.4/arch/powerpc/coffboot/vmlinux \
 	> examples/uImage.TQM850L-uncompressed
 	Image Name:   2.4.4 kernel for TQM850L
 	Created:      Wed Jul 19 02:34:59 2000

arch/arm/include/asm/mach-types.h

@@ -2773,6 +2773,57 @@ extern unsigned int __machine_arch_type;
 #define MACH_TYPE_SKAT91_S3E           2790
 #define MACH_TYPE_OMAP4_PANDA          2791
 #define MACH_TYPE_DF7220               2792
+#define MACH_TYPE_NEMINI               2793
+#define MACH_TYPE_T8200                2794
+#define MACH_TYPE_APF51                2795
+#define MACH_TYPE_DR_RC_UNIT           2796
+#define MACH_TYPE_BORDEAUX             2797
+#define MACH_TYPE_CATANIA_B            2798
+#define MACH_TYPE_MX51_OCEAN           2799
+#define MACH_TYPE_TI8168EVM            2800
+#define MACH_TYPE_NEOCOREOMAP          2801
+#define MACH_TYPE_WITHINGS_WBP         2802
+#define MACH_TYPE_DBPS                 2803
+#define MACH_TYPE_SBC9261              2804
+#define MACH_TYPE_PCBFP0001            2805
+#define MACH_TYPE_SPEEDY               2806
+#define MACH_TYPE_CHRYSAOR             2807
+#define MACH_TYPE_TANGO                2808
+#define MACH_TYPE_SYNOLOGY_DSX11       2809
+#define MACH_TYPE_HANLIN_V3EXT         2810
+#define MACH_TYPE_HANLIN_V5            2811
+#define MACH_TYPE_HANLIN_V3PLUS        2812
+#define MACH_TYPE_IRIVER_STORY         2813
+#define MACH_TYPE_IREX_ILIAD           2814
+#define MACH_TYPE_IREX_DR1000          2815
+#define MACH_TYPE_TETON_BGA            2816
+#define MACH_TYPE_SNAPPER9G45          2817
+#define MACH_TYPE_TAM3517              2818
+#define MACH_TYPE_PDC100               2819
+#define MACH_TYPE_EUKREA_CPUIMX25      2820
+#define MACH_TYPE_EUKREA_CPUIMX35      2821
+#define MACH_TYPE_EUKREA_CPUIMX51SD    2822
+#define MACH_TYPE_EUKREA_CPUIMX51      2823
+#define MACH_TYPE_P565                 2824
+#define MACH_TYPE_ACER_A4              2825
+#define MACH_TYPE_DAVINCI_DM368_BIP    2826
+#define MACH_TYPE_ESHARE               2827
+#define MACH_TYPE_HW_OMAPL138_EUROPA   2828
+#define MACH_TYPE_WLBARGN              2829
+#define MACH_TYPE_BM170                2830
+#define MACH_TYPE_NETSPACE_MINI_V2     2831
+#define MACH_TYPE_NETSPACE_PLUG_V2     2832
+#define MACH_TYPE_SIEMENS_L1           2833
+#define MACH_TYPE_ELV_LCU1             2834
+#define MACH_TYPE_MCU1                 2835
+#define MACH_TYPE_OMAP3_TAO3530        2836
+#define MACH_TYPE_OMAP3_PCUTOUCH       2837
+#define MACH_TYPE_SMDKC210             2838
+#define MACH_TYPE_OMAP3_BRAILLO        2839
+#define MACH_TYPE_SPYPLUG              2840
+#define MACH_TYPE_GINGER               2841
+#define MACH_TYPE_TNY_T3530            2842
+#define MACH_TYPE_PCA102               2843
 
 #ifdef CONFIG_ARCH_EBSA110
 # ifdef machine_arch_type
@@ -33573,9 +33624,9 @@ extern unsigned int __machine_arch_type;
 # else
 #  define machine_arch_type	MACH_TYPE_DAVINCI_CIO
 # endif
-# define machine_is_davinci_cio()	(machine_arch_type == MACH_TYPE_DAVINCI_CIO)
+# define machine_is_davinci_dm6467_cio()	(machine_arch_type == MACH_TYPE_DAVINCI_CIO)
 #else
-# define machine_is_davinci_cio()	(0)
+# define machine_is_davinci_dm6467_cio()	(0)
 #endif
 
 #ifdef CONFIG_MACH_SMARTMETER_DL
@@ -35906,6 +35957,618 @@ extern unsigned int __machine_arch_type;
 # define machine_is_df7220()	(0)
 #endif
 
+#ifdef CONFIG_MACH_NEMINI
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NEMINI
+# endif
+# define machine_is_nemini()	(machine_arch_type == MACH_TYPE_NEMINI)
+#else
+# define machine_is_nemini()	(0)
+#endif
+
+#ifdef CONFIG_MACH_T8200
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_T8200
+# endif
+# define machine_is_t8200()	(machine_arch_type == MACH_TYPE_T8200)
+#else
+# define machine_is_t8200()	(0)
+#endif
+
+#ifdef CONFIG_MACH_APF51
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_APF51
+# endif
+# define machine_is_apf51()	(machine_arch_type == MACH_TYPE_APF51)
+#else
+# define machine_is_apf51()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DR_RC_UNIT
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DR_RC_UNIT
+# endif
+# define machine_is_dr_rc_unit()	(machine_arch_type == MACH_TYPE_DR_RC_UNIT)
+#else
+# define machine_is_dr_rc_unit()	(0)
+#endif
+
+#ifdef CONFIG_MACH_BORDEAUX
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BORDEAUX
+# endif
+# define machine_is_bordeaux()	(machine_arch_type == MACH_TYPE_BORDEAUX)
+#else
+# define machine_is_bordeaux()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CATANIA_B
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CATANIA_B
+# endif
+# define machine_is_catania_b()	(machine_arch_type == MACH_TYPE_CATANIA_B)
+#else
+# define machine_is_catania_b()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MX51_OCEAN
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MX51_OCEAN
+# endif
+# define machine_is_mx51_ocean()	(machine_arch_type == MACH_TYPE_MX51_OCEAN)
+#else
+# define machine_is_mx51_ocean()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TI8168EVM
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TI8168EVM
+# endif
+# define machine_is_ti8168evm()	(machine_arch_type == MACH_TYPE_TI8168EVM)
+#else
+# define machine_is_ti8168evm()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NEOCOREOMAP
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NEOCOREOMAP
+# endif
+# define machine_is_neocoreomap()	(machine_arch_type == MACH_TYPE_NEOCOREOMAP)
+#else
+# define machine_is_neocoreomap()	(0)
+#endif
+
+#ifdef CONFIG_MACH_WITHINGS_WBP
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_WITHINGS_WBP
+# endif
+# define machine_is_withings_wbp()	(machine_arch_type == MACH_TYPE_WITHINGS_WBP)
+#else
+# define machine_is_withings_wbp()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DBPS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DBPS
+# endif
+# define machine_is_dbps()	(machine_arch_type == MACH_TYPE_DBPS)
+#else
+# define machine_is_dbps()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SBC9261
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SBC9261
+# endif
+# define machine_is_at91sam9261()	(machine_arch_type == MACH_TYPE_SBC9261)
+#else
+# define machine_is_at91sam9261()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PCBFP0001
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PCBFP0001
+# endif
+# define machine_is_pcbfp0001()	(machine_arch_type == MACH_TYPE_PCBFP0001)
+#else
+# define machine_is_pcbfp0001()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SPEEDY
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SPEEDY
+# endif
+# define machine_is_speedy()	(machine_arch_type == MACH_TYPE_SPEEDY)
+#else
+# define machine_is_speedy()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CHRYSAOR
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CHRYSAOR
+# endif
+# define machine_is_chrysaor()	(machine_arch_type == MACH_TYPE_CHRYSAOR)
+#else
+# define machine_is_chrysaor()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TANGO
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TANGO
+# endif
+# define machine_is_tango()	(machine_arch_type == MACH_TYPE_TANGO)
+#else
+# define machine_is_tango()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SYNOLOGY_DSX11
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SYNOLOGY_DSX11
+# endif
+# define machine_is_synology_dsx11()	(machine_arch_type == MACH_TYPE_SYNOLOGY_DSX11)
+#else
+# define machine_is_synology_dsx11()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HANLIN_V3EXT
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HANLIN_V3EXT
+# endif
+# define machine_is_hanlin_v3ext()	(machine_arch_type == MACH_TYPE_HANLIN_V3EXT)
+#else
+# define machine_is_hanlin_v3ext()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HANLIN_V5
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HANLIN_V5
+# endif
+# define machine_is_hanlin_v5()	(machine_arch_type == MACH_TYPE_HANLIN_V5)
+#else
+# define machine_is_hanlin_v5()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HANLIN_V3PLUS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HANLIN_V3PLUS
+# endif
+# define machine_is_hanlin_v3plus()	(machine_arch_type == MACH_TYPE_HANLIN_V3PLUS)
+#else
+# define machine_is_hanlin_v3plus()	(0)
+#endif
+
+#ifdef CONFIG_MACH_IRIVER_STORY
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IRIVER_STORY
+# endif
+# define machine_is_iriver_story()	(machine_arch_type == MACH_TYPE_IRIVER_STORY)
+#else
+# define machine_is_iriver_story()	(0)
+#endif
+
+#ifdef CONFIG_MACH_IREX_ILIAD
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IREX_ILIAD
+# endif
+# define machine_is_irex_iliad()	(machine_arch_type == MACH_TYPE_IREX_ILIAD)
+#else
+# define machine_is_irex_iliad()	(0)
+#endif
+
+#ifdef CONFIG_MACH_IREX_DR1000
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IREX_DR1000
+# endif
+# define machine_is_irex_dr1000()	(machine_arch_type == MACH_TYPE_IREX_DR1000)
+#else
+# define machine_is_irex_dr1000()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TETON_BGA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TETON_BGA
+# endif
+# define machine_is_teton_bga()	(machine_arch_type == MACH_TYPE_TETON_BGA)
+#else
+# define machine_is_teton_bga()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SNAPPER9G45
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SNAPPER9G45
+# endif
+# define machine_is_snapper9g45()	(machine_arch_type == MACH_TYPE_SNAPPER9G45)
+#else
+# define machine_is_snapper9g45()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TAM3517
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TAM3517
+# endif
+# define machine_is_tam3517()	(machine_arch_type == MACH_TYPE_TAM3517)
+#else
+# define machine_is_tam3517()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PDC100
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PDC100
+# endif
+# define machine_is_pdc100()	(machine_arch_type == MACH_TYPE_PDC100)
+#else
+# define machine_is_pdc100()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EUKREA_CPUIMX25
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EUKREA_CPUIMX25
+# endif
+# define machine_is_eukrea_cpuimx25sd()	(machine_arch_type == MACH_TYPE_EUKREA_CPUIMX25)
+#else
+# define machine_is_eukrea_cpuimx25sd()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EUKREA_CPUIMX35
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EUKREA_CPUIMX35
+# endif
+# define machine_is_eukrea_cpuimx35sd()	(machine_arch_type == MACH_TYPE_EUKREA_CPUIMX35)
+#else
+# define machine_is_eukrea_cpuimx35sd()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EUKREA_CPUIMX51SD
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EUKREA_CPUIMX51SD
+# endif
+# define machine_is_eukrea_cpuimx51sd()	(machine_arch_type == MACH_TYPE_EUKREA_CPUIMX51SD)
+#else
+# define machine_is_eukrea_cpuimx51sd()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EUKREA_CPUIMX51
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EUKREA_CPUIMX51
+# endif
+# define machine_is_eukrea_cpuimx51()	(machine_arch_type == MACH_TYPE_EUKREA_CPUIMX51)
+#else
+# define machine_is_eukrea_cpuimx51()	(0)
+#endif
+
+#ifdef CONFIG_MACH_P565
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_P565
+# endif
+# define machine_is_p565()	(machine_arch_type == MACH_TYPE_P565)
+#else
+# define machine_is_p565()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ACER_A4
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ACER_A4
+# endif
+# define machine_is_acer_a4()	(machine_arch_type == MACH_TYPE_ACER_A4)
+#else
+# define machine_is_acer_a4()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DAVINCI_DM368_BIP
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DAVINCI_DM368_BIP
+# endif
+# define machine_is_davinci_dm368_bip()	(machine_arch_type == MACH_TYPE_DAVINCI_DM368_BIP)
+#else
+# define machine_is_davinci_dm368_bip()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ESHARE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ESHARE
+# endif
+# define machine_is_eshare()	(machine_arch_type == MACH_TYPE_ESHARE)
+#else
+# define machine_is_eshare()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HW_OMAPL138_EUROPA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HW_OMAPL138_EUROPA
+# endif
+# define machine_is_hw_omapl138_europa()	(machine_arch_type == MACH_TYPE_HW_OMAPL138_EUROPA)
+#else
+# define machine_is_hw_omapl138_europa()	(0)
+#endif
+
+#ifdef CONFIG_MACH_WLBARGN
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_WLBARGN
+# endif
+# define machine_is_wlbargn()	(machine_arch_type == MACH_TYPE_WLBARGN)
+#else
+# define machine_is_wlbargn()	(0)
+#endif
+
+#ifdef CONFIG_MACH_BM170
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BM170
+# endif
+# define machine_is_bm170()	(machine_arch_type == MACH_TYPE_BM170)
+#else
+# define machine_is_bm170()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NETSPACE_MINI_V2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NETSPACE_MINI_V2
+# endif
+# define machine_is_netspace_mini_v2()	(machine_arch_type == MACH_TYPE_NETSPACE_MINI_V2)
+#else
+# define machine_is_netspace_mini_v2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NETSPACE_PLUG_V2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NETSPACE_PLUG_V2
+# endif
+# define machine_is_netspace_plug_v2()	(machine_arch_type == MACH_TYPE_NETSPACE_PLUG_V2)
+#else
+# define machine_is_netspace_plug_v2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SIEMENS_L1
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SIEMENS_L1
+# endif
+# define machine_is_siemens_l1()	(machine_arch_type == MACH_TYPE_SIEMENS_L1)
+#else
+# define machine_is_siemens_l1()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ELV_LCU1
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ELV_LCU1
+# endif
+# define machine_is_elv_lcu1()	(machine_arch_type == MACH_TYPE_ELV_LCU1)
+#else
+# define machine_is_elv_lcu1()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MCU1
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MCU1
+# endif
+# define machine_is_mcu1()	(machine_arch_type == MACH_TYPE_MCU1)
+#else
+# define machine_is_mcu1()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP3_TAO3530
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMAP3_TAO3530
+# endif
+# define machine_is_omap3_tao3530()	(machine_arch_type == MACH_TYPE_OMAP3_TAO3530)
+#else
+# define machine_is_omap3_tao3530()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP3_PCUTOUCH
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMAP3_PCUTOUCH
+# endif
+# define machine_is_omap3_pcutouch()	(machine_arch_type == MACH_TYPE_OMAP3_PCUTOUCH)
+#else
+# define machine_is_omap3_pcutouch()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SMDKC210
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SMDKC210
+# endif
+# define machine_is_smdkc210()	(machine_arch_type == MACH_TYPE_SMDKC210)
+#else
+# define machine_is_smdkc210()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP3_BRAILLO
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMAP3_BRAILLO
+# endif
+# define machine_is_omap3_braillo()	(machine_arch_type == MACH_TYPE_OMAP3_BRAILLO)
+#else
+# define machine_is_omap3_braillo()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SPYPLUG
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SPYPLUG
+# endif
+# define machine_is_spyplug()	(machine_arch_type == MACH_TYPE_SPYPLUG)
+#else
+# define machine_is_spyplug()	(0)
+#endif
+
+#ifdef CONFIG_MACH_GINGER
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_GINGER
+# endif
+# define machine_is_ginger()	(machine_arch_type == MACH_TYPE_GINGER)
+#else
+# define machine_is_ginger()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TNY_T3530
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TNY_T3530
+# endif
+# define machine_is_tny_t3530()	(machine_arch_type == MACH_TYPE_TNY_T3530)
+#else
+# define machine_is_tny_t3530()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PCA102
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PCA102
+# endif
+# define machine_is_pca102()	(machine_arch_type == MACH_TYPE_PCA102)
+#else
+# define machine_is_pca102()	(0)
+#endif
+
 /*
  * These have not yet been registered
  */

arch/microblaze/cpu/cache.c

@@ -50,6 +50,8 @@ void	icache_enable (void) {
 }
 
 void	icache_disable(void) {
+	/* we are not generate ICACHE size -> flush whole cache */
+	flush_cache(0, 32768);
 	MSRCLR(0x20);
 }
 
@@ -58,5 +60,31 @@ void	dcache_enable (void) {
 }
 
 void	dcache_disable(void) {
+#ifdef XILINX_USE_DCACHE
+#ifdef XILINX_DCACHE_BYTE_SIZE
+	flush_cache(0, XILINX_DCACHE_BYTE_SIZE);
+#else
+#warning please rebuild BSPs and update configuration
+	flush_cache(0, 32768);
+#endif
+#endif
 	MSRCLR(0x80);
 }
+
+void flush_cache (ulong addr, ulong size)
+{
+	int i;
+	for (i = 0; i < size; i += 4)
+		asm volatile (
+#ifdef CONFIG_ICACHE
+				"wic	%0, r0;"
+#endif
+				"nop;"
+#ifdef CONFIG_DCACHE
+				"wdc.flush	%0, r0;"
+#endif
+				"nop;"
+				:
+				: "r" (addr + i)
+				: "memory");
+}

arch/microblaze/cpu/interrupts.c

@@ -46,13 +46,6 @@ int disable_interrupts (void)
 }
 
 #ifdef CONFIG_SYS_INTC_0
-#ifdef CONFIG_SYS_TIMER_0
-extern void timer_init (void);
-#endif
-#ifdef CONFIG_SYS_FSL_2
-extern void fsl_init2 (void);
-#endif
-
 
 static struct irq_action vecs[CONFIG_SYS_INTC_0_NUM];
 
@@ -142,20 +135,14 @@ int interrupts_init (void)
 	}
 	/* initialize intc controller */
 	intc_init ();
-#ifdef CONFIG_SYS_TIMER_0
-	timer_init ();
-#endif
-#ifdef CONFIG_SYS_FSL_2
-	fsl_init2 ();
-#endif
 	enable_interrupts ();
 	return 0;
 }
 
 void interrupt_handler (void)
 {
-	int irqs = (intc->isr & intc->ier);	/* find active interrupt */
-	int i = 1;
+	int irqs = intc->ivr;	/* find active interrupt */
+	int mask = 1;
 #ifdef DEBUG_INT
 	int value;
 	printf ("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier,
@@ -163,23 +150,17 @@ void interrupt_handler (void)
 	R14(value);
 	printf ("Interrupt handler on %x line, r14 %x\n", irqs, value);
 #endif
-	struct irq_action *act = vecs;
-	while (irqs) {
-		if (irqs & 1) {
+	struct irq_action *act = vecs + irqs;
+
+	intc->iar = mask << irqs;
+
 #ifdef DEBUG_INT
-			printf
-			    ("Jumping to interrupt handler rutine addr %x,count %x,arg %x\n",
-			     act->handler, act->count, act->arg);
+	printf
+	    ("Jumping to interrupt handler rutine addr %x,count %x,arg %x\n",
+	     act->handler, act->count, act->arg);
 #endif
-			act->handler (act->arg);
-			act->count++;
-			intc->iar = i;
-			return;
-		}
-		irqs >>= 1;
-		act++;
-		i <<= 1;
-	}
+	act->handler (act->arg);
+	act->count++;
 
 #ifdef DEBUG_INT
 	printf ("Dump INTC reg, isr %x, ier %x, iar %x, mer %x\n", intc->isr,

arch/microblaze/cpu/irq.S

@@ -27,129 +27,71 @@
 	.text
 	.global _interrupt_handler
 _interrupt_handler:
-	addi	r1, r1, -4
-	swi	r2, r1, 0
-	addi	r1, r1, -4
-	swi	r3, r1, 0
-	addi	r1, r1, -4
-	swi	r4, r1, 0
-	addi	r1, r1, -4
-	swi	r5, r1, 0
-	addi	r1, r1, -4
-	swi	r6, r1, 0
-	addi	r1, r1, -4
-	swi	r7, r1, 0
-	addi	r1, r1, -4
-	swi	r8, r1, 0
-	addi	r1, r1, -4
-	swi	r9, r1, 0
-	addi	r1, r1, -4
-	swi	r10, r1, 0
-	addi	r1, r1, -4
-	swi	r11, r1, 0
-	addi	r1, r1, -4
-	swi	r12, r1, 0
-	addi	r1, r1, -4
-	swi	r13, r1, 0
-	addi	r1, r1, -4
-	swi	r14, r1, 0
-	addi	r1, r1, -4
-	swi	r15, r1, 0
-	addi	r1, r1, -4
-	swi	r16, r1, 0
-	addi	r1, r1, -4
-	swi	r17, r1, 0
-	addi	r1, r1, -4
-	swi	r18, r1, 0
-	addi	r1, r1, -4
-	swi	r19, r1, 0
-	addi	r1, r1, -4
-	swi	r20, r1, 0
-	addi	r1, r1, -4
-	swi	r21, r1, 0
-	addi	r1, r1, -4
-	swi	r22, r1, 0
-	addi	r1, r1, -4
-	swi	r23, r1, 0
-	addi	r1, r1, -4
-	swi	r24, r1, 0
-	addi	r1, r1, -4
-	swi	r25, r1, 0
-	addi	r1, r1, -4
-	swi	r26, r1, 0
-	addi	r1, r1, -4
-	swi	r27, r1, 0
-	addi	r1, r1, -4
-	swi	r28, r1, 0
-	addi	r1, r1, -4
-	swi	r29, r1, 0
-	addi	r1, r1, -4
-	swi	r30, r1, 0
-	addi	r1, r1, -4
-	swi	r31, r1, 0
+	swi	r2, r1, -4
+	swi	r3, r1, -8
+	swi	r4, r1, -12
+	swi	r5, r1, -16
+	swi	r6, r1, -20
+	swi	r7, r1, -24
+	swi	r8, r1, -28
+	swi	r9, r1, -32
+	swi	r10, r1, -36
+	swi	r11, r1, -40
+	swi	r12, r1, -44
+	swi	r13, r1, -48
+	swi	r14, r1, -52
+	swi	r15, r1, -56
+	swi	r16, r1, -60
+	swi	r17, r1, -64
+	swi	r18, r1, -68
+	swi	r19, r1, -72
+	swi	r20, r1, -76
+	swi	r21, r1, -80
+	swi	r22, r1, -84
+	swi	r23, r1, -88
+	swi	r24, r1, -92
+	swi	r25, r1, -96
+	swi	r26, r1, -100
+	swi	r27, r1, -104
+	swi	r28, r1, -108
+	swi	r29, r1, -112
+	swi	r30, r1, -116
+	swi	r31, r1, -120
+	addik	r1, r1, -124
 	brlid	r15, interrupt_handler
 	nop
 	nop
-	lwi	r31, r1, 0
-	addi	r1, r1, 4
-	lwi	r30, r1, 0
-	addi	r1, r1, 4
-	lwi	r29, r1, 0
-	addi	r1, r1, 4
-	lwi	r28, r1, 0
-	addi	r1, r1, 4
-	lwi	r27, r1, 0
-	addi	r1, r1, 4
-	lwi	r26, r1, 0
-	addi	r1, r1, 4
-	lwi	r25, r1, 0
-	addi	r1, r1, 4
-	lwi	r24, r1, 0
-	addi	r1, r1, 4
-	lwi	r23, r1, 0
-	addi	r1, r1, 4
-	lwi	r22, r1, 0
-	addi	r1, r1, 4
-	lwi	r21, r1, 0
-	addi	r1, r1, 4
-	lwi	r20, r1, 0
-	addi	r1, r1, 4
-	lwi	r19, r1, 0
-	addi	r1, r1, 4
-	lwi	r18, r1, 0
-	addi	r1, r1, 4
-	lwi	r17, r1, 0
-	addi	r1, r1, 4
-	lwi	r16, r1, 0
-	addi	r1, r1, 4
-	lwi	r15, r1, 0
-	addi	r1, r1, 4
-	lwi	r14, r1, 0
-	addi	r1, r1, 4
-	lwi	r13, r1, 0
-	addi	r1, r1, 4
-	lwi	r12, r1, 0
-	addi	r1, r1, 4
-	lwi	r11, r1, 0
-	addi	r1, r1, 4
-	lwi	r10, r1, 0
-	addi	r1, r1, 4
-	lwi	r9, r1, 0
-	addi	r1, r1, 4
-	lwi	r8, r1, 0
-	addi	r1, r1, 4
-	lwi	r7, r1, 0
-	addi	r1, r1, 4
-	lwi	r6, r1, 0
-	addi	r1, r1, 4
-	lwi	r5, r1, 0
-	addi	r1, r1, 4
-	lwi	r4, r1, 0
-	addi	r1, r1, 4
-	lwi	r3, r1, 0
-	addi	r1, r1, 4
-	lwi	r2, r1, 0
-	addi	r1, r1, 4
+	addik	r1, r1, 124
+	lwi	r31, r1, -120
+	lwi	r30, r1, -116
+	lwi	r29, r1, -112
+	lwi	r28, r1, -108
+	lwi	r27, r1, -104
+	lwi	r26, r1, -100
+	lwi	r25, r1, -96
+	lwi	r24, r1, -92
+	lwi	r23, r1, -88
+	lwi	r22, r1, -84
+	lwi	r21, r1, -80
+	lwi	r20, r1, -76
+	lwi	r19, r1, -72
+	lwi	r18, r1, -68
+	lwi	r17, r1, -64
+	lwi	r16, r1, -60
+	lwi	r15, r1, -56
+	lwi	r14, r1, -52
+	lwi	r13, r1, -48
+	lwi	r12, r1, -44
+	lwi	r11, r1, -40
+	lwi	r10, r1, -36
+	lwi	r9, r1, -32
+	lwi	r8, r1, -28
+	lwi	r7, r1, -24
+	lwi	r6, r1, -20
+	lwi	r5, r1, -16
+	lwi	r4, r1, -12
+	lwi	r3, r1, -8
+	lwi	r2, r1, -4
 
 	/* enable_interrupt */
 #ifdef XILINX_USE_MSR_INSTR

arch/microblaze/cpu/timer.c

@@ -60,7 +60,7 @@ void timer_isr (void *arg)
 	tmr->control = tmr->control | TIMER_INTERRUPT;
 }
 
-void timer_init (void)
+int timer_init (void)
 {
 	tmr->loadreg = CONFIG_SYS_TIMER_0_PRELOAD;
 	tmr->control = TIMER_INTERRUPT | TIMER_RESET;
@@ -68,6 +68,7 @@ void timer_init (void)
 	    TIMER_ENABLE | TIMER_ENABLE_INTR | TIMER_RELOAD | TIMER_DOWN_COUNT;
 	reset_timer ();
 	install_interrupt_handler (CONFIG_SYS_TIMER_0_IRQ, timer_isr, (void *)tmr);
+	return 0;
 }
 #endif
 #endif

arch/microblaze/lib/Makefile

@@ -29,7 +29,6 @@ SOBJS-y	+=
 
 COBJS-y	+= board.o
 COBJS-y	+= bootm.o
-COBJS-y	+= cache.o
 COBJS-y	+= time.o
 
 SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)

arch/microblaze/lib/board.c

@@ -30,6 +30,7 @@
 #include <timestamp.h>
 #include <version.h>
 #include <watchdog.h>
+#include <stdio_dev.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -44,6 +45,12 @@ extern int interrupts_init (void);
 #if defined(CONFIG_CMD_NET)
 extern int eth_init (bd_t * bis);
 #endif
+#ifdef CONFIG_SYS_TIMER_0
+extern int timer_init (void);
+#endif
+#ifdef CONFIG_SYS_FSL_2
+extern void fsl_init2 (void);
+#endif
 
 /*
  * All attempts to come up with a "common" initialization sequence
@@ -67,6 +74,12 @@ init_fnc_t *init_sequence[] = {
 #endif
 #ifdef CONFIG_SYS_INTC_0
 	interrupts_init,
+#endif
+#ifdef CONFIG_SYS_TIMER_0
+	timer_init,
+#endif
+#ifdef CONFIG_SYS_FSL_2
+	fsl_init2,
 #endif
 	NULL,
 };
@@ -76,6 +89,7 @@ void board_init (void)
 	bd_t *bd;
 	init_fnc_t **init_fnc_ptr;
 	gd = (gd_t *) CONFIG_SYS_GBL_DATA_OFFSET;
+	char *s;
 #if defined(CONFIG_CMD_FLASH)
 	ulong flash_size = 0;
 #endif
@@ -104,8 +118,8 @@ void board_init (void)
 	}
 
 	puts ("SDRAM :\n");
-	printf ("\t\tIcache:%s\n", icache_status() ? "OK" : "FAIL");
-	printf ("\t\tDcache:%s\n", dcache_status() ? "OK" : "FAIL");
+	printf ("\t\tIcache:%s\n", icache_status() ? "ON" : "OFF");
+	printf ("\t\tDcache:%s\n", dcache_status() ? "ON" : "OFF");
 	printf ("\tU-Boot Start:0x%08x\n", TEXT_BASE);
 
 #if defined(CONFIG_CMD_FLASH)
@@ -139,15 +153,22 @@ void board_init (void)
 	}
 #endif
 
+	/* relocate environment function pointers etc. */
+	env_relocate ();
+
+	/* Initialize stdio devices */
+	stdio_init ();
+
+	if ((s = getenv ("loadaddr")) != NULL) {
+		load_addr = simple_strtoul (s, NULL, 16);
+	}
+
 #if defined(CONFIG_CMD_NET)
 	/* IP Address */
 	bd->bi_ip_addr = getenv_IPaddr ("ipaddr");
 	eth_init (bd);
 #endif
 
-	/* relocate environment function pointers etc. */
-	env_relocate ();
-
 	/* main_loop */
 	for (;;) {
 		WATCHDOG_RESET ();

arch/microblaze/lib/bootm.c

@@ -35,22 +35,59 @@ DECLARE_GLOBAL_DATA_PTR;
 int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
 {
 	/* First parameter is mapped to $r5 for kernel boot args */
-	void	(*theKernel) (char *);
+	void	(*theKernel) (char *, ulong, ulong);
 	char	*commandline = getenv ("bootargs");
+	ulong	rd_data_start, rd_data_end;
 
 	if ((flag != 0) && (flag != BOOTM_STATE_OS_GO))
 		return 1;
 
-	theKernel = (void (*)(char *))images->ep;
+	int	ret;
+
+	char	*of_flat_tree = NULL;
+#if defined(CONFIG_OF_LIBFDT)
+	ulong	of_size = 0;
+
+	/* find flattened device tree */
+	ret = boot_get_fdt (flag, argc, argv, images, &of_flat_tree, &of_size);
+	if (ret)
+		return 1;
+#endif
+
+	theKernel = (void (*)(char *, ulong, ulong))images->ep;
+
+	/* find ramdisk */
+	ret = boot_get_ramdisk (argc, argv, images, IH_ARCH_MICROBLAZE,
+			&rd_data_start, &rd_data_end);
+	if (ret)
+		return 1;
 
 	show_boot_progress (15);
 
+	if (!(ulong) of_flat_tree)
+		of_flat_tree = (char *)simple_strtoul (argv[3], NULL, 16);
+
 #ifdef DEBUG
-	printf ("## Transferring control to Linux (at address %08lx) ...\n",
-		(ulong) theKernel);
+	printf ("## Transferring control to Linux (at address 0x%08lx) " \
+				"ramdisk 0x%08lx, FDT 0x%08lx...\n",
+		(ulong) theKernel, rd_data_start, (ulong) of_flat_tree);
 #endif
 
-	theKernel (commandline);
+#ifdef XILINX_USE_DCACHE
+#ifdef XILINX_DCACHE_BYTE_SIZE
+	flush_cache(0, XILINX_DCACHE_BYTE_SIZE);
+#else
+#warning please rebuild BSPs and update configuration
+	flush_cache(0, 32768);
+#endif
+#endif
+	/*
+	 * Linux Kernel Parameters (passing device tree):
+	 * r5: pointer to command line
+	 * r6: pointer to ramdisk
+	 * r7: pointer to the fdt, followed by the board info data
+	 */
+	theKernel (commandline, rd_data_start, (ulong) of_flat_tree);
 	/* does not return */
 
 	return 1;

arch/nios2/config.mk

@@ -28,3 +28,5 @@ STANDALONE_LOAD_ADDR = 0x02000000 -L $(gcclibdir)
 
 PLATFORM_CPPFLAGS += -DCONFIG_NIOS2 -D__NIOS2__
 PLATFORM_CPPFLAGS += -ffixed-r15 -G0
+
+LDSCRIPT ?= $(SRCTREE)/$(CPUDIR)/u-boot.lds

arch/nios2/cpu/start.S

@@ -34,6 +34,7 @@
 	.global _start
 
 _start:
+	wrctl	status, r0		/* Disable interrupts */
 	/* ICACHE INIT -- only the icache line at the reset address
 	 * is invalidated at reset. So the init must stay within
 	 * the cache line size (8 words). If GERMS is used, we'll
@@ -43,10 +44,9 @@ _start:
 	ori	r4, r0, %lo(CONFIG_SYS_ICACHELINE_SIZE)
 	movhi	r5, %hi(CONFIG_SYS_ICACHE_SIZE)
 	ori	r5, r5, %lo(CONFIG_SYS_ICACHE_SIZE)
-	mov	r6, r0
-0:	initi	r6
-	add	r6, r6, r4
-	bltu	r6, r5, 0b
+0:	initi	r5
+	sub	r5, r5, r4
+	bgt	r5, r0, 0b
 	br	_except_end	/* Skip the tramp */
 
 	/* EXCEPTION TRAMPOLINE -- the following gets copied
@@ -62,7 +62,6 @@ _except_end:
 	/* INTERRUPTS -- for now, all interrupts masked and globally
 	 * disabled.
 	 */
-	wrctl	status, r0		/* Disable interrupts */
 	wrctl	ienable, r0		/* All disabled	*/
 
 	/* DCACHE INIT -- if dcache not implemented, initd behaves as

arch/nios2/cpu/u-boot.lds

@@ -30,7 +30,7 @@ SECTIONS
 {
 	.text :
 	{
-	  arch/nios/cpu2/start.o (.text)
+	  arch/nios2/cpu/start.o (.text)
 	  *(.text)
 	  *(.text.*)
 	  *(.gnu.linkonce.t*)

arch/nios2/include/asm/byteorder.h

@@ -25,6 +25,12 @@
 #define __ASM_NIOS2_BYTEORDER_H_
 
 #include <asm/types.h>
+
+#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
+#  define __BYTEORDER_HAS_U64__
+#  define __SWAB_64_THRU_32__
+#endif
+
 #include <linux/byteorder/little_endian.h>
 
 #endif /* __ASM_NIOS2_BYTEORDER_H_ */

arch/nios2/include/asm/dma-mapping.h

@@ -0,0 +1,23 @@
+#ifndef __ASM_NIOS2_DMA_MAPPING_H
+#define __ASM_NIOS2_DMA_MAPPING_H
+
+/* dma_alloc_coherent() return cache-line aligned allocation which is mapped
+ * to uncached io region.
+ *
+ * IO_REGION_BASE should be defined in board config header file
+ *   0x80000000 for nommu, 0xe0000000 for mmu
+ */
+
+static inline void *dma_alloc_coherent(size_t len, unsigned long *handle)
+{
+	void *addr = malloc(len + CONFIG_SYS_DCACHELINE_SIZE);
+	if (!addr)
+		return 0;
+	flush_dcache((unsigned long)addr, len + CONFIG_SYS_DCACHELINE_SIZE);
+	*handle = ((unsigned long)addr +
+		   (CONFIG_SYS_DCACHELINE_SIZE - 1)) &
+		~(CONFIG_SYS_DCACHELINE_SIZE - 1) & ~(IO_REGION_BASE);
+	return (void *)(*handle | IO_REGION_BASE);
+}
+
+#endif /* __ASM_NIOS2_DMA_MAPPING_H */

arch/nios2/lib/board.c

@@ -28,6 +28,7 @@
 #include <stdio_dev.h>
 #include <watchdog.h>
 #include <malloc.h>
+#include <mmc.h>
 #include <net.h>
 #ifdef CONFIG_STATUS_LED
 #include <status_led.h>
@@ -35,6 +36,9 @@
 #if defined(CONFIG_SYS_NIOS_EPCSBASE)
 #include <nios2-epcs.h>
 #endif
+#ifdef CONFIG_CMD_NAND
+#include <nand.h>	/* cannot even include nand.h if it isnt configured */
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -100,7 +104,9 @@ void board_init (void)
 	bd = gd->bd;
 	bd->bi_memstart	= CONFIG_SYS_SDRAM_BASE;
 	bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+#ifndef CONFIG_SYS_NO_FLASH
 	bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
+#endif
 #if	defined(CONFIG_SYS_SRAM_BASE) && defined(CONFIG_SYS_SRAM_SIZE)
 	bd->bi_sramstart= CONFIG_SYS_SRAM_BASE;
 	bd->bi_sramsize	= CONFIG_SYS_SRAM_SIZE;
@@ -119,8 +125,20 @@ void board_init (void)
 	/* The Malloc area is immediately below the monitor copy in RAM */
 	mem_malloc_init(CONFIG_SYS_MALLOC_BASE, CONFIG_SYS_MALLOC_LEN);
 
+#ifndef CONFIG_SYS_NO_FLASH
 	WATCHDOG_RESET ();
 	bd->bi_flashsize = flash_init();
+#endif
+
+#ifdef CONFIG_CMD_NAND
+	puts("NAND:  ");
+	nand_init();
+#endif
+
+#ifdef CONFIG_GENERIC_MMC
+	puts("MMC:   ");
+	mmc_initialize(bd);
+#endif
 
 	WATCHDOG_RESET ();
 	env_relocate();

arch/powerpc/cpu/74xx_7xx/traps.c

@@ -1,5 +1,5 @@
 /*
- * linux/arch/ppc/kernel/traps.c
+ * linux/arch/powerpc/kernel/traps.c
  *
  * Copyright (C) 1995-1996  Gary Thomas (gdt@linuxppc.org)
  *

arch/powerpc/cpu/mpc512x/Makefile

@@ -29,6 +29,7 @@ LIB	= $(obj)lib$(CPU).a
 START	= start.o
 COBJS-y	:= cpu.o
 COBJS-y	+= traps.o
+COBJS-y += common.o
 COBJS-y += cpu_init.o
 COBJS-y += fixed_sdram.o
 COBJS-y += i2c.o

arch/powerpc/cpu/mpc512x/asm-offsets.h

@@ -1,5 +1,5 @@
 /*
- * needed for arch/ppc/cpu/mpc512x/start.S
+ * needed for arch/powerpc/cpu/mpc512x/start.S
  *
  * These should be auto-generated
  */

arch/powerpc/cpu/mpc512x/common.c

@@ -0,0 +1,25 @@
+#include <common.h>
+#include <asm/io.h>
+
+#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
+
+#if defined(CONFIG_SYS_POST_WORD_ADDR)
+# define _POST_ADDR	(CONFIG_SYS_POST_WORD_ADDR)
+#else
+#error echo "No POST word address defined"
+#endif
+
+void post_word_store(ulong a)
+{
+	volatile void *save_addr = (volatile void *)(_POST_ADDR);
+
+	out_be32(save_addr, a);
+}
+
+ulong post_word_load(void)
+{
+	volatile void *save_addr = (volatile void *)(_POST_ADDR);
+
+	return in_be32(save_addr);
+}
+#endif  /* CONFIG_POST || CONFIG_LOGBUFFER */

arch/powerpc/cpu/mpc512x/config.mk

@@ -26,4 +26,4 @@ PLATFORM_CPPFLAGS += -DCONFIG_MPC512X -DCONFIG_E300 \
 
 # Use default linker script.
 # A board port can override this setting in board/*/config.mk
-LDSCRIPT := $(SRCTREE)/arch/ppc/cpu/mpc512x/u-boot.lds
+LDSCRIPT := $(SRCTREE)/arch/powerpc/cpu/mpc512x/u-boot.lds

arch/powerpc/cpu/mpc512x/diu.c

@@ -34,6 +34,8 @@
 #include <video_fb.h>
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #ifdef CONFIG_FSL_DIU_LOGO_BMP
 extern unsigned int FSL_Logo_BMP[];
 #else
@@ -65,10 +67,11 @@ void diu_set_pixel_clock(unsigned int pixclock)
 char *valid_bmp(char *addr)
 {
 	unsigned long h_addr;
+	bd_t *bd = gd->bd;
 
 	h_addr = simple_strtoul(addr, NULL, 16);
-	if (h_addr < CONFIG_SYS_FLASH_BASE ||
-			h_addr >= (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - 1)) {
+	if (h_addr < bd->bi_flashstart ||
+	    h_addr >= (bd->bi_flashstart + bd->bi_flashsize - 1)) {
 		printf("bmp addr %lx is not a valid flash address\n", h_addr);
 		return 0;
 	} else if ((*(char *)(h_addr) != 'B') || (*(char *)(h_addr+1) != 'M')) {
@@ -84,8 +87,13 @@ int mpc5121_diu_init(void)
 	char *bmp = NULL;
 	char *bmp_env;
 
+#if defined(CONFIG_VIDEO_XRES) & defined(CONFIG_VIDEO_YRES)
+	xres = CONFIG_VIDEO_XRES;
+	yres = CONFIG_VIDEO_YRES;
+#else
 	xres = 1024;
 	yres = 768;
+#endif
 	pixel_format = 0x88883316;
 
 	debug("mpc5121_diu_init\n");

arch/powerpc/cpu/mpc512x/fixed_sdram.c

@@ -78,7 +78,7 @@ long int fixed_sdram(ddr512x_config_t *mddrc_config,
 			u32 *dram_init_seq, int seq_sz)
 {
 	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
+	u32 msize = CONFIG_SYS_MAX_RAM_SIZE;
 	u32 msize_log2 = __ilog2(msize);
 	u32 i;
 
@@ -91,7 +91,7 @@ long int fixed_sdram(ddr512x_config_t *mddrc_config,
 	}
 
 	/* Initialize IO Control */
-	out_be32(&im->io_ctrl.io_control_mem, IOCTRL_MUX_DDR);
+	out_be32(&im->io_ctrl.io_control_mem, CONFIG_SYS_IOCTRL_MUX_DDR);
 
 	/* Initialize DDR Local Window */
 	out_be32(&im->sysconf.ddrlaw.bar, CONFIG_SYS_DDR_BASE & 0xFFFFF000);
@@ -148,5 +148,10 @@ long int fixed_sdram(ddr512x_config_t *mddrc_config,
 	out_be32(&im->mddrc.ddr_time_config0, mddrc_config->ddr_time_config0);
 	out_be32(&im->mddrc.ddr_sys_config, mddrc_config->ddr_sys_config);
 
+	msize = get_ram_size(CONFIG_SYS_DDR_BASE, CONFIG_SYS_MAX_RAM_SIZE);
+	/* Fix DDR Local Window for new size */
+	out_be32(&im->sysconf.ddrlaw.ar, __ilog2(msize) - 1);
+	sync_law(&im->sysconf.ddrlaw.ar);
+
 	return msize;
 }

arch/powerpc/cpu/mpc512x/serial.c

@@ -0,0 +1,490 @@
+/*
+ * (C) Copyright 2000 - 2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Based ont the MPC5200 PSC driver.
+ * Adapted for MPC512x by Jan Wrobel <wrr@semihalf.com>
+ */
+
+/*
+ * Minimal serial functions needed to use one of the PSC ports
+ * as serial console interface.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <serial.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_PSC_CONSOLE) || defined(CONFIG_SERIAL_MULTI)
+
+static void fifo_init (volatile psc512x_t *psc)
+{
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	u32 tfsize, rfsize;
+
+	/* reset Rx & Tx fifo slice */
+	out_be32(&psc->rfcmd, PSC_FIFO_RESET_SLICE);
+	out_be32(&psc->tfcmd, PSC_FIFO_RESET_SLICE);
+
+	/* disable Tx & Rx FIFO interrupts */
+	out_be32(&psc->rfintmask, 0);
+	out_be32(&psc->tfintmask, 0);
+
+#if defined(CONFIG_SERIAL_MULTI)
+	switch (((u32)psc & 0xf00) >> 8) {
+	case 0:
+		tfsize = FIFOC_PSC0_TX_SIZE | (FIFOC_PSC0_TX_ADDR << 16);
+		rfsize = FIFOC_PSC0_RX_SIZE | (FIFOC_PSC0_RX_ADDR << 16);
+		break;
+	case 1:
+		tfsize = FIFOC_PSC1_TX_SIZE | (FIFOC_PSC1_TX_ADDR << 16);
+		rfsize = FIFOC_PSC1_RX_SIZE | (FIFOC_PSC1_RX_ADDR << 16);
+		break;
+	case 2:
+		tfsize = FIFOC_PSC2_TX_SIZE | (FIFOC_PSC2_TX_ADDR << 16);
+		rfsize = FIFOC_PSC2_RX_SIZE | (FIFOC_PSC2_RX_ADDR << 16);
+		break;
+	case 3:
+		tfsize = FIFOC_PSC3_TX_SIZE | (FIFOC_PSC3_TX_ADDR << 16);
+		rfsize = FIFOC_PSC3_RX_SIZE | (FIFOC_PSC3_RX_ADDR << 16);
+		break;
+	case 4:
+		tfsize = FIFOC_PSC4_TX_SIZE | (FIFOC_PSC4_TX_ADDR << 16);
+		rfsize = FIFOC_PSC4_RX_SIZE | (FIFOC_PSC4_RX_ADDR << 16);
+		break;
+	case 5:
+		tfsize = FIFOC_PSC5_TX_SIZE | (FIFOC_PSC5_TX_ADDR << 16);
+		rfsize = FIFOC_PSC5_RX_SIZE | (FIFOC_PSC5_RX_ADDR << 16);
+		break;
+	case 6:
+		tfsize = FIFOC_PSC6_TX_SIZE | (FIFOC_PSC6_TX_ADDR << 16);
+		rfsize = FIFOC_PSC6_RX_SIZE | (FIFOC_PSC6_RX_ADDR << 16);
+		break;
+	case 7:
+		tfsize = FIFOC_PSC7_TX_SIZE | (FIFOC_PSC7_TX_ADDR << 16);
+		rfsize = FIFOC_PSC7_RX_SIZE | (FIFOC_PSC7_RX_ADDR << 16);
+		break;
+	case 8:
+		tfsize = FIFOC_PSC8_TX_SIZE | (FIFOC_PSC8_TX_ADDR << 16);
+		rfsize = FIFOC_PSC8_RX_SIZE | (FIFOC_PSC8_RX_ADDR << 16);
+		break;
+	case 9:
+		tfsize = FIFOC_PSC9_TX_SIZE | (FIFOC_PSC9_TX_ADDR << 16);
+		rfsize = FIFOC_PSC9_RX_SIZE | (FIFOC_PSC9_RX_ADDR << 16);
+		break;
+	case 10:
+		tfsize = FIFOC_PSC10_TX_SIZE | (FIFOC_PSC10_TX_ADDR << 16);
+		rfsize = FIFOC_PSC10_RX_SIZE | (FIFOC_PSC10_RX_ADDR << 16);
+		break;
+	case 11:
+		tfsize = FIFOC_PSC11_TX_SIZE | (FIFOC_PSC11_TX_ADDR << 16);
+		rfsize = FIFOC_PSC11_RX_SIZE | (FIFOC_PSC11_RX_ADDR << 16);
+		break;
+	default:
+		return;
+	}
+#else
+	tfsize = CONSOLE_FIFO_TX_SIZE | (CONSOLE_FIFO_TX_ADDR << 16);
+	rfsize = CONSOLE_FIFO_RX_SIZE | (CONSOLE_FIFO_RX_ADDR << 16);
+#endif
+	out_be32(&psc->tfsize, tfsize);
+	out_be32(&psc->rfsize, rfsize);
+
+	/* enable Tx & Rx FIFO slice */
+	out_be32(&psc->rfcmd, PSC_FIFO_ENABLE_SLICE);
+	out_be32(&psc->tfcmd, PSC_FIFO_ENABLE_SLICE);
+
+	out_be32(&im->fifoc.fifoc_cmd, FIFOC_DISABLE_CLOCK_GATE);
+	__asm__ volatile ("sync");
+}
+
+void serial_setbrg_dev(unsigned int idx)
+{
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
+	unsigned long baseclk, div;
+	unsigned long baudrate;
+	char buf[16];
+	char *br_env;
+
+	baudrate = gd->baudrate;
+	if (idx != CONFIG_PSC_CONSOLE) {
+		/* Allows setting baudrate for other serial devices
+		 * on PSCx using environment. If not specified, use
+		 * the same baudrate as for console.
+		 */
+		sprintf(buf, "psc%d_baudrate", idx);
+		br_env = getenv(buf);
+		if (br_env)
+			baudrate = simple_strtoul(br_env, NULL, 10);
+
+		debug("%s: idx %d, baudrate %d\n", __func__, idx, baudrate);
+	}
+
+	/* calculate divisor for setting PSC CTUR and CTLR registers */
+	baseclk = (gd->ips_clk + 8) / 16;
+	div = (baseclk + (baudrate / 2)) / baudrate;
+
+	out_8(&psc->ctur, (div >> 8) & 0xff);
+	out_8(&psc->ctlr,  div & 0xff); /* set baudrate */
+}
+
+int serial_init_dev(unsigned int idx)
+{
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
+#if defined(CONFIG_SERIAL_MULTI)
+	u32 reg;
+
+	reg = in_be32(&im->clk.sccr[0]);
+	out_be32(&im->clk.sccr[0], reg | CLOCK_SCCR1_PSC_EN(idx));
+#endif
+
+	fifo_init (psc);
+
+	/* set MR register to point to MR1 */
+	out_8(&psc->command, PSC_SEL_MODE_REG_1);
+
+	/* disable Tx/Rx */
+	out_8(&psc->command, PSC_TX_DISABLE | PSC_RX_DISABLE);
+
+	/* choose the prescaler	by 16 for the Tx/Rx clock generation */
+	out_be16(&psc->psc_clock_select, 0xdd00);
+
+	/* switch to UART mode */
+	out_be32(&psc->sicr, 0);
+
+	/* mode register points to mr1 */
+	/* configure parity, bit length and so on in mode register 1*/
+	out_8(&psc->mode, PSC_MODE_8_BITS | PSC_MODE_PARNONE);
+	/* now, mode register points to mr2 */
+	out_8(&psc->mode, PSC_MODE_1_STOPBIT);
+
+	/* set baudrate */
+	serial_setbrg_dev(idx);
+
+	/* disable all interrupts */
+	out_be16(&psc->psc_imr, 0);
+
+	/* reset and enable Rx/Tx */
+	out_8(&psc->command, PSC_RST_RX);
+	out_8(&psc->command, PSC_RST_TX);
+	out_8(&psc->command, PSC_RX_ENABLE | PSC_TX_ENABLE);
+
+	return 0;
+}
+
+int serial_uninit_dev(unsigned int idx)
+{
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
+	u32 reg;
+
+	out_8(&psc->command, PSC_RX_DISABLE | PSC_TX_DISABLE);
+	reg = in_be32(&im->clk.sccr[0]);
+	reg &= ~CLOCK_SCCR1_PSC_EN(idx);
+	out_be32(&im->clk.sccr[0], reg);
+
+	return 0;
+}
+
+void serial_putc_dev(unsigned int idx, const char c)
+{
+	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
+
+	if (c == '\n')
+		serial_putc_dev(idx, '\r');
+
+	/* Wait for last character to go. */
+	while (!(in_be16(&psc->psc_status) & PSC_SR_TXEMP))
+		;
+
+	out_8(&psc->tfdata_8, c);
+}
+
+void serial_putc_raw_dev(unsigned int idx, const char c)
+{
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
+
+	/* Wait for last character to go. */
+	while (!(in_be16(&psc->psc_status) & PSC_SR_TXEMP))
+		;
+
+	out_8(&psc->tfdata_8, c);
+}
+
+void serial_puts_dev(unsigned int idx, const char *s)
+{
+	while (*s)
+		serial_putc_dev(idx, *s++);
+}
+
+int serial_getc_dev(unsigned int idx)
+{
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
+
+	/* Wait for a character to arrive. */
+	while (in_be32(&psc->rfstat) & PSC_FIFO_EMPTY)
+		;
+
+	return in_8(&psc->rfdata_8);
+}
+
+int serial_tstc_dev(unsigned int idx)
+{
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
+
+	return !(in_be32(&psc->rfstat) & PSC_FIFO_EMPTY);
+}
+
+void serial_setrts_dev(unsigned int idx, int s)
+{
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
+
+	if (s) {
+		/* Assert RTS (become LOW) */
+		out_8(&psc->op1, 0x1);
+	}
+	else {
+		/* Negate RTS (become HIGH) */
+		out_8(&psc->op0, 0x1);
+	}
+}
+
+int serial_getcts_dev(unsigned int idx)
+{
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
+
+	return (in_8(&psc->ip) & 0x1) ? 0 : 1;
+}
+#endif /* CONFIG_PSC_CONSOLE || CONFIG_SERIAL_MULTI */
+
+#if defined(CONFIG_SERIAL_MULTI)
+
+#define DECLARE_PSC_SERIAL_FUNCTIONS(port) \
+	int serial##port##_init(void) \
+	{ \
+		return serial_init_dev(port); \
+	} \
+	int serial##port##_uninit(void) \
+	{ \
+		return serial_uninit_dev(port); \
+	} \
+	void serial##port##_setbrg(void) \
+	{ \
+		serial_setbrg_dev(port); \
+	} \
+	int serial##port##_getc(void) \
+	{ \
+		return serial_getc_dev(port); \
+	} \
+	int serial##port##_tstc(void) \
+	{ \
+		return serial_tstc_dev(port); \
+	} \
+	void serial##port##_putc(const char c) \
+	{ \
+		serial_putc_dev(port, c); \
+	} \
+	void serial##port##_puts(const char *s) \
+	{ \
+		serial_puts_dev(port, s); \
+	}
+
+#define INIT_PSC_SERIAL_STRUCTURE(port, name, bus) { \
+	name, \
+	bus, \
+	serial##port##_init, \
+	serial##port##_uninit, \
+	serial##port##_setbrg, \
+	serial##port##_getc, \
+	serial##port##_tstc, \
+	serial##port##_putc, \
+	serial##port##_puts, \
+}
+
+#if defined(CONFIG_SYS_PSC1)
+DECLARE_PSC_SERIAL_FUNCTIONS(1);
+struct serial_device serial1_device =
+INIT_PSC_SERIAL_STRUCTURE(1, "psc1", "UART1");
+#endif
+
+#if defined(CONFIG_SYS_PSC3)
+DECLARE_PSC_SERIAL_FUNCTIONS(3);
+struct serial_device serial3_device =
+INIT_PSC_SERIAL_STRUCTURE(3, "psc3", "UART3");
+#endif
+
+#if defined(CONFIG_SYS_PSC4)
+DECLARE_PSC_SERIAL_FUNCTIONS(4);
+struct serial_device serial4_device =
+INIT_PSC_SERIAL_STRUCTURE(4, "psc4", "UART4");
+#endif
+
+#if defined(CONFIG_SYS_PSC6)
+DECLARE_PSC_SERIAL_FUNCTIONS(6);
+struct serial_device serial6_device =
+INIT_PSC_SERIAL_STRUCTURE(6, "psc6", "UART6");
+#endif
+
+#else
+
+void serial_setbrg(void)
+{
+	serial_setbrg_dev(CONFIG_PSC_CONSOLE);
+}
+
+int serial_init(void)
+{
+	return serial_init_dev(CONFIG_PSC_CONSOLE);
+}
+
+void serial_putc(const char c)
+{
+	serial_putc_dev(CONFIG_PSC_CONSOLE, c);
+}
+
+void serial_putc_raw(const char c)
+{
+	serial_putc_raw_dev(CONFIG_PSC_CONSOLE, c);
+}
+
+void serial_puts(const char *s)
+{
+	serial_puts_dev(CONFIG_PSC_CONSOLE, s);
+}
+
+int serial_getc(void)
+{
+	return serial_getc_dev(CONFIG_PSC_CONSOLE);
+}
+
+int serial_tstc(void)
+{
+	return serial_tstc_dev(CONFIG_PSC_CONSOLE);
+}
+
+void serial_setrts(int s)
+{
+	return serial_setrts_dev(CONFIG_PSC_CONSOLE, s);
+}
+
+int serial_getcts(void)
+{
+	return serial_getcts_dev(CONFIG_PSC_CONSOLE);
+}
+#endif /* CONFIG_PSC_CONSOLE */
+
+#if defined(CONFIG_SERIAL_MULTI)
+#include <stdio_dev.h>
+/*
+ * Routines for communication with serial devices over PSC
+ */
+/* Bitfield for initialized PSCs */
+static unsigned int initialized;
+
+struct stdio_dev *open_port(int num, int baudrate)
+{
+	struct stdio_dev *port;
+	char env_var[16];
+	char env_val[10];
+	char name[7];
+
+	if (num < 0 || num > 11)
+		return NULL;
+
+	sprintf(name, "psc%d", num);
+	port = stdio_get_by_name(name);
+	if (!port)
+		return NULL;
+
+	if (!test_bit(num, &initialized)) {
+		sprintf(env_var, "psc%d_baudrate", num);
+		sprintf(env_val, "%d", baudrate);
+		setenv(env_var, env_val);
+
+		if (port->start())
+			return NULL;
+
+		set_bit(num, &initialized);
+	}
+
+	return port;
+}
+
+int close_port(int num)
+{
+	struct stdio_dev *port;
+	int ret;
+	char name[7];
+
+	if (num < 0 || num > 11)
+		return -1;
+
+	sprintf(name, "psc%d", num);
+	port = stdio_get_by_name(name);
+	if (!port)
+		return -1;
+
+	ret = port->stop();
+	clear_bit(num, &initialized);
+
+	return ret;
+}
+
+int write_port(struct stdio_dev *port, char *buf)
+{
+	if (!port || !buf)
+		return -1;
+
+	port->puts(buf);
+
+	return 0;
+}
+
+int read_port(struct stdio_dev *port, char *buf, int size)
+{
+	int cnt = 0;
+
+	if (!port || !buf)
+		return -1;
+
+	if (!size)
+		return 0;
+
+	while (port->tstc()) {
+		buf[cnt++] = port->getc();
+		if (cnt > size)
+			break;
+	}
+
+	return cnt;
+}
+#endif /* CONFIG_SERIAL_MULTI */

arch/powerpc/cpu/mpc512x/u-boot.lds

@@ -49,7 +49,7 @@ SECTIONS
   .plt : { *(.plt) }
   .text      :
   {
-    arch/ppc/cpu/mpc512x/start.o	(.text)
+    arch/powerpc/cpu/mpc512x/start.o	(.text)
     *(.text)
     *(.got1)
     . = ALIGN(16);

arch/powerpc/cpu/mpc5xx/Makefile

@@ -25,11 +25,11 @@
 #
 
 #
-# File:			arch/ppc/cpu/mpc5xx/Makefile
+# File:			arch/powerpc/cpu/mpc5xx/Makefile
 #
 # Discription:		Makefile to build mpc5xx cpu configuration.
 #			Will include top config.mk which itselfs
-#			uses the definitions made in arch/ppc/cpu/mpc5xx/config.mk
+#			uses the definitions made in arch/powerpc/cpu/mpc5xx/config.mk
 #
 
 

arch/powerpc/cpu/mpc5xx/config.mk

@@ -33,4 +33,4 @@ PLATFORM_RELFLAGS +=	-fPIC -meabi
 PLATFORM_CPPFLAGS +=	-DCONFIG_5xx -ffixed-r2 -mpowerpc -msoft-float
 
 # Use default linker script.  Board port can override in board/*/config.mk
-LDSCRIPT := $(SRCTREE)/arch/ppc/cpu/mpc5xx/u-boot.lds
+LDSCRIPT := $(SRCTREE)/arch/powerpc/cpu/mpc5xx/u-boot.lds

arch/powerpc/cpu/mpc5xx/traps.c

@@ -1,5 +1,5 @@
 /*
- * linux/arch/ppc/kernel/traps.c
+ * linux/arch/powerpc/kernel/traps.c
  *
  * Copyright (C) 1995-1996  Gary Thomas (gdt@linuxppc.org)
  *

arch/powerpc/cpu/mpc5xx/u-boot.lds

@@ -55,7 +55,7 @@ SECTIONS
     /* WARNING - the following is hand-optimized to fit within	*/
     /* the sector layout of our flash chips!	XXX FIXME XXX	*/
 
-    arch/ppc/cpu/mpc5xx/start.o	(.text)
+    arch/powerpc/cpu/mpc5xx/start.o	(.text)
 
     *(.text)
     *(.got1)

arch/powerpc/cpu/mpc5xxx/config.mk

@@ -27,4 +27,4 @@ PLATFORM_CPPFLAGS += -DCONFIG_MPC5xxx -ffixed-r2 \
 		     -mstring -mcpu=603e -mmultiple
 
 # Use default linker script.  Board port can override in board/*/config.mk
-LDSCRIPT := $(SRCTREE)/arch/ppc/cpu/mpc5xxx/u-boot.lds
+LDSCRIPT := $(SRCTREE)/arch/powerpc/cpu/mpc5xxx/u-boot.lds

arch/powerpc/cpu/mpc5xxx/interrupts.c

@@ -27,7 +27,7 @@
  * MA 02111-1307 USA
  */
 
-/* this section was ripped out of arch/ppc/syslib/mpc52xx_pic.c in the
+/* this section was ripped out of arch/powerpc/syslib/mpc52xx_pic.c in the
  * Linux 2.6 source with the following copyright.
  *
  * Based on (well, mostly copied from) the code from the 2.4 kernel by

arch/powerpc/cpu/mpc5xxx/serial.c

@@ -21,7 +21,7 @@
  * MA 02111-1307 USA
  *
  * Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 19-Oct-00, with
- * changes based on the file arch/ppc/mbxboot/m8260_tty.c from the
+ * changes based on the file arch/powerpc/mbxboot/m8260_tty.c from the
  * Linux/PPC sources (m8260_tty.c had no copyright info in it).
  *
  * Martin Krause, 8 Jun 2006
@@ -340,6 +340,7 @@ struct serial_device serial0_device =
 	"serial0",
 	"UART0",
 	serial0_init,
+	NULL,
 	serial0_setbrg,
 	serial0_getc,
 	serial0_tstc,
@@ -352,6 +353,7 @@ struct serial_device serial1_device =
 	"serial1",
 	"UART1",
 	serial1_init,
+	NULL,
 	serial1_setbrg,
 	serial1_getc,
 	serial1_tstc,

arch/powerpc/cpu/mpc5xxx/start.S

@@ -442,7 +442,7 @@ init_5xxx_core:
 	/*								*/
 	/* bits 15-19 correspond to addresses 0x00000000 to 0x0001F000	*/
 	/* incrementing by 0x1000 each time. The code below is sort of	*/
-	/* based on code in "flush_tlbs" from arch/ppc/kernel/head.S	*/
+	/* based on code in "flush_tlbs" from arch/powerpc/kernel/head.S	*/
 	/*								*/
 	/*--------------------------------------------------------------*/
 

arch/powerpc/cpu/mpc5xxx/traps.c

@@ -1,5 +1,5 @@
 /*
- * linux/arch/ppc/kernel/traps.c
+ * linux/arch/powerpc/kernel/traps.c
  *
  * Copyright (C) 1995-1996  Gary Thomas (gdt@linuxppc.org)
  *

arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds

@@ -55,11 +55,11 @@ SECTIONS
     /* WARNING - the following is hand-optimized to fit within  */
     /* the sector layout of our flash chips!    XXX FIXME XXX   */
 
-    arch/ppc/cpu/mpc5xxx/start.o          (.text)
-    arch/ppc/cpu/mpc5xxx/traps.o          (.text)
+    arch/powerpc/cpu/mpc5xxx/start.o          (.text)
+    arch/powerpc/cpu/mpc5xxx/traps.o          (.text)
     lib/crc32.o         (.text)
-    arch/ppc/lib/cache.o             (.text)
-    arch/ppc/lib/time.o              (.text)
+    arch/powerpc/lib/cache.o             (.text)
+    arch/powerpc/lib/time.o              (.text)
 
     . = DEFINED(env_offset) ? env_offset : .;
     common/env_embedded.o        (.ppcenv)

arch/powerpc/cpu/mpc5xxx/u-boot.lds

@@ -52,7 +52,7 @@ SECTIONS
   .plt : { *(.plt) }
   .text      :
   {
-    arch/ppc/cpu/mpc5xxx/start.o	(.text)
+    arch/powerpc/cpu/mpc5xxx/start.o	(.text)
     *(.text)
     *(.got1)
     . = ALIGN(16);

arch/powerpc/cpu/mpc8220/config.mk

@@ -27,4 +27,4 @@ PLATFORM_CPPFLAGS += -DCONFIG_MPC8220 -ffixed-r2 \
 		     -mstring -mcpu=603e -mmultiple
 
 # Use default linker script.  Board port can override in board/*/config.mk
-LDSCRIPT := $(SRCTREE)/arch/ppc/cpu/mpc8220/u-boot.lds
+LDSCRIPT := $(SRCTREE)/arch/powerpc/cpu/mpc8220/u-boot.lds

arch/powerpc/cpu/mpc8220/start.S

@@ -419,7 +419,7 @@ init_8220_core:
 	/*								*/
 	/* bits 15-19 correspond to addresses 0x00000000 to 0x0001F000	*/
 	/* incrementing by 0x1000 each time. The code below is sort of	*/
-	/* based on code in "flush_tlbs" from arch/ppc/kernel/head.S	*/
+	/* based on code in "flush_tlbs" from arch/powerpc/kernel/head.S	*/
 	/*								*/
 	/*--------------------------------------------------------------*/