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board: Add Toby-Churchill SL50 board support.
Add support for Lightwriter SL50 series board, a small, robust and portable Voice Output Communication Aids (VOCA) designed to meet the particular and changing needs of people with speech loss resulting from a wide range of acquired, progressive and congenital conditions. Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
This commit is contained in:
Enric Balletbò i Serra
Tom Rini
parent
aa46b408a5
commit
9d1b298799
9 changed files with 768 additions and 0 deletions
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@ -363,6 +363,13 @@ config TARGET_AM335X_EVM
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select DM_SERIAL
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select DM_SERIAL
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select DM_GPIO
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select DM_GPIO
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config TARGET_AM335X_SL50
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bool "Support am335x_sl50"
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select CPU_V7
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select SUPPORT_SPL
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select DM
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select DM_SERIAL
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config TARGET_AM43XX_EVM
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config TARGET_AM43XX_EVM
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bool "Support am43xx_evm"
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bool "Support am43xx_evm"
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select CPU_V7
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select CPU_V7
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@ -755,6 +762,7 @@ source "board/st/stm32f429-discovery/Kconfig"
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source "board/st/stv0991/Kconfig"
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source "board/st/stv0991/Kconfig"
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source "board/sunxi/Kconfig"
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source "board/sunxi/Kconfig"
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source "board/syteco/zmx25/Kconfig"
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source "board/syteco/zmx25/Kconfig"
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source "board/tcl/sl50/Kconfig"
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source "board/ti/am335x/Kconfig"
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source "board/ti/am335x/Kconfig"
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source "board/ti/am43xx/Kconfig"
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source "board/ti/am43xx/Kconfig"
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source "board/birdland/bav335x/Kconfig"
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source "board/birdland/bav335x/Kconfig"
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31
board/tcl/sl50/Kconfig
Normal file
31
board/tcl/sl50/Kconfig
Normal file
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@ -0,0 +1,31 @@
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if TARGET_AM335X_SL50
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config SYS_BOARD
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default "sl50"
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config SYS_VENDOR
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default "tcl"
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config SYS_SOC
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default "am33xx"
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config SYS_CONFIG_NAME
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default "am335x_sl50"
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config CONS_INDEX
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int "UART used for console"
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range 1 6
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default 1
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help
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The AM335x SoC has a total of 6 UARTs (UART0 to UART5 as referenced
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in documentation, etc) available to it. Depending on your specific
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board you may want something other than UART0 as for example the IDK
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uses UART3 so enter 4 here.
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config DM_GPIO
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default y
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config DM_SERIAL
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default y
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endif
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6
board/tcl/sl50/MAINTAINERS
Normal file
6
board/tcl/sl50/MAINTAINERS
Normal file
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@ -0,0 +1,6 @@
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SL50 BOARD
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M: Enric Balletbo i Serra <enric.balletbo@collabora.com>
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S: Maintained
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F: board/tcl/sl50/
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F: include/configs/am335x_sl50.h
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F: configs/am335x_sl50_defconfig
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13
board/tcl/sl50/Makefile
Normal file
13
board/tcl/sl50/Makefile
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@ -0,0 +1,13 @@
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#
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# Makefile
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#
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# Copyright (C) 2015 Toby Churchill Ltd - http://www.toby-churchill.com/
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
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obj-y := mux.o
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endif
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obj-y += board.o
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386
board/tcl/sl50/board.c
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386
board/tcl/sl50/board.c
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@ -0,0 +1,386 @@
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/*
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* board.c
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*
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* Board functions for TCL SL50 board
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*
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* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <errno.h>
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#include <spl.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/omap.h>
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#include <asm/arch/ddr_defs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/mmc_host_def.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/mem.h>
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#include <asm/io.h>
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#include <asm/emif.h>
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#include <asm/gpio.h>
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#include <i2c.h>
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#include <miiphy.h>
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#include <cpsw.h>
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#include <power/tps65217.h>
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#include <power/tps65910.h>
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#include <environment.h>
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#include <watchdog.h>
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#include <environment.h>
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#include "board.h"
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DECLARE_GLOBAL_DATA_PTR;
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static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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static const struct ddr_data ddr3_sl50_data = {
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.datardsratio0 = MT41K256M16HA125E_RD_DQS,
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.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
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.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
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.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
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};
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static const struct cmd_control ddr3_sl50_cmd_ctrl_data = {
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.cmd0csratio = MT41K256M16HA125E_RATIO,
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.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
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.cmd1csratio = MT41K256M16HA125E_RATIO,
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.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
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.cmd2csratio = MT41K256M16HA125E_RATIO,
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.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
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};
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static struct emif_regs ddr3_sl50_emif_reg_data = {
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.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
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.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
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.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
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.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
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.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
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.zq_config = MT41K256M16HA125E_ZQ_CFG,
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.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
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};
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#ifdef CONFIG_SPL_OS_BOOT
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int spl_start_uboot(void)
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{
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/* break into full u-boot on 'c' */
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if (serial_tstc() && serial_getc() == 'c')
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return 1;
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#ifdef CONFIG_SPL_ENV_SUPPORT
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env_init();
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env_relocate_spec();
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if (getenv_yesno("boot_os") != 1)
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return 1;
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#endif
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return 0;
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}
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#endif
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#define OSC (V_OSCK/1000000)
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const struct dpll_params dpll_ddr_sl50 = {
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400, OSC-1, 1, -1, -1, -1, -1};
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void am33xx_spl_board_init(void)
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{
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int mpu_vdd;
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/* Get the frequency */
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dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
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/* BeagleBone PMIC Code */
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int usb_cur_lim;
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if (i2c_probe(TPS65217_CHIP_PM))
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return;
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/*
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* Increase USB current limit to 1300mA or 1800mA and set
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* the MPU voltage controller as needed.
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*/
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if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
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usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
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mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
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} else {
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usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
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mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
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}
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if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
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TPS65217_POWER_PATH,
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usb_cur_lim,
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TPS65217_USB_INPUT_CUR_LIMIT_MASK))
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puts("tps65217_reg_write failure\n");
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/* Set DCDC3 (CORE) voltage to 1.125V */
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if (tps65217_voltage_update(TPS65217_DEFDCDC3,
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TPS65217_DCDC_VOLT_SEL_1125MV)) {
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puts("tps65217_voltage_update failure\n");
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return;
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}
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/* Set CORE Frequencies to OPP100 */
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do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
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/* Set DCDC2 (MPU) voltage */
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if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
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puts("tps65217_voltage_update failure\n");
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return;
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}
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/*
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* Set LDO3 to 1.8V and LDO4 to 3.3V
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*/
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if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
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TPS65217_DEFLS1,
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TPS65217_LDO_VOLTAGE_OUT_1_8,
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TPS65217_LDO_MASK))
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puts("tps65217_reg_write failure\n");
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if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
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TPS65217_DEFLS2,
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TPS65217_LDO_VOLTAGE_OUT_3_3,
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TPS65217_LDO_MASK))
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puts("tps65217_reg_write failure\n");
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/* Set MPU Frequency to what we detected now that voltages are set */
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do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
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}
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const struct dpll_params *get_dpll_ddr_params(void)
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{
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enable_i2c0_pin_mux();
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i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
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return &dpll_ddr_sl50;
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}
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void set_uart_mux_conf(void)
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{
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#if CONFIG_CONS_INDEX == 1
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enable_uart0_pin_mux();
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#elif CONFIG_CONS_INDEX == 2
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enable_uart1_pin_mux();
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#elif CONFIG_CONS_INDEX == 3
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enable_uart2_pin_mux();
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#elif CONFIG_CONS_INDEX == 4
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enable_uart3_pin_mux();
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#elif CONFIG_CONS_INDEX == 5
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enable_uart4_pin_mux();
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#elif CONFIG_CONS_INDEX == 6
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enable_uart5_pin_mux();
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#endif
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}
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void set_mux_conf_regs(void)
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{
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enable_board_pin_mux();
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}
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const struct ctrl_ioregs ioregs_evmsk = {
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.cm0ioctl = MT41J128MJT125_IOCTRL_VALUE,
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.cm1ioctl = MT41J128MJT125_IOCTRL_VALUE,
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.cm2ioctl = MT41J128MJT125_IOCTRL_VALUE,
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.dt0ioctl = MT41J128MJT125_IOCTRL_VALUE,
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.dt1ioctl = MT41J128MJT125_IOCTRL_VALUE,
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};
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const struct ctrl_ioregs ioregs_bonelt = {
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.cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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.cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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.cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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.dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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.dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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};
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const struct ctrl_ioregs ioregs_evm15 = {
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.cm0ioctl = MT41J512M8RH125_IOCTRL_VALUE,
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.cm1ioctl = MT41J512M8RH125_IOCTRL_VALUE,
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.cm2ioctl = MT41J512M8RH125_IOCTRL_VALUE,
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.dt0ioctl = MT41J512M8RH125_IOCTRL_VALUE,
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.dt1ioctl = MT41J512M8RH125_IOCTRL_VALUE,
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};
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const struct ctrl_ioregs ioregs = {
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.cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
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.cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
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.cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
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.dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
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.dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
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};
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void sdram_init(void)
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{
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config_ddr(400, &ioregs_bonelt,
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&ddr3_sl50_data,
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&ddr3_sl50_cmd_ctrl_data,
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&ddr3_sl50_emif_reg_data, 0);
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}
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#endif
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/*
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* Basic board specific setup. Pinmux has been handled already.
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*/
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int board_init(void)
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{
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#if defined(CONFIG_HW_WATCHDOG)
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hw_watchdog_init();
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#endif
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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return 0;
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}
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#ifdef CONFIG_BOARD_LATE_INIT
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int board_late_init(void)
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{
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return 0;
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}
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#endif
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#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
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(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
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static void cpsw_control(int enabled)
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{
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/* VTP can be added here */
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return;
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}
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static struct cpsw_slave_data cpsw_slaves[] = {
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{
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.slave_reg_ofs = 0x208,
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.sliver_reg_ofs = 0xd80,
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.phy_addr = 0,
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},
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{
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.slave_reg_ofs = 0x308,
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.sliver_reg_ofs = 0xdc0,
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.phy_addr = 1,
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},
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};
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static struct cpsw_platform_data cpsw_data = {
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.mdio_base = CPSW_MDIO_BASE,
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.cpsw_base = CPSW_BASE,
|
||||||
|
.mdio_div = 0xff,
|
||||||
|
.channels = 8,
|
||||||
|
.cpdma_reg_ofs = 0x800,
|
||||||
|
.slaves = 1,
|
||||||
|
.slave_data = cpsw_slaves,
|
||||||
|
.ale_reg_ofs = 0xd00,
|
||||||
|
.ale_entries = 1024,
|
||||||
|
.host_port_reg_ofs = 0x108,
|
||||||
|
.hw_stats_reg_ofs = 0x900,
|
||||||
|
.bd_ram_ofs = 0x2000,
|
||||||
|
.mac_control = (1 << 5),
|
||||||
|
.control = cpsw_control,
|
||||||
|
.host_port_num = 0,
|
||||||
|
.version = CPSW_CTRL_VERSION_2,
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
* This function will:
|
||||||
|
* Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr
|
||||||
|
* in the environment
|
||||||
|
* Perform fixups to the PHY present on certain boards. We only need this
|
||||||
|
* function in:
|
||||||
|
* - SPL with either CPSW or USB ethernet support
|
||||||
|
* - Full U-Boot, with either CPSW or USB ethernet
|
||||||
|
* Build in only these cases to avoid warnings about unused variables
|
||||||
|
* when we build an SPL that has neither option but full U-Boot will.
|
||||||
|
*/
|
||||||
|
#if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) \
|
||||||
|
&& defined(CONFIG_SPL_BUILD)) || \
|
||||||
|
((defined(CONFIG_DRIVER_TI_CPSW) || \
|
||||||
|
defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \
|
||||||
|
!defined(CONFIG_SPL_BUILD))
|
||||||
|
int board_eth_init(bd_t *bis)
|
||||||
|
{
|
||||||
|
int rv, n = 0;
|
||||||
|
uint8_t mac_addr[6];
|
||||||
|
uint32_t mac_hi, mac_lo;
|
||||||
|
|
||||||
|
/* try reading mac address from efuse */
|
||||||
|
mac_lo = readl(&cdev->macid0l);
|
||||||
|
mac_hi = readl(&cdev->macid0h);
|
||||||
|
mac_addr[0] = mac_hi & 0xFF;
|
||||||
|
mac_addr[1] = (mac_hi & 0xFF00) >> 8;
|
||||||
|
mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
|
||||||
|
mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
|
||||||
|
mac_addr[4] = mac_lo & 0xFF;
|
||||||
|
mac_addr[5] = (mac_lo & 0xFF00) >> 8;
|
||||||
|
|
||||||
|
#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
|
||||||
|
(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
|
||||||
|
if (!getenv("ethaddr")) {
|
||||||
|
printf("<ethaddr> not set. Validating first E-fuse MAC\n");
|
||||||
|
|
||||||
|
if (is_valid_ethaddr(mac_addr))
|
||||||
|
eth_setenv_enetaddr("ethaddr", mac_addr);
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef CONFIG_DRIVER_TI_CPSW
|
||||||
|
|
||||||
|
mac_lo = readl(&cdev->macid1l);
|
||||||
|
mac_hi = readl(&cdev->macid1h);
|
||||||
|
mac_addr[0] = mac_hi & 0xFF;
|
||||||
|
mac_addr[1] = (mac_hi & 0xFF00) >> 8;
|
||||||
|
mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
|
||||||
|
mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
|
||||||
|
mac_addr[4] = mac_lo & 0xFF;
|
||||||
|
mac_addr[5] = (mac_lo & 0xFF00) >> 8;
|
||||||
|
|
||||||
|
if (!getenv("eth1addr")) {
|
||||||
|
if (is_valid_ethaddr(mac_addr))
|
||||||
|
eth_setenv_enetaddr("eth1addr", mac_addr);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
writel(MII_MODE_ENABLE, &cdev->miisel);
|
||||||
|
cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
|
||||||
|
PHY_INTERFACE_MODE_MII;
|
||||||
|
|
||||||
|
rv = cpsw_register(&cpsw_data);
|
||||||
|
if (rv < 0)
|
||||||
|
printf("Error %d registering CPSW switch\n", rv);
|
||||||
|
else
|
||||||
|
n += rv;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
*
|
||||||
|
* CPSW RGMII Internal Delay Mode is not supported in all PVT
|
||||||
|
* operating points. So we must set the TX clock delay feature
|
||||||
|
* in the AR8051 PHY. Since we only support a single ethernet
|
||||||
|
* device in U-Boot, we only do this for the first instance.
|
||||||
|
*/
|
||||||
|
#define AR8051_PHY_DEBUG_ADDR_REG 0x1d
|
||||||
|
#define AR8051_PHY_DEBUG_DATA_REG 0x1e
|
||||||
|
#define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5
|
||||||
|
#define AR8051_RGMII_TX_CLK_DLY 0x100
|
||||||
|
|
||||||
|
#endif
|
||||||
|
#if defined(CONFIG_USB_ETHER) && \
|
||||||
|
(!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))
|
||||||
|
if (is_valid_ether_addr(mac_addr))
|
||||||
|
eth_setenv_enetaddr("usbnet_devaddr", mac_addr);
|
||||||
|
|
||||||
|
rv = usb_eth_initialize(bis);
|
||||||
|
if (rv < 0)
|
||||||
|
printf("Error %d registering USB_ETHER\n", rv);
|
||||||
|
else
|
||||||
|
n += rv;
|
||||||
|
#endif
|
||||||
|
return n;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
22
board/tcl/sl50/board.h
Normal file
22
board/tcl/sl50/board.h
Normal file
|
|
@ -0,0 +1,22 @@
|
||||||
|
/*
|
||||||
|
* board.h
|
||||||
|
*
|
||||||
|
* TCL SL50 boards information header
|
||||||
|
*
|
||||||
|
* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: GPL-2.0+
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _BOARD_H_
|
||||||
|
#define _BOARD_H_
|
||||||
|
|
||||||
|
void enable_uart0_pin_mux(void);
|
||||||
|
void enable_uart1_pin_mux(void);
|
||||||
|
void enable_uart2_pin_mux(void);
|
||||||
|
void enable_uart3_pin_mux(void);
|
||||||
|
void enable_uart4_pin_mux(void);
|
||||||
|
void enable_uart5_pin_mux(void);
|
||||||
|
void enable_i2c0_pin_mux(void);
|
||||||
|
void enable_board_pin_mux(void);
|
||||||
|
#endif
|
||||||
154
board/tcl/sl50/mux.c
Normal file
154
board/tcl/sl50/mux.c
Normal file
|
|
@ -0,0 +1,154 @@
|
||||||
|
/*
|
||||||
|
* mux.c
|
||||||
|
*
|
||||||
|
* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: GPL-2.0+
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <common.h>
|
||||||
|
#include <asm/arch/sys_proto.h>
|
||||||
|
#include <asm/arch/hardware.h>
|
||||||
|
#include <asm/arch/mux.h>
|
||||||
|
#include <asm/io.h>
|
||||||
|
#include <i2c.h>
|
||||||
|
#include "board.h"
|
||||||
|
|
||||||
|
static struct module_pin_mux uart0_pin_mux[] = {
|
||||||
|
{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
|
||||||
|
{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
|
||||||
|
{-1},
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct module_pin_mux uart1_pin_mux[] = {
|
||||||
|
{OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */
|
||||||
|
{OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */
|
||||||
|
{-1},
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct module_pin_mux uart2_pin_mux[] = {
|
||||||
|
{OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */
|
||||||
|
{OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */
|
||||||
|
{-1},
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct module_pin_mux uart3_pin_mux[] = {
|
||||||
|
{OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */
|
||||||
|
{OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */
|
||||||
|
{-1},
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct module_pin_mux uart4_pin_mux[] = {
|
||||||
|
{OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */
|
||||||
|
{OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)}, /* UART4_TXD */
|
||||||
|
{-1},
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct module_pin_mux uart5_pin_mux[] = {
|
||||||
|
{OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)}, /* UART5_RXD */
|
||||||
|
{OFFSET(lcd_data8), (MODE(4) | PULLUDEN)}, /* UART5_TXD */
|
||||||
|
{-1},
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct module_pin_mux mmc0_pin_mux[] = {
|
||||||
|
{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
|
||||||
|
{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
|
||||||
|
{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
|
||||||
|
{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
|
||||||
|
{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
|
||||||
|
{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
|
||||||
|
{OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */
|
||||||
|
{OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
|
||||||
|
{-1},
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct module_pin_mux mmc1_pin_mux[] = {
|
||||||
|
{OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
|
||||||
|
{OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */
|
||||||
|
{OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */
|
||||||
|
{OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */
|
||||||
|
{OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */
|
||||||
|
{OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */
|
||||||
|
{OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */
|
||||||
|
{OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_CD */
|
||||||
|
{-1},
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct module_pin_mux i2c0_pin_mux[] = {
|
||||||
|
{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
|
||||||
|
PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
|
||||||
|
{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
|
||||||
|
PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
|
||||||
|
{-1},
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct module_pin_mux i2c1_pin_mux[] = {
|
||||||
|
{OFFSET(spi0_d1), (MODE(2) | RXACTIVE |
|
||||||
|
PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
|
||||||
|
{OFFSET(spi0_cs0), (MODE(2) | RXACTIVE |
|
||||||
|
PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
|
||||||
|
{-1},
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct module_pin_mux mii1_pin_mux[] = {
|
||||||
|
{OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
|
||||||
|
{OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
|
||||||
|
{OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
|
||||||
|
{OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
|
||||||
|
{OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */
|
||||||
|
{OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */
|
||||||
|
{OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */
|
||||||
|
{OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */
|
||||||
|
{OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */
|
||||||
|
{OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */
|
||||||
|
{OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */
|
||||||
|
{OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */
|
||||||
|
{OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */
|
||||||
|
{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
|
||||||
|
{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
|
||||||
|
{-1},
|
||||||
|
};
|
||||||
|
|
||||||
|
|
||||||
|
void enable_uart0_pin_mux(void)
|
||||||
|
{
|
||||||
|
configure_module_pin_mux(uart0_pin_mux);
|
||||||
|
}
|
||||||
|
|
||||||
|
void enable_uart1_pin_mux(void)
|
||||||
|
{
|
||||||
|
configure_module_pin_mux(uart1_pin_mux);
|
||||||
|
}
|
||||||
|
|
||||||
|
void enable_uart2_pin_mux(void)
|
||||||
|
{
|
||||||
|
configure_module_pin_mux(uart2_pin_mux);
|
||||||
|
}
|
||||||
|
|
||||||
|
void enable_uart3_pin_mux(void)
|
||||||
|
{
|
||||||
|
configure_module_pin_mux(uart3_pin_mux);
|
||||||
|
}
|
||||||
|
|
||||||
|
void enable_uart4_pin_mux(void)
|
||||||
|
{
|
||||||
|
configure_module_pin_mux(uart4_pin_mux);
|
||||||
|
}
|
||||||
|
|
||||||
|
void enable_uart5_pin_mux(void)
|
||||||
|
{
|
||||||
|
configure_module_pin_mux(uart5_pin_mux);
|
||||||
|
}
|
||||||
|
|
||||||
|
void enable_i2c0_pin_mux(void)
|
||||||
|
{
|
||||||
|
configure_module_pin_mux(i2c0_pin_mux);
|
||||||
|
}
|
||||||
|
|
||||||
|
void enable_board_pin_mux(void)
|
||||||
|
{
|
||||||
|
configure_module_pin_mux(i2c1_pin_mux);
|
||||||
|
configure_module_pin_mux(mii1_pin_mux);
|
||||||
|
configure_module_pin_mux(mmc0_pin_mux);
|
||||||
|
configure_module_pin_mux(mmc1_pin_mux);
|
||||||
|
}
|
||||||
10
configs/am335x_sl50_defconfig
Normal file
10
configs/am335x_sl50_defconfig
Normal file
|
|
@ -0,0 +1,10 @@
|
||||||
|
CONFIG_ARM=y
|
||||||
|
CONFIG_TARGET_AM335X_SL50=y
|
||||||
|
CONFIG_SPL=y
|
||||||
|
CONFIG_SPL_STACK_R=y
|
||||||
|
CONFIG_SPL_STACK_R_ADDR=0x82000000
|
||||||
|
CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT"
|
||||||
|
CONFIG_CONS_INDEX=1
|
||||||
|
# CONFIG_CMD_IMLS is not set
|
||||||
|
# CONFIG_CMD_FLASH is not set
|
||||||
|
# CONFIG_CMD_SETEXPR is not set
|
||||||
138
include/configs/am335x_sl50.h
Normal file
138
include/configs/am335x_sl50.h
Normal file
|
|
@ -0,0 +1,138 @@
|
||||||
|
/*
|
||||||
|
* am335x_sl50.h
|
||||||
|
*
|
||||||
|
* Copyright (C) 2015 Toby Churchill Ltd - http://www.toby-churchill.com/
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: GPL-2.0+
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __CONFIG_AM335X_EVM_H
|
||||||
|
#define __CONFIG_AM335X_EVM_H
|
||||||
|
|
||||||
|
#include <configs/ti_am335x_common.h>
|
||||||
|
#undef CONFIG_BOOTDELAY
|
||||||
|
|
||||||
|
#ifndef CONFIG_SPL_BUILD
|
||||||
|
#ifndef CONFIG_FIT
|
||||||
|
# define CONFIG_FIT
|
||||||
|
#endif
|
||||||
|
# define CONFIG_TIMESTAMP
|
||||||
|
# define CONFIG_LZO
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define CONFIG_SYS_BOOTM_LEN (16 << 20)
|
||||||
|
|
||||||
|
/*#define CONFIG_MACH_TYPE 3589 Until the next sync */
|
||||||
|
#define CONFIG_BOARD_LATE_INIT
|
||||||
|
|
||||||
|
/* Clock Defines */
|
||||||
|
#define V_OSCK 24000000 /* Clock output from T2 */
|
||||||
|
#define V_SCLK (V_OSCK)
|
||||||
|
|
||||||
|
/* Always 128 KiB env size */
|
||||||
|
#define CONFIG_ENV_SIZE (128 << 10)
|
||||||
|
|
||||||
|
/* Enhance our eMMC support / experience. */
|
||||||
|
#define CONFIG_CMD_GPT
|
||||||
|
#define CONFIG_EFI_PARTITION
|
||||||
|
|
||||||
|
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
|
||||||
|
|
||||||
|
#ifndef CONFIG_SPL_BUILD
|
||||||
|
|
||||||
|
#include <config_distro_defaults.h>
|
||||||
|
|
||||||
|
#define MEM_LAYOUT_ENV_SETTINGS \
|
||||||
|
"scriptaddr=0x80000000\0" \
|
||||||
|
"pxefile_addr_r=0x80100000\0" \
|
||||||
|
"kernel_addr_r=0x82000000\0" \
|
||||||
|
"fdt_addr_r=0x88000000\0" \
|
||||||
|
"ramdisk_addr_r=0x88080000\0" \
|
||||||
|
|
||||||
|
#define BOOT_TARGET_DEVICES(func) \
|
||||||
|
func(MMC, mmc, 0) \
|
||||||
|
func(MMC, mmc, 1)
|
||||||
|
|
||||||
|
#define AM335XX_BOARD_FDTFILE \
|
||||||
|
"fdtfile=am335x-sl50.dtb\0" \
|
||||||
|
|
||||||
|
#include <config_distro_bootcmd.h>
|
||||||
|
|
||||||
|
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||||
|
AM335XX_BOARD_FDTFILE \
|
||||||
|
MEM_LAYOUT_ENV_SETTINGS \
|
||||||
|
BOOTENV
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* NS16550 Configuration */
|
||||||
|
#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */
|
||||||
|
#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */
|
||||||
|
#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */
|
||||||
|
#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */
|
||||||
|
#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */
|
||||||
|
#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
|
||||||
|
#define CONFIG_BAUDRATE 115200
|
||||||
|
|
||||||
|
#define CONFIG_CMD_EEPROM
|
||||||
|
#define CONFIG_ENV_EEPROM_IS_ON_I2C
|
||||||
|
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
|
||||||
|
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
|
||||||
|
#define CONFIG_SYS_I2C_MULTI_EEPROMS
|
||||||
|
|
||||||
|
/* PMIC support */
|
||||||
|
#define CONFIG_POWER_TPS65217
|
||||||
|
#define CONFIG_POWER_TPS65910
|
||||||
|
|
||||||
|
/* SPL */
|
||||||
|
#define CONFIG_SPL_POWER_SUPPORT
|
||||||
|
#define CONFIG_SPL_YMODEM_SUPPORT
|
||||||
|
|
||||||
|
/* Bootcount using the RTC block */
|
||||||
|
#define CONFIG_BOOTCOUNT_LIMIT
|
||||||
|
#define CONFIG_BOOTCOUNT_AM33XX
|
||||||
|
#define CONFIG_SYS_BOOTCOUNT_BE
|
||||||
|
|
||||||
|
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds"
|
||||||
|
|
||||||
|
#ifndef CONFIG_SPL_USBETH_SUPPORT
|
||||||
|
/* To support eMMC booting */
|
||||||
|
#define CONFIG_STORAGE_EMMC
|
||||||
|
#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USBETH_SUPPORT)
|
||||||
|
/* Remove other SPL modes. */
|
||||||
|
#undef CONFIG_SPL_YMODEM_SUPPORT
|
||||||
|
#undef CONFIG_SPL_NAND_SUPPORT
|
||||||
|
#undef CONFIG_SPL_MMC_SUPPORT
|
||||||
|
#define CONFIG_ENV_IS_NOWHERE
|
||||||
|
#undef CONFIG_ENV_IS_IN_NAND
|
||||||
|
/* disable host part of MUSB in SPL */
|
||||||
|
#undef CONFIG_MUSB_HOST
|
||||||
|
/* disable EFI partitions and partition UUID support */
|
||||||
|
#undef CONFIG_PARTITION_UUIDS
|
||||||
|
#undef CONFIG_EFI_PARTITION
|
||||||
|
/* General network SPL */
|
||||||
|
#define CONFIG_SPL_NET_SUPPORT
|
||||||
|
#define CONFIG_SPL_ENV_SUPPORT
|
||||||
|
#define CONFIG_SPL_NET_VCI_STRING "AM335x U-Boot SPL"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_EMMC_BOOT)
|
||||||
|
#undef CONFIG_ENV_IS_NOWHERE
|
||||||
|
#define CONFIG_ENV_IS_IN_MMC
|
||||||
|
#define CONFIG_SPL_ENV_SUPPORT
|
||||||
|
#define CONFIG_SYS_MMC_ENV_DEV 1
|
||||||
|
#define CONFIG_SYS_MMC_ENV_PART 2
|
||||||
|
#define CONFIG_ENV_OFFSET 0x0
|
||||||
|
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
|
||||||
|
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Network. */
|
||||||
|
#define CONFIG_PHY_GIGE
|
||||||
|
#define CONFIG_PHYLIB
|
||||||
|
#define CONFIG_PHY_SMSC
|
||||||
|
|
||||||
|
#endif /* ! __CONFIG_AM335X_SL50_H */
|
||||||
Loading…
Reference in a new issue