mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-24 21:54:01 +00:00
arm: sunxi: Enable DRAM ODT by default on H3/H5
Most of the boards we support with H3/H5 enable DRAM on-die termination, which is consistent with the high DRAM clocks that are used. Make it the default (like it's done for other similar platforms) instead of defining it in each defconfig. Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
This commit is contained in:
parent
882b71e47d
commit
9d0f9e8374
27 changed files with 8 additions and 19 deletions
|
@ -439,6 +439,7 @@ config DRAM_ZQ
|
|||
config DRAM_ODT_EN
|
||||
bool "sunxi dram odt enable"
|
||||
default y if MACH_SUN8I_A23
|
||||
default y if MACH_SUNXI_H3_H5
|
||||
default y if MACH_SUN8I_R40
|
||||
default y if MACH_SUN50I
|
||||
default y if MACH_SUN50I_H6
|
||||
|
|
|
@ -3,7 +3,6 @@ CONFIG_ARCH_SUNXI=y
|
|||
CONFIG_SPL=y
|
||||
CONFIG_MACH_SUN8I_H3=y
|
||||
CONFIG_DRAM_CLK=672
|
||||
CONFIG_DRAM_ODT_EN=y
|
||||
CONFIG_MACPWR="PD6"
|
||||
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
|
|
|
@ -3,7 +3,6 @@ CONFIG_ARCH_SUNXI=y
|
|||
CONFIG_SPL=y
|
||||
CONFIG_MACH_SUN50I_H5=y
|
||||
CONFIG_DRAM_CLK=672
|
||||
CONFIG_DRAM_ODT_EN=y
|
||||
CONFIG_MACPWR="PD6"
|
||||
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
|
|
|
@ -3,7 +3,6 @@ CONFIG_ARCH_SUNXI=y
|
|||
CONFIG_SPL=y
|
||||
CONFIG_MACH_SUN8I_H3=y
|
||||
CONFIG_DRAM_CLK=408
|
||||
CONFIG_DRAM_ODT_EN=y
|
||||
CONFIG_MMC0_CD_PIN=""
|
||||
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
|
|
|
@ -4,6 +4,7 @@ CONFIG_SPL=y
|
|||
CONFIG_MACH_SUN50I_H5=y
|
||||
CONFIG_DRAM_CLK=408
|
||||
CONFIG_DRAM_ZQ=3881977
|
||||
# CONFIG_DRAM_ODT_EN is not set
|
||||
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
|
||||
|
|
|
@ -3,7 +3,6 @@ CONFIG_ARCH_SUNXI=y
|
|||
CONFIG_SPL=y
|
||||
CONFIG_MACH_SUN8I_H3=y
|
||||
CONFIG_DRAM_CLK=672
|
||||
CONFIG_DRAM_ODT_EN=y
|
||||
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
|
||||
|
|
|
@ -3,7 +3,6 @@ CONFIG_ARCH_SUNXI=y
|
|||
CONFIG_SPL=y
|
||||
CONFIG_MACH_SUN8I_H3=y
|
||||
CONFIG_DRAM_CLK=672
|
||||
CONFIG_DRAM_ODT_EN=y
|
||||
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
|
||||
|
|
|
@ -3,7 +3,6 @@ CONFIG_ARCH_SUNXI=y
|
|||
CONFIG_SPL=y
|
||||
CONFIG_MACH_SUN50I_H5=y
|
||||
CONFIG_DRAM_CLK=672
|
||||
CONFIG_DRAM_ODT_EN=y
|
||||
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
|
||||
|
|
|
@ -3,7 +3,6 @@ CONFIG_ARCH_SUNXI=y
|
|||
CONFIG_SPL=y
|
||||
CONFIG_MACH_SUN8I_H3=y
|
||||
CONFIG_DRAM_CLK=408
|
||||
CONFIG_DRAM_ODT_EN=y
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
|
|
|
@ -3,7 +3,6 @@ CONFIG_ARCH_SUNXI=y
|
|||
CONFIG_SPL=y
|
||||
CONFIG_MACH_SUN8I_H3=y
|
||||
CONFIG_DRAM_CLK=408
|
||||
CONFIG_DRAM_ODT_EN=y
|
||||
CONFIG_MMC0_CD_PIN="PH13"
|
||||
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
|
|
|
@ -4,6 +4,7 @@ CONFIG_SPL=y
|
|||
CONFIG_MACH_SUN50I_H5=y
|
||||
CONFIG_DRAM_CLK=672
|
||||
CONFIG_DRAM_ZQ=3881977
|
||||
# CONFIG_DRAM_ODT_EN is not set
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
|
|
|
@ -3,7 +3,6 @@ CONFIG_ARCH_SUNXI=y
|
|||
CONFIG_SPL=y
|
||||
CONFIG_MACH_SUN8I_H3=y
|
||||
CONFIG_DRAM_CLK=408
|
||||
CONFIG_DRAM_ODT_EN=y
|
||||
# CONFIG_VIDEO_DE2 is not set
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
|
||||
|
|
|
@ -3,7 +3,6 @@ CONFIG_ARCH_SUNXI=y
|
|||
CONFIG_SPL=y
|
||||
CONFIG_MACH_SUN8I_H3=y
|
||||
CONFIG_DRAM_CLK=408
|
||||
CONFIG_DRAM_ODT_EN=y
|
||||
# CONFIG_VIDEO_DE2 is not set
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
|
||||
|
|
|
@ -4,6 +4,7 @@ CONFIG_SPL=y
|
|||
CONFIG_MACH_SUN50I_H5=y
|
||||
CONFIG_DRAM_CLK=408
|
||||
CONFIG_DRAM_ZQ=3881977
|
||||
# CONFIG_DRAM_ODT_EN is not set
|
||||
CONFIG_MACPWR="PD6"
|
||||
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
|
|
|
@ -4,7 +4,6 @@ CONFIG_ARCH_SUNXI=y
|
|||
CONFIG_SPL=y
|
||||
CONFIG_MACH_SUN8I_H3=y
|
||||
CONFIG_DRAM_CLK=672
|
||||
CONFIG_DRAM_ODT_EN=y
|
||||
CONFIG_USB1_VBUS_PIN="PG13"
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
|
||||
|
|
|
@ -3,7 +3,6 @@ CONFIG_ARCH_SUNXI=y
|
|||
CONFIG_SPL=y
|
||||
CONFIG_MACH_SUN8I_H3=y
|
||||
CONFIG_DRAM_CLK=672
|
||||
CONFIG_DRAM_ODT_EN=y
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
|
|
|
@ -3,7 +3,6 @@ CONFIG_ARCH_SUNXI=y
|
|||
CONFIG_SPL=y
|
||||
CONFIG_MACH_SUN8I_H3=y
|
||||
CONFIG_DRAM_CLK=672
|
||||
CONFIG_DRAM_ODT_EN=y
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
|
|
|
@ -4,6 +4,7 @@ CONFIG_SPL=y
|
|||
CONFIG_MACH_SUN50I_H5=y
|
||||
CONFIG_DRAM_CLK=672
|
||||
CONFIG_DRAM_ZQ=3881977
|
||||
# CONFIG_DRAM_ODT_EN is not set
|
||||
CONFIG_MACPWR="PD6"
|
||||
CONFIG_SPL_SPI_SUNXI=y
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
|
|
|
@ -3,7 +3,6 @@ CONFIG_ARCH_SUNXI=y
|
|||
CONFIG_SPL=y
|
||||
CONFIG_MACH_SUN8I_H3=y
|
||||
CONFIG_DRAM_CLK=624
|
||||
CONFIG_DRAM_ODT_EN=y
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
|
||||
CONFIG_SPL_I2C_SUPPORT=y
|
||||
|
|
|
@ -3,7 +3,6 @@ CONFIG_ARCH_SUNXI=y
|
|||
CONFIG_SPL=y
|
||||
CONFIG_MACH_SUN8I_H3=y
|
||||
CONFIG_DRAM_CLK=624
|
||||
CONFIG_DRAM_ODT_EN=y
|
||||
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
|
||||
|
|
|
@ -3,7 +3,6 @@ CONFIG_ARCH_SUNXI=y
|
|||
CONFIG_SPL=y
|
||||
CONFIG_MACH_SUN8I_H3=y
|
||||
CONFIG_DRAM_CLK=672
|
||||
CONFIG_DRAM_ODT_EN=y
|
||||
CONFIG_MACPWR="PD6"
|
||||
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
|
|
|
@ -3,7 +3,6 @@ CONFIG_ARCH_SUNXI=y
|
|||
CONFIG_SPL=y
|
||||
CONFIG_MACH_SUN8I_H3=y
|
||||
CONFIG_DRAM_CLK=672
|
||||
CONFIG_DRAM_ODT_EN=y
|
||||
CONFIG_MACPWR="PD6"
|
||||
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
|
||||
CONFIG_USB1_VBUS_PIN="PG13"
|
||||
|
|
|
@ -4,6 +4,7 @@ CONFIG_SPL=y
|
|||
CONFIG_MACH_SUN50I_H5=y
|
||||
CONFIG_DRAM_CLK=672
|
||||
CONFIG_DRAM_ZQ=3881977
|
||||
# CONFIG_DRAM_ODT_EN is not set
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
|
|
|
@ -3,7 +3,6 @@ CONFIG_ARCH_SUNXI=y
|
|||
CONFIG_SPL=y
|
||||
CONFIG_MACH_SUN8I_H3=y
|
||||
CONFIG_DRAM_CLK=624
|
||||
CONFIG_DRAM_ODT_EN=y
|
||||
# CONFIG_VIDEO_DE2 is not set
|
||||
CONFIG_SPL_SPI_SUNXI=y
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
|
|
|
@ -3,7 +3,6 @@ CONFIG_ARCH_SUNXI=y
|
|||
CONFIG_SPL=y
|
||||
CONFIG_MACH_SUN8I_H3=y
|
||||
CONFIG_DRAM_CLK=624
|
||||
CONFIG_DRAM_ODT_EN=y
|
||||
# CONFIG_VIDEO_DE2 is not set
|
||||
CONFIG_SPL_SPI_SUNXI=y
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
|
|
|
@ -4,6 +4,7 @@ CONFIG_SPL=y
|
|||
CONFIG_MACH_SUN50I_H5=y
|
||||
CONFIG_DRAM_CLK=672
|
||||
CONFIG_DRAM_ZQ=3881977
|
||||
# CONFIG_DRAM_ODT_EN is not set
|
||||
CONFIG_MMC0_CD_PIN="PH13"
|
||||
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
|
|
|
@ -4,6 +4,7 @@ CONFIG_SPL=y
|
|||
CONFIG_MACH_SUN50I_H5=y
|
||||
CONFIG_DRAM_CLK=624
|
||||
CONFIG_DRAM_ZQ=3881977
|
||||
# CONFIG_DRAM_ODT_EN is not set
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
|
|
Loading…
Reference in a new issue