mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-25 14:10:43 +00:00
Merge branch 'master' of /home/stefan/git/u-boot/u-boot
This commit is contained in:
Stefan Roese
commit
9cfff9e9d4
41 changed files with 2484 additions and 268 deletions
2
CREDITS
2
CREDITS
|
|
@ -305,7 +305,7 @@ W: http://www.li-pro.net
|
|||
|
||||
N: Dave Liu
|
||||
E: daveliu@freescale.com
|
||||
D: Support for MPC832x, MPC8360, MPC837x
|
||||
D: Support for MPC8315, MPC832x, MPC8360, MPC837x
|
||||
W: www.freescale.com
|
||||
|
||||
N: Raymond Lo
|
||||
|
|
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|||
|
|
@ -58,6 +58,10 @@ Conn Clark <clark@esteem.com>
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|||
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ESTEEM192E MPC8xx
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||||
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||||
Joe D'Abbraccio <ljd015@freescale.com>
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||||
MPC837xERDB MPC837x
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||||
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||||
Kári Davíðsson <kd@flaga.is>
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||||
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||||
FLAGADM MPC823
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|
|
@ -233,6 +237,7 @@ The LEOX team <team@leox.org>
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|||
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||||
Dave Liu <daveliu@freescale.com>
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||||
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||||
MPC8315ERDB MPC8315
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||||
MPC832XEMDS MPC832x
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MPC8360EMDS MPC8360
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MPC837XEMDS MPC837x
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||||
|
|
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|||
2
MAKEALL
2
MAKEALL
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|
@ -310,6 +310,7 @@ LIST_8260=" \
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LIST_83xx=" \
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MPC8313ERDB_33 \
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MPC8313ERDB_66 \
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MPC8315ERDB \
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MPC8323ERDB \
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MPC832XEMDS \
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MPC832XEMDS_ATM \
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|
@ -321,6 +322,7 @@ LIST_83xx=" \
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MPC8360ERDK_33 \
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MPC8360ERDK_66 \
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MPC837XEMDS \
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MPC837XERDB \
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sbc8349 \
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TQM834x \
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"
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||||
|
|
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|||
6
Makefile
6
Makefile
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|
@ -1864,6 +1864,9 @@ MPC8313ERDB_66_config: unconfig
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|||
fi ;
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@$(MKCONFIG) -a MPC8313ERDB ppc mpc83xx mpc8313erdb freescale
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MPC8315ERDB_config: unconfig
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@$(MKCONFIG) -a MPC8315ERDB ppc mpc83xx mpc8315erdb freescale
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MPC8323ERDB_config: unconfig
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@$(MKCONFIG) -a MPC8323ERDB ppc mpc83xx mpc8323erdb freescale
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||||
|
|
@ -1971,6 +1974,9 @@ MPC837XEMDS_HOST_config: unconfig
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|||
fi ;
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@$(MKCONFIG) -a MPC837XEMDS ppc mpc83xx mpc837xemds freescale
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MPC837XERDB_config: unconfig
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||||
@$(MKCONFIG) -a MPC837XERDB ppc mpc83xx mpc837xerdb freescale
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||||
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||||
sbc8349_config: unconfig
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||||
@$(MKCONFIG) $(@:_config=) ppc mpc83xx sbc8349
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||||
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||||
|
|
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|||
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@ -29,14 +29,13 @@ endif
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LIB = $(obj)lib$(VENDOR).a
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COBJS := sys_eeprom.o \
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pixis.o \
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pq-mds-pib.o \
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fsl_logo_bmp.o \
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fsl_diu_fb.o
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COBJS-${CONFIG_PQ_MDS_PIB} += pq-mds-pib.o
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COBJS-${CONFIG_ID_EEPROM} += sys_eeprom.o
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COBJS-${CONFIG_FSL_DIU_FB} += fsl_diu_fb.o fsl_logo_bmp.o
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COBJS-${CONFIG_FSL_PIXIS} += pixis.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS-y))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS)
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|
|
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|
|
@ -27,8 +27,6 @@
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|||
#include <i2c.h>
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#include <malloc.h>
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#ifdef CONFIG_FSL_DIU_FB
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#include "fsl_diu_fb.h"
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||||
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#ifdef DEBUG
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|
|
@ -615,4 +613,3 @@ void fsl_diu_clear_screen(void)
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|||
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||||
memset(info->screen_base, 0, info->smem_len);
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||||
}
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#endif /* CONFIG_FSL_DIU_FB */
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|
|
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|||
|
|
@ -25,9 +25,8 @@
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|||
#include <common.h>
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#include <command.h>
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#include <watchdog.h>
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#ifdef CONFIG_FSL_PIXIS
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#include <asm/cache.h>
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#include "pixis.h"
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||||
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|
@ -184,7 +183,7 @@ int set_px_corepll(ulong corepll)
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void read_from_px_regs(int set)
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{
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u8 mask = 0x1C;
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u8 mask = 0x1C; /* COREPLL, MPXPLL, SYSCLK controlled by PIXIS */
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u8 tmp = in8(PIXIS_BASE + PIXIS_VCFGEN0);
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if (set)
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|
|
@ -197,7 +196,7 @@ void read_from_px_regs(int set)
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|||
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void read_from_px_regs_altbank(int set)
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{
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u8 mask = 0x04;
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u8 mask = 0x04; /* FLASHBANK and FLASHMAP controlled by PIXIS */
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u8 tmp = in8(PIXIS_BASE + PIXIS_VCFGEN1);
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if (set)
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|
@ -208,15 +207,26 @@ void read_from_px_regs_altbank(int set)
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}
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#ifndef CFG_PIXIS_VBOOT_MASK
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#define CFG_PIXIS_VBOOT_MASK 0x40
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#define CFG_PIXIS_VBOOT_MASK (0x40)
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#endif
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void clear_altbank(void)
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{
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u8 tmp;
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tmp = in8(PIXIS_BASE + PIXIS_VBOOT);
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tmp &= ~CFG_PIXIS_VBOOT_MASK;
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out8(PIXIS_BASE + PIXIS_VBOOT, tmp);
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}
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void set_altbank(void)
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{
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u8 tmp;
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tmp = in8(PIXIS_BASE + PIXIS_VBOOT);
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tmp ^= CFG_PIXIS_VBOOT_MASK;
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tmp |= CFG_PIXIS_VBOOT_MASK;
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out8(PIXIS_BASE + PIXIS_VBOOT, tmp);
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}
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|
@ -227,11 +237,11 @@ void set_px_go(void)
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u8 tmp;
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tmp = in8(PIXIS_BASE + PIXIS_VCTL);
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tmp = tmp & 0x1E;
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tmp = tmp & 0x1E; /* clear GO bit */
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out8(PIXIS_BASE + PIXIS_VCTL, tmp);
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tmp = in8(PIXIS_BASE + PIXIS_VCTL);
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tmp = tmp | 0x01;
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tmp = tmp | 0x01; /* set GO bit - start reset sequencer */
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out8(PIXIS_BASE + PIXIS_VCTL, tmp);
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}
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||||
|
|
@ -293,7 +303,7 @@ static ulong strfractoint(uchar *strptr)
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* simply create the intarr.
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*/
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||||
i = 0;
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||||
while (strptr[i] != 46) {
|
||||
while (strptr[i] != '.') {
|
||||
if (strptr[i] == 0) {
|
||||
no_dec = 1;
|
||||
break;
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||||
|
|
@ -313,7 +323,7 @@ static ulong strfractoint(uchar *strptr)
|
|||
} else {
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||||
j = 0;
|
||||
i++; /* Skipping the decimal point */
|
||||
while ((strptr[i] > 47) && (strptr[i] < 58)) {
|
||||
while ((strptr[i] >= '0') && (strptr[i] <= '9')) {
|
||||
decarr[j] = strptr[i];
|
||||
i++;
|
||||
j++;
|
||||
|
|
@ -340,8 +350,14 @@ static ulong strfractoint(uchar *strptr)
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|||
int
|
||||
pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
{
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||||
ulong val;
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||||
ulong corepll;
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unsigned int i;
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||||
char *p_cf = NULL;
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char *p_cf_sysclk = NULL;
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char *p_cf_corepll = NULL;
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char *p_cf_mpxpll = NULL;
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char *p_altbank = NULL;
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char *p_wd = NULL;
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unsigned int unknown_param = 0;
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|
||||
/*
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||||
* No args is a simple reset request.
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||||
|
|
@ -351,116 +367,97 @@ pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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|||
/* not reached */
|
||||
}
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||||
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||||
if (strcmp(argv[1], "cf") == 0) {
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||||
/*
|
||||
* Reset with frequency changed:
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* cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
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||||
*/
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if (argc < 5) {
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puts(cmdtp->usage);
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return 1;
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||||
}
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||||
|
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read_from_px_regs(0);
|
||||
|
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val = set_px_sysclk(simple_strtoul(argv[2], NULL, 10));
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|
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corepll = strfractoint((uchar *)argv[3]);
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val = val + set_px_corepll(corepll);
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val = val + set_px_mpxpll(simple_strtoul(argv[4], NULL, 10));
|
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if (val == 3) {
|
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puts("Setting registers VCFGEN0 and VCTL\n");
|
||||
read_from_px_regs(1);
|
||||
puts("Resetting board with values from ");
|
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puts("VSPEED0, VSPEED1, VCLKH, and VCLKL \n");
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set_px_go();
|
||||
} else {
|
||||
puts(cmdtp->usage);
|
||||
return 1;
|
||||
}
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||||
|
||||
while (1) ; /* Not reached */
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||||
|
||||
} else if (strcmp(argv[1], "altbank") == 0) {
|
||||
|
||||
/*
|
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* Reset using alternate flash bank:
|
||||
*/
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if (argv[2] == 0) {
|
||||
/*
|
||||
* Reset from alternate bank without changing
|
||||
* frequency and without watchdog timer enabled.
|
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* altbank
|
||||
*/
|
||||
read_from_px_regs(0);
|
||||
read_from_px_regs_altbank(0);
|
||||
if (argc > 2) {
|
||||
puts(cmdtp->usage);
|
||||
return 1;
|
||||
for (i = 1; i < argc; i++) {
|
||||
if (strcmp(argv[i], "cf") == 0) {
|
||||
p_cf = argv[i];
|
||||
if (i + 3 >= argc) {
|
||||
break;
|
||||
}
|
||||
puts("Setting registers VCFGNE1, VBOOT, and VCTL\n");
|
||||
set_altbank();
|
||||
read_from_px_regs_altbank(1);
|
||||
puts("Resetting board to boot from the other bank.\n");
|
||||
set_px_go();
|
||||
|
||||
} else if (strcmp(argv[2], "cf") == 0) {
|
||||
/*
|
||||
* Reset with frequency changed
|
||||
* altbank cf <SYSCLK freq> <COREPLL ratio>
|
||||
* <MPXPLL ratio>
|
||||
*/
|
||||
read_from_px_regs(0);
|
||||
read_from_px_regs_altbank(0);
|
||||
val = set_px_sysclk(simple_strtoul(argv[3], NULL, 10));
|
||||
corepll = strfractoint((uchar *)argv[4]);
|
||||
val = val + set_px_corepll(corepll);
|
||||
val = val + set_px_mpxpll(simple_strtoul(argv[5],
|
||||
NULL, 10));
|
||||
if (val == 3) {
|
||||
puts("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n");
|
||||
set_altbank();
|
||||
read_from_px_regs(1);
|
||||
read_from_px_regs_altbank(1);
|
||||
puts("Enabling watchdog timer on the FPGA\n");
|
||||
puts("Resetting board with values from ");
|
||||
puts("VSPEED0, VSPEED1, VCLKH and VCLKL ");
|
||||
puts("to boot from the other bank.\n");
|
||||
set_px_go_with_watchdog();
|
||||
} else {
|
||||
puts(cmdtp->usage);
|
||||
return 1;
|
||||
}
|
||||
|
||||
while (1) ; /* Not reached */
|
||||
|
||||
} else if (strcmp(argv[2], "wd") == 0) {
|
||||
/*
|
||||
* Reset from alternate bank without changing
|
||||
* frequencies but with watchdog timer enabled:
|
||||
* altbank wd
|
||||
*/
|
||||
read_from_px_regs(0);
|
||||
read_from_px_regs_altbank(0);
|
||||
puts("Setting registers VCFGEN1, VBOOT, and VCTL\n");
|
||||
set_altbank();
|
||||
read_from_px_regs_altbank(1);
|
||||
puts("Enabling watchdog timer on the FPGA\n");
|
||||
puts("Resetting board to boot from the other bank.\n");
|
||||
set_px_go_with_watchdog();
|
||||
while (1) ; /* Not reached */
|
||||
|
||||
} else {
|
||||
puts(cmdtp->usage);
|
||||
return 1;
|
||||
p_cf_sysclk = argv[i+1];
|
||||
p_cf_corepll = argv[i+2];
|
||||
p_cf_mpxpll = argv[i+3];
|
||||
i += 3;
|
||||
continue;
|
||||
}
|
||||
|
||||
} else {
|
||||
puts(cmdtp->usage);
|
||||
if (strcmp(argv[i], "altbank") == 0) {
|
||||
p_altbank = argv[i];
|
||||
continue;
|
||||
}
|
||||
|
||||
if (strcmp(argv[i], "wd") == 0) {
|
||||
p_wd = argv[i];
|
||||
continue;
|
||||
}
|
||||
|
||||
unknown_param = 1;
|
||||
}
|
||||
|
||||
/*
|
||||
* Check that cf has all required parms
|
||||
*/
|
||||
if ((p_cf && !(p_cf_sysclk && p_cf_corepll && p_cf_mpxpll))
|
||||
|| unknown_param) {
|
||||
puts(cmdtp->help);
|
||||
return 1;
|
||||
}
|
||||
|
||||
/*
|
||||
* PIXIS seems to be sensitive to the ordering of
|
||||
* the registers that are touched.
|
||||
*/
|
||||
read_from_px_regs(0);
|
||||
|
||||
if (p_altbank) {
|
||||
read_from_px_regs_altbank(0);
|
||||
}
|
||||
clear_altbank();
|
||||
|
||||
/*
|
||||
* Clock configuration specified.
|
||||
*/
|
||||
if (p_cf) {
|
||||
unsigned long sysclk;
|
||||
unsigned long corepll;
|
||||
unsigned long mpxpll;
|
||||
|
||||
sysclk = simple_strtoul(p_cf_sysclk, NULL, 10);
|
||||
corepll = strfractoint((uchar *) p_cf_corepll);
|
||||
mpxpll = simple_strtoul(p_cf_mpxpll, NULL, 10);
|
||||
|
||||
if (!(set_px_sysclk(sysclk)
|
||||
&& set_px_corepll(corepll)
|
||||
&& set_px_mpxpll(mpxpll))) {
|
||||
puts(cmdtp->help);
|
||||
return 1;
|
||||
}
|
||||
read_from_px_regs(1);
|
||||
}
|
||||
|
||||
/*
|
||||
* Altbank specified
|
||||
*
|
||||
* NOTE CHANGE IN BEHAVIOR: previous code would default
|
||||
* to enabling watchdog if altbank is specified.
|
||||
* Now the watchdog must be enabled explicitly using 'wd'.
|
||||
*/
|
||||
if (p_altbank) {
|
||||
set_altbank();
|
||||
read_from_px_regs_altbank(1);
|
||||
}
|
||||
|
||||
/*
|
||||
* Reset with watchdog specified.
|
||||
*/
|
||||
if (p_wd) {
|
||||
set_px_go_with_watchdog();
|
||||
} else {
|
||||
set_px_go();
|
||||
}
|
||||
|
||||
/*
|
||||
* Shouldn't be reached.
|
||||
*/
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -474,4 +471,3 @@ U_BOOT_CMD(
|
|||
" pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n"
|
||||
" pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n"
|
||||
);
|
||||
#endif /* CONFIG_FSL_PIXIS */
|
||||
|
|
|
|||
|
|
@ -12,8 +12,6 @@
|
|||
#include <i2c.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#ifdef CONFIG_PQ_MDS_PIB
|
||||
|
||||
#include "pq-mds-pib.h"
|
||||
|
||||
int pib_init(void)
|
||||
|
|
@ -102,4 +100,3 @@ int pib_init(void)
|
|||
i2c_set_bus_num(orig_i2c_bus);
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_PQ_MDS_PIB */
|
||||
|
|
|
|||
|
|
@ -27,7 +27,6 @@
|
|||
#include <i2c.h>
|
||||
#include <linux/ctype.h>
|
||||
|
||||
#ifdef CFG_ID_EEPROM
|
||||
typedef struct {
|
||||
unsigned char id[4]; /* 0x0000 - 0x0003 */
|
||||
unsigned char sn[12]; /* 0x0004 - 0x000F */
|
||||
|
|
@ -253,4 +252,3 @@ int mac_read_from_eeprom(void)
|
|||
}
|
||||
return 0;
|
||||
}
|
||||
#endif /* CFG_ID_EEPROM */
|
||||
|
|
|
|||
|
|
@ -32,7 +32,7 @@ OBJS := $(addprefix $(obj),$(COBJS))
|
|||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS)
|
||||
$(AR) crv $@ $(OBJS)
|
||||
$(AR) $(ARFLAGS) $@ $(OBJS)
|
||||
|
||||
clean:
|
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
|
|
|||
50
board/freescale/mpc8315erdb/Makefile
Normal file
50
board/freescale/mpc8315erdb/Makefile
Normal file
|
|
@ -0,0 +1,50 @@
|
|||
#
|
||||
# (C) Copyright 2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS := $(BOARD).o sdram.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS)
|
||||
$(AR) $(ARFLAGS) $@ $(OBJS)
|
||||
|
||||
clean:
|
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
||||
distclean: clean
|
||||
rm -f $(LIB) core *.bak .depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
1
board/freescale/mpc8315erdb/config.mk
Normal file
1
board/freescale/mpc8315erdb/config.mk
Normal file
|
|
@ -0,0 +1 @@
|
|||
TEXT_BASE = 0xFE000000
|
||||
132
board/freescale/mpc8315erdb/mpc8315erdb.c
Normal file
132
board/freescale/mpc8315erdb/mpc8315erdb.c
Normal file
|
|
@ -0,0 +1,132 @@
|
|||
/*
|
||||
* Copyright (C) 2007 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Author: Scott Wood <scottwood@freescale.com>
|
||||
* Dave Liu <daveliu@freescale.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <i2c.h>
|
||||
#if defined(CONFIG_OF_LIBFDT)
|
||||
#include <libfdt.h>
|
||||
#endif
|
||||
#include <pci.h>
|
||||
#include <mpc83xx.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
volatile immap_t *im = (immap_t *)CFG_IMMR;
|
||||
|
||||
if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
|
||||
gd->flags |= GD_FLG_SILENT;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static u8 read_board_info(void)
|
||||
{
|
||||
u8 val8;
|
||||
i2c_set_bus_num(0);
|
||||
|
||||
if (i2c_read(CFG_I2C_PCF8574A_ADDR, 0, 0, &val8, 1) == 0)
|
||||
return val8;
|
||||
else
|
||||
return 0;
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
static const char * const rev_str[] = {
|
||||
"0.0",
|
||||
"0.1",
|
||||
"1.0",
|
||||
"1.1",
|
||||
"<unknown>",
|
||||
};
|
||||
u8 info;
|
||||
int i;
|
||||
|
||||
info = read_board_info();
|
||||
i = (!info) ? 4: info & 0x03;
|
||||
|
||||
printf("Board: Freescale MPC8315ERDB Rev %s\n", rev_str[i]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct pci_region pci_regions[] = {
|
||||
{
|
||||
bus_start: CFG_PCI_MEM_BASE,
|
||||
phys_start: CFG_PCI_MEM_PHYS,
|
||||
size: CFG_PCI_MEM_SIZE,
|
||||
flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
|
||||
},
|
||||
{
|
||||
bus_start: CFG_PCI_MMIO_BASE,
|
||||
phys_start: CFG_PCI_MMIO_PHYS,
|
||||
size: CFG_PCI_MMIO_SIZE,
|
||||
flags: PCI_REGION_MEM
|
||||
},
|
||||
{
|
||||
bus_start: CFG_PCI_IO_BASE,
|
||||
phys_start: CFG_PCI_IO_PHYS,
|
||||
size: CFG_PCI_IO_SIZE,
|
||||
flags: PCI_REGION_IO
|
||||
}
|
||||
};
|
||||
|
||||
void pci_init_board(void)
|
||||
{
|
||||
volatile immap_t *immr = (volatile immap_t *)CFG_IMMR;
|
||||
volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
|
||||
volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
|
||||
struct pci_region *reg[] = { pci_regions };
|
||||
int warmboot;
|
||||
|
||||
/* Enable all 3 PCI_CLK_OUTPUTs. */
|
||||
clk->occr |= 0xe0000000;
|
||||
|
||||
/*
|
||||
* Configure PCI Local Access Windows
|
||||
*/
|
||||
pci_law[0].bar = CFG_PCI_MEM_PHYS & LAWBAR_BAR;
|
||||
pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
|
||||
|
||||
pci_law[1].bar = CFG_PCI_IO_PHYS & LAWBAR_BAR;
|
||||
pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
|
||||
|
||||
warmboot = gd->bd->bi_bootflags & BOOTFLAG_WARM;
|
||||
warmboot |= immr->pmc.pmccr1 & PMCCR1_POWER_OFF;
|
||||
|
||||
mpc83xx_pci_init(1, reg, warmboot);
|
||||
}
|
||||
|
||||
#if defined(CONFIG_OF_BOARD_SETUP)
|
||||
void ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
ft_cpu_setup(blob, bd);
|
||||
#ifdef CONFIG_PCI
|
||||
ft_pci_setup(blob, bd);
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
120
board/freescale/mpc8315erdb/sdram.c
Normal file
120
board/freescale/mpc8315erdb/sdram.c
Normal file
|
|
@ -0,0 +1,120 @@
|
|||
/*
|
||||
* Copyright (C) 2007 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Authors: Nick.Spence@freescale.com
|
||||
* Wilson.Lo@freescale.com
|
||||
* scottwood@freescale.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <mpc83xx.h>
|
||||
#include <spd_sdram.h>
|
||||
|
||||
#include <asm/bitops.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#include <asm/processor.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
static void resume_from_sleep(void)
|
||||
{
|
||||
u32 magic = *(u32 *)0;
|
||||
|
||||
typedef void (*func_t)(void);
|
||||
func_t resume = *(func_t *)4;
|
||||
|
||||
if (magic == 0xf5153ae5)
|
||||
resume();
|
||||
|
||||
gd->flags &= ~GD_FLG_SILENT;
|
||||
puts("\nResume from sleep failed: bad magic word\n");
|
||||
}
|
||||
|
||||
/* Fixed sdram init -- doesn't use serial presence detect.
|
||||
*
|
||||
* This is useful for faster booting in configs where the RAM is unlikely
|
||||
* to be changed, or for things like NAND booting where space is tight.
|
||||
*/
|
||||
static long fixed_sdram(void)
|
||||
{
|
||||
volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
|
||||
u32 msize = CFG_DDR_SIZE * 1024 * 1024;
|
||||
u32 msize_log2 = __ilog2(msize);
|
||||
|
||||
im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE >> 12;
|
||||
im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
|
||||
im->sysconf.ddrcdr = CFG_DDRCDR_VALUE;
|
||||
|
||||
/*
|
||||
* Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
|
||||
* or the DDR2 controller may fail to initialize correctly.
|
||||
*/
|
||||
udelay(50000);
|
||||
|
||||
im->ddr.csbnds[0].csbnds = (msize - 1) >> 24;
|
||||
im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG;
|
||||
|
||||
/* Currently we use only one CS, so disable the other bank. */
|
||||
im->ddr.cs_config[1] = 0;
|
||||
|
||||
im->ddr.sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL;
|
||||
im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3;
|
||||
im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
|
||||
im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
|
||||
im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0;
|
||||
|
||||
if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
|
||||
im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG | SDRAM_CFG_BI;
|
||||
else
|
||||
im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG;
|
||||
|
||||
im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2;
|
||||
im->ddr.sdram_mode = CFG_DDR_MODE;
|
||||
im->ddr.sdram_mode2 = CFG_DDR_MODE2;
|
||||
|
||||
im->ddr.sdram_interval = CFG_DDR_INTERVAL;
|
||||
sync();
|
||||
|
||||
/* enable DDR controller */
|
||||
im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
|
||||
sync();
|
||||
|
||||
return msize;
|
||||
}
|
||||
|
||||
long int initdram(int board_type)
|
||||
{
|
||||
volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
|
||||
u32 msize;
|
||||
|
||||
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
|
||||
return -1;
|
||||
|
||||
/* DDR SDRAM */
|
||||
msize = fixed_sdram();
|
||||
|
||||
if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
|
||||
resume_from_sleep();
|
||||
|
||||
/* return total bus SDRAM size(bytes) -- DDR */
|
||||
return msize;
|
||||
}
|
||||
|
|
@ -31,7 +31,7 @@ OBJS := $(addprefix $(obj),$(COBJS))
|
|||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS)
|
||||
$(AR) crv $@ $(OBJS)
|
||||
$(AR) $(ARFLAGS) $@ $(OBJS)
|
||||
|
||||
clean:
|
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
|
|
|||
|
|
@ -316,30 +316,36 @@ void ft_board_setup(void *blob, bd_t *bd)
|
|||
immr->sysconf.spridr == SPR_8360E_REV21) {
|
||||
int nodeoffset;
|
||||
const char *prop;
|
||||
const char *path;
|
||||
int path;
|
||||
|
||||
nodeoffset = fdt_path_offset(fdt, "/aliases");
|
||||
nodeoffset = fdt_path_offset(blob, "/aliases");
|
||||
if (nodeoffset >= 0) {
|
||||
#if defined(CONFIG_HAS_ETH0)
|
||||
/* fixup UCC 1 if using rgmii-id mode */
|
||||
path = fdt_getprop(blob, nodeoffset, "ethernet0", NULL);
|
||||
if (path) {
|
||||
prop = fdt_getprop(blob, nodeoffset,
|
||||
"phy-connection-type", 0);
|
||||
prop = fdt_getprop(blob, nodeoffset, "ethernet0", NULL);
|
||||
if (prop) {
|
||||
path = fdt_path_offset(blob, prop);
|
||||
prop = fdt_getprop(blob, path,
|
||||
"phy-connection-type", 0);
|
||||
if (prop && (strcmp(prop, "rgmii-id") == 0))
|
||||
fdt_setprop(blob, nodeoffset, "phy-connection-type",
|
||||
"rgmii-rxid", sizeof("rgmii-rxid"));
|
||||
fdt_setprop(blob, path,
|
||||
"phy-connection-type",
|
||||
"rgmii-rxid",
|
||||
sizeof("rgmii-rxid"));
|
||||
}
|
||||
#endif
|
||||
#if defined(CONFIG_HAS_ETH1)
|
||||
/* fixup UCC 2 if using rgmii-id mode */
|
||||
path = fdt_getprop(blob, nodeoffset, "ethernet1", NULL);
|
||||
if (path) {
|
||||
prop = fdt_getprop(blob, nodeoffset,
|
||||
"phy-connection-type", 0);
|
||||
prop = fdt_getprop(blob, nodeoffset, "ethernet1", NULL);
|
||||
if (prop) {
|
||||
path = fdt_path_offset(blob, prop);
|
||||
prop = fdt_getprop(blob, path,
|
||||
"phy-connection-type", 0);
|
||||
if (prop && (strcmp(prop, "rgmii-id") == 0))
|
||||
fdt_setprop(blob, nodeoffset, "phy-connection-type",
|
||||
"rgmii-rxid", sizeof("rgmii-rxid"));
|
||||
fdt_setprop(blob, path,
|
||||
"phy-connection-type",
|
||||
"rgmii-rxid",
|
||||
sizeof("rgmii-rxid"));
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
|
|
|||
50
board/freescale/mpc837xerdb/Makefile
Normal file
50
board/freescale/mpc837xerdb/Makefile
Normal file
|
|
@ -0,0 +1,50 @@
|
|||
#
|
||||
# (C) Copyright 2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS := $(BOARD).o pci.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS)
|
||||
$(AR) $(ARFLAGS) $@ $(OBJS)
|
||||
|
||||
clean:
|
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
||||
distclean: clean
|
||||
rm -f $(LIB) core *.bak .depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
28
board/freescale/mpc837xerdb/config.mk
Normal file
28
board/freescale/mpc837xerdb/config.mk
Normal file
|
|
@ -0,0 +1,28 @@
|
|||
#
|
||||
# (C) Copyright 2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
#
|
||||
# MPC837xERDB
|
||||
#
|
||||
|
||||
TEXT_BASE = 0xFE000000
|
||||
150
board/freescale/mpc837xerdb/mpc837xerdb.c
Normal file
150
board/freescale/mpc837xerdb/mpc837xerdb.c
Normal file
|
|
@ -0,0 +1,150 @@
|
|||
/*
|
||||
* Copyright (C) 2007 Freescale Semiconductor, Inc.
|
||||
* Kevin Lam <kevin.lam@freescale.com>
|
||||
* Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <i2c.h>
|
||||
#include <spd.h>
|
||||
#include <asm/io.h>
|
||||
#if defined(CONFIG_SPD_EEPROM)
|
||||
#include <spd_sdram.h>
|
||||
#endif
|
||||
|
||||
#if defined(CFG_DRAM_TEST)
|
||||
int
|
||||
testdram(void)
|
||||
{
|
||||
uint *pstart = (uint *) CFG_MEMTEST_START;
|
||||
uint *pend = (uint *) CFG_MEMTEST_END;
|
||||
uint *p;
|
||||
|
||||
printf("Testing DRAM from 0x%08x to 0x%08x\n",
|
||||
CFG_MEMTEST_START,
|
||||
CFG_MEMTEST_END);
|
||||
|
||||
printf("DRAM test phase 1:\n");
|
||||
for (p = pstart; p < pend; p++)
|
||||
*p = 0xaaaaaaaa;
|
||||
|
||||
for (p = pstart; p < pend; p++) {
|
||||
if (*p != 0xaaaaaaaa) {
|
||||
printf("DRAM test fails at: %08x\n", (uint) p);
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
printf("DRAM test phase 2:\n");
|
||||
for (p = pstart; p < pend; p++)
|
||||
*p = 0x55555555;
|
||||
|
||||
for (p = pstart; p < pend; p++) {
|
||||
if (*p != 0x55555555) {
|
||||
printf("DRAM test fails at: %08x\n", (uint) p);
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
printf("DRAM test passed.\n");
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
|
||||
void ddr_enable_ecc(unsigned int dram_size);
|
||||
#endif
|
||||
int fixed_sdram(void);
|
||||
|
||||
long int initdram(int board_type)
|
||||
{
|
||||
immap_t *im = (immap_t *) CFG_IMMR;
|
||||
u32 msize = 0;
|
||||
|
||||
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
|
||||
return -1;
|
||||
|
||||
#if defined(CONFIG_SPD_EEPROM)
|
||||
msize = spd_sdram();
|
||||
#else
|
||||
msize = fixed_sdram();
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
|
||||
/* Initialize DDR ECC byte */
|
||||
ddr_enable_ecc(msize * 1024 * 1024);
|
||||
#endif
|
||||
/* return total bus DDR size(bytes) */
|
||||
return (msize * 1024 * 1024);
|
||||
}
|
||||
|
||||
#if !defined(CONFIG_SPD_EEPROM)
|
||||
/*************************************************************************
|
||||
* fixed sdram init -- doesn't use serial presence detect.
|
||||
************************************************************************/
|
||||
int fixed_sdram(void)
|
||||
{
|
||||
immap_t *im = (immap_t *) CFG_IMMR;
|
||||
u32 msize = CFG_DDR_SIZE * 1024 * 1024;
|
||||
u32 msize_log2 = __ilog2(msize);
|
||||
|
||||
im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE >> 12;
|
||||
im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
|
||||
|
||||
im->sysconf.ddrcdr = CFG_DDRCDR_VALUE;
|
||||
udelay(50000);
|
||||
|
||||
im->ddr.sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL;
|
||||
udelay(1000);
|
||||
|
||||
im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS;
|
||||
im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG;
|
||||
udelay(1000);
|
||||
|
||||
im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0;
|
||||
im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
|
||||
im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
|
||||
im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3;
|
||||
im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG;
|
||||
im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2;
|
||||
im->ddr.sdram_mode = CFG_DDR_MODE;
|
||||
im->ddr.sdram_mode2 = CFG_DDR_MODE2;
|
||||
im->ddr.sdram_interval = CFG_DDR_INTERVAL;
|
||||
sync();
|
||||
udelay(1000);
|
||||
|
||||
im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
|
||||
udelay(2000);
|
||||
return CFG_DDR_SIZE;
|
||||
}
|
||||
#endif /*!CFG_SPD_EEPROM */
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
puts("Board: Freescale MPC837xERDB\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_OF_BOARD_SETUP)
|
||||
|
||||
void ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
#ifdef CONFIG_PCI
|
||||
ft_pci_setup(blob, bd);
|
||||
#endif
|
||||
ft_cpu_setup(blob, bd);
|
||||
}
|
||||
#endif /* CONFIG_OF_BOARD_SETUP */
|
||||
59
board/freescale/mpc837xerdb/pci.c
Normal file
59
board/freescale/mpc837xerdb/pci.c
Normal file
|
|
@ -0,0 +1,59 @@
|
|||
/*
|
||||
* Copyright (C) 2007 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <mpc83xx.h>
|
||||
#include <pci.h>
|
||||
|
||||
#if defined(CONFIG_PCI)
|
||||
static struct pci_region pci_regions[] = {
|
||||
{
|
||||
bus_start: CFG_PCI_MEM_BASE,
|
||||
phys_start: CFG_PCI_MEM_PHYS,
|
||||
size: CFG_PCI_MEM_SIZE,
|
||||
flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
|
||||
},
|
||||
{
|
||||
bus_start: CFG_PCI_MMIO_BASE,
|
||||
phys_start: CFG_PCI_MMIO_PHYS,
|
||||
size: CFG_PCI_MMIO_SIZE,
|
||||
flags: PCI_REGION_MEM
|
||||
},
|
||||
{
|
||||
bus_start: CFG_PCI_IO_BASE,
|
||||
phys_start: CFG_PCI_IO_PHYS,
|
||||
size: CFG_PCI_IO_SIZE,
|
||||
flags: PCI_REGION_IO
|
||||
}
|
||||
};
|
||||
|
||||
void pci_init_board(void)
|
||||
{
|
||||
volatile immap_t *immr = (volatile immap_t *)CFG_IMMR;
|
||||
volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
|
||||
volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
|
||||
struct pci_region *reg[] = { pci_regions };
|
||||
|
||||
/* Enable all 5 PCI_CLK_OUTPUTS */
|
||||
clk->occr |= 0xf8000000;
|
||||
udelay(2000);
|
||||
|
||||
/* Configure PCI Local Access Windows */
|
||||
pci_law[0].bar = CFG_PCI_MEM_PHYS & LAWBAR_BAR;
|
||||
pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
|
||||
|
||||
pci_law[1].bar = CFG_PCI_IO_PHYS & LAWBAR_BAR;
|
||||
pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
|
||||
|
||||
mpc83xx_pci_init(1, reg, 0);
|
||||
}
|
||||
#endif /* CONFIG_PCI */
|
||||
|
|
@ -27,14 +27,14 @@ endif
|
|||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS := $(BOARD).o \
|
||||
../common/sys_eeprom.o \
|
||||
../common/pixis.o \
|
||||
mpc8610hpcd_diu.o \
|
||||
../common/fsl_diu_fb.o
|
||||
|
||||
SOBJS := init.o
|
||||
|
||||
COBJS := $(BOARD).o
|
||||
|
||||
COBJS-${CONFIG_FSL_DIU_FB} += mpc8610hpcd_diu.o
|
||||
|
||||
COBJS += ${COBJS-y}
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
|
|
|||
|
|
@ -73,59 +73,93 @@ void cpu_init_f (volatile immap_t * im)
|
|||
(CFG_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT);
|
||||
#endif
|
||||
|
||||
#ifdef CFG_SPCR_TSEC1EP
|
||||
/* TSEC1 Emergency priority */
|
||||
im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC1EP) | (CFG_SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT);
|
||||
#endif
|
||||
|
||||
#ifdef CFG_SPCR_TSEC2EP
|
||||
/* TSEC2 Emergency priority */
|
||||
im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC2EP) | (CFG_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT);
|
||||
#endif
|
||||
|
||||
#ifdef CFG_SCCR_TSEC1CM
|
||||
/* TSEC1 clock mode */
|
||||
im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1CM) | (CFG_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT);
|
||||
#endif
|
||||
|
||||
#ifdef CFG_SCCR_TSEC2CM
|
||||
/* TSEC2 & I2C1 clock mode */
|
||||
im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2CM) | (CFG_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT);
|
||||
#endif
|
||||
|
||||
#ifdef CFG_SCCR_TSEC1ON
|
||||
/* TSEC1 clock switch */
|
||||
im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1ON) | (CFG_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT);
|
||||
#endif
|
||||
|
||||
#ifdef CFG_SCCR_TSEC2ON
|
||||
/* TSEC2 clock switch */
|
||||
im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2ON) | (CFG_SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT);
|
||||
#endif
|
||||
|
||||
#ifdef CFG_SCCR_USBMPHCM
|
||||
/* USB MPH clock mode */
|
||||
im->clk.sccr = (im->clk.sccr & ~SCCR_USBMPHCM) | (CFG_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT);
|
||||
#endif
|
||||
|
||||
#ifdef CFG_SCCR_PCICM
|
||||
/* PCI & DMA clock mode */
|
||||
im->clk.sccr = (im->clk.sccr & ~SCCR_PCICM) | (CFG_SCCR_PCICM << SCCR_PCICM_SHIFT);
|
||||
#endif
|
||||
|
||||
#ifdef CFG_SCCR_USBDRCM
|
||||
/* USB DR clock mode */
|
||||
im->clk.sccr = (im->clk.sccr & ~SCCR_USBDRCM) | (CFG_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT);
|
||||
#endif
|
||||
|
||||
#ifdef CFG_SCCR_ENCCM
|
||||
/* Encryption clock mode */
|
||||
im->clk.sccr = (im->clk.sccr & ~SCCR_ENCCM) | (CFG_SCCR_ENCCM << SCCR_PCICM_SHIFT);
|
||||
#ifdef CFG_SPCR_TSECEP
|
||||
/* eTSEC Emergency priority */
|
||||
im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSECEP) | (CFG_SPCR_TSECEP << SPCR_TSECEP_SHIFT);
|
||||
#endif
|
||||
|
||||
#ifdef CFG_ACR_RPTCNT
|
||||
/* Arbiter repeat count */
|
||||
im->arbiter.acr = ((im->arbiter.acr & ~(ACR_RPTCNT)) | (CFG_ACR_RPTCNT << ACR_RPTCNT_SHIFT));
|
||||
im->arbiter.acr = (im->arbiter.acr & ~(ACR_RPTCNT)) |
|
||||
(CFG_ACR_RPTCNT << ACR_RPTCNT_SHIFT);
|
||||
#endif
|
||||
|
||||
#ifdef CFG_SPCR_TSECEP
|
||||
/* all TSEC's Emergency priority */
|
||||
im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSECEP) |
|
||||
(CFG_SPCR_TSECEP << SPCR_TSECEP_SHIFT);
|
||||
#endif
|
||||
|
||||
#ifdef CFG_SPCR_TSEC1EP
|
||||
/* TSEC1 Emergency priority */
|
||||
im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC1EP) |
|
||||
(CFG_SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT);
|
||||
#endif
|
||||
|
||||
#ifdef CFG_SPCR_TSEC2EP
|
||||
/* TSEC2 Emergency priority */
|
||||
im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC2EP) |
|
||||
(CFG_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT);
|
||||
#endif
|
||||
|
||||
#ifdef CFG_SCCR_ENCCM
|
||||
/* Encryption clock mode */
|
||||
im->clk.sccr = (im->clk.sccr & ~SCCR_ENCCM) |
|
||||
(CFG_SCCR_ENCCM << SCCR_PCICM_SHIFT);
|
||||
#endif
|
||||
|
||||
#ifdef CFG_SCCR_PCICM
|
||||
/* PCI & DMA clock mode */
|
||||
im->clk.sccr = (im->clk.sccr & ~SCCR_PCICM) |
|
||||
(CFG_SCCR_PCICM << SCCR_PCICM_SHIFT);
|
||||
#endif
|
||||
|
||||
#ifdef CFG_SCCR_TSECCM
|
||||
/* all TSEC's clock mode */
|
||||
im->clk.sccr = (im->clk.sccr & ~SCCR_TSECCM) |
|
||||
(CFG_SCCR_TSECCM << SCCR_TSECCM_SHIFT);
|
||||
#endif
|
||||
|
||||
#ifdef CFG_SCCR_TSEC1CM
|
||||
/* TSEC1 clock mode */
|
||||
im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1CM) |
|
||||
(CFG_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT);
|
||||
#endif
|
||||
|
||||
#ifdef CFG_SCCR_TSEC2CM
|
||||
/* TSEC2 clock mode */
|
||||
im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2CM) |
|
||||
(CFG_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT);
|
||||
#endif
|
||||
|
||||
#ifdef CFG_SCCR_TSEC1ON
|
||||
/* TSEC1 clock switch */
|
||||
im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1ON) |
|
||||
(CFG_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT);
|
||||
#endif
|
||||
|
||||
#ifdef CFG_SCCR_TSEC2ON
|
||||
/* TSEC2 clock switch */
|
||||
im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2ON) |
|
||||
(CFG_SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT);
|
||||
#endif
|
||||
|
||||
#ifdef CFG_SCCR_USBMPHCM
|
||||
/* USB MPH clock mode */
|
||||
im->clk.sccr = (im->clk.sccr & ~SCCR_USBMPHCM) |
|
||||
(CFG_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT);
|
||||
#endif
|
||||
|
||||
#ifdef CFG_SCCR_USBDRCM
|
||||
/* USB DR clock mode */
|
||||
im->clk.sccr = (im->clk.sccr & ~SCCR_USBDRCM) |
|
||||
(CFG_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT);
|
||||
#endif
|
||||
|
||||
#ifdef CFG_SCCR_SATACM
|
||||
/* SATA controller clock mode */
|
||||
im->clk.sccr = (im->clk.sccr & ~SCCR_SATACM) |
|
||||
(CFG_SCCR_SATACM << SCCR_SATACM_SHIFT);
|
||||
#endif
|
||||
|
||||
/* RSR - Reset Status Register - clear all status (4.6.1.3) */
|
||||
|
|
|
|||
|
|
@ -367,21 +367,21 @@ int get_clocks(void)
|
|||
#endif
|
||||
|
||||
#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315)
|
||||
switch ((sccr & SCCR_SATA1CM) >> SCCR_SATA1CM_SHIFT) {
|
||||
case 0:
|
||||
switch ((sccr & SCCR_SATACM) >> SCCR_SATACM_SHIFT) {
|
||||
case SCCR_SATACM_0:
|
||||
sata_clk = 0;
|
||||
break;
|
||||
case 1:
|
||||
case SCCR_SATACM_1:
|
||||
sata_clk = csb_clk;
|
||||
break;
|
||||
case 2:
|
||||
case SCCR_SATACM_2:
|
||||
sata_clk = csb_clk / 2;
|
||||
break;
|
||||
case 3:
|
||||
case SCCR_SATACM_3:
|
||||
sata_clk = csb_clk / 3;
|
||||
break;
|
||||
default:
|
||||
/* unkown SCCR_SATA1CM value */
|
||||
/* unkown SCCR_SATACM value */
|
||||
return -11;
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
80
doc/README.mpc8315erdb
Normal file
80
doc/README.mpc8315erdb
Normal file
|
|
@ -0,0 +1,80 @@
|
|||
Freescale MPC8315ERDB Board
|
||||
-----------------------------------------
|
||||
|
||||
1. Board Switches and Jumpers
|
||||
|
||||
S3 is used to set CFG_RESET_SOURCE.
|
||||
|
||||
To boot the image at 0xFE000000 in NOR flash, use these DIP
|
||||
switche settings for S3 S4:
|
||||
|
||||
+------+ +------+
|
||||
| | | **** |
|
||||
| **** | | |
|
||||
+------+ ON +------+ ON
|
||||
4321 4321
|
||||
(where the '*' indicates the position of the tab of the switch.)
|
||||
|
||||
2. Memory Map
|
||||
The memory map looks like this:
|
||||
|
||||
0x0000_0000 0x07ff_ffff DDR 128M
|
||||
0x8000_0000 0x8fff_ffff PCI MEM 256M
|
||||
0x9000_0000 0x9fff_ffff PCI_MMIO 256M
|
||||
0xe000_0000 0xe00f_ffff IMMR 1M
|
||||
0xe030_0000 0xe03f_ffff PCI IO 1M
|
||||
0xe060_0000 0xe060_7fff NAND FLASH (CS1) 32K
|
||||
0xfe00_0000 0xfe7f_ffff NOR FLASH (CS0) 8M
|
||||
|
||||
3. Definitions
|
||||
|
||||
3.1 Explanation of NEW definitions in:
|
||||
|
||||
include/configs/MPC8315ERDB.h
|
||||
|
||||
CONFIG_MPC83xx MPC83xx family
|
||||
CONFIG_MPC831x MPC831x specific
|
||||
CONFIG_MPC8315 MPC8315 specific
|
||||
CONFIG_MPC8315ERDB MPC8315ERDB board specific
|
||||
|
||||
4. Compilation
|
||||
|
||||
Assuming you're using BASH (or similar) as your shell:
|
||||
|
||||
export CROSS_COMPILE=your-cross-compiler-prefix-
|
||||
make distclean
|
||||
make MPC8315ERDB_config
|
||||
make all
|
||||
|
||||
5. Downloading and Flashing Images
|
||||
|
||||
5.1 Reflash U-boot Image using U-boot
|
||||
|
||||
tftp 40000 u-boot.bin
|
||||
protect off all
|
||||
erase fe000000 fe1fffff
|
||||
|
||||
cp.b 40000 fe000000 xxxx
|
||||
protect on all
|
||||
|
||||
You have to supply the correct byte count with 'xxxx'
|
||||
from the TFTP result log.
|
||||
|
||||
5.2 Downloading and Booting Linux Kernel
|
||||
|
||||
Ensure that all networking-related environment variables are set
|
||||
properly (including ipaddr, serverip, gatewayip (if needed),
|
||||
netmask, ethaddr, eth1addr, rootpath (if using NFS root),
|
||||
fdtfile, and bootfile).
|
||||
|
||||
Then, do one of the following, depending on whether you
|
||||
want an NFS root or a ramdisk root:
|
||||
|
||||
=>run nfsboot
|
||||
or
|
||||
=>run ramboot
|
||||
|
||||
6 Notes
|
||||
|
||||
Booting from NAND flash is not yet supported.
|
||||
The console baudrate for MPC8315ERDB is 115200bps.
|
||||
98
doc/README.mpc837xerdb
Normal file
98
doc/README.mpc837xerdb
Normal file
|
|
@ -0,0 +1,98 @@
|
|||
Freescale MPC837xEMDS Board
|
||||
-----------------------------------------
|
||||
|
||||
1. Board Description
|
||||
|
||||
The MPC837xE-RDB are reference boards featuring the Freescale MPC8377E,
|
||||
MPC8378E, and the MPC8379E processors in a Mini-ITX form factor.
|
||||
|
||||
The MPC837xE-RDB's have the following common features:
|
||||
|
||||
A) 256-MBytes on-board DDR2 unbuffered SDRAM
|
||||
B) 8-Mbytes NOR Flash
|
||||
C) 32-MBytes NAND Flash
|
||||
D) 1 Secure Digital High Speed Card (SDHC) Interface
|
||||
E) 1 Gigabit Ethernet
|
||||
F) 5-port Ethernet switch (Vitesse 7385)
|
||||
G) 1 32-bit, 3.3 V, PCI slot
|
||||
H) 1 32-bit, 3.3 V, Mini-PCI slot
|
||||
I) 4-port USB 2.0 Hub
|
||||
J) 1-port OTG USB
|
||||
K) 2 serial ports (top main console)
|
||||
L) on board Oscillator: 66M
|
||||
|
||||
The MPC837xE-RDB's have the following differences:
|
||||
|
||||
MPC8377E-RDB MPC8378E-RDB MPC8379E-RDB
|
||||
SATA controllers 2 0 4
|
||||
PCI-Express (mini) 2 2 0
|
||||
SGMII Ports 0 2 0
|
||||
|
||||
|
||||
2. Memory Map
|
||||
|
||||
2.1. The memory map should look pretty much like this:
|
||||
|
||||
Address Range Device Size Port Size
|
||||
(Bytes) (Bits)
|
||||
=========================== ================= ======= =========
|
||||
0x0000_0000 0x0fff_ffff DDR 256M 64
|
||||
0x1000_0000 0x7fff_ffff Empty 1.75G -
|
||||
0x8000_0000 0x9fff_ffff PCI1 memory space 512M 32
|
||||
0xa000_0000 0xbfff_ffff PCI2 memory space 512M 32
|
||||
0xc200_0000 0xc2ff_ffff PCI1 I/O space 16M 32
|
||||
0xc300_0000 0xc3ff_ffff PCI2 I/O space 16M 32
|
||||
0xe000_0000 0xe00f_ffff Int Mem Reg Space 1M -
|
||||
0xe280_0000 0xe47f_ffff NAND Flash 32M 8
|
||||
0xfe00_0000 0xfe7f_ffff NOR Flash on CS0 8M 16
|
||||
|
||||
|
||||
3. Definitions
|
||||
|
||||
3.1 Explanation of NEW definitions in:
|
||||
|
||||
include/configs/MPC837XERDB.h
|
||||
|
||||
CONFIG_MPC83XX MPC83xx family for both MPC8349 and MPC8360
|
||||
CONFIG_MPC837X MPC837x specific
|
||||
CONFIG_MPC837XERDB MPC837XEMDS board specific
|
||||
|
||||
|
||||
4. Compilation
|
||||
|
||||
Assuming you're using BASH shell:
|
||||
|
||||
export CROSS_COMPILE=your-cross-compile-prefix
|
||||
cd u-boot
|
||||
make distclean
|
||||
make MPC837XERDB_config
|
||||
make
|
||||
|
||||
|
||||
5. Downloading and Flashing Images
|
||||
|
||||
5.0 Download over serial line using Kermit:
|
||||
|
||||
loadb $loadaddr
|
||||
[Drop to kermit:
|
||||
^\c
|
||||
send <u-boot-bin-image>
|
||||
c
|
||||
]
|
||||
|
||||
|
||||
Or via tftp:
|
||||
|
||||
tftp $loadaddr u-boot.bin
|
||||
|
||||
5.1 Reflash U-boot Image using U-boot
|
||||
|
||||
tftp $loadaddr u-boot.bin
|
||||
protect off fe000000 fe0fffff
|
||||
erase fe000000 fe0fffff
|
||||
cp.b $loadaddr fe000000 $filesize
|
||||
|
||||
|
||||
6. Additional Notes:
|
||||
1) The console is connected to the top RS-232 connector and the
|
||||
baudrate for MPC837XE-RDB is 115200bps.
|
||||
|
|
@ -32,6 +32,8 @@ COBJS-y += nand_ecc.o
|
|||
COBJS-y += nand_bbt.o
|
||||
COBJS-y += nand_util.o
|
||||
|
||||
COBJS-y += fsl_upm.o
|
||||
|
||||
COBJS := $(COBJS-y)
|
||||
SRCS := $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
|
|
|||
201
drivers/mtd/nand/fsl_upm.c
Normal file
201
drivers/mtd/nand/fsl_upm.c
Normal file
|
|
@ -0,0 +1,201 @@
|
|||
/*
|
||||
* FSL UPM NAND driver
|
||||
*
|
||||
* Copyright (C) 2007 MontaVista Software, Inc.
|
||||
* Anton Vorontsov <avorontsov@ru.mvista.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
|
||||
#if defined(CONFIG_CMD_NAND) && defined(CONFIG_NAND_FSL_UPM)
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/errno.h>
|
||||
#include <linux/mtd/mtd.h>
|
||||
#include <linux/mtd/fsl_upm.h>
|
||||
#include <nand.h>
|
||||
|
||||
#define FSL_UPM_MxMR_OP_NO (0 << 28) /* normal operation */
|
||||
#define FSL_UPM_MxMR_OP_WA (1 << 28) /* write array */
|
||||
#define FSL_UPM_MxMR_OP_RA (2 << 28) /* read array */
|
||||
#define FSL_UPM_MxMR_OP_RP (3 << 28) /* run pattern */
|
||||
|
||||
static void fsl_upm_start_pattern(struct fsl_upm *upm, u32 pat_offset)
|
||||
{
|
||||
out_be32(upm->mxmr, FSL_UPM_MxMR_OP_RP | pat_offset);
|
||||
}
|
||||
|
||||
static void fsl_upm_end_pattern(struct fsl_upm *upm)
|
||||
{
|
||||
out_be32(upm->mxmr, FSL_UPM_MxMR_OP_NO);
|
||||
while (in_be32(upm->mxmr) != FSL_UPM_MxMR_OP_NO)
|
||||
eieio();
|
||||
}
|
||||
|
||||
static void fsl_upm_run_pattern(struct fsl_upm *upm, int width, u32 cmd)
|
||||
{
|
||||
out_be32(upm->mar, cmd << (32 - width * 8));
|
||||
out_8(upm->io_addr, 0x0);
|
||||
}
|
||||
|
||||
static void fsl_upm_setup(struct fsl_upm *upm)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* write upm array */
|
||||
out_be32(upm->mxmr, FSL_UPM_MxMR_OP_WA);
|
||||
|
||||
for (i = 0; i < 64; i++) {
|
||||
out_be32(upm->mdr, upm->array[i]);
|
||||
out_8(upm->io_addr, 0x0);
|
||||
}
|
||||
|
||||
/* normal operation */
|
||||
out_be32(upm->mxmr, FSL_UPM_MxMR_OP_NO);
|
||||
while (in_be32(upm->mxmr) != FSL_UPM_MxMR_OP_NO)
|
||||
eieio();
|
||||
}
|
||||
|
||||
static void fun_cmdfunc(struct mtd_info *mtd, unsigned command, int column,
|
||||
int page_addr)
|
||||
{
|
||||
struct nand_chip *chip = mtd->priv;
|
||||
struct fsl_upm_nand *fun = chip->priv;
|
||||
|
||||
fsl_upm_start_pattern(&fun->upm, fun->upm_cmd_offset);
|
||||
|
||||
if (command == NAND_CMD_SEQIN) {
|
||||
int readcmd;
|
||||
|
||||
if (column >= mtd->oobblock) {
|
||||
/* OOB area */
|
||||
column -= mtd->oobblock;
|
||||
readcmd = NAND_CMD_READOOB;
|
||||
} else if (column < 256) {
|
||||
/* First 256 bytes --> READ0 */
|
||||
readcmd = NAND_CMD_READ0;
|
||||
} else {
|
||||
column -= 256;
|
||||
readcmd = NAND_CMD_READ1;
|
||||
}
|
||||
fsl_upm_run_pattern(&fun->upm, fun->width, readcmd);
|
||||
}
|
||||
|
||||
fsl_upm_run_pattern(&fun->upm, fun->width, command);
|
||||
|
||||
fsl_upm_end_pattern(&fun->upm);
|
||||
|
||||
fsl_upm_start_pattern(&fun->upm, fun->upm_addr_offset);
|
||||
|
||||
if (column != -1)
|
||||
fsl_upm_run_pattern(&fun->upm, fun->width, column);
|
||||
|
||||
if (page_addr != -1) {
|
||||
fsl_upm_run_pattern(&fun->upm, fun->width, page_addr);
|
||||
fsl_upm_run_pattern(&fun->upm, fun->width,
|
||||
(page_addr >> 8) & 0xFF);
|
||||
if (chip->chipsize > (32 << 20)) {
|
||||
fsl_upm_run_pattern(&fun->upm, fun->width,
|
||||
(page_addr >> 16) & 0x0f);
|
||||
}
|
||||
}
|
||||
|
||||
fsl_upm_end_pattern(&fun->upm);
|
||||
|
||||
if (fun->wait_pattern) {
|
||||
/*
|
||||
* Some boards/chips needs this. At least on MPC8360E-RDK we
|
||||
* need it. Probably weird chip, because I don't see any need
|
||||
* for this on MPC8555E + Samsung K9F1G08U0A. Usually here are
|
||||
* 0-2 unexpected busy states per block read.
|
||||
*/
|
||||
while (!fun->dev_ready())
|
||||
debug("unexpected busy state\n");
|
||||
}
|
||||
}
|
||||
|
||||
static void nand_write_byte(struct mtd_info *mtd, u_char byte)
|
||||
{
|
||||
struct nand_chip *chip = mtd->priv;
|
||||
|
||||
out_8(chip->IO_ADDR_W, byte);
|
||||
}
|
||||
|
||||
static u8 nand_read_byte(struct mtd_info *mtd)
|
||||
{
|
||||
struct nand_chip *chip = mtd->priv;
|
||||
|
||||
return in_8(chip->IO_ADDR_R);
|
||||
}
|
||||
|
||||
static void nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
|
||||
{
|
||||
int i;
|
||||
struct nand_chip *chip = mtd->priv;
|
||||
|
||||
for (i = 0; i < len; i++)
|
||||
out_8(chip->IO_ADDR_W, buf[i]);
|
||||
}
|
||||
|
||||
static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
|
||||
{
|
||||
int i;
|
||||
struct nand_chip *chip = mtd->priv;
|
||||
|
||||
for (i = 0; i < len; i++)
|
||||
buf[i] = in_8(chip->IO_ADDR_R);
|
||||
}
|
||||
|
||||
static int nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
|
||||
{
|
||||
int i;
|
||||
struct nand_chip *chip = mtd->priv;
|
||||
|
||||
for (i = 0; i < len; i++) {
|
||||
if (buf[i] != in_8(chip->IO_ADDR_R))
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void nand_hwcontrol(struct mtd_info *mtd, int cmd)
|
||||
{
|
||||
}
|
||||
|
||||
static int nand_dev_ready(struct mtd_info *mtd)
|
||||
{
|
||||
struct nand_chip *chip = mtd->priv;
|
||||
struct fsl_upm_nand *fun = chip->priv;
|
||||
|
||||
return fun->dev_ready();
|
||||
}
|
||||
|
||||
int fsl_upm_nand_init(struct nand_chip *chip, struct fsl_upm_nand *fun)
|
||||
{
|
||||
/* yet only 8 bit accessors implemented */
|
||||
if (fun->width != 1)
|
||||
return -ENOSYS;
|
||||
|
||||
fsl_upm_setup(&fun->upm);
|
||||
|
||||
chip->priv = fun;
|
||||
chip->chip_delay = fun->chip_delay;
|
||||
chip->eccmode = NAND_ECC_SOFT;
|
||||
chip->cmdfunc = fun_cmdfunc;
|
||||
chip->hwcontrol = nand_hwcontrol;
|
||||
chip->read_byte = nand_read_byte;
|
||||
chip->read_buf = nand_read_buf;
|
||||
chip->write_byte = nand_write_byte;
|
||||
chip->write_buf = nand_write_buf;
|
||||
chip->verify_buf = nand_verify_buf;
|
||||
chip->dev_ready = nand_dev_ready;
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_CMD_NAND */
|
||||
|
|
@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
|
|||
|
||||
LIB := $(obj)libonenand.a
|
||||
|
||||
COBJS := onenand_base.o onenand_bbt.o
|
||||
COBJS := onenand_uboot.o onenand_base.o onenand_bbt.o
|
||||
|
||||
SRCS := $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
|
|
|||
|
|
@ -1271,24 +1271,4 @@ void onenand_release(struct mtd_info *mtd)
|
|||
{
|
||||
}
|
||||
|
||||
/*
|
||||
* OneNAND initialization at U-Boot
|
||||
*/
|
||||
struct mtd_info onenand_mtd;
|
||||
struct onenand_chip onenand_chip;
|
||||
|
||||
void onenand_init(void)
|
||||
{
|
||||
memset(&onenand_mtd, 0, sizeof(struct mtd_info));
|
||||
memset(&onenand_chip, 0, sizeof(struct onenand_chip));
|
||||
|
||||
onenand_chip.base = (void *)CFG_ONENAND_BASE;
|
||||
onenand_mtd.priv = &onenand_chip;
|
||||
|
||||
onenand_scan(&onenand_mtd, 1);
|
||||
|
||||
puts("OneNAND: ");
|
||||
print_size(onenand_mtd.size, "\n");
|
||||
}
|
||||
|
||||
#endif /* CONFIG_CMD_ONENAND */
|
||||
|
|
|
|||
41
drivers/mtd/onenand/onenand_uboot.c
Normal file
41
drivers/mtd/onenand/onenand_uboot.c
Normal file
|
|
@ -0,0 +1,41 @@
|
|||
/*
|
||||
* drivers/mtd/onenand/onenand_uboot.c
|
||||
*
|
||||
* Copyright (C) 2005-2008 Samsung Electronics
|
||||
* Kyungmin Park <kyungmin.park@samsung.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/*
|
||||
* OneNAND initialization at U-Boot
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
|
||||
#ifdef CONFIG_CMD_ONENAND
|
||||
|
||||
#include <linux/mtd/compat.h>
|
||||
#include <linux/mtd/mtd.h>
|
||||
#include <linux/mtd/onenand.h>
|
||||
|
||||
struct mtd_info onenand_mtd;
|
||||
struct onenand_chip onenand_chip;
|
||||
|
||||
void onenand_init(void)
|
||||
{
|
||||
memset(&onenand_mtd, 0, sizeof(struct mtd_info));
|
||||
memset(&onenand_chip, 0, sizeof(struct onenand_chip));
|
||||
|
||||
onenand_chip.base = (void *) CFG_ONENAND_BASE;
|
||||
onenand_mtd.priv = &onenand_chip;
|
||||
|
||||
onenand_scan(&onenand_mtd, 1);
|
||||
|
||||
puts("OneNAND: ");
|
||||
print_size(onenand_mtd.size, "\n");
|
||||
}
|
||||
|
||||
#endif /* CONFIG_CMD_ONENAND */
|
||||
|
|
@ -76,10 +76,10 @@
|
|||
* seem to have the SPD connected to I2C.
|
||||
*/
|
||||
#define CFG_DDR_SIZE 128 /* MB */
|
||||
#define CFG_DDR_CONFIG ( CSCONFIG_EN | CSCONFIG_AP \
|
||||
| 0x00040000 /* TODO */ \
|
||||
#define CFG_DDR_CONFIG ( CSCONFIG_EN \
|
||||
| 0x00010000 /* TODO */ \
|
||||
| CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 )
|
||||
/* 0x80840102 */
|
||||
/* 0x80010102 */
|
||||
|
||||
#define CFG_DDR_TIMING_3 0x00000000
|
||||
#define CFG_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
|
||||
|
|
@ -92,25 +92,25 @@
|
|||
| ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
|
||||
/* 0x00220802 */
|
||||
#define CFG_DDR_TIMING_1 ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \
|
||||
| ( 9 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
|
||||
| ( 8 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
|
||||
| ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \
|
||||
| ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
|
||||
| (13 << TIMING_CFG1_REFREC_SHIFT ) \
|
||||
| (10 << TIMING_CFG1_REFREC_SHIFT ) \
|
||||
| ( 3 << TIMING_CFG1_WRREC_SHIFT ) \
|
||||
| ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
|
||||
| ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
|
||||
/* 0x3935d322 */
|
||||
#define CFG_DDR_TIMING_2 ( ( 0 << TIMING_CFG2_ADD_LAT_SHIFT ) \
|
||||
| (31 << TIMING_CFG2_CPO_SHIFT ) \
|
||||
/* 0x3835a322 */
|
||||
#define CFG_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \
|
||||
| ( 5 << TIMING_CFG2_CPO_SHIFT ) \
|
||||
| ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
|
||||
| ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
|
||||
| ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
|
||||
| ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
|
||||
| (10 << TIMING_CFG2_FOUR_ACT_SHIFT) )
|
||||
/* 0x0f9048ca */ /* P9-45,may need tuning */
|
||||
#define CFG_DDR_INTERVAL ( ( 800 << SDRAM_INTERVAL_REFINT_SHIFT ) \
|
||||
| ( 100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
|
||||
/* 0x03200064 */
|
||||
| ( 6 << TIMING_CFG2_FOUR_ACT_SHIFT) )
|
||||
/* 0x129048c6 */ /* P9-45,may need tuning */
|
||||
#define CFG_DDR_INTERVAL ( ( 1296 << SDRAM_INTERVAL_REFINT_SHIFT ) \
|
||||
| ( 1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
|
||||
/* 0x05100500 */
|
||||
#if defined(CONFIG_DDR_2T_TIMING)
|
||||
#define CFG_SDRAM_CFG ( SDRAM_CFG_SREN \
|
||||
| SDRAM_CFG_SDRAM_TYPE_DDR2 \
|
||||
|
|
@ -124,9 +124,9 @@
|
|||
#endif
|
||||
#define CFG_SDRAM_CFG2 0x00401000;
|
||||
/* set burst length to 8 for 32-bit data path */
|
||||
#define CFG_DDR_MODE ( ( 0x4440 << SDRAM_MODE_ESD_SHIFT ) \
|
||||
| ( 0x0232 << SDRAM_MODE_SD_SHIFT ) )
|
||||
/* 0x44400232 */
|
||||
#define CFG_DDR_MODE ( ( 0x4448 << SDRAM_MODE_ESD_SHIFT ) \
|
||||
| ( 0x0632 << SDRAM_MODE_SD_SHIFT ) )
|
||||
/* 0x44480632 */
|
||||
#define CFG_DDR_MODE_2 0x8000C000;
|
||||
|
||||
#define CFG_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
|
||||
|
|
|
|||
547
include/configs/MPC8315ERDB.h
Normal file
547
include/configs/MPC8315ERDB.h
Normal file
|
|
@ -0,0 +1,547 @@
|
|||
/*
|
||||
* Copyright (C) 2007 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Dave Liu <daveliu@freescale.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#undef DEBUG
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
*/
|
||||
#define CONFIG_E300 1 /* E300 family */
|
||||
#define CONFIG_MPC83XX 1 /* MPC83xx family */
|
||||
#define CONFIG_MPC831X 1 /* MPC831x CPU family */
|
||||
#define CONFIG_MPC8315 1 /* MPC8315 CPU specific */
|
||||
#define CONFIG_MPC8315ERDB 1 /* MPC8315ERDB board specific */
|
||||
|
||||
/*
|
||||
* System Clock Setup
|
||||
*/
|
||||
#define CONFIG_83XX_CLKIN 66666667 /* in Hz */
|
||||
#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
|
||||
|
||||
/*
|
||||
* Hardware Reset Configuration Word
|
||||
* if CLKIN is 66.66MHz, then
|
||||
* CSB = 133MHz, CORE = 400MHz, DDRC = 266MHz, LBC = 133MHz
|
||||
*/
|
||||
#define CFG_HRCW_LOW (\
|
||||
HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
|
||||
HRCWL_DDR_TO_SCB_CLK_2X1 |\
|
||||
HRCWL_SVCOD_DIV_2 |\
|
||||
HRCWL_CSB_TO_CLKIN_2X1 |\
|
||||
HRCWL_CORE_TO_CSB_3X1)
|
||||
#define CFG_HRCW_HIGH (\
|
||||
HRCWH_PCI_HOST |\
|
||||
HRCWH_PCI1_ARBITER_ENABLE |\
|
||||
HRCWH_CORE_ENABLE |\
|
||||
HRCWH_FROM_0X00000100 |\
|
||||
HRCWH_BOOTSEQ_DISABLE |\
|
||||
HRCWH_SW_WATCHDOG_DISABLE |\
|
||||
HRCWH_ROM_LOC_LOCAL_16BIT |\
|
||||
HRCWH_RL_EXT_LEGACY |\
|
||||
HRCWH_TSEC1M_IN_RGMII |\
|
||||
HRCWH_TSEC2M_IN_RGMII |\
|
||||
HRCWH_BIG_ENDIAN |\
|
||||
HRCWH_LALE_NORMAL)
|
||||
|
||||
/*
|
||||
* System IO Config
|
||||
*/
|
||||
#define CFG_SICRH 0x00000000
|
||||
#define CFG_SICRL 0x00000000 /* 3.3V, no delay */
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
|
||||
|
||||
/*
|
||||
* IMMR new address
|
||||
*/
|
||||
#define CFG_IMMR 0xE0000000
|
||||
|
||||
/*
|
||||
* Arbiter Setup
|
||||
*/
|
||||
#define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
|
||||
#define CFG_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
|
||||
#define CFG_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
|
||||
|
||||
/*
|
||||
* DDR Setup
|
||||
*/
|
||||
#define CFG_DDR_BASE 0x00000000 /* DDR is system memory */
|
||||
#define CFG_SDRAM_BASE CFG_DDR_BASE
|
||||
#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE
|
||||
#define CFG_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
|
||||
#define CFG_DDRCDR_VALUE ( DDRCDR_EN \
|
||||
| DDRCDR_PZ_LOZ \
|
||||
| DDRCDR_NZ_LOZ \
|
||||
| DDRCDR_ODT \
|
||||
| DDRCDR_Q_DRN )
|
||||
/* 0x7b880001 */
|
||||
/*
|
||||
* Manually set up DDR parameters
|
||||
* consist of two chips HY5PS12621BFP-C4 from HYNIX
|
||||
*/
|
||||
#define CFG_DDR_SIZE 128 /* MB */
|
||||
#define CFG_DDR_CS0_BNDS 0x00000007
|
||||
#define CFG_DDR_CS0_CONFIG ( CSCONFIG_EN \
|
||||
| 0x00010000 /* ODT_WR to CSn */ \
|
||||
| CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 )
|
||||
/* 0x80010102 */
|
||||
#define CFG_DDR_TIMING_3 0x00000000
|
||||
#define CFG_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
|
||||
| ( 0 << TIMING_CFG0_WRT_SHIFT ) \
|
||||
| ( 0 << TIMING_CFG0_RRT_SHIFT ) \
|
||||
| ( 0 << TIMING_CFG0_WWT_SHIFT ) \
|
||||
| ( 2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \
|
||||
| ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \
|
||||
| ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \
|
||||
| ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
|
||||
/* 0x00220802 */
|
||||
#define CFG_DDR_TIMING_1 ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \
|
||||
| ( 9 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
|
||||
| ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \
|
||||
| ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
|
||||
| ( 6 << TIMING_CFG1_REFREC_SHIFT ) \
|
||||
| ( 2 << TIMING_CFG1_WRREC_SHIFT ) \
|
||||
| ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
|
||||
| ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
|
||||
/* 0x39356222 */
|
||||
#define CFG_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \
|
||||
| ( 4 << TIMING_CFG2_CPO_SHIFT ) \
|
||||
| ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
|
||||
| ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
|
||||
| ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
|
||||
| ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
|
||||
| ( 7 << TIMING_CFG2_FOUR_ACT_SHIFT) )
|
||||
/* 0x121048c7 */
|
||||
#define CFG_DDR_INTERVAL ( ( 0x0360 << SDRAM_INTERVAL_REFINT_SHIFT ) \
|
||||
| ( 0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
|
||||
/* 0x03600100 */
|
||||
#define CFG_DDR_SDRAM_CFG ( SDRAM_CFG_SREN \
|
||||
| SDRAM_CFG_SDRAM_TYPE_DDR2 \
|
||||
| SDRAM_CFG_32_BE )
|
||||
/* 0x43080000 */
|
||||
#define CFG_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
|
||||
#define CFG_DDR_MODE ( ( 0x0448 << SDRAM_MODE_ESD_SHIFT ) \
|
||||
| ( 0x0232 << SDRAM_MODE_SD_SHIFT ) )
|
||||
/* ODT 150ohm CL=3, AL=1 on SDRAM */
|
||||
#define CFG_DDR_MODE2 0x00000000
|
||||
|
||||
/*
|
||||
* Memory test
|
||||
*/
|
||||
#undef CFG_DRAM_TEST /* memory test, takes time */
|
||||
#define CFG_MEMTEST_START 0x00040000 /* memtest region */
|
||||
#define CFG_MEMTEST_END 0x00140000
|
||||
|
||||
/*
|
||||
* The reserved memory
|
||||
*/
|
||||
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
|
||||
|
||||
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
|
||||
#define CFG_RAMBOOT
|
||||
#else
|
||||
#undef CFG_RAMBOOT
|
||||
#endif
|
||||
|
||||
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
|
||||
#define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
|
||||
|
||||
/*
|
||||
* Initial RAM Base Address Setup
|
||||
*/
|
||||
#define CFG_INIT_RAM_LOCK 1
|
||||
#define CFG_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
|
||||
#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM */
|
||||
#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */
|
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
|
||||
|
||||
/*
|
||||
* Local Bus Configuration & Clock Setup
|
||||
*/
|
||||
#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_2)
|
||||
#define CFG_LBC_LBCR 0x00040000
|
||||
|
||||
/*
|
||||
* FLASH on the Local Bus
|
||||
*/
|
||||
#define CFG_FLASH_CFI /* use the Common Flash Interface */
|
||||
#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
|
||||
#define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
|
||||
|
||||
#define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */
|
||||
#define CFG_FLASH_SIZE 8 /* FLASH size is 8M */
|
||||
|
||||
#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */
|
||||
#define CFG_LBLAWAR0_PRELIM 0x80000016 /* 8MB window size */
|
||||
|
||||
#define CFG_BR0_PRELIM ( CFG_FLASH_BASE /* Flash Base address */ \
|
||||
| (2 << BR_PS_SHIFT) /* 16 bit port size */ \
|
||||
| BR_V ) /* valid */
|
||||
#define CFG_OR0_PRELIM ( (~(CFG_FLASH_SIZE - 1) << 20) \
|
||||
| OR_UPM_XAM \
|
||||
| OR_GPCM_CSNT \
|
||||
| OR_GPCM_ACS_0b11 \
|
||||
| OR_GPCM_XACS \
|
||||
| OR_GPCM_SCY_15 \
|
||||
| OR_GPCM_TRLX \
|
||||
| OR_GPCM_EHTR \
|
||||
| OR_GPCM_EAD )
|
||||
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
|
||||
#define CFG_MAX_FLASH_SECT 135 /* 127 64KB sectors and 8 8KB top sectors per device */
|
||||
|
||||
#undef CFG_FLASH_CHECKSUM
|
||||
#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
|
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
|
||||
|
||||
/*
|
||||
* NAND Flash on the Local Bus
|
||||
*/
|
||||
#define CFG_NAND_BASE 0xE0600000 /* 0xE0600000 */
|
||||
#define CFG_MAX_NAND_DEVICE 1
|
||||
#define NAND_MAX_CHIPS 1
|
||||
#define CONFIG_MTD_NAND_VERIFY_WRITE
|
||||
|
||||
#define CFG_BR1_PRELIM ( CFG_NAND_BASE \
|
||||
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
|
||||
| BR_PS_8 /* Port Size = 8 bit */ \
|
||||
| BR_MS_FCM /* MSEL = FCM */ \
|
||||
| BR_V ) /* valid */
|
||||
#define CFG_OR1_PRELIM ( 0xFFFF8000 /* length 32K */ \
|
||||
| OR_FCM_CSCT \
|
||||
| OR_FCM_CST \
|
||||
| OR_FCM_CHT \
|
||||
| OR_FCM_SCY_1 \
|
||||
| OR_FCM_TRLX \
|
||||
| OR_FCM_EHTR )
|
||||
/* 0xFFFF8396 */
|
||||
|
||||
#define CFG_LBLAWBAR1_PRELIM CFG_NAND_BASE
|
||||
#define CFG_LBLAWAR1_PRELIM 0x8000000E /* 32KB */
|
||||
|
||||
/*
|
||||
* Serial Port
|
||||
*/
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
#undef CONFIG_SERIAL_SOFTWARE_FIFO
|
||||
#define CFG_NS16550
|
||||
#define CFG_NS16550_SERIAL
|
||||
#define CFG_NS16550_REG_SIZE 1
|
||||
#define CFG_NS16550_CLK get_bus_freq(0)
|
||||
|
||||
#define CFG_BAUDRATE_TABLE \
|
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
|
||||
|
||||
#define CFG_NS16550_COM1 (CFG_IMMR+0x4500)
|
||||
#define CFG_NS16550_COM2 (CFG_IMMR+0x4600)
|
||||
|
||||
/* Use the HUSH parser */
|
||||
#define CFG_HUSH_PARSER
|
||||
#ifdef CFG_HUSH_PARSER
|
||||
#define CFG_PROMPT_HUSH_PS2 "> "
|
||||
#endif
|
||||
|
||||
/* Pass open firmware flat tree */
|
||||
#define CONFIG_OF_LIBFDT 1
|
||||
#define CONFIG_OF_BOARD_SETUP 1
|
||||
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#define CONFIG_FSL_I2C
|
||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CFG_I2C_SLAVE 0x7F
|
||||
#define CFG_I2C_NOPROBES {0x51} /* Don't probe these addrs */
|
||||
#define CFG_I2C_OFFSET 0x3000
|
||||
#define CFG_I2C2_OFFSET 0x3100
|
||||
|
||||
/*
|
||||
* Board info - revision and where boot from
|
||||
*/
|
||||
#define CFG_I2C_PCF8574A_ADDR 0x39
|
||||
|
||||
/*
|
||||
* Config on-board RTC
|
||||
*/
|
||||
#define CONFIG_RTC_DS1337 /* ds1339 on board, use ds1337 rtc via i2c */
|
||||
#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
|
||||
|
||||
/*
|
||||
* General PCI
|
||||
* Addresses are mapped 1-1.
|
||||
*/
|
||||
#define CFG_PCI_MEM_BASE 0x80000000
|
||||
#define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BASE
|
||||
#define CFG_PCI_MEM_SIZE 0x10000000 /* 256M */
|
||||
#define CFG_PCI_MMIO_BASE 0x90000000
|
||||
#define CFG_PCI_MMIO_PHYS CFG_PCI_MMIO_BASE
|
||||
#define CFG_PCI_MMIO_SIZE 0x10000000 /* 256M */
|
||||
#define CFG_PCI_IO_BASE 0xE0300000
|
||||
#define CFG_PCI_IO_PHYS 0xE0300000
|
||||
#define CFG_PCI_IO_SIZE 0x100000 /* 1M */
|
||||
|
||||
#define CFG_PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE
|
||||
#define CFG_PCI_SLV_MEM_BUS 0x00000000
|
||||
#define CFG_PCI_SLV_MEM_SIZE 0x80000000
|
||||
|
||||
#define CONFIG_PCI
|
||||
#define CONFIG_83XX_GENERIC_PCI 1 /* Use generic PCI setup */
|
||||
|
||||
#define CONFIG_NET_MULTI
|
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
||||
|
||||
#define CONFIG_EEPRO100
|
||||
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
||||
#define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
|
||||
|
||||
#ifndef CONFIG_NET_MULTI
|
||||
#define CONFIG_NET_MULTI 1
|
||||
#endif
|
||||
|
||||
/*
|
||||
* TSEC
|
||||
*/
|
||||
#define CONFIG_TSEC_ENET /* TSEC ethernet support */
|
||||
#define CFG_TSEC1_OFFSET 0x24000
|
||||
#define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET)
|
||||
#define CFG_TSEC2_OFFSET 0x25000
|
||||
#define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET)
|
||||
|
||||
/*
|
||||
* TSEC ethernet configuration
|
||||
*/
|
||||
#define CONFIG_MII 1 /* MII PHY management */
|
||||
#define CONFIG_TSEC1 1
|
||||
#define CONFIG_TSEC1_NAME "eTSEC0"
|
||||
#define CONFIG_TSEC2 1
|
||||
#define CONFIG_TSEC2_NAME "eTSEC1"
|
||||
#define TSEC1_PHY_ADDR 0
|
||||
#define TSEC2_PHY_ADDR 1
|
||||
#define TSEC1_PHYIDX 0
|
||||
#define TSEC2_PHYIDX 0
|
||||
#define TSEC1_FLAGS TSEC_GIGABIT
|
||||
#define TSEC2_FLAGS TSEC_GIGABIT
|
||||
|
||||
/* Options are: eTSEC[0-1] */
|
||||
#define CONFIG_ETHPRIME "eTSEC1"
|
||||
|
||||
/*
|
||||
* Environment
|
||||
*/
|
||||
#ifndef CFG_RAMBOOT
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
|
||||
#define CFG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
|
||||
#define CFG_ENV_SIZE 0x2000
|
||||
#else
|
||||
#define CFG_NO_FLASH 1 /* Flash is not usable now */
|
||||
#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
|
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
|
||||
#define CFG_ENV_SIZE 0x2000
|
||||
#endif
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
||||
#define CONFIG_BOOTP_BOOTPATH
|
||||
#define CONFIG_BOOTP_GATEWAY
|
||||
#define CONFIG_BOOTP_HOSTNAME
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_DATE
|
||||
#define CONFIG_CMD_PCI
|
||||
|
||||
#if defined(CFG_RAMBOOT)
|
||||
#undef CONFIG_CMD_ENV
|
||||
#undef CONFIG_CMD_LOADS
|
||||
#endif
|
||||
|
||||
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
|
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CFG_LONGHELP /* undef to save memory */
|
||||
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
|
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
|
||||
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CFG_MAXARGS 16 /* max number of command args */
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
|
||||
/*
|
||||
* Core HID Setup
|
||||
*/
|
||||
#define CFG_HID0_INIT 0x000000000
|
||||
#define CFG_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
|
||||
HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
|
||||
#define CFG_HID2 HID2_HBE
|
||||
|
||||
/*
|
||||
* MMU Setup
|
||||
*/
|
||||
|
||||
/* DDR: cache cacheable */
|
||||
#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
|
||||
#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_128M | BATU_VS | BATU_VP)
|
||||
#define CFG_DBAT0L CFG_IBAT0L
|
||||
#define CFG_DBAT0U CFG_IBAT0U
|
||||
|
||||
/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
|
||||
#define CFG_IBAT1L (CFG_IMMR | BATL_PP_10 | \
|
||||
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
||||
#define CFG_IBAT1U (CFG_IMMR | BATU_BL_8M | BATU_VS | BATU_VP)
|
||||
#define CFG_DBAT1L CFG_IBAT1L
|
||||
#define CFG_DBAT1U CFG_IBAT1U
|
||||
|
||||
/* FLASH: icache cacheable, but dcache-inhibit and guarded */
|
||||
#define CFG_IBAT2L (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
|
||||
#define CFG_IBAT2U (CFG_FLASH_BASE | BATU_BL_8M | BATU_VS | BATU_VP)
|
||||
#define CFG_DBAT2L (CFG_FLASH_BASE | BATL_PP_10 | \
|
||||
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
||||
#define CFG_DBAT2U CFG_IBAT2U
|
||||
|
||||
/* Stack in dcache: cacheable, no memory coherence */
|
||||
#define CFG_IBAT3L (CFG_INIT_RAM_ADDR | BATL_PP_10)
|
||||
#define CFG_IBAT3U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
|
||||
#define CFG_DBAT3L CFG_IBAT3L
|
||||
#define CFG_DBAT3U CFG_IBAT3U
|
||||
|
||||
/* PCI MEM space: cacheable */
|
||||
#define CFG_IBAT4L (CFG_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
|
||||
#define CFG_IBAT4U (CFG_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
|
||||
#define CFG_DBAT4L CFG_IBAT4L
|
||||
#define CFG_DBAT4U CFG_IBAT4U
|
||||
|
||||
/* PCI MMIO space: cache-inhibit and guarded */
|
||||
#define CFG_IBAT5L (CFG_PCI_MMIO_PHYS | BATL_PP_10 | \
|
||||
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
||||
#define CFG_IBAT5U (CFG_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
|
||||
#define CFG_DBAT5L CFG_IBAT5L
|
||||
#define CFG_DBAT5U CFG_IBAT5U
|
||||
|
||||
#define CFG_IBAT6L 0
|
||||
#define CFG_IBAT6U 0
|
||||
#define CFG_DBAT6L CFG_IBAT6L
|
||||
#define CFG_DBAT6U CFG_IBAT6U
|
||||
|
||||
#define CFG_IBAT7L 0
|
||||
#define CFG_IBAT7U 0
|
||||
#define CFG_DBAT7L CFG_IBAT7L
|
||||
#define CFG_DBAT7U CFG_IBAT7U
|
||||
|
||||
/*
|
||||
* Internal Definitions
|
||||
*
|
||||
* Boot Flags
|
||||
*/
|
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||||
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
|
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Environment Configuration
|
||||
*/
|
||||
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
#if defined(CONFIG_TSEC_ENET)
|
||||
#define CONFIG_HAS_ETH0
|
||||
#define CONFIG_ETHADDR 04:00:00:00:00:0A
|
||||
#define CONFIG_HAS_ETH1
|
||||
#define CONFIG_ETH1ADDR 04:00:00:00:00:0B
|
||||
#endif
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
|
||||
|
||||
#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
|
||||
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"netdev=eth0\0" \
|
||||
"consoledev=ttyS0\0" \
|
||||
"ramdiskaddr=1000000\0" \
|
||||
"ramdiskfile=ramfs.83xx\0" \
|
||||
"fdtaddr=400000\0" \
|
||||
"fdtfile=mpc8315erdb.dtb\0" \
|
||||
""
|
||||
|
||||
#define CONFIG_NFSBOOTCOMMAND \
|
||||
"setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=$serverip:$rootpath " \
|
||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr - $fdtaddr"
|
||||
|
||||
#define CONFIG_RAMBOOTCOMMAND \
|
||||
"setenv bootargs root=/dev/ram rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $ramdiskaddr $ramdiskfile;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr $ramdiskaddr $fdtaddr"
|
||||
|
||||
|
||||
#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
|
@ -321,7 +321,7 @@
|
|||
* QE UEC ethernet configuration
|
||||
*/
|
||||
#define CONFIG_UEC_ETH
|
||||
#define CONFIG_ETHPRIME "Freescale GETH"
|
||||
#define CONFIG_ETHPRIME "FSL UEC0"
|
||||
|
||||
#define CONFIG_UEC_ETH1 /* ETH3 */
|
||||
|
||||
|
|
|
|||
|
|
@ -377,7 +377,7 @@
|
|||
* QE UEC ethernet configuration
|
||||
*/
|
||||
#define CONFIG_UEC_ETH
|
||||
#define CONFIG_ETHPRIME "Freescale GETH"
|
||||
#define CONFIG_ETHPRIME "FSL UEC0"
|
||||
|
||||
#define CONFIG_UEC_ETH1 /* ETH3 */
|
||||
|
||||
|
|
|
|||
|
|
@ -405,7 +405,7 @@
|
|||
* QE UEC ethernet configuration
|
||||
*/
|
||||
#define CONFIG_UEC_ETH
|
||||
#define CONFIG_ETHPRIME "Freescale GETH"
|
||||
#define CONFIG_ETHPRIME "FSL UEC0"
|
||||
#define CONFIG_PHY_MODE_NEED_CHANGE
|
||||
|
||||
#define CONFIG_UEC_ETH1 /* GETH1 */
|
||||
|
|
@ -466,6 +466,7 @@
|
|||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_CMD_ASKENV
|
||||
#define CONFIG_CMD_SDRAM
|
||||
|
||||
#if defined(CONFIG_PCI)
|
||||
#define CONFIG_CMD_PCI
|
||||
|
|
|
|||
|
|
@ -282,7 +282,7 @@
|
|||
* QE UEC ethernet configuration
|
||||
*/
|
||||
#define CONFIG_UEC_ETH
|
||||
#define CONFIG_ETHPRIME "Freescale GETH"
|
||||
#define CONFIG_ETHPRIME "FSL UEC0"
|
||||
|
||||
#define CONFIG_UEC_ETH1 /* GETH1 */
|
||||
|
||||
|
|
@ -386,15 +386,6 @@
|
|||
#define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
|
||||
#define CFG_HID2 HID2_HBE
|
||||
|
||||
/*
|
||||
* Cache Config
|
||||
*/
|
||||
#define CFG_DCACHE_SIZE 32768
|
||||
#define CFG_CACHELINE_SIZE 32
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* MMU Setup
|
||||
*/
|
||||
|
|
|
|||
596
include/configs/MPC837XERDB.h
Normal file
596
include/configs/MPC837XERDB.h
Normal file
|
|
@ -0,0 +1,596 @@
|
|||
/*
|
||||
* Copyright (C) 2007 Freescale Semiconductor, Inc.
|
||||
* Kevin Lam <kevin.lam@freescale.com>
|
||||
* Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
*/
|
||||
#define CONFIG_E300 1 /* E300 family */
|
||||
#define CONFIG_MPC83XX 1 /* MPC83XX family */
|
||||
#define CONFIG_MPC837X 1 /* MPC837X CPU specific */
|
||||
#define CONFIG_MPC837XERDB 1
|
||||
|
||||
#define CONFIG_PCI 1
|
||||
|
||||
/*
|
||||
* System Clock Setup
|
||||
*/
|
||||
#ifdef CONFIG_PCISLAVE
|
||||
#define CONFIG_83XX_PCICLK 66666667 /* in HZ */
|
||||
#else
|
||||
#define CONFIG_83XX_CLKIN 66666667 /* in Hz */
|
||||
#define CONFIG_83XX_GENERIC_PCI 1
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SYS_CLK_FREQ
|
||||
#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Hardware Reset Configuration Word
|
||||
*/
|
||||
#define CFG_HRCW_LOW (\
|
||||
HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
|
||||
HRCWL_DDR_TO_SCB_CLK_1X1 |\
|
||||
HRCWL_SVCOD_DIV_2 |\
|
||||
HRCWL_CSB_TO_CLKIN_5X1 |\
|
||||
HRCWL_CORE_TO_CSB_2X1)
|
||||
|
||||
#ifdef CONFIG_PCISLAVE
|
||||
#define CFG_HRCW_HIGH (\
|
||||
HRCWH_PCI_AGENT |\
|
||||
HRCWH_PCI1_ARBITER_DISABLE |\
|
||||
HRCWH_CORE_ENABLE |\
|
||||
HRCWH_FROM_0XFFF00100 |\
|
||||
HRCWH_BOOTSEQ_DISABLE |\
|
||||
HRCWH_SW_WATCHDOG_DISABLE |\
|
||||
HRCWH_ROM_LOC_LOCAL_16BIT |\
|
||||
HRCWH_RL_EXT_LEGACY |\
|
||||
HRCWH_TSEC1M_IN_RGMII |\
|
||||
HRCWH_TSEC2M_IN_RGMII |\
|
||||
HRCWH_BIG_ENDIAN |\
|
||||
HRCWH_LDP_CLEAR)
|
||||
#else
|
||||
#define CFG_HRCW_HIGH (\
|
||||
HRCWH_PCI_HOST |\
|
||||
HRCWH_PCI1_ARBITER_ENABLE |\
|
||||
HRCWH_CORE_ENABLE |\
|
||||
HRCWH_FROM_0X00000100 |\
|
||||
HRCWH_BOOTSEQ_DISABLE |\
|
||||
HRCWH_SW_WATCHDOG_DISABLE |\
|
||||
HRCWH_ROM_LOC_LOCAL_16BIT |\
|
||||
HRCWH_RL_EXT_LEGACY |\
|
||||
HRCWH_TSEC1M_IN_RGMII |\
|
||||
HRCWH_TSEC2M_IN_RGMII |\
|
||||
HRCWH_BIG_ENDIAN |\
|
||||
HRCWH_LDP_CLEAR)
|
||||
#endif
|
||||
|
||||
/* System performance - define the value i.e. CFG_XXX
|
||||
*/
|
||||
|
||||
/* Arbiter Configuration Register */
|
||||
#define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
|
||||
#define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
|
||||
|
||||
/* System Priority Control Regsiter */
|
||||
#define CFG_SPCR_TSECEP 3 /* eTSEC1&2 emergency priority (0-3) */
|
||||
|
||||
/* System Clock Configuration Register */
|
||||
#define CFG_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */
|
||||
#define CFG_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */
|
||||
#define CFG_SCCR_SATACM SCCR_SATACM_1 /* SATA1-4 clock mode (0-3) */
|
||||
|
||||
/*
|
||||
* System IO Config
|
||||
*/
|
||||
#define CFG_SICRH 0x08200000
|
||||
#define CFG_SICRL 0x00000000
|
||||
|
||||
/*
|
||||
* Output Buffer Impedance
|
||||
*/
|
||||
#define CFG_OBIR 0x30100000
|
||||
|
||||
/*
|
||||
* IMMR new address
|
||||
*/
|
||||
#define CFG_IMMR 0xE0000000
|
||||
|
||||
/*
|
||||
* DDR Setup
|
||||
*/
|
||||
#define CFG_DDR_BASE 0x00000000 /* DDR is system memory */
|
||||
#define CFG_SDRAM_BASE CFG_DDR_BASE
|
||||
#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE
|
||||
#define CFG_DDR_SDRAM_CLK_CNTL 0x03000000
|
||||
#define CFG_83XX_DDR_USES_CS0
|
||||
|
||||
#define CFG_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN)
|
||||
|
||||
#undef CONFIG_DDR_ECC /* support DDR ECC function */
|
||||
#undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
|
||||
|
||||
#undef CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */
|
||||
|
||||
/*
|
||||
* Manually set up DDR parameters
|
||||
*/
|
||||
#define CFG_DDR_SIZE 256 /* MB */
|
||||
#define CFG_DDR_CS0_BNDS 0x0000000f
|
||||
#define CFG_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_ODT_WR_ACS \
|
||||
| CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
|
||||
|
||||
#define CFG_DDR_TIMING_3 0x00000000
|
||||
#define CFG_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
|
||||
| (0 << TIMING_CFG0_WRT_SHIFT) \
|
||||
| (0 << TIMING_CFG0_RRT_SHIFT) \
|
||||
| (0 << TIMING_CFG0_WWT_SHIFT) \
|
||||
| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
|
||||
| (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
|
||||
| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
|
||||
| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
|
||||
/* 0x00220802 */
|
||||
/* 0x00260802 */ /* DDR400 */
|
||||
#define CFG_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
|
||||
| (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
|
||||
| (3 << TIMING_CFG1_ACTTORW_SHIFT) \
|
||||
| (7 << TIMING_CFG1_CASLAT_SHIFT) \
|
||||
| (13 << TIMING_CFG1_REFREC_SHIFT) \
|
||||
| (3 << TIMING_CFG1_WRREC_SHIFT) \
|
||||
| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
|
||||
| (2 << TIMING_CFG1_WRTORD_SHIFT))
|
||||
/* 0x3935d322 */
|
||||
/* 0x3937d322 */
|
||||
#define CFG_DDR_TIMING_2 0x02984cc8
|
||||
|
||||
#define CFG_DDR_INTERVAL ((1545 << SDRAM_INTERVAL_REFINT_SHIFT) \
|
||||
| (256 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
|
||||
/* 0x06090100 */
|
||||
|
||||
#if defined(CONFIG_DDR_2T_TIMING)
|
||||
#define CFG_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
|
||||
| 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \
|
||||
| SDRAM_CFG_2T_EN \
|
||||
| SDRAM_CFG_DBW_32)
|
||||
#else
|
||||
#define CFG_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
|
||||
| 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT)
|
||||
/* 0x43000000 */
|
||||
#endif
|
||||
#define CFG_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */
|
||||
#define CFG_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \
|
||||
| (0x0442 << SDRAM_MODE_SD_SHIFT))
|
||||
/* 0x04400442 */ /* DDR400 */
|
||||
#define CFG_DDR_MODE2 0x00000000;
|
||||
|
||||
/*
|
||||
* Memory test
|
||||
*/
|
||||
#undef CFG_DRAM_TEST /* memory test, takes time */
|
||||
#define CFG_MEMTEST_START 0x00040000 /* memtest region */
|
||||
#define CFG_MEMTEST_END 0x0ef70010
|
||||
|
||||
/*
|
||||
* The reserved memory
|
||||
*/
|
||||
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
|
||||
|
||||
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
|
||||
#define CFG_RAMBOOT
|
||||
#else
|
||||
#undef CFG_RAMBOOT
|
||||
#endif
|
||||
|
||||
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
|
||||
#define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
|
||||
|
||||
/*
|
||||
* Initial RAM Base Address Setup
|
||||
*/
|
||||
#define CFG_INIT_RAM_LOCK 1
|
||||
#define CFG_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
|
||||
#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM */
|
||||
#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */
|
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
|
||||
|
||||
/*
|
||||
* Local Bus Configuration & Clock Setup
|
||||
*/
|
||||
#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_8)
|
||||
#define CFG_LBC_LBCR 0x00000000
|
||||
|
||||
/*
|
||||
* FLASH on the Local Bus
|
||||
*/
|
||||
#define CFG_FLASH_CFI /* use the Common Flash Interface */
|
||||
#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
|
||||
#define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */
|
||||
#define CFG_FLASH_SIZE 8 /* max FLASH size is 32M */
|
||||
|
||||
#define CFG_FLASH_EMPTY_INFO /* display empty sectors */
|
||||
#define CFG_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */
|
||||
|
||||
#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */
|
||||
#define CFG_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */
|
||||
|
||||
#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* Flash Base address */ \
|
||||
(2 << BR_PS_SHIFT) | /* 16 bit port size */ \
|
||||
BR_V) /* valid */
|
||||
#define CFG_OR0_PRELIM (0xFF800000 /* 8 MByte */ \
|
||||
| OR_GPCM_XACS \
|
||||
| OR_GPCM_SCY_9 \
|
||||
| OR_GPCM_EHTR \
|
||||
| OR_GPCM_EAD)
|
||||
/* 0xFF806FF7 TODO SLOW 8 MB flash size */
|
||||
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
|
||||
#define CFG_MAX_FLASH_SECT 256 /* max sectors per device */
|
||||
|
||||
#undef CFG_FLASH_CHECKSUM
|
||||
#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
|
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
|
||||
|
||||
#define CFG_VSC7385_BASE 0xF0000000
|
||||
|
||||
/* VSC7385 Gigabit Switch support */
|
||||
#define CONFIG_VSC7385_ENET
|
||||
#define CFG_BR2_PRELIM 0xf0000801 /* Base address */
|
||||
#define CFG_OR2_PRELIM 0xfffe09ff /* 128K bytes*/
|
||||
#define CFG_LBLAWBAR2_PRELIM CFG_VSC7385_BASE /* Access Base */
|
||||
#define CFG_LBLAWAR2_PRELIM 0x80000010 /* Access Size 128K */
|
||||
|
||||
/*
|
||||
* Serial Port
|
||||
*/
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
#undef CONFIG_SERIAL_SOFTWARE_FIFO
|
||||
#define CFG_NS16550
|
||||
#define CFG_NS16550_SERIAL
|
||||
#define CFG_NS16550_REG_SIZE 1
|
||||
#define CFG_NS16550_CLK get_bus_freq(0)
|
||||
|
||||
#define CFG_BAUDRATE_TABLE \
|
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
|
||||
|
||||
#define CFG_NS16550_COM1 (CFG_IMMR+0x4500)
|
||||
#define CFG_NS16550_COM2 (CFG_IMMR+0x4600)
|
||||
|
||||
/* Use the HUSH parser */
|
||||
#define CFG_HUSH_PARSER
|
||||
#ifdef CFG_HUSH_PARSER
|
||||
#define CFG_PROMPT_HUSH_PS2 "> "
|
||||
#endif
|
||||
|
||||
/* Pass open firmware flat tree */
|
||||
#define CONFIG_OF_LIBFDT 1
|
||||
#define CONFIG_OF_BOARD_SETUP 1
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
|
||||
#define CONFIG_FSL_I2C
|
||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CFG_I2C_SLAVE 0x7F
|
||||
#define CFG_I2C_NOPROBES {0x51} /* Don't probe these addrs */
|
||||
#define CFG_I2C_OFFSET 0x3000
|
||||
#define CFG_I2C2_OFFSET 0x3100
|
||||
|
||||
/*
|
||||
* Config on-board RTC
|
||||
*/
|
||||
#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
|
||||
#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
|
||||
|
||||
/*
|
||||
* General PCI
|
||||
* Addresses are mapped 1-1.
|
||||
*/
|
||||
#define CFG_PCI_MEM_BASE 0x80000000
|
||||
#define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BASE
|
||||
#define CFG_PCI_MEM_SIZE 0x10000000 /* 256M */
|
||||
#define CFG_PCI_MMIO_BASE 0x90000000
|
||||
#define CFG_PCI_MMIO_PHYS CFG_PCI_MMIO_BASE
|
||||
#define CFG_PCI_MMIO_SIZE 0x10000000 /* 256M */
|
||||
#define CFG_PCI_IO_BASE 0xE0300000
|
||||
#define CFG_PCI_IO_PHYS 0xE0300000
|
||||
#define CFG_PCI_IO_SIZE 0x100000 /* 1M */
|
||||
|
||||
#define CFG_PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE
|
||||
#define CFG_PCI_SLV_MEM_BUS 0x00000000
|
||||
#define CFG_PCI_SLV_MEM_SIZE 0x80000000
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
#define CONFIG_NET_MULTI
|
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
||||
|
||||
#undef CONFIG_EEPRO100
|
||||
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
||||
#define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
|
||||
#endif /* CONFIG_PCI */
|
||||
|
||||
#ifndef CONFIG_NET_MULTI
|
||||
#define CONFIG_NET_MULTI 1
|
||||
#endif
|
||||
|
||||
/*
|
||||
* TSEC
|
||||
*/
|
||||
#define CONFIG_TSEC_ENET /* TSEC ethernet support */
|
||||
#define CFG_TSEC1_OFFSET 0x24000
|
||||
#define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET)
|
||||
#define CFG_TSEC2_OFFSET 0x25000
|
||||
#define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET)
|
||||
|
||||
/*
|
||||
* TSEC ethernet configuration
|
||||
*/
|
||||
#define CONFIG_GMII 1 /* MII PHY management */
|
||||
#define CONFIG_TSEC1 1
|
||||
#define CONFIG_TSEC1_NAME "TSEC0"
|
||||
#define CONFIG_TSEC2 1
|
||||
#define CONFIG_TSEC2_NAME "TSEC1"
|
||||
#define TSEC1_PHY_ADDR 2
|
||||
#define TSEC2_PHY_ADDR 0x1c
|
||||
#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
|
||||
#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
|
||||
#define TSEC1_PHYIDX 0
|
||||
#define TSEC2_PHYIDX 0
|
||||
|
||||
|
||||
/* Options are: TSEC[0-1] */
|
||||
#define CONFIG_ETHPRIME "TSEC0"
|
||||
|
||||
/*
|
||||
* Environment
|
||||
*/
|
||||
#ifndef CFG_RAMBOOT
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE+CFG_MONITOR_LEN)
|
||||
#define CFG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for env */
|
||||
#define CFG_ENV_SIZE 0x4000
|
||||
#else
|
||||
#define CFG_NO_FLASH 1 /* Flash is not usable now */
|
||||
#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
|
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-0x1000)
|
||||
#define CFG_ENV_SIZE 0x2000
|
||||
#endif
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
||||
#define CONFIG_BOOTP_BOOTPATH
|
||||
#define CONFIG_BOOTP_GATEWAY
|
||||
#define CONFIG_BOOTP_HOSTNAME
|
||||
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_DATE
|
||||
|
||||
#if defined(CONFIG_PCI)
|
||||
#define CONFIG_CMD_PCI
|
||||
#endif
|
||||
|
||||
#if defined(CFG_RAMBOOT)
|
||||
#undef CONFIG_CMD_ENV
|
||||
#undef CONFIG_CMD_LOADS
|
||||
#endif
|
||||
|
||||
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
|
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CFG_LONGHELP /* undef to save memory */
|
||||
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
|
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
|
||||
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CFG_MAXARGS 16 /* max number of command args */
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
|
||||
/*
|
||||
* Core HID Setup
|
||||
*/
|
||||
#define CFG_HID0_INIT 0x000000000
|
||||
#define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
|
||||
#define CFG_HID2 HID2_HBE
|
||||
|
||||
/*
|
||||
* MMU Setup
|
||||
*/
|
||||
|
||||
/* DDR: cache cacheable */
|
||||
#define CFG_SDRAM_LOWER CFG_SDRAM_BASE
|
||||
#define CFG_SDRAM_UPPER (CFG_SDRAM_BASE + 0x10000000)
|
||||
|
||||
#define CFG_IBAT0L (CFG_SDRAM_LOWER | BATL_PP_10 | BATL_MEMCOHERENCE)
|
||||
#define CFG_IBAT0U (CFG_SDRAM_LOWER | BATU_BL_256M | BATU_VS | BATU_VP)
|
||||
#define CFG_DBAT0L CFG_IBAT0L
|
||||
#define CFG_DBAT0U CFG_IBAT0U
|
||||
|
||||
#define CFG_IBAT1L (CFG_SDRAM_UPPER | BATL_PP_10 | BATL_MEMCOHERENCE)
|
||||
#define CFG_IBAT1U (CFG_SDRAM_UPPER | BATU_BL_256M | BATU_VS | BATU_VP)
|
||||
#define CFG_DBAT1L CFG_IBAT1L
|
||||
#define CFG_DBAT1U CFG_IBAT1U
|
||||
|
||||
/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
|
||||
#define CFG_IBAT2L (CFG_IMMR | BATL_PP_10 | \
|
||||
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
||||
#define CFG_IBAT2U (CFG_IMMR | BATU_BL_8M | BATU_VS | BATU_VP)
|
||||
#define CFG_DBAT2L CFG_IBAT2L
|
||||
#define CFG_DBAT2U CFG_IBAT2U
|
||||
|
||||
/* L2 Switch: cache-inhibit and guarded */
|
||||
#define CFG_IBAT3L (CFG_VSC7385_BASE | BATL_PP_10 | \
|
||||
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
||||
#define CFG_IBAT3U (CFG_VSC7385_BASE | BATU_BL_128K | BATU_VS | BATU_VP)
|
||||
#define CFG_DBAT3L CFG_IBAT3L
|
||||
#define CFG_DBAT3U CFG_IBAT3U
|
||||
|
||||
/* FLASH: icache cacheable, but dcache-inhibit and guarded */
|
||||
#define CFG_IBAT4L (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
|
||||
#define CFG_IBAT4U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
|
||||
#define CFG_DBAT4L (CFG_FLASH_BASE | BATL_PP_10 | \
|
||||
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
||||
#define CFG_DBAT4U CFG_IBAT4U
|
||||
|
||||
/* Stack in dcache: cacheable, no memory coherence */
|
||||
#define CFG_IBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_10)
|
||||
#define CFG_IBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
|
||||
#define CFG_DBAT5L CFG_IBAT5L
|
||||
#define CFG_DBAT5U CFG_IBAT5U
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
/* PCI MEM space: cacheable */
|
||||
#define CFG_IBAT6L (CFG_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
|
||||
#define CFG_IBAT6U (CFG_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
|
||||
#define CFG_DBAT6L CFG_IBAT6L
|
||||
#define CFG_DBAT6U CFG_IBAT6U
|
||||
/* PCI MMIO space: cache-inhibit and guarded */
|
||||
#define CFG_IBAT7L (CFG_PCI_MMIO_PHYS | BATL_PP_10 | \
|
||||
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
||||
#define CFG_IBAT7U (CFG_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
|
||||
#define CFG_DBAT7L CFG_IBAT7L
|
||||
#define CFG_DBAT7U CFG_IBAT7U
|
||||
#else
|
||||
#define CFG_IBAT6L (0)
|
||||
#define CFG_IBAT6U (0)
|
||||
#define CFG_IBAT7L (0)
|
||||
#define CFG_IBAT7U (0)
|
||||
#define CFG_DBAT6L CFG_IBAT6L
|
||||
#define CFG_DBAT6U CFG_IBAT6U
|
||||
#define CFG_DBAT7L CFG_IBAT7L
|
||||
#define CFG_DBAT7U CFG_IBAT7U
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Internal Definitions
|
||||
*
|
||||
* Boot Flags
|
||||
*/
|
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||||
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
|
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Environment Configuration
|
||||
*/
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
#define CONFIG_HAS_ETH0 /* add support for "ethaddr" */
|
||||
#define CONFIG_ETHADDR 00:04:9f:ef:04:01
|
||||
#define CONFIG_HAS_ETH1 /* add support for "eth1addr" */
|
||||
#define CONFIG_ETH1ADDR 00:04:9f:ef:04:02
|
||||
|
||||
#define CONFIG_IPADDR 10.0.0.2
|
||||
#define CONFIG_SERVERIP 10.0.0.1
|
||||
#define CONFIG_GATEWAYIP 10.0.0.1
|
||||
#define CONFIG_NETMASK 255.0.0.0
|
||||
#define CONFIG_NETDEV eth1
|
||||
|
||||
#define CONFIG_HOSTNAME mpc837x_rdb
|
||||
#define CONFIG_ROOTPATH /nfsroot
|
||||
#define CONFIG_RAMDISKFILE rootfs.ext2.gz.uboot
|
||||
#define CONFIG_BOOTFILE uImage
|
||||
#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
|
||||
#define CONFIG_FDTFILE mpc837x_rdb.dtb
|
||||
|
||||
#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
|
||||
#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
#define XMK_STR(x) #x
|
||||
#define MK_STR(x) XMK_STR(x)
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"netdev=" MK_STR(CONFIG_NETDEV) "\0" \
|
||||
"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
|
||||
"tftpflash=tftp $loadaddr $uboot;" \
|
||||
"protect off " MK_STR(TEXT_BASE) " +$filesize; " \
|
||||
"erase " MK_STR(TEXT_BASE) " +$filesize; " \
|
||||
"cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
|
||||
"protect on " MK_STR(TEXT_BASE) " +$filesize; " \
|
||||
"cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
|
||||
"fdtaddr=400000\0" \
|
||||
"fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \
|
||||
"ramdiskaddr=1000000\0" \
|
||||
"ramdiskfile=" MK_STR(CONFIG_RAMDISKFILE) "\0" \
|
||||
"console=ttyS0\0" \
|
||||
"setbootargs=setenv bootargs " \
|
||||
"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
|
||||
"setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
|
||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
||||
"root=$rootdev rw console=$console,$baudrate $othbootargs\0"
|
||||
|
||||
#define CONFIG_NFSBOOTCOMMAND \
|
||||
"setenv rootdev /dev/nfs;" \
|
||||
"run setbootargs;" \
|
||||
"run setipargs;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr - $fdtaddr"
|
||||
|
||||
#define CONFIG_RAMBOOTCOMMAND \
|
||||
"setenv rootdev /dev/ram;" \
|
||||
"run setbootargs;" \
|
||||
"tftp $ramdiskaddr $ramdiskfile;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr $ramdiskaddr $fdtaddr"
|
||||
|
||||
#undef MK_STR
|
||||
#undef XMK_STR
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
|
@ -141,6 +141,9 @@
|
|||
#endif
|
||||
|
||||
#define CFG_ID_EEPROM
|
||||
#ifdef CFG_ID_EEPROM
|
||||
#define CONFIG_ID_EEPROM
|
||||
#endif
|
||||
#define ID_EEPROM_ADDR 0x57
|
||||
|
||||
|
||||
|
|
@ -312,11 +315,8 @@
|
|||
#define CONFIG_CMD_NET
|
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
||||
|
||||
#define CONFIG_RTL8139
|
||||
#define CONFIG_SK98
|
||||
#define CONFIG_EEPRO100
|
||||
#define CONFIG_TULIP
|
||||
#ifdef CONFIG_TULIP
|
||||
#define CONFIG_ULI526X
|
||||
#ifdef CONFIG_ULI526X
|
||||
#define CONFIG_ETHADDR 00:E0:0C:00:00:01
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -152,6 +152,9 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
|
|||
#endif
|
||||
|
||||
#define CFG_ID_EEPROM 1
|
||||
#ifdef CFG_ID_EEPROM
|
||||
#define CONFIG_ID_EEPROM
|
||||
#endif
|
||||
#define ID_EEPROM_ADDR 0x57
|
||||
|
||||
/*
|
||||
|
|
|
|||
39
include/linux/mtd/fsl_upm.h
Normal file
39
include/linux/mtd/fsl_upm.h
Normal file
|
|
@ -0,0 +1,39 @@
|
|||
/*
|
||||
* FSL UPM NAND driver
|
||||
*
|
||||
* Copyright (C) 2007 MontaVista Software, Inc.
|
||||
* Anton Vorontsov <avorontsov@ru.mvista.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef __LINUX_MTD_NAND_FSL_UPM
|
||||
#define __LINUX_MTD_NAND_FSL_UPM
|
||||
|
||||
#include <linux/mtd/nand.h>
|
||||
|
||||
struct fsl_upm {
|
||||
const u32 *array;
|
||||
void __iomem *mdr;
|
||||
void __iomem *mxmr;
|
||||
void __iomem *mar;
|
||||
void __iomem *io_addr;
|
||||
};
|
||||
|
||||
struct fsl_upm_nand {
|
||||
struct fsl_upm upm;
|
||||
|
||||
int width;
|
||||
int upm_cmd_offset;
|
||||
int upm_addr_offset;
|
||||
int wait_pattern;
|
||||
int (*dev_ready)(void);
|
||||
int chip_delay;
|
||||
};
|
||||
|
||||
extern int fsl_upm_nand_init(struct nand_chip *chip, struct fsl_upm_nand *fun);
|
||||
|
||||
#endif
|
||||
|
|
@ -725,13 +725,20 @@
|
|||
#define SCCR_USBCM_3 0x00F00000
|
||||
|
||||
#elif defined(CONFIG_MPC8313)
|
||||
/* TSEC1 bits are for TSEC2 as well */
|
||||
#define SCCR_TSEC1CM 0xc0000000
|
||||
#define SCCR_TSEC1CM_SHIFT 30
|
||||
#define SCCR_TSEC1CM_0 0x00000000
|
||||
#define SCCR_TSEC1CM_1 0x40000000
|
||||
#define SCCR_TSEC1CM_2 0x80000000
|
||||
#define SCCR_TSEC1CM_3 0xC0000000
|
||||
|
||||
#define SCCR_TSEC2CM 0x30000000
|
||||
#define SCCR_TSEC2CM_SHIFT 28
|
||||
#define SCCR_TSEC2CM_0 0x00000000
|
||||
#define SCCR_TSEC2CM_1 0x10000000
|
||||
#define SCCR_TSEC2CM_2 0x20000000
|
||||
#define SCCR_TSEC2CM_3 0x30000000
|
||||
|
||||
#define SCCR_TSEC1ON 0x20000000
|
||||
#define SCCR_TSEC1ON_SHIFT 29
|
||||
#define SCCR_TSEC2ON 0x10000000
|
||||
|
|
@ -831,8 +838,6 @@
|
|||
#define SCCR_PCIEXP2CM_3 0x000c0000
|
||||
|
||||
/* All of the four SATA controllers must have the same clock ratio */
|
||||
#define SCCR_SATA1CM 0x000000c0
|
||||
#define SCCR_SATA1CM_SHIFT 6
|
||||
#define SCCR_SATACM 0x000000ff
|
||||
#define SCCR_SATACM_SHIFT 0
|
||||
#define SCCR_SATACM_0 0x00000000
|
||||
|
|
@ -852,6 +857,7 @@
|
|||
*/
|
||||
#define CSCONFIG_EN 0x80000000
|
||||
#define CSCONFIG_AP 0x00800000
|
||||
#define CSCONFIG_ODT_WR_ACS 0x00010000
|
||||
#define CSCONFIG_ROW_BIT 0x00000700
|
||||
#define CSCONFIG_ROW_BIT_12 0x00000000
|
||||
#define CSCONFIG_ROW_BIT_13 0x00000100
|
||||
|
|
@ -1480,6 +1486,7 @@
|
|||
|
||||
/* DDRCDR - DDR Control Driver Register
|
||||
*/
|
||||
#define DDRCDR_DHC_EN 0x80000000
|
||||
#define DDRCDR_EN 0x40000000
|
||||
#define DDRCDR_PZ 0x3C000000
|
||||
#define DDRCDR_PZ_MAXZ 0x00000000
|
||||
|
|
|
|||
Loading…
Reference in a new issue