mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-28 15:41:40 +00:00
Merge with /home/hs/PanDacom/u-boot-dev
This commit is contained in:
Wolfgang Denk
commit
9cdc838613
3 changed files with 385 additions and 5 deletions
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@ -2,6 +2,9 @@
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Changes since U-Boot 1.1.4:
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======================================================================
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* Add basic support for the SMMACO4 Board from PanDaCom.
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Patch by Heiko Schocher, 20 Feb 2006
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* Add GIT version information (commid ID) to untagged U-Boot versions
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As done in the linux kernel, the U-Boot version (U_BOOT_VERSION)
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13
Makefile
13
Makefile
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@ -315,6 +315,14 @@ PM520_ROMBOOT_DDR_config: unconfig
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}
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@./mkconfig -a PM520 ppc mpc5xxx pm520
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SMMACO4_config: unconfig
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@./mkconfig -a SMMACO4 ppc mpc5xxx tqm5200
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spieval_config: unconfig
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echo "#define CONFIG_CS_AUTOCONF">>include/config.h
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echo "... with automatic CS configuration"
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@./mkconfig -a spieval ppc mpc5xxx tqm5200
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MINI5200_config \
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EVAL5200_config \
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TOP5200_config: unconfig
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@ -380,11 +388,6 @@ MiniFAP_config: unconfig
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}
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@./mkconfig -a TQM5200 ppc mpc5xxx tqm5200
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spieval_config: unconfig
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echo "#define CONFIG_CS_AUTOCONF">>include/config.h
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echo "... with automatic CS configuration"
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@./mkconfig -a spieval ppc mpc5xxx tqm5200
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#########################################################################
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## MPC8xx Systems
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#########################################################################
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374
include/configs/SMMACO4.h
Normal file
374
include/configs/SMMACO4.h
Normal file
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@ -0,0 +1,374 @@
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/*
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* (C) Copyright 2003-2006
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2004-2005
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* Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
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#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
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#define CONFIG_TQM5200 1 /* ... on TQM5200 module */
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#undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */
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#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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#endif
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/*
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* Serial console configuration
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*/
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#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
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#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
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/* Partitions */
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#define CONFIG_MAC_PARTITION
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#define CONFIG_DOS_PARTITION
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#define CONFIG_ISO_PARTITION
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/* POST support */
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#define CONFIG_POST (CFG_POST_MEMORY | \
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CFG_POST_CPU | \
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CFG_POST_I2C)
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#ifdef CONFIG_POST
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#define CFG_CMD_POST_DIAG CFG_CMD_DIAG
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/* preserve space for the post_word at end of on-chip SRAM */
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#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
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#else
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#define CFG_CMD_POST_DIAG 0
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#endif
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/*
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* Supported commands
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*/
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#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
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CFG_CMD_ASKENV | \
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CFG_CMD_DATE | \
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CFG_CMD_DHCP | \
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CFG_CMD_ECHO | \
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CFG_CMD_EEPROM | \
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CFG_CMD_I2C | \
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CFG_CMD_JFFS2 | \
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CFG_CMD_MII | \
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CFG_CMD_NFS | \
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CFG_CMD_PING | \
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CFG_CMD_POST_DIAG | \
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CFG_CMD_REGINFO | \
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CFG_CMD_SNTP | \
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CFG_CMD_BSP)
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#include <cmd_confdefs.h>
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#define CONFIG_TIMESTAMP /* display image timestamps */
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#if (TEXT_BASE == 0xFC000000) /* Boot low */
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# define CFG_LOWBOOT 1
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#endif
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/*
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* Autobooting
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*/
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#define CONFIG_PREBOOT "echo;" \
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"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
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"echo"
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#undef CONFIG_BOOTARGS
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"rootpath=/opt/eldk/ppc_6xx\0" \
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"ramargs=setenv bootargs root=/dev/ram rw\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=${serverip}:${rootpath}\0" \
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"addip=setenv bootargs ${bootargs} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
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":${hostname}:${netdev}:off panic=1\0" \
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"flash_self=run ramargs addip;" \
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"bootm ${kernel_addr} ${ramdisk_addr}\0" \
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"flash_nfs=run nfsargs addip;" \
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"bootm ${kernel_addr}\0" \
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"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
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"bootfile=/tftpboot/smmaco4/uImage\0" \
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"load=tftp 200000 ${u-boot}\0" \
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"u-boot=/tftpboot/smmaco4/u-boot.bin\0" \
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"update=protect off FC000000 FC05FFFF;" \
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"erase FC000000 FC05FFFF;" \
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"cp.b 200000 FC000000 ${filesize};" \
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"protect on FC000000 FC05FFFF\0" \
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""
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#define CONFIG_BOOTCOMMAND "run net_nfs"
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/*
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* IPB Bus clocking configuration.
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*/
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#define CFG_IPBSPEED_133 /* define for 133MHz speed */
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#if defined(CFG_IPBSPEED_133)
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/*
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* PCI Bus clocking configuration
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*
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* Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
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* CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
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* been tested with a IPB Bus Clock of 66 MHz.
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*/
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#define CFG_PCISPEED_66 /* define for 66MHz speed */
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#endif
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/*
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* I2C configuration
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*/
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#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
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#ifdef CONFIG_TQM5200_REV100
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#define CFG_I2C_MODULE 1 /* Select I2C module #1 for rev. 100 board */
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#else
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#define CFG_I2C_MODULE 2 /* Select I2C module #2 for all other revs */
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#endif
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/*
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* I2C clock frequency
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*
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* Please notice, that the resulting clock frequency could differ from the
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* configured value. This is because the I2C clock is derived from system
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* clock over a frequency divider with only a few divider values. U-boot
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* calculates the best approximation for CFG_I2C_SPEED. However the calculated
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* approximation allways lies below the configured value, never above.
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*/
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#define CFG_I2C_SPEED 100000 /* 100 kHz */
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#define CFG_I2C_SLAVE 0x7F
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/*
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* EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
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* also). For other EEPROMs configuration should be verified. On Mini-FAP the
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* EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
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* same configuration could be used.
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*/
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#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
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#define CFG_I2C_EEPROM_ADDR_LEN 2
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#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
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#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
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/*
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* Flash configuration
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*/
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#define CFG_FLASH_BASE TEXT_BASE /* 0xFC000000 */
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/* use CFI flash driver if no module variant is spezified */
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#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
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#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
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#define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START }
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#define CFG_FLASH_EMPTY_INFO
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#define CFG_FLASH_SIZE 0x04000000 /* 64 MByte */
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#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */
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#undef CFG_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */
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#if !defined(CFG_LOWBOOT)
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#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00760000 + 0x00800000)
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#else /* CFG_LOWBOOT */
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#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00060000)
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#endif /* CFG_LOWBOOT */
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#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks
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(= chip selects) */
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#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
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/* Dynamic MTD partition support */
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#define CONFIG_JFFS2_CMDLINE
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#define MTDIDS_DEFAULT "nor0=TQM5200-0"
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#define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \
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"1408k(kernel)," \
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"2m(initrd)," \
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"4m(small-fs)," \
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"16m(big-fs)," \
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"8m(misc)"
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/*
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* Environment settings
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*/
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#define CFG_ENV_IS_IN_FLASH 1
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#define CFG_ENV_SIZE 0x10000
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#define CFG_ENV_SECT_SIZE 0x20000
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#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
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#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
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/*
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* Memory map
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*/
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#define CFG_MBAR 0xF0000000
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_DEFAULT_MBAR 0x80000000
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/* Use ON-Chip SRAM until RAM will be available */
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#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
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#ifdef CONFIG_POST
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/* preserve space for the post_word at end of on-chip SRAM */
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#define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
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#else
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#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE
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#endif
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#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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#define CFG_MONITOR_BASE TEXT_BASE
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#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
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# define CFG_RAMBOOT 1
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#endif
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#define CFG_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
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#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*
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* Ethernet configuration
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*/
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#define CONFIG_MPC5xxx_FEC 1
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/*
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* Define CONFIG_FEC_10MBIT to force FEC at 10Mb
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*/
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/* #define CONFIG_FEC_10MBIT 1 */
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#define CONFIG_PHY_ADDR 0x00
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/*
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* GPIO configuration
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*
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* use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1):
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* Bit 0 (mask: 0x80000000): 1
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* use ALT CAN position: Bits 2-3 (mask: 0x30000000):
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* 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
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* 01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
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* Use for REV200 STK52XX boards. Do not use with REV100 modules
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* (because, there I2C1 is used as I2C bus)
|
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* use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
|
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* use PSC2 as CAN: Bits 25:27 (mask: 0x00000030)
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* 000 -> All PSC2 pins are GIOPs
|
||||
* 001 -> CAN1/2 on PSC2 pins
|
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* Use for REV100 STK52xx boards
|
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* use PSC6:
|
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* on STK52xx:
|
||||
* use as UART. Pins PSC6_0 to PSC6_3 are used.
|
||||
* Bits 9:11 (mask: 0x00700000):
|
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* 101 -> PSC6 : Extended POST test is not available
|
||||
* on MINI-FAP and TQM5200_IB:
|
||||
* use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000):
|
||||
* 000 -> PSC6 could not be used as UART, CODEC or IrDA
|
||||
* GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
|
||||
* tests.
|
||||
*/
|
||||
#if defined (CONFIG_MINIFAP)
|
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# define CFG_GPS_PORT_CONFIG 0x91000004
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||||
#elif defined (CONFIG_STK52XX)
|
||||
# if defined (CONFIG_STK52XX_REV100)
|
||||
# define CFG_GPS_PORT_CONFIG 0x81500014
|
||||
# else /* STK52xx REV200 and above */
|
||||
# if defined (CONFIG_TQM5200_REV100)
|
||||
# error TQM5200 REV100 not supported on STK52XX REV200 or above
|
||||
# else/* TQM5200 REV200 and above */
|
||||
# define CFG_GPS_PORT_CONFIG 0x91500004
|
||||
# endif
|
||||
# endif
|
||||
#else /* TMQ5200 Inbetriebnahme-Board */
|
||||
# define CFG_GPS_PORT_CONFIG 0x81000004
|
||||
#endif
|
||||
|
||||
/*
|
||||
* RTC configuration
|
||||
*/
|
||||
#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CFG_LONGHELP /* undef to save memory */
|
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CFG_MAXARGS 16 /* max number of command args */
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
/* Enable an alternate, more extensive memory test */
|
||||
#define CFG_ALT_MEMTEST
|
||||
|
||||
#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
|
||||
#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
|
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */
|
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
|
||||
|
||||
/*
|
||||
* Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
|
||||
* which is normally part of the default commands (CFV_CMD_DFL)
|
||||
*/
|
||||
#define CONFIG_LOOPW
|
||||
|
||||
/*
|
||||
* Various low-level settings
|
||||
*/
|
||||
#if defined(CONFIG_MPC5200)
|
||||
#define CFG_HID0_INIT HID0_ICE | HID0_ICFI
|
||||
#define CFG_HID0_FINAL HID0_ICE
|
||||
#else
|
||||
#define CFG_HID0_INIT 0
|
||||
#define CFG_HID0_FINAL 0
|
||||
#endif
|
||||
|
||||
#define CFG_BOOTCS_START CFG_FLASH_BASE
|
||||
#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
|
||||
#ifdef CFG_PCISPEED_66
|
||||
#define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
|
||||
#else
|
||||
#define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
|
||||
#endif
|
||||
#define CFG_CS0_START CFG_FLASH_BASE
|
||||
#define CFG_CS0_SIZE CFG_FLASH_SIZE
|
||||
|
||||
#define CFG_CS_BURST 0x00000000
|
||||
#define CFG_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */
|
||||
|
||||
#define CFG_RESET_ADDRESS 0xff000000
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
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