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i2c: Add support for Qualcomm I2C driver
Add support for Qualcomm I2C QUP driver which is inspired from corresponding driver in Linux: drivers/i2c/busses/i2c-qup.c. Currently this driver only support FIFO polling mode which is sufficient to support devices like eeprom, rtc etc. Co-developed-by: Mike Worsfold <mworsfold@impinj.com> Signed-off-by: Mike Worsfold <mworsfold@impinj.com> Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
This commit is contained in:
Sumit Garg
Tom Rini
parent
c9ec1971c6
commit
9bdec960b2
3 changed files with 592 additions and 0 deletions
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@ -580,6 +580,18 @@ config SYS_I2C_OCTEON
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chips have several I2C ports and all are provided, controlled by
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the device tree.
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config SYS_I2C_QUP
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bool "Qualcomm QUP I2C controller"
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depends on ARCH_SNAPDRAGON
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help
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Support for Qualcomm QUP I2C controller based on Qualcomm Universal
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Peripherals (QUP) engine. The QUP engine is an advanced high
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performance slave port that provides a common data path (an output
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FIFO and an input FIFO) for I2C and SPI interfaces. The I2C/SPI QUP
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controller is publicly documented in the Snapdragon 410E (APQ8016E)
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Technical Reference Manual, chapter "6.1 Qualcomm Universal
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Peripherals Engine (QUP)".
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config SYS_I2C_S3C24X0
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bool "Samsung I2C driver"
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depends on (ARCH_EXYNOS4 || ARCH_EXYNOS5) && DM_I2C
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@ -37,6 +37,7 @@ obj-$(CONFIG_SYS_I2C_NPCM) += npcm_i2c.o
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obj-$(CONFIG_SYS_I2C_OCORES) += ocores_i2c.o
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obj-$(CONFIG_SYS_I2C_OCTEON) += octeon_i2c.o
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obj-$(CONFIG_SYS_I2C_OMAP24XX) += omap24xx_i2c.o
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obj-$(CONFIG_SYS_I2C_QUP) += qup_i2c.o
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obj-$(CONFIG_SYS_I2C_RCAR_I2C) += rcar_i2c.o
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obj-$(CONFIG_SYS_I2C_RCAR_IIC) += rcar_iic.o
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obj-$(CONFIG_SYS_I2C_ROCKCHIP) += rk_i2c.o
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579
drivers/i2c/qup_i2c.c
Normal file
579
drivers/i2c/qup_i2c.c
Normal file
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@ -0,0 +1,579 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2009-2013, 2016-2018, The Linux Foundation. All rights reserved.
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* Copyright (c) 2014, Sony Mobile Communications AB.
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* Copyright (c) 2022-2023, Sumit Garg <sumit.garg@linaro.org>
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*
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* Inspired by corresponding driver in Linux: drivers/i2c/busses/i2c-qup.c
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*/
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#include <init.h>
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#include <env.h>
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#include <common.h>
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#include <log.h>
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#include <dm/device_compat.h>
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#include <linux/delay.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/compat.h>
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#include <linux/bitops.h>
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#include <asm/io.h>
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#include <i2c.h>
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#include <watchdog.h>
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#include <fdtdec.h>
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#include <clk.h>
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#include <reset.h>
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#include <asm/arch/gpio.h>
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#include <cpu_func.h>
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#include <asm/system.h>
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#include <asm/gpio.h>
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#include <dm.h>
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#include <dm/pinctrl.h>
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/* QUP Registers */
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#define QUP_CONFIG 0x000
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#define QUP_STATE 0x004
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#define QUP_IO_MODE 0x008
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#define QUP_SW_RESET 0x00c
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#define QUP_OPERATIONAL 0x018
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#define QUP_ERROR_FLAGS 0x01c /* NOT USED */
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#define QUP_ERROR_FLAGS_EN 0x020 /* NOT USED */
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#define QUP_TEST_CTRL 0x024 /* NOT USED */
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#define QUP_OPERATIONAL_MASK 0x028 /* NOT USED */
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#define QUP_HW_VERSION 0x030
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#define QUP_MX_OUTPUT_CNT 0x100
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#define QUP_OUT_DEBUG 0x108 /* NOT USED */
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#define QUP_OUT_FIFO_CNT 0x10C /* NOT USED */
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#define QUP_OUT_FIFO_BASE 0x110
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#define QUP_MX_WRITE_CNT 0x150
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#define QUP_MX_INPUT_CNT 0x200
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#define QUP_MX_READ_CNT 0x208
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#define QUP_IN_READ_CUR 0x20C /* NOT USED */
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#define QUP_IN_DEBUG 0x210 /* NOT USED */
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#define QUP_IN_FIFO_CNT 0x214 /* NOT USED */
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#define QUP_IN_FIFO_BASE 0x218
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#define QUP_I2C_CLK_CTL 0x400
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#define QUP_I2C_STATUS 0x404 /* NOT USED */
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#define QUP_I2C_MASTER_GEN 0x408
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#define QUP_I2C_MASTER_BUS_CLR 0x40C /* NOT USED */
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/* QUP States and reset values */
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#define QUP_RESET_STATE 0
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#define QUP_RUN_STATE 1
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#define QUP_PAUSE_STATE 3
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#define QUP_STATE_MASK 3
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#define QUP_STATE_VALID BIT(2)
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#define QUP_I2C_MAST_GEN BIT(4)
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#define QUP_I2C_FLUSH BIT(6)
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#define QUP_OPERATIONAL_RESET 0x000ff0
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#define QUP_I2C_STATUS_RESET 0xfffffc
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/* QUP OPERATIONAL FLAGS */
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#define QUP_I2C_NACK_FLAG BIT(3)
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#define QUP_OUT_NOT_EMPTY BIT(4)
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#define QUP_IN_NOT_EMPTY BIT(5)
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#define QUP_OUT_FULL BIT(6)
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#define QUP_OUT_SVC_FLAG BIT(8)
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#define QUP_IN_SVC_FLAG BIT(9)
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#define QUP_MX_OUTPUT_DONE BIT(10)
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#define QUP_MX_INPUT_DONE BIT(11)
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#define OUT_BLOCK_WRITE_REQ BIT(12)
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#define IN_BLOCK_READ_REQ BIT(13)
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/*
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* QUP engine acting as I2C controller is referred to as
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* I2C mini core, following are related macros.
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*/
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#define QUP_NO_OUTPUT BIT(6)
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#define QUP_NO_INPUT BIT(7)
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#define QUP_CLOCK_AUTO_GATE BIT(13)
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#define QUP_I2C_MINI_CORE (2 << 8)
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#define QUP_I2C_N_VAL_V2 7
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/* Packing/Unpacking words in FIFOs, and IO modes */
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#define QUP_OUTPUT_BLK_MODE BIT(10)
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#define QUP_OUTPUT_BAM_MODE (BIT(10) | BIT(11))
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#define QUP_INPUT_BLK_MODE BIT(12)
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#define QUP_INPUT_BAM_MODE (BIT(12) | BIT(13))
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#define QUP_BAM_MODE (QUP_OUTPUT_BAM_MODE | QUP_INPUT_BAM_MODE)
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#define QUP_BLK_MODE (QUP_OUTPUT_BLK_MODE | QUP_INPUT_BLK_MODE)
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#define QUP_UNPACK_EN BIT(14)
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#define QUP_PACK_EN BIT(15)
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#define QUP_REPACK_EN (QUP_UNPACK_EN | QUP_PACK_EN)
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#define QUP_V2_TAGS_EN 1
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#define QUP_OUTPUT_BLOCK_SIZE(x) (((x) >> 0) & 0x03)
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#define QUP_OUTPUT_FIFO_SIZE(x) (((x) >> 2) & 0x07)
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#define QUP_INPUT_BLOCK_SIZE(x) (((x) >> 5) & 0x03)
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#define QUP_INPUT_FIFO_SIZE(x) (((x) >> 7) & 0x07)
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/* QUP v2 tags */
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#define QUP_TAG_V2_START 0x81
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#define QUP_TAG_V2_DATAWR 0x82
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#define QUP_TAG_V2_DATAWR_STOP 0x83
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#define QUP_TAG_V2_DATARD 0x85
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#define QUP_TAG_V2_DATARD_NACK 0x86
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#define QUP_TAG_V2_DATARD_STOP 0x87
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#define QUP_I2C_MX_CONFIG_DURING_RUN BIT(31)
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/* Minimum transfer timeout for i2c transfers in micro seconds */
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#define TOUT_CNT (2 * 1000 * 1000)
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/* Default values. Use these if FW query fails */
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#define DEFAULT_CLK_FREQ I2C_SPEED_STANDARD_RATE
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#define DEFAULT_SRC_CLK 19200000
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/*
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* Max tags length (start, stop and maximum 2 bytes address) for each QUP
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* data transfer
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*/
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#define QUP_MAX_TAGS_LEN 4
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/* Max data length for each DATARD tags */
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#define RECV_MAX_DATA_LEN 254
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/* TAG length for DATA READ in RX FIFO */
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#define READ_RX_TAGS_LEN 2
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struct qup_i2c_priv {
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phys_addr_t base;
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struct clk core;
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struct clk iface;
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u32 in_fifo_sz;
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u32 out_fifo_sz;
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u32 clk_ctl;
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u32 config_run;
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};
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static inline u8 i2c_8bit_addr_from_msg(const struct i2c_msg *msg)
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{
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return (msg->addr << 1) | (msg->flags & I2C_M_RD ? 1 : 0);
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}
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static int qup_i2c_poll_state_mask(struct qup_i2c_priv *qup,
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u32 req_state, u32 req_mask)
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{
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int retries = 1;
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u32 state;
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/*
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* State transition takes 3 AHB clocks cycles + 3 I2C master clock
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* cycles. So retry once after a 1uS delay.
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*/
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do {
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state = readl(qup->base + QUP_STATE);
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if (state & QUP_STATE_VALID &&
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(state & req_mask) == req_state)
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return 0;
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udelay(1);
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} while (retries--);
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return -ETIMEDOUT;
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}
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static int qup_i2c_poll_state(struct qup_i2c_priv *qup, u32 req_state)
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{
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return qup_i2c_poll_state_mask(qup, req_state, QUP_STATE_MASK);
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}
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static int qup_i2c_poll_state_valid(struct qup_i2c_priv *qup)
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{
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return qup_i2c_poll_state_mask(qup, 0, 0);
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}
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static int qup_i2c_poll_state_i2c_master(struct qup_i2c_priv *qup)
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{
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return qup_i2c_poll_state_mask(qup, QUP_I2C_MAST_GEN, QUP_I2C_MAST_GEN);
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}
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static int qup_i2c_change_state(struct qup_i2c_priv *qup, u32 state)
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{
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if (qup_i2c_poll_state_valid(qup) != 0)
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return -EIO;
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writel(state, qup->base + QUP_STATE);
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if (qup_i2c_poll_state(qup, state) != 0)
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return -EIO;
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return 0;
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}
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/*
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* Function to check wheather Input or Output FIFO
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* has data to be serviced
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*/
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static int qup_i2c_check_fifo_status(struct qup_i2c_priv *qup, u32 reg_addr,
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u32 flags)
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{
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unsigned long count = TOUT_CNT;
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u32 val, status_flag;
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int ret = 0;
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do {
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val = readl(qup->base + reg_addr);
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status_flag = val & flags;
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if (!count) {
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printf("%s, timeout\n", __func__);
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ret = -ETIMEDOUT;
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break;
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}
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count--;
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udelay(1);
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} while (!status_flag);
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return ret;
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}
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/*
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* Function to configure Input and Output enable/disable
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*/
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static void qup_i2c_enable_io_config(struct qup_i2c_priv *qup, u32 write_cnt,
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u32 read_cnt)
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{
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u32 qup_config = QUP_I2C_MINI_CORE | QUP_I2C_N_VAL_V2;
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writel(qup->config_run | write_cnt, qup->base + QUP_MX_WRITE_CNT);
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if (read_cnt)
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writel(qup->config_run | read_cnt, qup->base + QUP_MX_READ_CNT);
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else
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qup_config |= QUP_NO_INPUT;
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writel(qup_config, qup->base + QUP_CONFIG);
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}
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static unsigned int qup_i2c_read_word(struct qup_i2c_priv *qup)
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{
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return readl(qup->base + QUP_IN_FIFO_BASE);
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}
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static void qup_i2c_write_word(struct qup_i2c_priv *qup, u32 word)
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{
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writel(word, qup->base + QUP_OUT_FIFO_BASE);
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}
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static int qup_i2c_blsp_read(struct qup_i2c_priv *qup, unsigned int addr,
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bool last, u8 *buffer, unsigned int bytes)
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{
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unsigned int i, j, word;
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int ret = 0;
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/* FIFO mode size limitation, for larger size implement block mode */
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if (bytes > (qup->in_fifo_sz - READ_RX_TAGS_LEN))
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return -EINVAL;
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qup_i2c_enable_io_config(qup, QUP_MAX_TAGS_LEN,
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bytes + READ_RX_TAGS_LEN);
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if (last)
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qup_i2c_write_word(qup, QUP_TAG_V2_START | addr << 8 |
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QUP_TAG_V2_DATARD_STOP << 16 |
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bytes << 24);
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else
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qup_i2c_write_word(qup, QUP_TAG_V2_START | addr << 8 |
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QUP_TAG_V2_DATARD << 16 | bytes << 24);
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ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
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if (ret)
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return ret;
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ret = qup_i2c_check_fifo_status(qup, QUP_OPERATIONAL, QUP_OUT_SVC_FLAG);
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if (ret)
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return ret;
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writel(QUP_OUT_SVC_FLAG, qup->base + QUP_OPERATIONAL);
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ret = qup_i2c_check_fifo_status(qup, QUP_OPERATIONAL, QUP_IN_SVC_FLAG);
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if (ret)
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return ret;
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writel(QUP_IN_SVC_FLAG, qup->base + QUP_OPERATIONAL);
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word = qup_i2c_read_word(qup);
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*(buffer++) = (word >> (8 * READ_RX_TAGS_LEN)) & 0xff;
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if (bytes > 1)
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*(buffer++) = (word >> (8 * (READ_RX_TAGS_LEN + 1))) & 0xff;
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for (i = 2; i < bytes; i += 4) {
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word = qup_i2c_read_word(qup);
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for (j = 0; j < 4; j++) {
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if ((i + j) == bytes)
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break;
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*buffer = (word >> (j * 8)) & 0xff;
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buffer++;
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}
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}
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ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE);
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return ret;
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}
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static int qup_i2c_blsp_write(struct qup_i2c_priv *qup, unsigned int addr,
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bool first, bool last, const u8 *buffer,
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unsigned int bytes)
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{
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unsigned int i;
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u32 word = 0;
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int ret = 0;
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/* FIFO mode size limitation, for larger size implement block mode */
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if (bytes > (qup->out_fifo_sz - QUP_MAX_TAGS_LEN))
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return -EINVAL;
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qup_i2c_enable_io_config(qup, bytes + QUP_MAX_TAGS_LEN, 0);
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if (first) {
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ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
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if (ret)
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return ret;
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writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
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ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE);
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if (ret)
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return ret;
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}
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if (last)
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qup_i2c_write_word(qup, QUP_TAG_V2_START | addr << 8 |
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QUP_TAG_V2_DATAWR_STOP << 16 |
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bytes << 24);
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else
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qup_i2c_write_word(qup, QUP_TAG_V2_START | addr << 8 |
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QUP_TAG_V2_DATAWR << 16 | bytes << 24);
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for (i = 0; i < bytes; i++) {
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/* Write the byte of data */
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word |= *buffer << ((i % 4) * 8);
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if ((i % 4) == 3) {
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qup_i2c_write_word(qup, word);
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word = 0;
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}
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buffer++;
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}
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if ((i % 4) != 0)
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qup_i2c_write_word(qup, word);
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ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
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if (ret)
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return ret;
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ret = qup_i2c_check_fifo_status(qup, QUP_OPERATIONAL, QUP_OUT_SVC_FLAG);
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if (ret)
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return ret;
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writel(QUP_OUT_SVC_FLAG, qup->base + QUP_OPERATIONAL);
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ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE);
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return ret;
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}
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static void qup_i2c_conf_mode_v2(struct qup_i2c_priv *qup)
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{
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u32 io_mode = QUP_REPACK_EN;
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writel(0, qup->base + QUP_MX_OUTPUT_CNT);
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writel(0, qup->base + QUP_MX_INPUT_CNT);
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writel(io_mode, qup->base + QUP_IO_MODE);
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}
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|
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static int qup_i2c_xfer_v2(struct udevice *bus, struct i2c_msg msgs[], int num)
|
||||
{
|
||||
struct qup_i2c_priv *qup = dev_get_priv(bus);
|
||||
int ret, idx = 0;
|
||||
u32 i2c_addr;
|
||||
|
||||
writel(1, qup->base + QUP_SW_RESET);
|
||||
ret = qup_i2c_poll_state(qup, QUP_RESET_STATE);
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
/* Configure QUP as I2C mini core */
|
||||
writel(QUP_I2C_MINI_CORE | QUP_I2C_N_VAL_V2 | QUP_NO_INPUT,
|
||||
qup->base + QUP_CONFIG);
|
||||
writel(QUP_V2_TAGS_EN, qup->base + QUP_I2C_MASTER_GEN);
|
||||
|
||||
if (qup_i2c_poll_state_i2c_master(qup)) {
|
||||
ret = -EIO;
|
||||
goto out;
|
||||
}
|
||||
|
||||
qup_i2c_conf_mode_v2(qup);
|
||||
|
||||
for (idx = 0; idx < num; idx++) {
|
||||
struct i2c_msg *m = &msgs[idx];
|
||||
|
||||
qup->config_run = !idx ? 0 : QUP_I2C_MX_CONFIG_DURING_RUN;
|
||||
i2c_addr = i2c_8bit_addr_from_msg(m);
|
||||
|
||||
if (m->flags & I2C_M_RD)
|
||||
ret = qup_i2c_blsp_read(qup, i2c_addr, idx == (num - 1),
|
||||
m->buf, m->len);
|
||||
else
|
||||
ret = qup_i2c_blsp_write(qup, i2c_addr, idx == 0,
|
||||
idx == (num - 1), m->buf,
|
||||
m->len);
|
||||
if (ret)
|
||||
break;
|
||||
}
|
||||
out:
|
||||
qup_i2c_change_state(qup, QUP_RESET_STATE);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int qup_i2c_enable_clocks(struct udevice *dev, struct qup_i2c_priv *qup)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = clk_enable(&qup->core);
|
||||
if (ret) {
|
||||
dev_err(dev, "clk_enable failed %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = clk_enable(&qup->iface);
|
||||
if (ret) {
|
||||
dev_err(dev, "clk_enable failed %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int qup_i2c_probe(struct udevice *dev)
|
||||
{
|
||||
static const int blk_sizes[] = {4, 16, 32};
|
||||
struct qup_i2c_priv *qup = dev_get_priv(dev);
|
||||
u32 io_mode, hw_ver, size, size_idx;
|
||||
int ret;
|
||||
|
||||
qup->base = (phys_addr_t)dev_read_addr_ptr(dev);
|
||||
if (!qup->base)
|
||||
return -EINVAL;
|
||||
|
||||
ret = clk_get_by_name(dev, "core", &qup->core);
|
||||
if (ret) {
|
||||
pr_err("clk_get_by_name(core) failed: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
ret = clk_get_by_name(dev, "iface", &qup->iface);
|
||||
if (ret) {
|
||||
pr_err("clk_get_by_name(iface) failed: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
qup_i2c_enable_clocks(dev, qup);
|
||||
|
||||
writel(1, qup->base + QUP_SW_RESET);
|
||||
ret = qup_i2c_poll_state_valid(qup);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
hw_ver = readl(qup->base + QUP_HW_VERSION);
|
||||
dev_dbg(dev, "Revision %x\n", hw_ver);
|
||||
|
||||
io_mode = readl(qup->base + QUP_IO_MODE);
|
||||
|
||||
/*
|
||||
* The block/fifo size w.r.t. 'actual data' is 1/2 due to 'tag'
|
||||
* associated with each byte written/received
|
||||
*/
|
||||
size_idx = QUP_OUTPUT_BLOCK_SIZE(io_mode);
|
||||
if (size_idx >= ARRAY_SIZE(blk_sizes)) {
|
||||
ret = -EIO;
|
||||
return ret;
|
||||
}
|
||||
size = QUP_OUTPUT_FIFO_SIZE(io_mode);
|
||||
qup->out_fifo_sz = blk_sizes[size_idx] * (2 << size);
|
||||
|
||||
size_idx = QUP_INPUT_BLOCK_SIZE(io_mode);
|
||||
if (size_idx >= ARRAY_SIZE(blk_sizes)) {
|
||||
ret = -EIO;
|
||||
return ret;
|
||||
}
|
||||
size = QUP_INPUT_FIFO_SIZE(io_mode);
|
||||
qup->in_fifo_sz = blk_sizes[size_idx] * (2 << size);
|
||||
|
||||
dev_dbg(dev, "IN:fifo:%d, OUT:fifo:%d\n", qup->in_fifo_sz,
|
||||
qup->out_fifo_sz);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int qup_i2c_set_bus_speed(struct udevice *dev, unsigned int clk_freq)
|
||||
{
|
||||
struct qup_i2c_priv *qup = dev_get_priv(dev);
|
||||
unsigned int src_clk_freq;
|
||||
int fs_div, hs_div;
|
||||
|
||||
/* We support frequencies up to FAST Mode Plus (1MHz) */
|
||||
if (!clk_freq || clk_freq > I2C_SPEED_FAST_PLUS_RATE) {
|
||||
dev_err(dev, "clock frequency not supported %d\n", clk_freq);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
src_clk_freq = clk_get_rate(&qup->iface);
|
||||
if ((int)src_clk_freq < 0) {
|
||||
src_clk_freq = DEFAULT_SRC_CLK;
|
||||
dev_dbg(dev, "using default core freq %d\n", src_clk_freq);
|
||||
}
|
||||
|
||||
dev_dbg(dev, "src_clk_freq %u\n", src_clk_freq);
|
||||
dev_dbg(dev, "clk_freq %u\n", clk_freq);
|
||||
|
||||
hs_div = 3;
|
||||
if (clk_freq <= I2C_SPEED_STANDARD_RATE) {
|
||||
fs_div = ((src_clk_freq / clk_freq) / 2) - 3;
|
||||
qup->clk_ctl = (hs_div << 8) | (fs_div & 0xff);
|
||||
} else {
|
||||
/* 33%/66% duty cycle */
|
||||
fs_div = ((src_clk_freq / clk_freq) - 6) * 2 / 3;
|
||||
qup->clk_ctl = ((fs_div / 2) << 16) | (hs_div << 8) | (fs_div & 0xff);
|
||||
}
|
||||
|
||||
dev_dbg(dev, "clk_ctl %u\n", qup->clk_ctl);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Probe to see if a chip is present. */
|
||||
static int qup_i2c_probe_chip(struct udevice *dev, uint chip_addr,
|
||||
uint chip_flags)
|
||||
{
|
||||
struct qup_i2c_priv *qup = dev_get_priv(dev);
|
||||
u32 hw_ver = readl(qup->base + QUP_HW_VERSION);
|
||||
|
||||
return hw_ver ? 0 : -1;
|
||||
}
|
||||
|
||||
static const struct dm_i2c_ops qup_i2c_ops = {
|
||||
.xfer = qup_i2c_xfer_v2,
|
||||
.probe_chip = qup_i2c_probe_chip,
|
||||
.set_bus_speed = qup_i2c_set_bus_speed,
|
||||
};
|
||||
|
||||
/*
|
||||
* Currently this driver only supports v2.x of QUP I2C controller, hence
|
||||
* functions above are named with a _v2 suffix. So when we have the
|
||||
* v1.1.1 support added as per the Linux counterpart then it should be easy
|
||||
* to add corresponding functions named with a _v1 suffix.
|
||||
*/
|
||||
static const struct udevice_id qup_i2c_ids[] = {
|
||||
{ .compatible = "qcom,i2c-qup-v2.1.1" },
|
||||
{ .compatible = "qcom,i2c-qup-v2.2.1" },
|
||||
{}
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(i2c_qup) = {
|
||||
.name = "i2c_qup",
|
||||
.id = UCLASS_I2C,
|
||||
.of_match = qup_i2c_ids,
|
||||
.probe = qup_i2c_probe,
|
||||
.priv_auto = sizeof(struct qup_i2c_priv),
|
||||
.ops = &qup_i2c_ops,
|
||||
};
|
||||
Loading…
Reference in a new issue