mirror of
https://github.com/AsahiLinux/u-boot
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kirkwood: add support for Iomega iConnect board
Add support for new board iConnect from Iomega. More information about the device can be found here: http://go.iomega.com/en/products/network-storage-desktop/wireless-data-station/network-hard-drive-iconnect/?partner=4735 Signed-off-by: Luka Perkov <uboot@lukaperkov.net> Tested-by: Wojciech Dubowik <wojciech.dubowik@neratec.com> Tested-by: Tim Fletcher <tim@night-shade.org.uk>
This commit is contained in:
Luka Perkov
Prafulla Wadaskar
parent
6d4ebd159e
commit
9b914727ce
7 changed files with 485 additions and 0 deletions
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@ -799,6 +799,7 @@ Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.com>
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Luka Perkov <uboot@lukaperkov.net>
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ib62x0 ARM926EJS
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iconnect ARM926EJS
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Dave Peverley <dpeverley@mpc-data.co.uk>
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43
board/iomega/iconnect/Makefile
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43
board/iomega/iconnect/Makefile
Normal file
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@ -0,0 +1,43 @@
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#
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# (C) Copyright 2009
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# Marvell Semiconductor <www.marvell.com>
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# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program. If not, see <http://www.gnu.org/licenses/>.
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).o
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COBJS := iconnect.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS)
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$(call cmd_link_o_target, $(OBJS) $(SOBJS))
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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107
board/iomega/iconnect/iconnect.c
Normal file
107
board/iomega/iconnect/iconnect.c
Normal file
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@ -0,0 +1,107 @@
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/*
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* Copyright (C) 2009-2012
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* Wojciech Dubowik <wojciech.dubowik@neratec.com>
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* Luka Perkov <uboot@lukaperkov.net>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <common.h>
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#include <miiphy.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/kirkwood.h>
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#include <asm/arch/mpp.h>
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#include "iconnect.h"
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DECLARE_GLOBAL_DATA_PTR;
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int board_early_init_f(void)
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{
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/*
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* default gpio configuration
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* There are maximum 64 gpios controlled through 2 sets of registers
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* the below configuration configures mainly initial LED status
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*/
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kw_config_gpio(ICONNECT_OE_VAL_LOW,
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ICONNECT_OE_VAL_HIGH,
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ICONNECT_OE_LOW, ICONNECT_OE_HIGH);
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/* Multi-Purpose Pins Functionality configuration */
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u32 kwmpp_config[] = {
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MPP0_NF_IO2,
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MPP1_NF_IO3,
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MPP2_NF_IO4,
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MPP3_NF_IO5,
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MPP4_NF_IO6,
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MPP5_NF_IO7,
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MPP6_SYSRST_OUTn, /* Reset signal */
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MPP7_GPO,
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MPP8_TW_SDA, /* I2C */
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MPP9_TW_SCK, /* I2C */
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MPP10_UART0_TXD,
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MPP11_UART0_RXD,
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MPP12_GPO, /* Reset button */
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MPP13_SD_CMD,
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MPP14_SD_D0,
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MPP15_SD_D1,
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MPP16_SD_D2,
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MPP17_SD_D3,
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MPP18_NF_IO0,
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MPP19_NF_IO1,
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MPP20_GE1_0,
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MPP21_GE1_1,
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MPP22_GE1_2,
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MPP23_GE1_3,
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MPP24_GE1_4,
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MPP25_GE1_5,
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MPP26_GE1_6,
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MPP27_GE1_7,
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MPP28_GPIO,
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MPP29_GPIO,
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MPP30_GE1_10,
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MPP31_GE1_11,
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MPP32_GE1_12,
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MPP33_GE1_13,
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MPP34_GE1_14,
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MPP35_GPIO, /* OTB button */
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MPP36_AUDIO_SPDIFI,
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MPP37_AUDIO_SPDIFO,
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MPP38_GPIO,
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MPP39_TDM_SPI_CS0,
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MPP40_TDM_SPI_SCK,
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MPP41_GPIO, /* LED brightness */
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MPP42_GPIO, /* LED power (blue) */
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MPP43_GPIO, /* LED power (red) */
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MPP44_GPIO, /* LED USB 1 */
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MPP45_GPIO, /* LED USB 2 */
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MPP46_GPIO, /* LED USB 3 */
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MPP47_GPIO, /* LED USB 4 */
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MPP48_GPIO, /* LED OTB */
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MPP49_GPIO,
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0
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};
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kirkwood_mpp_conf(kwmpp_config, NULL);
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return 0;
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}
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int board_init(void)
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{
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/* adress of boot parameters */
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gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
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return 0;
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}
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39
board/iomega/iconnect/iconnect.h
Normal file
39
board/iomega/iconnect/iconnect.h
Normal file
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@ -0,0 +1,39 @@
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/*
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* Copyright (C) 2009-2012
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* Wojciech Dubowik <wojciech.dubowik@neratec.com>
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* Luka Perkov <uboot@lukaperkov.net>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ICONNECT_H
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#define __ICONNECT_H
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#define ICONNECT_OE_LOW (~(1 << 7))
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#define ICONNECT_OE_HIGH (~(1 << 10))
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#define ICONNECT_OE_VAL_LOW (0)
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#define ICONNECT_OE_VAL_HIGH (1 << 10)
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/* PHY related */
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#define MV88E1116_LED_FCTRL_REG 10
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#define MV88E1116_CPRSP_CR3_REG 21
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#define MV88E1116_MAC_CTRL_REG 21
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#define MV88E1116_PGADR_REG 22
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#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
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#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
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#endif /* __ICONNECT_H */
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165
board/iomega/iconnect/kwbimage.cfg
Normal file
165
board/iomega/iconnect/kwbimage.cfg
Normal file
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@ -0,0 +1,165 @@
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#
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# (C) Copyright 2009-2012
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# Wojciech Dubowik <wojciech.dubowik@neratec.com>
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# Luka Perkov <uboot@lukaperkov.net>
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program. If not, see <http://www.gnu.org/licenses/>.
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#
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# Refer docs/README.kwimage for more details about how-to configure
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# and create kirkwood boot image
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#
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# Boot Media configurations
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BOOT_FROM nand
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NAND_ECC_MODE default
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NAND_PAGE_SIZE 0x0800
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# SOC registers configuration using bootrom header extension
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# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
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# Configure RGMII-0 interface pad voltage to 1.8V
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DATA 0xffd100e0 0x1b1b1b9b
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#Dram initalization for SINGLE x16 CL=5 @ 400MHz
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DATA 0xffd01400 0x43000c30 # DDR Configuration register
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# bit13-0: 0xc30, (3120 DDR2 clks refresh rate)
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# bit23-14: 0x0,
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# bit24: 0x1, enable exit self refresh mode on DDR access
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# bit25: 0x1, required
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# bit29-26: 0x0,
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# bit31-30: 0x1,
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DATA 0xffd01404 0x37543000 # DDR Controller Control Low
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# bit4: 0x0, addr/cmd in smame cycle
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# bit5: 0x0, clk is driven during self refresh, we don't care for APX
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# bit6: 0x0, use recommended falling edge of clk for addr/cmd
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# bit14: 0x0, input buffer always powered up
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# bit18: 0x1, cpu lock transaction enabled
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# bit23-20: 0x5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
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# bit27-24: 0x7, CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
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# bit30-28: 0x3, required
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# bit31: 0x0, no additional STARTBURST delay
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DATA 0xffd01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
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# bit3-0: TRAS lsbs
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# bit7-4: TRCD
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# bit11-8: TRP
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# bit15-12: TWR
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# bit19-16: TWTR
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# bit20: TRAS msb
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# bit23-21: 0x0
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# bit27-24: TRRD
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# bit31-28: TRTP
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DATA 0xffd0140c 0x00000a33 # DDR Timing (High)
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# bit6-0: TRFC
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# bit8-7: TR2R
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# bit10-9: TR2W
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# bit12-11: TW2W
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# bit31-13: 0x0, required
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DATA 0xffd01410 0x000000cc # DDR Address Control
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# bit1-0: 00, Cs0width (x8)
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# bit3-2: 11, Cs0size (1Gb)
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# bit5-4: 00, Cs1width (x8)
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# bit7-6: 11, Cs1size (1Gb)
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# bit9-8: 00, Cs2width (nonexistent)
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# bit11-10: 00, Cs2size (nonexistent)
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# bit13-12: 00, Cs3width (nonexistent)
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# bit15-14: 00, Cs3size (nonexistent)
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# bit16: 0, Cs0AddrSel
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# bit17: 0, Cs1AddrSel
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# bit18: 0, Cs2AddrSel
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# bit19: 0, Cs3AddrSel
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# bit31-20: 0x0, required
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DATA 0xffd01414 0x00000000 # DDR Open Pages Control
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# bit0: 0, OpenPage enabled
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# bit31-1: 0x0, required
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DATA 0xffd01418 0x00000000 # DDR Operation
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# bit3-0: 0x0, DDR cmd
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# bit31-4: 0x0, required
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DATA 0xffd0141c 0x00000c52 # DDR Mode
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# bit2-0: 0x2, BurstLen=2 required
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# bit3: 0x0, BurstType=0 required
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# bit6-4: 0x4, CL=5
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# bit7: 0x0, TestMode=0 normal
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# bit8: 0x0, DLL reset=0 normal
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# bit11-9: 0x6, auto-precharge write recovery ????????????
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# bit12: 0x0, PD must be zero
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# bit31-13: 0x0, required
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DATA 0xffd01420 0x00000040 # DDR Extended Mode
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# bit0: 0, DDR DLL enabled
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# bit1: 0, DDR drive strenght normal
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# bit2: 0, DDR ODT control lsd (disabled)
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# bit5-3: 0x0, required
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# bit6: 1, DDR ODT control msb, (disabled)
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# bit9-7: 0x0, required
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# bit10: 0, differential DQS enabled
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# bit11: 0, required
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# bit12: 0, DDR output buffer enabled
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# bit31-13: 0x0, required
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DATA 0xffd01424 0x0000f17f # DDR Controller Control High
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# bit2-0: 0x7, required
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# bit3: 0x1, MBUS Burst Chop disabled
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# bit6-4: 0x7, required
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# bit7: 0x0,
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# bit8: 0x1, add writepath sample stage, must be 1 for DDR freq >= 300MHz
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# bit9: 0x0, no half clock cycle addition to dataout
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# bit10: 0x0, 1/4 clock cycle skew enabled for addr/ctl signals
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# bit11: 0x0, 1/4 clock cycle skew disabled for write mesh
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# bit15-12: 0xf, required
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# bit31-16: 0x0, required
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DATA 0xffd01428 0x00085520 # DDR2 ODT Read Timing (default values)
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DATA 0xffd0147c 0x00008552 # DDR2 ODT Write Timing (default values)
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DATA 0xffd01500 0x00000000 # CS[0]n Base address to 0x0
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DATA 0xffd01504 0x0ffffff1 # CS[0]n Size
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# bit0: 0x1, Window enabled
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# bit1: 0x0, Write Protect disabled
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# bit3-2: 0x0, CS0 hit selected
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# bit23-4: 0xfffff, required
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# bit31-24: 0x0f, Size (i.e. 256MB)
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DATA 0xffd01508 0x00000000 # CS[1]n Base address to 256Mb
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DATA 0xffd0150c 0x00000000 # CS[1]n Size, window disabled
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DATA 0xffd01514 0x00000000 # CS[2]n Size, window disabled
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DATA 0xffd0151c 0x00000000 # CS[3]n Size, window disabled
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DATA 0xffd01494 0x00030000 # DDR ODT Control (Low)
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# bit3-0: ODT0Rd, MODT[0] asserted during read from DRAM CS1
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# bit7-4: ODT0Rd, MODT[0] asserted during read from DRAM CS0
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# bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1
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# bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
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DATA 0xffd01498 0x00000000 # DDR ODT Control (High)
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# bit1-0: 0x0, ODT0 controlled by ODT Control (low) register above
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# bit3-2: 0x1, ODT1 active NEVER!
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# bit31-4: 0x0, required
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DATA 0xffd0149c 0x0000e803 # CPU ODT Control
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DATA 0xffd01480 0x00000001 # DDR Initialization Control
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# bit0: 0x1, enable DDR init upon this register write
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# End of Header extension
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DATA 0x0 0x0
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@ -151,6 +151,7 @@ enbw_cmc arm arm926ejs enbw_cmc enbw
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calimain arm arm926ejs calimain omicron davinci
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pogo_e02 arm arm926ejs - cloudengines kirkwood
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dns325 arm arm926ejs - d-link kirkwood
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iconnect arm arm926ejs - iomega kirkwood
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lschlv2 arm arm926ejs lsxl buffalo kirkwood lsxl:LSCHLV2
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lsxhl arm arm926ejs lsxl buffalo kirkwood lsxl:LSXHL
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km_kirkwood arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD
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129
include/configs/iconnect.h
Normal file
129
include/configs/iconnect.h
Normal file
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@ -0,0 +1,129 @@
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/*
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* (C) Copyright 2009-2012
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||||
* Wojciech Dubowik <wojciech.dubowik@neratec.com>
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* Luka Perkov <uboot@lukaperkov.net>
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||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
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||||
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#ifndef _CONFIG_ICONNECT_H
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#define _CONFIG_ICONNECT_H
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/*
|
||||
* Version number information
|
||||
*/
|
||||
#define CONFIG_IDENT_STRING " Iomega iConnect"
|
||||
|
||||
/*
|
||||
* High level configuration options
|
||||
*/
|
||||
#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */
|
||||
#define CONFIG_KIRKWOOD /* SOC Family Name */
|
||||
#define CONFIG_KW88F6281 /* SOC Name */
|
||||
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
|
||||
|
||||
/*
|
||||
* Machine type
|
||||
*/
|
||||
#define CONFIG_MACH_TYPE MACH_TYPE_ICONNECT
|
||||
|
||||
/*
|
||||
* Compression configuration
|
||||
*/
|
||||
#define CONFIG_BZIP2
|
||||
#define CONFIG_LZMA
|
||||
#define CONFIG_LZO
|
||||
|
||||
/*
|
||||
* Commands configuration
|
||||
*/
|
||||
#define CONFIG_SYS_NO_FLASH /* declare no flash (NOR/SPI) */
|
||||
#define CONFIG_SYS_MVFS
|
||||
#include <config_cmd_default.h>
|
||||
#define CONFIG_CMD_ENV
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_NAND
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_USB
|
||||
|
||||
/*
|
||||
* mv-common.h should be defined after CMD configs since it used them
|
||||
* to enable certain macros
|
||||
*/
|
||||
#include "mv-common.h"
|
||||
|
||||
#undef CONFIG_SYS_PROMPT
|
||||
#define CONFIG_SYS_PROMPT "iconnect => "
|
||||
|
||||
/*
|
||||
* Environment variables configuration
|
||||
*/
|
||||
#ifdef CONFIG_CMD_NAND
|
||||
#define CONFIG_ENV_IS_IN_NAND
|
||||
#define CONFIG_ENV_SECT_SIZE 0x20000
|
||||
#else
|
||||
#define CONFIG_ENV_IS_NOWHERE
|
||||
#endif
|
||||
#define CONFIG_ENV_SIZE 0x20000
|
||||
#define CONFIG_ENV_OFFSET 0x80000
|
||||
|
||||
/*
|
||||
* Default environment variables
|
||||
*/
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \
|
||||
"ubi part rootfs; " \
|
||||
"ubifsmount rootfs; " \
|
||||
"ubifsload 0x800000 ${kernel}; " \
|
||||
"bootm 0x800000"
|
||||
|
||||
#define CONFIG_MTDPARTS \
|
||||
"mtdparts=orion_nand:" \
|
||||
"0x80000@0x0(uboot)," \
|
||||
"0x20000@0x80000(uboot_env)," \
|
||||
"-@0xa0000(rootfs)\0"
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"console=console=ttyS0,115200\0" \
|
||||
"mtdids=nand0=orion_nand\0" \
|
||||
"mtdparts="CONFIG_MTDPARTS \
|
||||
"kernel=/boot/uImage\0" \
|
||||
"bootargs_root=noinitrd ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs\0"
|
||||
|
||||
/*
|
||||
* Ethernet driver configuration
|
||||
*/
|
||||
#ifdef CONFIG_CMD_NET
|
||||
#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
|
||||
#define CONFIG_PHY_BASE_ADR 11
|
||||
#undef CONFIG_RESET_PHY_R
|
||||
#endif /* CONFIG_CMD_NET */
|
||||
|
||||
/*
|
||||
* File system
|
||||
*/
|
||||
#define CONFIG_CMD_EXT2
|
||||
#define CONFIG_CMD_FAT
|
||||
#define CONFIG_CMD_JFFS2
|
||||
#define CONFIG_CMD_UBI
|
||||
#define CONFIG_CMD_UBIFS
|
||||
#define CONFIG_RBTREE
|
||||
#define CONFIG_MTD_DEVICE
|
||||
#define CONFIG_MTD_PARTITIONS
|
||||
#define CONFIG_CMD_MTDPARTS
|
||||
|
||||
#endif /* _CONFIG_ICONNECT_H */
|
||||
Loading…
Reference in a new issue