mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-28 15:41:40 +00:00
arm/pxa: remove unused arch-pxa/macro.h
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com>
This commit is contained in:
Mikhail Kshevetskiy
Marek Vasut
parent
908614f20f
commit
9b8081a452
4 changed files with 0 additions and 368 deletions
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@ -33,7 +33,6 @@
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#include <config.h>
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#include <version.h>
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#include <asm/arch/pxa-regs.h>
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#include <asm/arch/macro.h>
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/* takes care the CP15 update has taken place */
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.macro CPWAIT reg
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@ -1,328 +0,0 @@
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/*
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* arch/arm/include/asm/arch-pxa/macro.h
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*
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* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __ASM_ARCH_PXA_MACRO_H__
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#define __ASM_ARCH_PXA_MACRO_H__
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#ifdef __ASSEMBLY__
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#include <asm/macro.h>
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#include <asm/arch/pxa-regs.h>
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/*
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* This macro performs a 32bit write to a memory location and makes sure the
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* write operation really happened by performing a read back.
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*
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* Clobbered regs: r4, r5
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*/
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.macro write32rb addr, data
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ldr r4, =\addr
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ldr r5, =\data
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str r5, [r4]
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ldr r5, [r4]
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.endm
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/*
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* This macro waits according to OSCR incrementation
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*
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* Clobbered regs: r4, r5, r6
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*/
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.macro pxa_wait_ticks ticks
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ldr r4, =OSCR
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mov r5, #0
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str r5, [r4]
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ldr r5, =\ticks
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1:
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ldr r6, [r4]
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cmp r5, r6
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bgt 1b
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.endm
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/*
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* This macro sets up the GPIO pins of the PXA2xx/PXA3xx CPU
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*
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* Clobbered regs: r4, r5
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*/
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.macro pxa_gpio_setup
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write32 GPSR0, CONFIG_SYS_GPSR0_VAL
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write32 GPSR1, CONFIG_SYS_GPSR1_VAL
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write32 GPSR2, CONFIG_SYS_GPSR2_VAL
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#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
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write32 GPSR3, CONFIG_SYS_GPSR3_VAL
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#endif
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write32 GPCR0, CONFIG_SYS_GPCR0_VAL
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write32 GPCR1, CONFIG_SYS_GPCR1_VAL
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write32 GPCR2, CONFIG_SYS_GPCR2_VAL
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#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
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write32 GPCR3, CONFIG_SYS_GPCR3_VAL
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#endif
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write32 GPDR0, CONFIG_SYS_GPDR0_VAL
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write32 GPDR1, CONFIG_SYS_GPDR1_VAL
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write32 GPDR2, CONFIG_SYS_GPDR2_VAL
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#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
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write32 GPDR3, CONFIG_SYS_GPDR3_VAL
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#endif
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write32 GAFR0_L, CONFIG_SYS_GAFR0_L_VAL
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write32 GAFR0_U, CONFIG_SYS_GAFR0_U_VAL
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write32 GAFR1_L, CONFIG_SYS_GAFR1_L_VAL
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write32 GAFR1_U, CONFIG_SYS_GAFR1_U_VAL
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write32 GAFR2_L, CONFIG_SYS_GAFR2_L_VAL
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write32 GAFR2_U, CONFIG_SYS_GAFR2_U_VAL
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#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
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write32 GAFR3_L, CONFIG_SYS_GAFR3_L_VAL
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write32 GAFR3_U, CONFIG_SYS_GAFR3_U_VAL
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#endif
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write32 PSSR, CONFIG_SYS_PSSR_VAL
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.endm
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/*
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* This macro sets up the Memory controller of the PXA2xx CPU
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*
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* WARNING: This macro uses internally r3 and r7 regs for MEMC_BASE
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* and CONFIG_SYS_MDREFR_VAL correspondingly. Please do not
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* use this regs for other purpose inside this macro.
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*
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* Clobbered regs: r3, r4, r5, r6, r7
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*/
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.macro pxa_mem_setup
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/* This comes handy when setting MDREFR */
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ldr r3, =MEMC_BASE
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/*
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* 1) Initialize Asynchronous static memory controller
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*/
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/* MSC0: nCS(0,1) */
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write32rb (MEMC_BASE + MSC0_OFFSET), CONFIG_SYS_MSC0_VAL
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/* MSC1: nCS(2,3) */
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write32rb (MEMC_BASE + MSC1_OFFSET), CONFIG_SYS_MSC1_VAL
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/* MSC2: nCS(4,5) */
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write32rb (MEMC_BASE + MSC2_OFFSET), CONFIG_SYS_MSC2_VAL
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/*
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* 2) Initialize Card Interface
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*/
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/* MECR: Memory Expansion Card Register */
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write32rb (MEMC_BASE + MECR_OFFSET), CONFIG_SYS_MECR_VAL
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/* MCMEM0: Card Interface slot 0 timing */
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write32rb (MEMC_BASE + MCMEM0_OFFSET), CONFIG_SYS_MCMEM0_VAL
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/* MCMEM1: Card Interface slot 1 timing */
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write32rb (MEMC_BASE + MCMEM1_OFFSET), CONFIG_SYS_MCMEM1_VAL
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/* MCATT0: Card Interface Attribute Space Timing, slot 0 */
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write32rb (MEMC_BASE + MCATT0_OFFSET), CONFIG_SYS_MCATT0_VAL
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/* MCATT1: Card Interface Attribute Space Timing, slot 1 */
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write32rb (MEMC_BASE + MCATT1_OFFSET), CONFIG_SYS_MCATT1_VAL
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/* MCIO0: Card Interface I/O Space Timing, slot 0 */
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write32rb (MEMC_BASE + MCIO0_OFFSET), CONFIG_SYS_MCIO0_VAL
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/* MCIO1: Card Interface I/O Space Timing, slot 1 */
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write32rb (MEMC_BASE + MCIO1_OFFSET), CONFIG_SYS_MCIO1_VAL
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/*
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* 3) Configure Fly-By DMA register
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*/
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write32rb (MEMC_BASE + FLYCNFG_OFFSET), CONFIG_SYS_FLYCNFG_VAL
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/*
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* 4) Initialize Timing for Sync Memory (SDCLK0)
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*/
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/*
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* Before accessing MDREFR we need a valid DRI field, so we set
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* this to power on defaults + DRI field.
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*/
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ldr r5, [r3, #MDREFR_OFFSET]
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bic r5, r5, #0x0ff
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bic r5, r5, #0xf00 /* MDREFR user config with zeroed DRI */
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ldr r4, =CONFIG_SYS_MDREFR_VAL
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mov r7, r4
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lsl r4, #20
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lsr r4, #20 /* Get a valid DRI field */
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orr r5, r5, r4 /* MDREFR user config with correct DRI */
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orr r5, #MDREFR_K0RUN
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orr r5, #MDREFR_SLFRSH
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bic r5, #MDREFR_APD
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bic r5, #MDREFR_E1PIN
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str r5, [r3, #MDREFR_OFFSET]
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ldr r4, [r3, #MDREFR_OFFSET]
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/*
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* 5) Initialize Synchronous Static Memory (Flash/Peripherals)
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*/
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/* Initialize SXCNFG register. Assert the enable bits.
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*
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* Write SXMRS to cause an MRS command to all enabled banks of
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* synchronous static memory. Note that SXLCR need not be written
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* at this time.
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*/
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write32rb (MEMC_BASE + SXCNFG_OFFSET), CONFIG_SYS_SXCNFG_VAL
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/*
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* 6) Initialize SDRAM
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*/
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bic r7, #MDREFR_SLFRSH
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str r7, [r3, #MDREFR_OFFSET]
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ldr r4, [r3, #MDREFR_OFFSET]
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orr r7, #MDREFR_E1PIN
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str r7, [r3, #MDREFR_OFFSET]
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ldr r4, [r3, #MDREFR_OFFSET]
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/*
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* 7) Write MDCNFG with MDCNFG:DEx deasserted (set to 0), to configure
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* but not enable each SDRAM partition pair.
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*/
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/* Fetch platform value of MDCNFG */
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ldr r4, =CONFIG_SYS_MDCNFG_VAL
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/* Disable all sdram banks */
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bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
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bic r4, r4, #(MDCNFG_DE2|MDCNFG_DE3)
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/* Write initial value of MDCNFG, w/o enabling sdram banks */
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str r4, [r3, #MDCNFG_OFFSET]
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ldr r4, [r3, #MDCNFG_OFFSET]
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/* Wait for the clock to the SDRAMs to stabilize, 100..200 usec. */
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pxa_wait_ticks 0x300
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/*
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* 8) Trigger a number (usually 8) refresh cycles by attempting
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* non-burst read or write accesses to disabled SDRAM, as commonly
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* specified in the power up sequence documented in SDRAM data
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* sheets. The address(es) used for this purpose must not be
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* cacheable.
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*/
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ldr r4, =CONFIG_SYS_DRAM_BASE
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.rept 9
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str r5, [r4]
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.endr
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/*
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* 9) Write MDCNFG with enable bits asserted (MDCNFG:DEx set to 1).
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*/
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ldr r5, =CONFIG_SYS_MDCNFG_VAL
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ldr r4, =(MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3)
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and r5, r5, r4
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ldr r4, [r3, #MDCNFG_OFFSET]
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orr r4, r4, r5
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str r4, [r3, #MDCNFG_OFFSET]
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ldr r4, [r3, #MDCNFG_OFFSET]
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/*
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* 10) Write MDMRS.
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*/
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ldr r4, =CONFIG_SYS_MDMRS_VAL
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str r4, [r3, #MDMRS_OFFSET]
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ldr r4, [r3, #MDMRS_OFFSET]
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/*
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* 11) Enable APD
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*/
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ldr r4, [r3, #MDREFR_OFFSET]
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and r7, r7, #MDREFR_APD
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orr r4, r4, r7
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str r4, [r3, #MDREFR_OFFSET]
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ldr r4, [r3, #MDREFR_OFFSET]
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.endm
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/*
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* This macro tests if the CPU woke up from sleep and eventually resumes
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*
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* Clobbered regs: r4, r5
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*/
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.macro pxa_wakeup
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ldr r4, =RCSR
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ldr r5, [r4]
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and r5, r5, #(RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR)
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str r5, [r4]
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teq r5, #RCSR_SMR
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bne pxa_wakeup_exit
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ldr r4, =PSSR
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mov r5, #PSSR_PH
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str r5, [r4]
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ldr r4, =PSPR
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ldr pc, [r4]
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pxa_wakeup_exit:
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.endm
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/*
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* This macro disables all interupts on PXA2xx/PXA3xx CPU
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*
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* Clobbered regs: r4, r5
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*/
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.macro pxa_intr_setup
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write32 ICLR, 0
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write32 ICMR, 0
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#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
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write32 ICLR2, 0
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write32 ICMR2, 0
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#endif
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.endm
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/*
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* This macro configures clock on PXA2xx/PXA3xx CPU
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*
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* Clobbered regs: r4, r5
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*/
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.macro pxa_clock_setup
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/* Disable the peripheral clocks, and set the core clock frequency */
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/* Turn Off ALL on-chip peripheral clocks for re-configuration */
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write32 CKEN, CONFIG_SYS_CKEN
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/* Write CCCR */
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write32 CCCR, CONFIG_SYS_CCCR
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#ifdef CONFIG_RTC
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/* enable the 32Khz oscillator for RTC and PowerManager */
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write32 OSCC, #OSCC_OON
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ldr r4, =OSCC
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/* Spin here until OSCC.OOK get set, meaning the PLL has settled. */
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2:
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ldr r5, [r4]
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ands r5, r5, #1
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beq 2b
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#endif
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.endm
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#endif /* __ASSEMBLY__ */
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#endif /* __ASM_ARCH_PXA_MACRO_H__ */
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@ -8,7 +8,6 @@ AFLAGS += -DCONFIG_PRELOADER -DCONFIG_ONENAND_IPL
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CFLAGS += -DCONFIG_PRELOADER -DCONFIG_ONENAND_IPL
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OBJCFLAGS += --gap-fill=0x00
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SOBJS := lowlevel_init.o
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SOBJS += start.o
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COBJS := vpac270.o
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COBJS += onenand_read.o
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@ -62,10 +61,6 @@ ifneq ($(OBJTREE), $(SRCTREE))
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$(obj)vpac270.c:
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@rm -f $@
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ln -s $(SRCTREE)/onenand_ipl/board/$(BOARDDIR)/vpac270.c $@
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$(obj)lowlevel_init.S:
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@rm -f $@
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ln -s $(SRCTREE)/onenand_ipl/board/$(BOARDDIR)/lowlevel_init.S $@
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endif
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#########################################################################
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@ -1,34 +0,0 @@
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/*
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* Voipac PXA270 Lowlevel Hardware Initialization
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*
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* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
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*
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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* GNU General Public License for more details.
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||||
*
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||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <version.h>
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#include <asm/arch/pxa-regs.h>
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#include <asm/arch/macro.h>
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.globl lowlevel_init
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lowlevel_init:
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pxa_clock_setup
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mov pc, lr
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